Emulate per-model CPU bus access sequences (RMW, dummy reads, interrupt entry)

[highbyte]

Makes CPU instructions perform their real per-model bus access sequences — every read and write in hardware order — so memory-mapped I/O with access side effects behaves as it does on real machines. Follow-up to the CPU model architecture PR (#288); milestone M2 of that work.

Behavioral highlights

• Read-modify-write sequences per model: NMOS RMW instructions (official and undocumented) perform read-write-write — the unmodified value is written back before the result. The 65C02 performs read-read-write. Exhaustively guarded by a sequence matrix test over all 66 NMOS and 28 65C02 memory-RMW opcode bytes.
• Apple II language card is now Sather-correct (write-enable requires two consecutive odd READS; a write never completes the sequence — previously a read+write could unlock). Combined with the RMW sequences this makes INC $C083 CPU-model observable: it unlocks the card on a 65C02 (read-read-write) but not on an NMOS 6502 (read-write-write) — exactly as on real hardware.
• NMOS indexed dummy reads: reads that cross a page touch the un-carried address first; indexed stores and RMW always do. Classic consequence now emulated: STA $DC0D,X with X=0 silently acknowledges pending C64 CIA interrupts through its dummy read (covered by an acceptance test).
• Zero-page pointer wrap: (zp,X), (zp),Y, and 65C02 (zp) pointers at $FF take their high byte from $00 (wrapping within zero page) instead of $0100 — a result-level fix on both models, same class as the JMP ($xxFF) fix in Add CPU model architecture with NCR 65C02 support #288.
• Interrupt-entry sequences: IRQ/NMI entry performs the two hardware dummy reads of the next opcode byte before the stack pushes and vector reads; BRK fetches its padding byte as a real bus access (pushed return address unchanged).

Design

• Sequences are composed at CPU-construction time per model (a PerformsIndexedDummyReads model trait; single source of truth per model); the 65C02 keeps its own read-read-write RMW handlers. No model branches on the hot path, no tracing hooks on the memory path.
• Tests observe bus traffic via a BusAccessRecorder built purely on the production memory-mapped-I/O mechanism (Memory.MapReader/MapWriter).
• Language-card rules verified against Sather (Understanding the Apple IIe, 5-23) via two independent emulator implementations before coding.

Deliberately deferred (documented in code)

• 65C02-specific dummy-read addresses (the CMOS part re-targeted them; no observable case yet).
• zp,X base-address dummy reads (not page-cross-related) and RTI/pull stack dummies.
• Interrupt-entry cycle accounting (entry currently consumes 0 cycles, real hardware 7) — pre-existing gap, discovered here; changing it shifts C64/VIC-20 frame timing so it needs its own decision.

Tests & performance

• ~40 new/updated tests: per-model sequence characterization, exhaustive RMW matrix, pointer-wrap, language-card model divergence, C64 $DC0D, interrupt-entry ordering.
• All suites green incl. Klaus NMOS functional/BCD locally and the Klaus 65C02 extended-opcodes test on Windows CI.
• Benchmarks: representative C64 workload and hot-path benchmarks at or below the milestone baseline after all changes (per-part measurements recorded during development; no benchmark moved ≥5%).

[sonarqubecloud]

Quality Gate passed

Issues
11 New issues
0 Accepted issues

Measures
0 Security Hotspots
98.9% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud