Converge instruction implementations to operation cores and static handlers

[highbyte]

What

Completes the CPU instruction-dispatch modernization started with the per-model descriptor tables (#288) and ordered bus sequences (#289): every opcode on both CPU models now executes through small operation cores composed per addressing mode, or bespoke static handlers where composition doesn't fit. The ~70 per-instruction classes and the interface-probing composition path are deleted.

Changes

• Operation cores (InstructionCores): one static method per operation (loads/stores, transfers, logic, compares, shifts/rotates, INC/DEC, ADC/SBC per model, TSB/TRB, flags, and all NMOS-undocumented operations), bound to addressing modes by ComposeRead/ComposeStore/ComposeImplied/ComposeRmw/ComposeBranch.
• Bespoke static handlers for instructions that don't fit composition: shared (SharedHandlers: stack, flow, BRK, NOP), NMOS-specific (NmosHandlers: JMP (addr) page-wrap bug, JAM), and 65C02-specific (CmosHandlers: JMP variants, PHX/PHY/PLX/PLY, defined-NOP family).
• InstructionBindings: the single table both models compose their 256-entry descriptor tables from, with undocumented NMOS opcodes gated by the CPU's compatibility profile at binding time.
• InstructionList is now a projection: its metadata is generated from the NMOS model's descriptor table instead of the descriptor tables being composed from instruction objects — the two views can no longer drift. InstructionDictionary/GetInstruction and the Instruction class hierarchy are removed (pre-1.0 clean break).
• Deleted: all Instructions/* classes, the four IInstructionUses* interfaces, IReadModifyWriteInstruction, AddrModeCalcResult, InstructionExtraCyclesCalculator, and the legacy table composition. Net −4.0k lines.

Behavior

Zero behavior change by design, verified per migration step against the previous implementation:

• Byte-for-byte descriptor/metadata parity across all four compatibility profiles (guarded by test).
• All test suites green on macOS and Windows (incl. Klaus Dormann functional/BCD/65C02 tests and the exhaustive RMW bus-sequence matrix).
• Hot-path benchmarks at parity with the pre-migration baseline (same-machine-state pairing); allocations unchanged.
• Live end-to-end check: C64 boots to BASIC and executes correctly in the Avalonia desktop app.

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
99.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud