Fix #16032: propagate channels_last dim_order to out-variant TensorSp…

[nefainl]

FP16 convolution ops produce channels_last tensors (dim_order [0,2,3,1]) for performance. SpecPropPass, however, was assigning contiguous dim_order ([0,1,2,3]) to the pre-allocated out TensorSpec for format-preserving ops like clone.out, because it derived the spec from an empty FakeTensor rather than from the primary input.

At runtime, op_clone.cpp asserts tensors_have_same_dim_order(self, out). When self is channels_last and out is contiguous, this fails with Code=18 InvalidArgument.

Fix: in SpecPropPass.call, in the same node loop that handles output/getitem/delegate, add a branch for format-preserving ops with an out kwarg: override the out node's TensorSpec.dim_order to match the primary input's dim_order from its FakeTensor strides. Uses dim_order_from_stride() in exir/tensor.py.

Also improves op_clone.cpp error message with dtypes and issue reference.

Fixes #16032

Test plan

• New tests in exir/tests/test_spec_prop_dim_order.py: TestDimOrderFromFakeTensor, TestShouldPropagateDimOrder, TestSpecPropPassDimOrder (FP32 contiguous clone, FP16 conv→clone, FP16 conv→relu→clone). Run with: python -m pytest exir/tests/test_spec_prop_dim_order.py -v.
• CI will run the full test suite on this PR.
• Manual check: verified file presence and grep for dim_order_utils and 16032 in the changed files.

[pytorch-bot]

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[nefainl]

I’ve opened a PR with a fix: #17463. SpecPropPass now propagates the primary input’s dim_order to the out TensorSpec for format-preserving ops (e.g. clone.out), so the memory planner allocates the correct layout and the runtime check in op_clone.cpp no longer fails with Code 18 for channels_last FP16 conv→clone.

@pytorchbot label "release notes: bug fix"

Suggested one-liner for release notes: Fixes Code 18 (InvalidArgument) at clone.out when using FP16 models with channels_last tensors by propagating the primary input's dim_order to the out TensorSpec in SpecPropPass.

[pytorch-bot]

Didn't find following labels among repository labels: release notes: bug fix

[nefainl]

@pytorchbot label "release notes: compiler"

[pytorch-bot]

Didn't find following labels among repository labels: release notes: compiler

[nefainl]

@pytorchbot label "release notes: fix"

[pytorch-bot]

Didn't find following labels among repository labels: release notes: fix

[nefainl]

I couldn't find a matching "release notes:" label in this repo (pytorchbot reported none of the ones I tried exist). This PR fixes a user-facing bug (Code 18 at clone.out for FP16 channels_last). Please add the appropriate release-notes label if this repo uses them. Otherwise happy to leave labeling to maintainers.

[nefainl]

@pytorchbot label "release notes: exir"

[nefainl]

Some comments for the reviewer(s) on potential improvements or hazards:

Core fix (#16032): The SpecPropPass change propagates dim_order from the primary input’s FakeTensor strides to the out-variant TensorSpec for format-preserving ops (e.g. clone.out), and correctly treats _clone_dim_order / _to_dim_order_copy as layout-changing ops that use their explicit dim_order kwarg instead of the input layout.

Scope: The PR grew from a small fix into 7 commits across 15 files. Several changes are unrelated to the core dim_order fix and would be easier to review if split out.

Recommendations if you choose to split the PR:

Core: SpecPropPass + dim_order_utils.py + test_spec_prop_dim_order.py + op_clone.cpp error message.

Separate PRs: ensure_graph_node_specs, emitter/memory_planning/view_copy fixes, test skips, and the flatc fallback.

Early return on delegate
In spec_prop_pass.py, the executorch_call_delegate branch does return res, which exits the pass before processing later nodes (output, getitem, format-preserving ops). ensure_graph_node_specs compensates for this. Consider changing to continue (or removing the early return) so the pass processes all nodes and ensure_graph_node_specs is not needed as a workaround.

Downstream fixes
The emitter getitem, memory.alloc skip, and replace_view_copy changes address real bugs exposed by the spec changes. They are reasonable fixes but should be reviewed on their own; splitting them out would help.

Flatc fallback
The flatc path fallback is unrelated to dim_order and should be moved to a separate PR.
FORMAT_PRESERVING_OPS
The list is manually maintained. Consider adding a short comment or docstring noting that new format-preserving ops may need to be added here.

Main risk (technical debt):
ensure_graph_node_specs() in MemoryPlanningPass. Adding a defensive "fill in missing specs" call at the start of memory planning papers over a symptom rather than a cause. Nodes missing meta['spec'] after delegation are a sign that something upstream didn't run correctly. You lose visibility into cases where the spec is missing for a bad reason — not just the delegation case. The guard needed to skip memory.alloc nodes (which already have a spec) shows the function has to be spec-aware, and that complexity could hide edge cases.

[nefainl]

Ok all tests pass now, ready for review - I hope this implementation is much cleaner going for the root causes instead of the symptoms.

[nefainl]

Removing some other clutter (cmake apple etc.)

[SS-JIA]

cc: @JacobSzwejbka @larryliu0820 perhaps

[nefainl]

Removed some more clutter from previous implementation, tests still pass hope this is more clean now :)

[GregoryComer]

@nefainl Can you explain more what the original problem is - maybe provide a standalone repro? You mention fp16 convolutions. Are these custom ops, or is this an issue that gets hit with standard aten ops (torch.nn.Convolution)?

Regarding the approach in the PR, we'd need to talk through some of the dim order semantics in the IR. Additionally, there are a large number of unrelated changes. Could you cut down the PR to only core changes? I'd recommend that we align on the approach to fix the core issue / bug before going further on implementation.

Thanks!

[nefainl]

@nefainl Can you explain more what the original problem is - maybe provide a standalone repro? You mention fp16 convolutions. Are these custom ops, or is this an issue that gets hit with standard aten ops (torch.nn.Convolution)?

Regarding the approach in the PR, we'd need to talk through some of the dim order semantics in the IR. Additionally, there are a large number of unrelated changes. Could you cut down the PR to only core changes? I'd recommend that we align on the approach to fix the core issue / bug before going further on implementation.

Thanks!

Thanks for the detailed feedback — happy to align on the core issue before going further on implementation.

---

What the original problem is

This is a standard torch.nn.Conv2d — no custom ops. The issue is entirely within the ExecuTorch export and runtime pipeline.

torch.nn.Conv2d on a channels_last input produces a channels-last output tensor (dim_order [0,2,3,1]). When you follow that with .clone(), SpecPropPass assigns the wrong dim_order to the pre-allocated out buffer — it uses [0,1,2,3] (contiguous) instead of inheriting [0,2,3,1] from the input. The memory planner then allocates a contiguous buffer. At runtime, op_clone.cpp asserts tensors_have_same_dim_order(self, out), finds [0,2,3,1] ≠ [0,1,2,3], and raises Code=18 InvalidArgument.

Standalone repro

import torch
from torch.export import export
from executorch.exir import to_edge, EdgeCompileConfig
from executorch.extension.pybindings.portable_lib import _load_for_executorch_from_buffer

class ConvClone(torch.nn.Module):
    def __init__(self):
        super().__init__()
        self.conv = torch.nn.Conv2d(3, 16, kernel_size=3, padding=1)  # standard aten, no custom ops

    def forward(self, x):
        return self.conv(x).clone()

# FP32 channels_last reproduces just as well — FP16 is not the special ingredient
model = ConvClone().to(memory_format=torch.channels_last)
x = torch.randn(1, 3, 8, 8).to(memory_format=torch.channels_last)

exported = export(model, (x,))
edge = to_edge(exported, compile_config=EdgeCompileConfig(_skip_dim_order=False))

# Show the bug before running: inspect the out kwarg node's spec
for node in edge.exported_program().graph_module.graph.nodes:
    if node.op == "call_function" and "clone" in str(node.target):
        out_node = node.kwargs.get("out")
        if out_node is not None:
            spec = out_node.meta.get("spec")
            print(f"clone.out spec.dim_order = {spec.dim_order}")
            # Prints [0, 1, 2, 3]  ← BUG, expected [0, 2, 3, 1]

# Crash: Code=18 InvalidArgument at clone.out
buf = edge.to_executorch().buffer
rt = _load_for_executorch_from_buffer(buf)
rt.run_method("forward", (x,))  # raises here

FP16 isn't special to the bug itself — the same crash occurs with FP32 channels_last. FP16 just makes it more common in practice because hardware backends (CoreML, Vulkan, etc.) tend to promote channels-last layouts, so the combination comes up more often with half-precision models.

The core bug in one sentence

SpecPropPass derives the out kwarg node's TensorSpec.dim_order from the pre-allocated out FakeTensor, which is always contiguous — for format-preserving ops like clone, the correct dim_order is the primary input's.

dim_order IR semantics — questions before going further

Before implementing anything, I want to make sure I have the right mental model:

Q1. For an out-variant like clone.out(self, out=buf), is buf's TensorSpec.dim_order the layout the memory planner will actually allocate for that buffer — and is the contract that the kernel requires self.dim_order() == buf.dim_order() at runtime?

Q2. For layout-transforming ops like _clone_dim_order and _to_dim_order_copy (which carry an explicit dim_order kwarg), should the output node's spec reflect the kwarg rather than the input's layout? That's what I've assumed, but want to confirm.

Q3. Is there a broader invariant that meta["spec"].dim_order should always agree with what dim_order_from_stride(meta["val"]) returns? Or is the spec the authoritative source of truth and the FakeTensor strides advisory?

What the minimal stripped-down change looks like

Dropping everything unrelated, the core fix is three files:

• exir/lowered_backend_module.py (+2 lines): set meta["spec"] for getitem nodes at creation time, eliminating the missing-spec gap that caused several downstream failures in the current PR.
• exir/passes/spec_prop_pass.py (~80 lines net): add _fix_out_spec_dim_order() with two disjoint frozensets (_LAYOUT_TRANSFORMING_OPS, _FORMAT_PRESERVING_OPS), called per-node after make_spec().
• exir/tests/test_spec_prop_dim_order.py (new): tests using the repro above.

Everything else in the current PR — test skips, _flatbuffer.py, replace_view_copy_with_view_pass.py, the quant and parameter removal test changes — can be dropped entirely or filed as separate PRs if worth pursuing independently.

Happy to open a clean PR with just those three files once we've agreed on the semantic questions above.

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[GregoryComer]

@nefainl If that is the case, it sounds like the meta value for clone is incorrect after the clone op gets converted to the edge dim order op variant. I printed the node dim order below from your repro:

EP:
p_conv_weight: (0, 2, 3, 1)
p_conv_bias: (0,)
x: (0, 2, 3, 1)
conv2d: (0, 2, 3, 1)
clone: (0, 2, 3, 1)
output: None

Edge:
p_conv_weight: (0, 2, 3, 1)
p_conv_bias: (0,)
x: (0, 2, 3, 1)
aten_convolution_default: (0, 2, 3, 1)
dim_order_ops__clone_dim_order_default: (0, 1, 2, 3)

Likely, the pass that transforms the clone is incorrect. I'd look there. In general, the meta val in graph is the source of truth for dim order. We should not modify the spec dim order directly.

[GregoryComer]

Specifically, I think the bug is that memory_format_ops_pass assumes contiguous when no kwarg is present, when it should treat no memory_format kwarg as preserve_format, at least for clone and to. I'd recommend writing 1 or 2 concise tests for the minimal repro (likely in test_passes.py or similar). and updating the memory format ops pass.

[nefainl]

Thanks for the input, I will look further tomorrow and with your guidance go for a minimal implementation.

[GregoryComer]

Thanks. The change for tensor ambiguity in the runtime C++ code is also good, and a separate issue from the clone/_to_copy dim order. I'd recommend raising that as a standalone PR and re-write to not use goto. We can probably merge that one independently of the clone fix.

[nefainl]

Update on PR B (C++ stride fallback) - Seeking Guidance

@GregoryComer - Following your advice, we split the fix into two PRs:

• PR A (Python fix): fix(MemoryFormatOpsPass): preserve input dim_order for clone/to_copy with no memory_format kwarg #17611 - MemoryFormatOpsPass preserve_format semantics ✅ opened
• PR B (C++ fix): tensors_have_same_dim_order stride fallback - on hold pending this discussion

What We Discovered

While implementing PR B, we tested ExecuTorch's strides_from_dim_order and found that it computes different strides for NCHW vs NHWC even for degenerate shapes:

Shape	NCHW strides	NHWC strides	Same?
[2,3,8,8]	[192,64,8,1]	[192,1,24,3]	No
[2,1,4,4] (C=1)	[16,16,4,1]	[16,1,4,1]	No
[2,3,1,1] (H=W=1)	[3,1,1,1]	[3,1,3,3]	No

This differs from PyTorch's behavior where degenerate shapes produce identical strides for NCHW/NHWC.

The Implication

The stride fallback in two_tensors_same_dim_order() will never return true for any tensor pair produced by ExecuTorch's own TensorFactory or memory planner. The fallback would only activate for:

• Tensors from external delegates that allocate their own memory
• User-constructed TensorImpl with custom strides

Questions

1. Is the stride fallback still valuable as defense-in-depth for delegate/external tensors, even though it doesn't help with ExecuTorch-internal degenerate shapes?

2. Should we proceed with PR B with updated documentation clarifying its actual scope, or is it not worth the complexity given PR A fixes the root cause?

3. Alternative: Should ExecuTorch's strides_from_dim_order be modified to match PyTorch's behavior for degenerate shapes? (This would be a larger change with potential compatibility implications.)

Implementation Status

PR B is ready with:

• ✅ No goto (uses helper function with break/return)
• ✅ Correct int loop variables (no sign-compare warnings)
• ✅ 6 tests covering label matching and stride comparison
• ⚠️ Missing: test that exercises the slow path returning true (requires manual TensorImpl construction)

Happy to proceed in whichever direction you recommend.

[nefainl]

Correction: PyTorch and ExecuTorch Stride Behavior Are Identical

After further investigation, I need to correct my earlier analysis. PyTorch and ExecuTorch produce identical strides for all shapes, including degenerate ones:

Shape	NCHW strides	NHWC strides	Same?
[2,3,8,8] (normal)	[192,64,8,1]	[192,1,24,3]	No
[2,1,4,4] (C=1)	[16,16,4,1]	[16,1,4,1]	No
[2,3,1,1] (H=W=1)	[3,1,1,1]	[3,1,3,3]	No

Both frameworks compute different strides for NCHW vs NHWC even when dimensions are size-1. The reason PyTorch's is_contiguous(memory_format=channels_last) returns True for degenerate shapes is that it has special logic that ignores stride values for size-1 dimensions — it's not that the strides are the same.

What This Means for PR B

The stride fallback in tensors_have_same_dim_order() will never return true for any tensor pair where one is NCHW and one is NHWC, regardless of shape. The fallback only activates when:

• Two tensors have different dim_order labels
• But happen to have identical strides (e.g., from a delegate that allocates memory differently)

This is a much narrower scope than "handling degenerate shapes."

Updated Questions

1. Is PR B still valuable as defense-in-depth for delegate/external tensors with non-standard strides?

2. Alternative approach: Should tensors_have_same_dim_order() adopt PyTorch's is_contiguous logic — i.e., ignore stride mismatches for size-1 dimensions? This would make it semantically equivalent to PyTorch's behavior and actually handle the degenerate shape case. However, this is a semantic change that may have broader implications.

3. Or is PR A sufficient? Since PR A (fix(MemoryFormatOpsPass): preserve input dim_order for clone/to_copy with no memory_format kwarg #17611) fixes the root cause at export time, the runtime check in PR B may not be necessary.

Happy to proceed in whichever direction you recommend. The code for PR B is ready (no goto, proper loop types, 6 tests), but I want to ensure the scope and rationale are accurate before opening it.

[nefainl]

Update: Fix Split into Two Focused PRs

Following @GregoryComer's guidance, I've split the fix into two independent, focused PRs:

PR A: Python Export Pipeline Fix

PR: #17611
Status: Open, awaiting review

Fixes MemoryFormatOpsPass to correctly handle torch.preserve_format semantics for clone() and _to_copy.default operations. This is the primary fix that ensures the correct dim_order is assigned during export.

PR C: C++ Runtime Defense-in-Depth

PR: #17612
Status: Open, awaiting review

Implements semantic equivalence checking in tensors_have_same_dim_order() to handle degenerate tensor shapes (size-1 dimensions) where NCHW and NHWC have identical physical memory layouts despite different dim_order labels.

---

Why PR C Instead of PR B (Stride Equality)?

The original plan included a "PR B" that would add a simple stride equality fallback:

// PR B approach: simple stride equality
for (int i = 0; i < ndim; ++i) {
  if (a.strides()[i] != b.strides()[i]) {
    return false;
  }
}
return true;

However, testing revealed that ExecuTorch's strides_from_dim_order computes different strides for NCHW vs NHWC even for degenerate shapes:

Shape	NCHW strides	NHWC strides	Equal?
[2,1,4,4] (C=1)	[16,16,4,1]	[16,1,4,1]	❌ No
[2,3,1,1] (H=W=1)	[3,1,1,1]	[3,1,3,3]	❌ No

A simple stride equality check would still fail for these degenerate cases.

PR C: Semantic Equivalence (Implemented)

PR C implements semantic equivalence that mirrors PyTorch's is_contiguous logic from c10/core/Contiguity.h:

// PR C approach: semantic equivalence (skip size-1 dimensions)
for (int i = 0; i < ndim; ++i) {
  // Skip dimensions where both tensors have size 1
  if (a.sizes()[i] == 1 && b.sizes()[i] == 1) {
    continue;
  }
  // For non-trivial dimensions, strides must match
  if (a.strides()[i] != b.strides()[i]) {
    return false;
  }
}
return true;

This correctly identifies that [2,1,4,4] NCHW and NHWC are memory-equivalent because:

• Dimension 1 (C=1) is skipped (both have size 1)
• Remaining dimensions have matching strides: [16,_,4,1] vs [16,_,4,1]

---

Summary

PR	Focus	Approach
#17611 (PR A)	Python export	Fix MemoryFormatOpsPass to preserve input dim_order
#17612 (PR C)	C++ runtime	Semantic equivalence (skip size-1 dims, match PyTorch)
PR B	C++ runtime	Stride equality — Not implemented (doesn't work for degenerate shapes)

Both PRs are independent and can be reviewed/merged separately. PR A is the primary fix; PR C provides defense-in-depth at the runtime level.

[nefainl]

Changing this branch to draft since the two other PR's supersede it.