[dv] Repair the single-step test environment

dv/cosim/spike_cosim.cc

@@ -217,6 +217,10 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
   // (If the current step causes a synchronous trap, it will be
   //  recorded against the current pc)
   initial_spike_pc = (processor->get_state()->pc & 0xffffffff);
+  // Debug-mode state the instruction executes in; a trap on a stepped
+  // instruction enters debug mode within this same step, but the cpuctrlsts
+  // flag update is decided by the mode at trap take.
+  bool initial_spike_debug_mode = processor->get_state()->debug_mode;
   processor->step(1);
 
   // ISS
@@ -277,7 +281,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
         return false;
       }
 
-      handle_cpuctrl_exception_entry();
+      handle_cpuctrl_exception_entry(initial_spike_debug_mode);
 
       // This is all the checking possible when consider a
       // synchronously-trapping instruction that never retired.
@@ -533,8 +537,8 @@ void SpikeCosim::leave_nmi_mode() {
 #endif
 }
 
-void SpikeCosim::handle_cpuctrl_exception_entry() {
-  if (!processor->get_state()->debug_mode) {
+void SpikeCosim::handle_cpuctrl_exception_entry(bool debug_mode_at_trap) {
+  if (!debug_mode_at_trap) {
     bool old_sync_exc_seen = change_cpuctrlsts_sync_exc_seen(true);
     if (old_sync_exc_seen) {
       set_cpuctrlsts_double_fault_seen();

dv/cosim/spike_cosim.h

@@ -88,7 +88,7 @@ class SpikeCosim : public simif_t, public Cosim {
 
   bool change_cpuctrlsts_sync_exc_seen(bool flag);
   void set_cpuctrlsts_double_fault_seen();
-  void handle_cpuctrl_exception_entry();
+  void handle_cpuctrl_exception_entry(bool debug_mode_at_trap);
 
   void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
                           uint32_t mhpm_counter_num);

dv/uvm/core_ibex/directed_tests/directed_testlist.yaml

@@ -475,18 +475,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/scall.S
   config: riscv-tests
 
-- test: shamt
+- test: sh-misaligned
   desc: >
-    riscv test - shamt
+    riscv test - sh-misaligned
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S
   config: riscv-tests
 
-- test: sh-misaligned
+- test: shamt
   desc: >
-    riscv test - sh-misaligned
+    riscv test - shamt
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S
   config: riscv-tests
 
 - test: sw-misaligned
@@ -524,6 +524,13 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/divu.S
   config: riscv-tests
 
+- test: mul
+  desc: >
+    riscv test - mul
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S
+  config: riscv-tests
+
 - test: mulh
   desc: >
     riscv test - mulh
@@ -545,13 +552,6 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhu.S
   config: riscv-tests
 
-- test: mul
-  desc: >
-    riscv test - mul
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S
-  config: riscv-tests
-
 - test: rem
   desc: >
     riscv test - rem
@@ -566,25 +566,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/remu.S
   config: riscv-tests
 
-- test: addi
-  desc: >
-    riscv test - addi
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/addi.S
-  config: riscv-tests
-
 - test: add
   desc: >
     riscv test - add
   iterations: 1
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/add.S
   config: riscv-tests
 
-- test: andi
+- test: addi
   desc: >
-    riscv test - andi
+    riscv test - addi
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/andi.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/addi.S
   config: riscv-tests
 
 - test: and
@@ -594,6 +587,13 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/and.S
   config: riscv-tests
 
+- test: andi
+  desc: >
+    riscv test - andi
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/andi.S
+  config: riscv-tests
+
 - test: auipc
   desc: >
     riscv test - auipc
@@ -650,18 +650,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/fence_i.S
   config: riscv-tests
 
-- test: jalr
+- test: jal
   desc: >
-    riscv test - jalr
+    riscv test - jal
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jalr.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jal.S
   config: riscv-tests
 
-- test: jal
+- test: jalr
   desc: >
-    riscv test - jal
+    riscv test - jalr
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jal.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jalr.S
   config: riscv-tests
 
 - test: lb
@@ -706,18 +706,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lw.S
   config: riscv-tests
 
-- test: ori
+- test: or
   desc: >
-    riscv test - ori
+    riscv test - or
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/ori.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/or.S
   config: riscv-tests
 
-- test: or
+- test: ori
   desc: >
-    riscv test - or
+    riscv test - ori
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/or.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/ori.S
   config: riscv-tests
 
 - test: sb
@@ -741,18 +741,25 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/simple.S
   config: riscv-tests
 
+- test: sll
+  desc: >
+    riscv test - sll
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sll.S
+  config: riscv-tests
+
 - test: slli
   desc: >
     riscv test - slli
   iterations: 1
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slli.S
   config: riscv-tests
 
-- test: sll
+- test: slt
   desc: >
-    riscv test - sll
+    riscv test - slt
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sll.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slt.S
   config: riscv-tests
 
 - test: slti
@@ -769,18 +776,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltiu.S
   config: riscv-tests
 
-- test: slt
+- test: sltu
   desc: >
-    riscv test - slt
+    riscv test - sltu
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slt.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltu.S
   config: riscv-tests
 
-- test: sltu
+- test: sra
   desc: >
-    riscv test - sltu
+    riscv test - sra
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltu.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sra.S
   config: riscv-tests
 
 - test: srai
@@ -790,11 +797,11 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srai.S
   config: riscv-tests
 
-- test: sra
+- test: srl
   desc: >
-    riscv test - sra
+    riscv test - srl
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sra.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srl.S
   config: riscv-tests
 
 - test: srli
@@ -804,13 +811,6 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srli.S
   config: riscv-tests
 
-- test: srl
-  desc: >
-    riscv test - srl
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srl.S
-  config: riscv-tests
-
 - test: sub
   desc: >
     riscv test - sub
@@ -825,18 +825,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sw.S
   config: riscv-tests
 
-- test: xori
+- test: xor
   desc: >
-    riscv test - xori
+    riscv test - xor
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xori.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S
   config: riscv-tests
 
-- test: xor
+- test: xori
   desc: >
-    riscv test - xor
+    riscv test - xori
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xori.S
   config: riscv-tests
 
 # Test-suite: riscv-arch-tests

dv/uvm/core_ibex/directed_tests/gen_testlist.py

@@ -432,13 +432,11 @@ def append_directed_testlist(tests, test_suite, test_suite_name, is_assembly):
 # Test-suite: {test_suite_name}
 '''.format(test_suite_name = test_suite_name)
     extension = '.S' if is_assembly else '.c'
-    extension_grep = ' | egrep .S' if is_assembly else ' | egrep .c'
 
     for test_group_name in tests:
-        available_tests = os.popen('ls '+test_suite+test_group_name+extension_grep).read()
-        available_testlist = []
-        for test in available_tests.split('\n')[:-1]:
-            available_testlist.append(test)
+        # Sort the directory listing so the output does not depend on the locale.
+        available_testlist = sorted(f for f in os.listdir(test_suite + test_group_name)
+                                    if f.endswith(extension))
         for test_name_str in available_testlist:
             test_name = test_name_str.split(extension)[0]
             testlist_string = testlist_string + '''
@@ -455,11 +453,8 @@ def append_directed_testlist(tests, test_suite, test_suite_name, is_assembly):
         f.write(testlist_string)
 
 def list_tests(dir):
-    testlist_str = os.popen('ls '+dir).read()
-    testlist = []
-    for test in testlist_str.split('\n')[:-1]:
-        testlist.append(test)
-        print(testlist)
+    testlist = sorted(os.listdir(dir))
+    print(testlist)
     return testlist
 
 def _main() -> int:

dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv

@@ -75,6 +75,9 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
              $sformatf("addi  x%0d, x%0d, 4", cfg.gpr[0], cfg.gpr[0]),
              $sformatf("csrw  0x%0x, x%0d", MEPC, cfg.gpr[0])
              };
+    // The trap dispatcher pushed a kernel-stack frame on entry; a returning
+    // handler must pop it, or every ECALL leaks one frame.
+    pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, cfg.sp, cfg.tp, instr);
     instr.push_back("mret");
     gen_section(get_label("ecall_handler", hart), instr);
   endfunction

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -653,11 +653,11 @@
     +no_ebreak=0
     +no_ecall=0
     +no_branch_jump=0
-    +instr_cnt=10000
+    +instr_cnt=2000
     +no_csr_instr=0
     +randomize_csr=1
     +gen_all_csrs_by_default=1
-    +add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+    +add_csr_write=0x7c0,0x7c1
     +no_fence=0
     +no_wfi=0
     +num_of_sub_program=1

dv/uvm/core_ibex/scripts/directed_test_schema.py

@@ -8,7 +8,7 @@
 import sys
 import pydantic
 import pathlib3x as pathlib
-from typing import List, Any
+from typing import List, Any, Optional
 
 import scripts_lib
 
@@ -52,6 +52,11 @@ class Config:  # noqa
     rtl_test: str
     rtl_params: dict
     timeout_s: pydantic.conint(gt=0)
+    # Optional plusargs appended to the simulator command line. run_rtl.py
+    # already reads 'sim_opts' from the test options for both test types, but
+    # for a directed test the options come from this schema, so without this
+    # field pydantic silently dropped it.
+    sim_opts: Optional[str] = None
 
     # Directed Test Build Options
     gcc_opts: str  # any options that don't specify a path eg. "-O3 -g -static"

dv/uvm/core_ibex/scripts/ibex_cmd.py

@@ -182,8 +182,8 @@ def filter_tests_by_config(cfg: ibex_config.Config,
                         f"rtl_params of {p_val}, which doesn't contain the "
                         f"expected '{config_val}'.")
                     break
-
-                # The test is accepted if we got this far
+            else:
+                # The test is accepted if every parameter matched
                 filtered_test_list.append(test)
 
     return filtered_test_list