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Pull requests: llvm/circt

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Pull requests list

[ImportVerilog] Pass library files to slang
#9680 opened Feb 17, 2026 by rhanqtl Loading…
1
[ImportVerilog] Add dynamic array creation + 'size' and 'length' instructions to the moore dialect
#9679 opened Feb 16, 2026 by yuriyKulinchenko Loading…
[FIRRTL] Support merging layers in LinkCircuits
#9677 opened Feb 14, 2026 by unlsycn Loading…
4
[FIRRTL] Change FInstanceLike to consider multiple referred modules
#9676 opened Feb 14, 2026 by uenoku Loading…
3
[RTG] Add register_to_index and index_to_register ops RTG Involving the `rtg` dialect
#9674 opened Feb 13, 2026 by maerhart Loading…
[LTL][ImportVerilog] Add support for $sampled
#9673 opened Feb 13, 2026 by Arya-Golkari Loading…
[PyRTG] Add instruction decorator RTG Involving the `rtg` dialect
#9671 opened Feb 13, 2026 by maerhart Loading…
[RTG] Immediate & Register to_string RTG Involving the `rtg` dialect
#9670 opened Feb 13, 2026 by maerhart Loading…
[RTG] Support some missing integer operations RTG Involving the `rtg` dialect
#9669 opened Feb 13, 2026 by maerhart Loading…
[PyRTG] Better diagnostics RTG Involving the `rtg` dialect
#9661 opened Feb 12, 2026 by maerhart Loading…
2
[ImportVerilog] Modify sampled value functions to use Comb operators
#9656 opened Feb 12, 2026 by Arya-Golkari Loading…
9
Move ESI runtime tests into pytest suite
#9655 opened Feb 12, 2026 by teqdruid Loading…
1
[HW] Guard bitcast canonicalization against cyclic input (Fixes #9648)
#9649 opened Feb 11, 2026 by m2kar • Draft
3
[MooreToCore] Support supply0/1 Moore
#9635 opened Feb 9, 2026 by rhanqtl Loading…
1
4
[Transforms] FlattenMemRefs: handle resource-backed globals
#9625 opened Feb 6, 2026 by RCoeurjoly • Draft
3
fix: handle global memrefs in flatten-memref pass
#9615 opened Feb 5, 2026 by Abhilekhgautam Loading…
1
1
[HW] Add HW IMDCE pass
#9609 opened Feb 5, 2026 by stomfaig Loading…
5
[Comb] Fix assertion failure in extractConcatToConcatExtract pattern (Fixes #9573)
#9598 opened Feb 3, 2026 by m2kar Loading…
1
10
[Arc] Complete inout support for arcilator path (Fixes #9574)
#9597 opened Feb 3, 2026 by m2kar Loading…
1
4
[circt-verilog] add error message for multiple driver targetting same bits
#9590 opened Feb 2, 2026 by 5iri Loading…
1
2
[LLHD] teach Deseq about projected fields via ValueField keys
#9588 opened Feb 2, 2026 by 5iri Loading…
16
[FIRRTL][NotForCommit] Add ReadDesignConfigInt intrinsic for post-Verilog configuration
#9586 opened Feb 2, 2026 by uenoku • Draft
5
[firtool] Only run verifiers at required points in the pipeline FIRRTL Involving the `firrtl` dialect
#9559 opened Jan 30, 2026 by youngar Loading…
6
Force constant evaluation in slang front-end
#9547 opened Jan 29, 2026 by dinoruic Loading…
4
[Arc] Add Support for Dynamic Strings to the Arcilator Runtime Arc Involving the `arc` dialect
#9546 opened Jan 29, 2026 by KavyaChopra04 Loading…
15
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