ci(faiss): Gate the LVQ/LeanVec examples on the build, not the CPU vendor - #376
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ci(faiss): Gate the LVQ/LeanVec examples on the build, not the CPU vendor#376ahuber21 wants to merge 1 commit into
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ahuber21
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August 25, 2026 09:18
The faiss LVQ/LeanVec tutorials carry no capability gate, so they only run successfully with an LVQ/LeanVec-enabled runtime on Intel hardware. test-faiss.sh inferred that from the CPU vendor alone, which is wrong for the public-only build: the formats are compiled out there, so the examples abort on every runner and that leg was green only when GitHub allocated a non-Intel one. Derive the expectation from ENABLE_LVQ_LEANVEC as well, plumbed into the test job from the same value the artifact was built with, and name the actual reason in the log. The examples still run in that case and must still fail, but now they have to fail with the runtime's storage-kind rejection: a bare nonzero exit also covers a missing library or a segfault, which is not what is under test. Supersedes #314, which keyed off the -public-only artifact name. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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LVQ/LeanVec examples should fail on non-Intel and if lib was built from public sources only. The second part was missing, which lead to test failures on Intel runner with public sources. This PR fixes it.
Supersedes #314, which keyed off the
-public-onlyartifact name and was closed as a sporadic issue.The comment states
This is not correct. We do in fact want a failure. So all good.