arch/arm/stm32n6: Add STM32N6 chip and Nucleo-N657X0-Q board support#18892
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Introduce minimal chip support for the STMicro STM32N6 family
(Cortex-M55, ARMv8.1-M with TrustZone and FPU), sufficient to bring
up an NSH console over USART1.
Scope (deliberately minimal first drop):
- Chip selector ARCH_CHIP_STM32N6 wired into arch/arm/Kconfig and
chip-name mapping ("stm32n6").
- Sub-Kconfig under arch/arm/src/stm32n6 with the STM32N657X0 chip
selector and a single user-selectable USART (USART1).
- Boot path: stm32_start with a naked dispatcher that clears the
boot-ROM MSPLIM/PSPLIM stack limits before any compiler-emitted
prologue, then runs vector relocation and SRAM-only heap init.
The chip runs entirely in the Secure state; SAU is left in its
reset configuration.
- PLL1-based clock tree fed from HSI64 targeting 200 MHz CPU, with
USART1 kernel-clock routed to HSI for a predictable BRR that is
independent of any later clock change.
- Low-level USART driver with full serial framework support.
stm32_serial.c is adapted from arch/arm/src/stm32h5/stm32_serial.c
(sibling ARMv8-M Mainline port with the same USART IP), stripped
of DMA-RX, LPUART, the per-USART2..5 plumbing, RS-485 driver-enable,
TIOCSINVERT/SWAP and HALFDUPLEX paths.
- SysTick system timer.
- GPIO, PWR and RCC helpers.
TrustZone, MPU, I/D-cache and Helium (MVE) are left disabled to
minimise bring-up surface; these will be added in follow-up patches
alongside the drivers that need them.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
Add board support for the STMicro Nucleo-N657X0-Q, sufficient to boot NSH over the on-board ST-LINK virtual COM port (USART1, 115200 8N1) in DEV (serial) boot mode. Two defconfigs are shipped: - nsh: minimal NuttShell prompt. - ostest: nsh + apps/testing/ostest for RTOS smoke testing. Production signed XSPI flash boot is deferred to a follow-up; in DEV mode the image is loaded directly into AXISRAM at 0x34000400 by the host (e.g. STM32CubeProgrammer over ST-LINK), keeping the linker script trivial — .text/.rodata/.data/.bss/.heap all in AXISRAM. Signed-off-by: ImBonkers <samuelnlinden@pm.me>
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Arch: arm
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Awesome! Could you please attach the full OS Test logs? |
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Full |
linguini1
reviewed
May 17, 2026
linguini1
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May 17, 2026
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Looks good to me besides docs comment! Nice work!
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Rewrote the docs, added a photo of the board. |
linguini1
approved these changes
May 17, 2026
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@ImBonkers Could you squash these 2 commits into One Single Commit:
And shorten the Commit Title to "Documentation/arm: Add STM32N6 and Nucleo-N657X0-Q"? Thanks :-) https://github.com/apache/nuttx/actions/runs/26004136077/job/76439720447#step:3:129 |
jerpelea
approved these changes
May 18, 2026
xiaoxiang781216
approved these changes
May 18, 2026
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@ImBonkers please fix https://github.com/apache/nuttx/actions/runs/26004136077/job/76439720447?pr=18892: |
Add documentation for the STMicro STM32N6 chip family and the
Nucleo-N657X0-Q development board introduced in the previous two
commits.
- platforms/arm/stm32n6/index.rst
Chip overview: core, peripherals supported in the initial
port, and a pointer to the board page.
- platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst
Board page, structured per Documentation/contributing/
doc_templates/board.rst: hardware summary, user LED and
button pin map, the two shipped configs (nsh, ostest),
and the DEV-mode flash recipe used to load NuttX into
AXISRAM via ST-LINK.
- platforms/arm/stm32n6/boards/nucleo-n657x0-q/nucleo-n657x0-q.jpg
Photograph of the board, referenced from the board page.
The pages are picked up by the existing glob-based toctree in
Documentation/platforms/arm/index.rst, no parent index changes are
required.
Signed-off-by: ImBonkers <samuelnlinden@pm.me>
Contributor
Author
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Squashed into a single docs commit and shortened the title. |
jerpelea
approved these changes
May 18, 2026
xiaoxiang781216
approved these changes
May 18, 2026
acassis
approved these changes
May 18, 2026
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@ImBonkers Samuel, amazing first PR! Kudos!!! |
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Thank you all for the swift review! |
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Summary
arch/arm/src/stm32n6and new board directoryboards/arm/stm32n6/nucleo-n657x0-q, plus chip and board documentation pages. Three commits:arch/arm/stm32n6: Add STM32N6 chip support.boards/arm/stm32n6/nucleo-n657x0-q: Add Nucleo-N657X0-Q board support.Documentation/platforms/arm: Add STM32N6 chip and Nucleo-N657X0-Q pages.nuttx.bindirectly to AXISRAM at0x34000400.stm32_serial.cis a stripped down version ofarch/arm/src/stm32h5/stm32_serial.c.Impact
Is new feature added? Is existing feature changed? YES
new chip family
stm32n6and new boardnucleo-n657x0-q. No existing feature changed.Impact on user (will user need to adapt to change)? NO
Impact on build (will build process change)? NO
tools/ci/testlist/arm-14.datalready covers this chip via the/arm/stm32n*glob; CMake chip pickup viaadd_subdirectory(${NUTTX_CHIP_ABS_DIR})works without changes toarch/arm/src/CMakeLists.txt.Impact on hardware (will arch(s) / board(s) / driver(s) change)? YES
new chip and new board. No sibling arch or board files modified.
Impact on documentation (is update required / provided)? YES
new files:
Documentation/platforms/arm/stm32n6/index.rstandDocumentation/platforms/arm/stm32n6/boards/nucleo-n657x0-q/index.rst.Impact on security (any sort of implications)? NO
the chip runs in the Secure state with SAU in its reset configuration. No TrustZone Non-Secure programming and no RIF re-configuration.
Impact on compatibility (backward/forward/interoperability)? NO.
Anything else? The three commits each build on their own.
Testing
I confirm that changes are verified on local setup and works as intended:
Build Host: Ubuntu 24.04 x86_64,
arm-none-eabi-gccfrom theghcr.io/apache/nuttx/apache-nuttx-ci-linuxcontainer image (latest tag as of this PR).Target: STM Nucleo-N657X0-Q, flashed via the on-board ST-Link in DEV mode. Configs:
nucleo-n657x0-q:nshandnucleo-n657x0-q:ostest.Reproduction steps:
Testing logs: