[Bug] [RISC-V] PLIC completion before ISR dispatch in non-DM mode #12010

RT-Thread Version

master 5.4.0

Affected area

Architecture / libcpu

Hardware/BSP vendor

Not applicable / Other

Architecture

RISC-V

Board and hardware details

Not applicable / Other

Develop Toolchain

GCC

Describe the bug

In the new RISC-V common port, the non-DM PLIC handler completes the interrupt before dispatching it to the device ISR:

static rt_bool_t handler_plic_irq(int hwirq, void *data)
{
    plic_irq_ack_or_eoi(rt_hw_cpu_id(), hwirq);

    return handler_irq(hwirq, data);
}

For level-triggered interrupts, this may cause the same IRQ to be dispatched again before the device handler clears the interrupt source.

According to the RISC-V PLIC specification, completion normally follows interrupt servicing.

The DM path already handles level-triggered interrupts in this order, with plic_irq_eoi() called after rt_pic_handle_isr().

Would it make sense to adjust the completion order in the non-DM path as well? I noticed that the DM path handles edge-triggered interrupts differently, so I'd appreciate some guidance on the intended behavior here.

Other additional context

• The code is in libcpu/risc-v/common/interrupt.c, introduced by [ARCH/RISC-V] Next RISC-V #10320.
• A similar ordering issue was fixed in the legacy virt64 PLIC driver by [libcpu][risc-v] Fix PLIC interrupt processing order #11305.
• Found while reviewing interrupt handling for an ArtInChip D213 BSP using M-mode without DM.
• This is currently based on code inspection and the PLIC specification; no hardware A/B test has been performed yet.