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…unit test Add scan_output_for_result(lines) to caliptra_runner.py: a standalone function that scans detokenized output lines for a PASS/FAIL sentinel, with no dependency on the emulator subprocess. This is what Task 5's fpga interface will reuse, and it's what makes this file unit-testable in a sandbox with no board/emulator binary available. Add caliptra_runner_test.py covering the no-sentinel, PASS, FAIL, and first-sentinel-wins cases, and wire it into BUILD.bazel as a py_test.
Adds an `elif interface == "fpga":` branch alongside the existing "emulator" branch in load_and_run(). It reads the VCK190_FPGA_HOST env var (FPGA_HOST constant), fails loudly with a non-zero exit if unset, scps the image to the board, invokes launch_openocd.sh over ssh, detokenizes the captured output with the existing pw_tokenizer Detokenizer mechanism, and calls scan_output_for_result() (from Task 4) to decide pass/fail.
Wraps the scp subprocess.run(check=True) call in a try/except so a failed copy (bad host, network down, wrong path) logs a clean _LOG.fatal diagnostic and exits 1 instead of propagating a raw CalledProcessError traceback. Also logs the ssh/launch_openocd.sh subprocess's captured stderr (previously discarded), including it in the "no PASS/FAIL sentinel" fatal message so a real remote failure (auth, missing script, wrong path) is diagnosable from the output instead of being silently swallowed behind a generic error.
- target/veer/BUILD.bazel: add the crate_features select to the console rust_library that entry/config already had, so #[cfg(feature = "fpga")] in console.rs actually compiles in when building for the fpga target_type. Previously the fpga console backend (writing to the FPGA wrapper's debug FIFO) was dead code and fpga images silently kept using the emulator-only UART address. - target/veer/tooling/caliptra_runner.py: in the fpga branch of load_and_run, drop the Detokenizer/detokenize_text call (this target's log backend is log_backend_basic, a plain-text logger, so detokenization was a no-op that only added a hard, unmet ELF-file runfiles dependency causing a FileNotFoundError at runtime) and scan proc.stdout directly instead. Also: print the captured device output so operators get diagnostics on both PASS and FAIL, add a timeout to the remote subprocess.run call with a TimeoutExpired handler (the VeeR core spins forever after signaling its exit sentinel, so an unreachable/stuck board no longer hangs indefinitely), and check proc.returncode so an outright ssh/remote failure is logged distinctly from "board ran but printed nothing". - .bazelrc: forward VCK190_FPGA_HOST into the k_veer test sandbox (Bazel scrubs the test environment by default), matching the existing k_ast1060_evb pattern.
Adds a build-only (no lab hardware needed) CI job that builds //target/veer/unittest_runner:fpga_test under target_type=fpga, so a regression like the console rust_library silently losing its fpga cfg feature (caught by the final review of the fpga-target plan) gets flagged automatically instead of only being visible under bazel aquery. Actually running the test still requires a VCK190 board and is left manual/opt-in.
CI's presubmit format check flagged two lines in the fpga branch that didn't match the repo's formatting style.
rusty1968
marked this pull request as ready for review
September 14, 2026 22:25
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