diff --git a/cortex-m/CHANGELOG.md b/cortex-m/CHANGELOG.md
index 941655ce..91f92098 100644
--- a/cortex-m/CHANGELOG.md
+++ b/cortex-m/CHANGELOG.md
@@ -7,6 +7,22 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Blanket implementation of `interrupt::InterruptNumber` for implementors of new
+  `cortex_m_types::InterruptNumber` trait. This allows NVIC methods to work with both
+  trait implementations.
+
+### Changed
+
+- Old `interrupt::InterruptNumber` trait is marked as deprecated to encourage PACs/HALs
+  to switch to new trait.
+
+### Removed
+
+- `bare_metal::interrupt::Nr` blanket implementation of `InterruptNumber`
+- `Nr` re-export from `interrupt`
+
 ## [v0.7.10] - 2026-10-21
 
 ### Removed
diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml
index 832902d5..995f0119 100644
--- a/cortex-m/Cargo.toml
+++ b/cortex-m/Cargo.toml
@@ -20,6 +20,7 @@ bitfield = "0.13.2"
 eh0 = { package = "embedded-hal", version = "0.2.4" }
 eh1 = { package = "embedded-hal", version = "1.0.0" }
 cortex-m-macros = { path = "macros", version = "=0.7.8" }
+cortex-m-types = { path = "../cortex-m-types", version = "0.1" }
 
 [dependencies.serde]
 version = "1"
diff --git a/cortex-m/src/interrupt.rs b/cortex-m/src/interrupt.rs
index bdf63ded..34bf7ab2 100644
--- a/cortex-m/src/interrupt.rs
+++ b/cortex-m/src/interrupt.rs
@@ -1,12 +1,15 @@
 //! Interrupts
 
-pub use bare_metal::{CriticalSection, Mutex, Nr};
+pub use bare_metal::{CriticalSection, Mutex};
 #[cfg(cortex_m)]
 use core::arch::asm;
 #[cfg(cortex_m)]
 use core::sync::atomic::{Ordering, compiler_fence};
 use cortex_m_macros::asm_cfg;
 
+/// This trait is only here for backwards compatibility. Implement the
+/// cortex_m_types::InterruptNumber trait instead
+///
 /// Trait for enums of external interrupt numbers.
 ///
 /// This trait should be implemented by a peripheral access crate (PAC)
@@ -21,6 +24,10 @@ use cortex_m_macros::asm_cfg;
 /// and must always return the same value (do not change at runtime).
 ///
 /// These requirements ensure safe nesting of critical sections.
+#[deprecated(
+    since = "0.8.0",
+    note = "Implement the cortex_m_types::InterruptNumber trait instead"
+)]
 pub unsafe trait InterruptNumber: Copy {
     /// Return the interrupt number associated with this variant.
     ///
@@ -28,12 +35,17 @@ pub unsafe trait InterruptNumber: Copy {
     fn number(self) -> u16;
 }
 
-/// Implement InterruptNumber for the old bare_metal::Nr trait.
-/// This implementation is for backwards compatibility only and will be removed in cortex-m 0.8.
-unsafe impl<T: Nr + Copy> InterruptNumber for T {
+#[allow(deprecated)]
+unsafe impl<T: cortex_m_types::InterruptNumber> InterruptNumber for T {
     #[inline]
     fn number(self) -> u16 {
-        self.nr() as u16
+        const {
+            assert!(
+                T::MAX_INTERRUPT_NUMBER <= u16::MAX as usize,
+                "interrupt numbers must fit into a u16"
+            )
+        };
+        <Self as cortex_m_types::InterruptNumber>::number(self) as u16
     }
 }
 
diff --git a/cortex-m/src/peripheral/nvic.rs b/cortex-m/src/peripheral/nvic.rs
index 8f0b73d7..ad0cd4a7 100644
--- a/cortex-m/src/peripheral/nvic.rs
+++ b/cortex-m/src/peripheral/nvic.rs
@@ -1,5 +1,8 @@
 //! Nested Vector Interrupt Controller
 
+// NVIC stays on the old trait so that PACs implementing it directly keep working.
+#![allow(deprecated)]
+
 use volatile_register::RW;
 #[cfg(not(armv6m))]
 use volatile_register::{RO, WO};