diff --git a/flow/designs/gf180/gcd/config.mk b/flow/designs/gf180/gcd/config.mk
new file mode 100644
index 0000000000..84640f3d70
--- /dev/null
+++ b/flow/designs/gf180/gcd/config.mk
@@ -0,0 +1,6 @@
+export PLATFORM          = gf180
+export DESIGN_NAME       = gcd
+export VERILOG_FILES     = $(DESIGN_HOME)/src/gcd/gcd.v
+export SDC_FILE          = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
+export CORE_UTILIZATION  = 50
+export PLACE_DENSITY     = 0.70
diff --git a/flow/designs/gf180/gcd/constraint.sdc b/flow/designs/gf180/gcd/constraint.sdc
new file mode 100644
index 0000000000..d23e09c86a
--- /dev/null
+++ b/flow/designs/gf180/gcd/constraint.sdc
@@ -0,0 +1,19 @@
+current_design gcd
+
+set clk_name core_clock
+set clk_port_name clk
+set clk_period 3
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+set clk_io_name vclk_$clk_name
+create_clock -name $clk_io_name -period $clk_period
+set_clock_latency 0.070 [get_clocks $clk_name]
+set_clock_latency 0.070 [get_clocks $clk_io_name]
+
+set non_clock_inputs [all_inputs -no_clocks]
+
+set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_io_name [all_outputs]