From 1c26118f0ec0ebb77eb9d19b0fd771efccfa16be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 26 Oct 2026 22:16:20 +0100 Subject: [PATCH 1/7] tools/OpenROAD: bump to 89e24308eb8f, generate_ram's register-file options MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenROAD #11723 adds the register-file options to generate_ram that AUTO_MEMORIES_REGFILES, in the next commit, asks for. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- tools/OpenROAD | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/OpenROAD b/tools/OpenROAD index bc739caf43..89e24308eb 160000 --- a/tools/OpenROAD +++ b/tools/OpenROAD @@ -1 +1 @@ -Subproject commit bc739caf43047bfc2e225fe10dd968d672b617f8 +Subproject commit 89e24308eb8f6a5662aab79ec77bd6eb1eb510b5 From 1167cce9ac1d5cbf81f8ed63d9e79a1d55ddc34a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 26 Oct 2026 22:16:20 +0100 Subject: [PATCH 2/7] AUTO_MEMORIES_REGFILES: register files of placed standard cells, built by generate_ram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A register file, many ports over few words, is not an SRAM: FakeRAM's single-port model does not describe it, and synthesised to flops its mux trees are placed by a placer that does not know they are an array. AUTO_MEMORIES_REGFILES lists spec files, one per RTL module. memories/regfile_ram.py translates each to OpenROAD generate_ram_netlist options (ports, banks, folds, the zero word, reset, read latency, write style and priority, cells), checks it against the module's ports from synthesis (a stray, missing or mis-sized port stops the build), and writes a wrapper in the module's place around the RAM, _ram: an active-high reset inverted for an active-low flop, addresses narrowed or widened. A register file is inlined unless AUTO_MEMORIES_MACRO_PLACE names it: its cells are then placed, sized and buffered with the rest of the design. A named one is a macro to synthesis and macro placement (an abstract LEF and a liberty of its area beside the FakeRAM views, in blackboxes.txt; a parameterized module's instances lose parameters the netlist does not declare). In `mode netlist` it dissolves into its cells at the end of macro placement (regfile_dissolve.tcl): the core FIRM where the placer put the macro, flipped as it was, row parity kept; the periphery left to global placement and the resizer; then eliminate_dead_logic. `mode macro` keeps it, with pins, a power grid and a timing model from write_timing_model. Where a row holds several words they sit side by side, and a word whose bits would run more than 150 um is folded into more rows: XiangShan's RobEntryFile and RenameBufferFile, dissolved into a parent, did not legalize otherwise (the parent buffers the word's selects inside the full array). A module named in a spec whose memory has an initial value stops the build: generate_ram's storage has none, and the value would be lost without a word. The spec's read_latency, a key shared with structured_gen's specs, is generate_ram's -register_read_address. The RAMs the wrappers instantiate as macros are listed in regfile_cores.txt: they are in blackboxes.txt but no module of the sources, so ORFS's check that every AUTO_MEMORIES module is a black box after read_slang skips them. Needs generate_ram's register-file options, OpenROAD #11723. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- docs/user/AutoMemories.md | 125 ++++ docs/user/FlowVariables.md | 4 + flow/Makefile | 8 +- flow/scripts/macro_place.tcl | 28 + flow/scripts/memories/detect.py | 17 + flow/scripts/memories/detect_test.py | 19 + flow/scripts/memories/gen_memories.py | 222 +++++- flow/scripts/memories/gen_memories_test.py | 47 ++ flow/scripts/memories/regfile_ram.py | 742 +++++++++++++++++++++ flow/scripts/memories/schema.py | 16 +- flow/scripts/regfile_dissolve.tcl | 352 ++++++++++ flow/scripts/synth_preamble.tcl | 67 +- flow/scripts/variables.json | 12 + flow/scripts/variables.yaml | 31 + 14 files changed, 1682 insertions(+), 8 deletions(-) create mode 100644 flow/scripts/memories/regfile_ram.py create mode 100644 flow/scripts/regfile_dissolve.tcl diff --git a/docs/user/AutoMemories.md b/docs/user/AutoMemories.md index d6c9b7aa47..3fe7a9c505 100644 --- a/docs/user/AutoMemories.md +++ b/docs/user/AutoMemories.md @@ -122,6 +122,129 @@ the left edge, alternating horizontal M4 `VDD`/`VSS` straps across the macro (which the platform's PDN macro grid connects to M5), and an `OBS` covering M1 to M4. +## Register files + +A register file, many read and write ports over a few words, is no +SRAM: FakeRAM's single-port model does not describe it, and synthesised +to flops its mux trees are placed by a placer that does not know they +are an array. `AUTO_MEMORIES_REGFILES` lists spec files, one per RTL +module, and OpenROAD's `generate_ram` builds each as an array of placed +standard cells: a flop per bit, its write logic beside it, the read +trees in columns. The spec names the module, its words and bits, its +read and write ports by the module's own port names, and the cells: + +``` +module RegFile +mode netlist +words 16 +bits 8 +clock clock +read io_r0_addr io_r0_data +write io_w0_addr io_w0_data io_w0_en +cell flop DFFHQNx1_ASAP7_75t_R +... +``` + +`memories/regfile_ram.py` translates the spec to `generate_ram_netlist` +options (ports, banks, folds, the zero word, reset, read latency, write +style and priority, cells) and checks it against the module's ports, +from synthesis: a port in one and not the other, or a data port of +another width, stops the build rather than miswire the parent. The RAM +is a block `_ram`, and a wrapper takes the module's place, +connecting the module's ports to the RAM's (an active-high reset +inverted for an active-low flop, an address narrowed or widened). What +happens next depends on `AUTO_MEMORIES_MACRO_PLACE`, the register files +to place as macros: + +- **Not listed (the default): inlined.** Synthesis reads the wrapper + and the RAM's netlist in the module's place; from there on their cells + are placed, sized and buffered with the rest of the design. No macro, + no abstract, no dissolve. The better shape for a small design, where a + macro's outline and channels cost more core than the array saves. +- **Listed: a macro.** `_ram` is a macro to synthesis and macro + placement: its abstract `_ram.lef` and a liberty of its area and + pins land beside the FakeRAM views and it joins `blackboxes.txt`. In + `mode netlist` (the usual one) `generate_ram` places only the array's + core and leaves its periphery (decode, select and input buffers) to + the parent, and the macro dissolves into its cells at the end of macro + placement (`regfile_dissolve.tcl`): the core lands FIRM where the + macro was placed, flipped as the macro was, on the parent's rows; the + periphery is left to global placement and the resizer, and dead logic + is eliminated as at synthesis. `mode macro` keeps the macro to the + end, its pins placed on its edges, a power grid with `VDD`/`VSS` pins + and a timing model from `write_timing_model`. A large design whose + floorplan plans its register files lists them. + +A word holds its value between writes either through a hold mux per +bit (`write_style mux`, the default here) or through one integrated +clock gate per word, enabled by its write selects (`write_style +clock_gate`, `generate_ram`'s own default). Where a row holds more than +one word (`bank_columns`), each word's bits sit side by side, so its +selects and write enables are no longer than its bits; and a word whose +bits would run more than 150 um is folded into more rows. `tap_columns` +and `service_sites` leave empty columns in the array for the buffers a +parent puts on the nets that cross it. + +Listed register files appear in `memories.json` with kind `regfile`; +the rest have kind `fakeram` or `flops`. + +Moving the dissolve into OpenROAD is left for later: it would make it +faster, testable at unit level and maintained with the database it +edits. + +### Designs to measure it on + +What a register file of placed cells buys is a shorter minimum clock +period (the read mux trees are columns, not a cloud) and a shorter +build (fewer cells for synthesis, placement and the resizer to work +on). The ORFS designs whose register file is flip-flops today and its +own module, the seam a spec needs, measured as flops against +`AUTO_MEMORIES_REGFILES`: + +| Design | Module | Today | Shape | Ready? | +|---|---|---|---|---| +| asap7/riscv32i | `regfile` | flip-flops: `reg [31:0] rf[31:0]`, mapped to flops (no AUTO_MEMORIES) | 32 x 32, 2R1W, x0 reads 0 | Yes: the ports are the spec's (`zero_word 0`). Also exercises `OPENROAD_HIERARCHICAL=1` beside two FakeRAM macros. | +| asap7/ibex | `ibex_register_file_ff` | flip-flops: `RegFile = RegFileFF`, the default | 32 x 32, 2R1W, x0 reads 0 | Yes: `unused` names `test_en_i` and `dummy_instr_id_i`, ports the array does not use, and `async_reset rst_ni low` resets the flops to 0 as ibex does; simulated against ibex's RTL. | +| asap7/cva6 | `ariane_regfile` (`ariane_regfile_ff.sv`) | flip-flops: cv32a65x has `FpgaEn` 0 | 32 x 32, 2R1W | Not yet: the ports are packed arrays (`raddr_i[1:0][4:0]`), one port per slice, which a spec cannot yet address; asynchronous reset as ibex. | +| asap7/swerv_wrapper | `dec_gpr_ctl_*` | flip-flops | 32 x 32, 4R3W | Not yet: read enables, bank ids and scan ports around the array need a seam in the RTL. | + +coralnpu's `Regfile` (8R4W) and `FRegfile` (3R2W) carry their +scoreboard and bypass logic in the same module, and picorv32 and +tinyRocket keep their register file inside the CPU module: those need a +seam in their RTL first. + +### Status: at parity on riscv32i, on a smaller core + +riscv32i with its register file generated and inlined (a spec in +`AUTO_MEMORIES_REGFILES`, `zero_word 0`), at riscv32i's own +utilisation, against `designs/asap7/riscv32i`. To global route, 950 ps +clock, minimum period from placement parasitics on the global-route +database: + +| | flops | register file | +|---|---|---| +| minimum period | 950 ps | 943 ps | +| core area | 4 012 um2 | 3 503 um2 | + +Both are limited by the same single-cycle path: the instruction into +the register file's read, the ALU, the data memory and back into the +register file's write. The register file's share of it, decode and read +tree, is about 260 ps in either. + +What did not pay, measured on the same design: + +- the register file as a macro dissolved after macro placement: it does + not fit riscv32i's 62 % beside the four FakeRAMs, and at 55 % it is + 959 ps on a 4 644 um2 core; +- a hold mux per bit instead of the clock gate: 994 ps inlined, every + array endpoint carrying the mux; +- predecoded read selects: 960 ps; +- a tree of 2:1 muxes steered by the address bits instead of a decoded + one-hot read: 959 ps, the address bits' fanout (about 1 000 inputs a + port) needs as many buffer levels as the decode it replaces; +- four-input gates in the read tree, stronger cells: 950 to 954 ps, + within what any change to the placement moves. + ## Platform support **asap7 only.** `gen_memories.py` rejects any other platform. The @@ -183,3 +306,5 @@ bazel-orfs implements this. - [AUTO_MEMORIES](FlowVariables.md#AUTO_MEMORIES) - [ADDITIONAL_MEMORIES](FlowVariables.md#ADDITIONAL_MEMORIES) +- [AUTO_MEMORIES_MACRO_PLACE](FlowVariables.md#AUTO_MEMORIES_MACRO_PLACE) +- [AUTO_MEMORIES_REGFILES](FlowVariables.md#AUTO_MEMORIES_REGFILES) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 8d32a9d6ad..1ae8bae2a2 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -104,6 +104,8 @@ configuration file. | ADDITIONAL_SITES| Passed as -additional_sites to initialize_floorplan.| | | ASAP7_USE_VT| A space separated list of VT options to use with the ASAP7 standard cell library: RVT, LVT, SLVT.| RVT| | AUTO_MEMORIES| Experimental. When set to 1, memories that yosys infers in the RTL (`$mem_v2` cells, module boundary only) are detected pre-synthesis, inventoried in `$(RESULTS_DIR)/memories.json`, and — when idiomatic as an SRAM macro — given generated .lib/.lef views under `$(RESULTS_DIR)/memories/`. Synthesis blackboxes those modules and all later stages read the generated views, so an existing design gets macro-based results without a memory compiler. Supported for the asap7 platform only. See docs/user/AutoMemories.md.| 0| +| AUTO_MEMORIES_MACRO_PLACE| Experimental. Space-separated list of module names of AUTO_MEMORIES_REGFILES register files to place as macros, blackboxed in synthesis and placed by the macro placer (and, in `mode netlist`, dissolved after macro placement). A register file not listed is inlined: its generated netlist of standard cells replaces the module's body in synthesis, and its cells are placed, sized and buffered with the rest of the design -- the better shape for a small design, where a macro's outline and channels cost more core than the array saves. A name no spec builds stops the build. Requires AUTO_MEMORIES=1.| | +| AUTO_MEMORIES_REGFILES| Experimental. Space-separated list of register-file spec files, one per RTL module to build as a register file of placed standard cells rather than synthesise to flops. Each spec names its module, words, bits, read and write ports by the RTL's own port names, and the cells. memories/regfile_ram.py checks the spec against the module's ports and has OpenROAD's generate_ram build it as `_ram`, under `$(RESULTS_DIR)/memories/`, with a wrapper in the module's place. A module named in AUTO_MEMORIES_MACRO_PLACE is blackboxed like an AUTO_MEMORIES macro and placed as one; any other is inlined as its generated netlist. A placed spec in `mode netlist` then dissolves into its cells after macro placement: its core FIRM where the macro was placed, in the macro's orientation, its periphery left to placement. Every register file appears in memories.json with kind `regfile`. Requires AUTO_MEMORIES=1.| | | BALANCE_ROWS| Balance rows during placement.| 0| | BLOCKS| Blocks used as hard macros in a hierarchical flow. Do note that you have to specify block-specific inputs file in the directory mentioned by Makefile.| | | BUFFER_PORTS_ARGS| Specify arguments to the buffer_ports call during placement. Only used if DONT_BUFFER_PORTS=0.| | @@ -347,6 +349,8 @@ configuration file. - [ABC_SCRIPT](#ABC_SCRIPT) - [ADDER_MAP_FILE](#ADDER_MAP_FILE) - [ADDITIONAL_MEMORIES](#ADDITIONAL_MEMORIES) +- [AUTO_MEMORIES_MACRO_PLACE](#AUTO_MEMORIES_MACRO_PLACE) +- [AUTO_MEMORIES_REGFILES](#AUTO_MEMORIES_REGFILES) - [CACHED_REPORTS](#CACHED_REPORTS) - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE) - [DFF_LIB_FILE](#DFF_LIB_FILE) diff --git a/flow/Makefile b/flow/Makefile index 759e13578d..bcef4554d9 100644 --- a/flow/Makefile +++ b/flow/Makefile @@ -279,10 +279,14 @@ do-auto-memories: $(RESULTS_DIR)/memories_inferred.json --yosys-json $(RESULTS_DIR)/memories_inferred.json \ --out-dir $(RESULTS_DIR)/memories \ --json $(RESULTS_DIR)/memories.json \ - $(foreach file,$(ADDITIONAL_MEMORIES),--memories $(file)) + $(foreach file,$(ADDITIONAL_MEMORIES),--memories $(file)) \ + $(foreach file,$(AUTO_MEMORIES_REGFILES),--regfile-spec $(file)) \ + $(foreach m,$(AUTO_MEMORIES_MACRO_PLACE),--macro-place $(m)) \ + $(if $(AUTO_MEMORIES_REGFILES),--openroad $(OPENROAD_EXE)) \ + $(foreach file,$(TECH_LEF) $(SC_LEF),--lef $(file)) $(RESULTS_DIR)/memories.json: $(RESULTS_DIR)/memories_inferred.json $(ADDITIONAL_MEMORIES) \ - $(wildcard $(SCRIPTS_DIR)/memories/*.py) + $(AUTO_MEMORIES_REGFILES) $(wildcard $(SCRIPTS_DIR)/memories/*.py) $(UNSET_AND_MAKE) do-auto-memories yosys-dependencies: $(RESULTS_DIR)/memories.json diff --git a/flow/scripts/macro_place.tcl b/flow/scripts/macro_place.tcl index 0789129e42..556cc30ccc 100644 --- a/flow/scripts/macro_place.tcl +++ b/flow/scripts/macro_place.tcl @@ -3,10 +3,38 @@ erase_non_stage_variables floorplan load_design 2_1_floorplan.odb 2_1_floorplan.sdc source_step_tcl PRE MACRO_PLACE +# A register file in `mode netlist` dissolves onto the parent's rows +# after macro placement, and the rows are then cut MACRO_ROWS_HALO_X/Y +# around every other macro: a halo that wide keeps them off its core, +# which fills its outline to the edge. +set regfile_list "$::env(RESULTS_DIR)/memories/regfiles.txt" +if { [env_var_equals AUTO_MEMORIES 1] && [file exists $regfile_list] } { + set f [open $regfile_list r] + set regfile_masters [split [string trim [read $f]] "\n"] + close $f + set dbu [[ord::get_db_tech] getDbUnitsPerMicron] + set halo {} + foreach v {MACRO_ROWS_HALO_X MACRO_ROWS_HALO_Y} { + set um [expr { [env_var_exists_and_non_empty $v] ? $::env($v) : 0 }] + lappend halo [expr { round($um * $dbu) }] + } + lassign $halo x y + foreach inst [[ord::get_db_block] getInsts] { + if { [[$inst getMaster] getName] in $regfile_masters } { + # the instance's own halo, left bottom right top, which the macro + # placer keeps clear of other macros + odb::dbBox_create $inst $x $y $x $y + } + } +} + source $::env(SCRIPTS_DIR)/macro_place_util.tcl source_step_tcl POST MACRO_PLACE +# register files in `mode netlist` become their cells +source $::env(SCRIPTS_DIR)/regfile_dissolve.tcl + report_design_area orfs_write_db $::env(RESULTS_DIR)/2_2_floorplan_macro.odb diff --git a/flow/scripts/memories/detect.py b/flow/scripts/memories/detect.py index 2343350429..83ab8ce65f 100644 --- a/flow/scripts/memories/detect.py +++ b/flow/scripts/memories/detect.py @@ -305,6 +305,23 @@ def scan_yosys_json( return dedupe(out) +def initialized_modules(data: dict | str | Path, top: str | None = None) -> set[str]: + """Modules holding a memory with an initial value: a $mem_v2 whose INIT + has a 0 or 1 bit (yosys writes an uninitialized memory's INIT as x).""" + if isinstance(data, (str, Path)): + data = json.loads(Path(data).read_text()) + out = set() + for mod_name, mod_info in data.get("modules", {}).items(): + name = mod_name[1:] if mod_name.startswith("\\") else mod_name + for cell in mod_info.get("cells", {}).values(): + if cell.get("type", "") not in ("$mem_v2", "$mem"): + continue + init = str(cell.get("parameters", {}).get("INIT", "")) + if "0" in init or "1" in init: + out.add(definition_name(name, top)) + return out + + def definition_name(module: str, top: str | None) -> str: """`array_64x114$top.u0` -> `array_64x114` for top module `top`. diff --git a/flow/scripts/memories/detect_test.py b/flow/scripts/memories/detect_test.py index c1f70e0ef7..dd5940b216 100644 --- a/flow/scripts/memories/detect_test.py +++ b/flow/scripts/memories/detect_test.py @@ -270,5 +270,24 @@ def test_inline_array_with_other_logic_is_named_per_cell(self): self.assertEqual([m.name for m in mems], ["am_regs.Memory"]) +class InitializedModulesTest(unittest.TestCase): + def test_only_a_memory_with_a_0_or_1_bit_is_initialized(self): + def module(init): + params = {"SIZE": 2, "WIDTH": 2, "RD_PORTS": 1, "WR_PORTS": 1} + if init is not None: + params["INIT"] = init + return {"cells": {"\\m": {"type": "$mem_v2", "parameters": params}}} + + data = { + "modules": { + "\\none": module(None), + "\\all_x": module("xxxx"), + "\\zeros": module("0000"), + "\\some$top.u0": module("xx1x"), + } + } + self.assertEqual(detect.initialized_modules(data, "top"), {"zeros", "some"}) + + if __name__ == "__main__": unittest.main() diff --git a/flow/scripts/memories/gen_memories.py b/flow/scripts/memories/gen_memories.py index 98e3febea6..67f7bfc383 100644 --- a/flow/scripts/memories/gen_memories.py +++ b/flow/scripts/memories/gen_memories.py @@ -10,6 +10,14 @@ /.lib Liberty view per converted memory /_pre_layout.lib ideal-clock variant for pre-CTS consumers /.lef abstract LEF per converted memory + /regfiles.txt register files to dissolve into their cells + after macro placement (`mode netlist`) + /inline.txt register files whose generated netlist + replaces their module in synthesis (those + not in AUTO_MEMORIES_MACRO_PLACE) + /regfile_cores.txt the RAMs those wrappers instantiate as + macros: in blackboxes.txt, but no module of + the sources, so not there after read_slang /blackboxes.txt ` ` per line, area in um^2 as the .lib states it — what synthesis blackboxes and the cost it gives each @@ -21,6 +29,8 @@ from __future__ import annotations import argparse +import json +import re import sys from pathlib import Path @@ -30,11 +40,160 @@ import detect # noqa: E402 import idiomatic # noqa: E402 +import regfile_ram # noqa: E402 import schema # noqa: E402 FAKERAM_RUN_PY = Path(__file__).resolve().parents[3] / "tools/FakeRAM2.0/run.py" +def _spec_module(spec: Path) -> str: + """The `module ` line of a register-file spec.""" + for line in spec.read_text().splitlines(): + parts = line.split("#", 1)[0].split() + if len(parts) == 2 and parts[0] == "module": + return parts[1] + raise SystemExit(f"gen_memories: {spec}: no `module` line") + + +def _spec_value(spec: Path, key: str) -> list[list[str]]: + """Every `key ...` line of a register-file spec, as word lists.""" + out = [] + for line in spec.read_text().splitlines(): + parts = line.split("#", 1)[0].split() + if parts and parts[0] == key: + out.append(parts[1:]) + return out + + +def _spec_mode(spec: Path) -> str: + """`mode macro` (the default) or `mode netlist` of a register-file spec.""" + for line in spec.read_text().splitlines(): + parts = line.split("#", 1)[0].split() + if len(parts) == 2 and parts[0] == "mode": + if parts[1] not in ("macro", "netlist"): + raise SystemExit( + f"gen_memories: {spec}: mode is macro or netlist, not {parts[1]}" + ) + return parts[1] + return "macro" + + +def _lib_area(lib: Path) -> str: + """The cell area `lib` states, in um^2: what blackboxes.txt gives a + register file beside its name, as FakeRAM does for its macros.""" + m = re.search(r"^\s*area\s*:\s*([0-9.eE+-]+)\s*;", lib.read_text(), re.M) + if not m: + raise SystemExit(f"gen_memories: {lib} states no area") + return m.group(1) + + +def _regfile_memory(spec: Path, module: str, reason: str) -> schema.Memory: + """A register file's memories.json record, its shape from its spec.""" + mem = schema.Memory(name=module, kind="regfile", source="listed", spec=str(spec)) + words = _spec_value(spec, "words") + bits = _spec_value(spec, "bits") + mem.rows = int(words[0][0]) if words else 0 + mem.bits = int(bits[0][0]) if bits else 0 + mem.read_ports = len(_spec_value(spec, "read")) + len( + _spec_value(spec, "read_banked") + ) + mem.write_ports = len(_spec_value(spec, "write")) + mem.reason = reason + return mem + + +def run_regfiles( + specs: list[Path], + openroad: str | None, + lefs: list[Path], + out_dir: Path, + macro_place: list[str] | None = None, +) -> list[schema.Memory]: + """Generate every listed register file with OpenROAD's generate_ram, + through regfile_ram.py: a wrapper in the RTL module's place connects + its ports to the generated RAM's. + + A register file not named in AUTO_MEMORIES_MACRO_PLACE is inlined: its + generated netlist replaces the module's body in synthesis (inline.txt), + and from there on its cells are placed, sized and buffered with the + rest of the design. No macro, no abstract, no dissolve: the best shape + for a small design, where a macro's outline and channels cost more + core than the array saves. + + A register file named in AUTO_MEMORIES_MACRO_PLACE is a macro to + synthesis and to macro placement: its + abstract LEF and model liberty land beside the FakeRAM views and the + module joins blackboxes.txt. In `mode netlist` it then dissolves into + its placed cells after macro placement (regfile_dissolve.tcl), which + reads its structural netlist and the placement of its core + (.v, .place) and finds it in regfiles.txt. A spec whose ports + are not the module's stops the build here rather than miswire the + parent. + """ + macro_place = set(macro_place or []) + if not specs: + (out_dir / "regfiles.txt").write_text("") + (out_dir / "inline.txt").write_text("") + (out_dir / "regfile_cores.txt").write_text("") + if macro_place: + raise SystemExit( + "gen_memories: AUTO_MEMORIES_MACRO_PLACE names " + + " ".join(sorted(macro_place)) + + " but AUTO_MEMORIES_REGFILES lists no register file" + ) + return [] + if not openroad: + raise SystemExit( + "gen_memories: AUTO_MEMORIES_REGFILES is set but OPENROAD_EXE is not" + ) + if not lefs: + raise SystemExit( + "gen_memories: AUTO_MEMORIES_REGFILES needs TECH_LEF and SC_LEF" + ) + modules = [_spec_module(spec) for spec in specs] + unknown = sorted(macro_place - set(modules)) + if unknown: + raise SystemExit( + "gen_memories: AUTO_MEMORIES_MACRO_PLACE names " + + " ".join(unknown) + + ", which no AUTO_MEMORIES_REGFILES spec builds; it lists " + + " ".join(modules) + ) + memories = [] + dissolve = [] + cores = [] + inline = [] + for spec, module in zip(specs, modules): + mode = _spec_mode(spec) + # the RTL module's place taken by a wrapper around the RAM + shape = mode if module in macro_place else "inline" + regfile_ram.check(spec) + ram = regfile_ram.generate(spec, module, shape, openroad, lefs, out_dir) + memories.append( + _regfile_memory(spec, module, f"register file, generate_ram, {shape}") + ) + inline.append(module) + if ram["macro"]: + cores.append(ram["block"]) + if ram["dissolve"]: + dissolve.append(ram["block"]) + sys.stderr.write( + f"gen_memories: {module} -> register file, generate_ram, " + f"{shape} ({spec.name})\n" + ) + with (out_dir / "blackboxes.txt").open("a") as f: + f.write( + "".join( + f"{name} {_lib_area(out_dir / f'{name}.lib')}\n" + for name in [m.name for m in memories if m.name not in inline] + cores + ) + ) + (out_dir / "regfiles.txt").write_text("".join(f"{m}\n" for m in dissolve)) + (out_dir / "inline.txt").write_text("".join(f"{m}\n" for m in inline)) + (out_dir / "regfile_cores.txt").write_text("".join(f"{m}\n" for m in cores)) + return memories + + def run( yosys_json: Path, memories_files: list[Path], @@ -42,6 +201,10 @@ def run( out_dir: Path, json_path: Path, top: str | None = None, + regfile_specs: list[Path] | None = None, + openroad: str | None = None, + lefs: list[Path] | None = None, + macro_place: list[str] | None = None, ) -> int: if platform != "asap7": sys.stderr.write(f"gen_memories: unsupported platform {platform}\n") @@ -49,12 +212,29 @@ def run( found = detect.scan_yosys_json(yosys_json, top) + # generate_ram builds storage with no initial value: a register file + # with one would lose it without a word + initialized = detect.initialized_modules(yosys_json, top) + for spec in regfile_specs or []: + module = _spec_module(spec) + if module in initialized: + raise SystemExit( + f"gen_memories: {module} ({spec}) has a memory with an initial " + "value, which a register file from generate_ram does not " + "have; remove it from AUTO_MEMORIES_REGFILES" + ) + idiomatic.apply(found) overrides: list[schema.Memory] = [] for path in memories_files: overrides.extend(schema.load(path)) memories = schema.merge(found, overrides) + override_names = {o.name for o in overrides} + for mem in memories: + mem.kind = "fakeram" if mem.idiomatic else "flops" + if mem.name in override_names: + mem.source = "override" out_dir.mkdir(parents=True, exist_ok=True) json_path.parent.mkdir(parents=True, exist_ok=True) @@ -75,8 +255,18 @@ def run( ] ) + # After FakeRAM has written blackboxes.txt for the inferred memories, + # and recorded in memories.json beside them. + regfiles = run_regfiles( + regfile_specs or [], openroad, lefs or [], out_dir, macro_place + ) + if regfiles: + listed = {m.name for m in regfiles} + memories = [m for m in memories if m.name not in listed] + regfiles + schema.dump(memories, json_path, platform) + for mem in sorted(memories, key=lambda m: m.name): - verdict = "macro" if mem.idiomatic else "flops" + verdict = mem.kind sys.stderr.write( f"gen_memories: {mem.name} {mem.rows}x{mem.bits} " f"R={mem.read_ports} W={mem.write_ports} RW={mem.rw_ports} " @@ -103,6 +293,32 @@ def main(argv: list[str] | None = None) -> int: help="User-supplied .memories file merged onto the " "detected set (repeatable).", ) + p.add_argument( + "--regfile-spec", + action="append", + default=[], + type=Path, + help="Register-file spec, AUTO_MEMORIES_REGFILES (repeatable).", + ) + p.add_argument( + "--openroad", + default=None, + help="The openroad that runs generate_ram (OPENROAD_EXE).", + ) + p.add_argument( + "--lef", + action="append", + default=[], + type=Path, + help="Technology and cell LEF for the generator (repeatable).", + ) + p.add_argument( + "--macro-place", + action="append", + default=[], + help="A register file placed as a macro, AUTO_MEMORIES_MACRO_PLACE " + "(repeatable); the others are inlined.", + ) p.add_argument("--platform", required=True) p.add_argument( "--out-dir", @@ -129,6 +345,10 @@ def main(argv: list[str] | None = None) -> int: args.out_dir, args.json, args.top, + args.regfile_spec, + args.openroad, + args.lef, + args.macro_place, ) diff --git a/flow/scripts/memories/gen_memories_test.py b/flow/scripts/memories/gen_memories_test.py index e71aed7844..1596ae5e11 100644 --- a/flow/scripts/memories/gen_memories_test.py +++ b/flow/scripts/memories/gen_memories_test.py @@ -114,9 +114,12 @@ def test_flow_contract(self): sorted(p.name for p in mems_dir.iterdir()), [ "blackboxes.txt", + "inline.txt", "mem_128x32.lef", "mem_128x32.lib", "mem_128x32_pre_layout.lib", + "regfile_cores.txt", + "regfiles.txt", ], ) # one ` ` line; the area is the one the .lib states, @@ -224,6 +227,50 @@ def test_no_memories_still_writes_contract_files(self): self.assertEqual(code, 0) self.assertEqual(json.loads((d / "memories.json").read_text())["memories"], []) self.assertEqual((d / "memories" / "blackboxes.txt").read_text(), "") + self.assertEqual((d / "memories" / "regfiles.txt").read_text(), "") + self.assertEqual((d / "memories" / "inline.txt").read_text(), "") + self.assertEqual((d / "memories" / "regfile_cores.txt").read_text(), "") + + def test_regfile_area_is_the_lib_cell_area(self): + # a register file's blackboxes.txt line carries the area its + # generated .lib states, as FakeRAM's do + with tempfile.TemporaryDirectory() as d: + lib = Path(d) / "RegFile.lib" + lib.write_text( + "library (RegFile) {\n cell (RegFile) {\n" + " area : 153.527400;\n }\n}\n" + ) + self.assertEqual(gen_memories._lib_area(lib), "153.527400") + + def test_regfile_lib_without_area_fails(self): + with tempfile.TemporaryDirectory() as d: + lib = Path(d) / "RegFile.lib" + lib.write_text("library (RegFile) {\n cell (RegFile) {\n }\n}\n") + with self.assertRaises(SystemExit): + gen_memories._lib_area(lib) + + def test_initialized_register_file_stops(self): + # a spec naming a module whose memory has an initial value stops: + # generate_ram's storage has none, and the value would be lost + d = Path(self.tmp.name) + netlist = json.loads(json.dumps(SAMPLE_YOSYS_NETLIST)) + cell = netlist["modules"]["\\cache_tags"]["cells"]["\\$mem_0"] + cell["parameters"]["INIT"] = "x" * 75 + "01" * 12 + "1" + netlist_json = d / "memories_inferred.json" + netlist_json.write_text(json.dumps(netlist)) + spec = d / "cache_tags.regfile" + spec.write_text("module cache_tags\n") + with self.assertRaises(SystemExit) as stop: + gen_memories.run( + netlist_json, + [], + "asap7", + d / "memories", + d / "memories.json", + regfile_specs=[spec], + ) + self.assertIn("cache_tags", str(stop.exception)) + self.assertIn("initial value", str(stop.exception)) if __name__ == "__main__": diff --git a/flow/scripts/memories/regfile_ram.py b/flow/scripts/memories/regfile_ram.py new file mode 100644 index 0000000000..1eac6d18c0 --- /dev/null +++ b/flow/scripts/memories/regfile_ram.py @@ -0,0 +1,742 @@ +"""AUTO_MEMORIES_REGFILES through OpenROAD's generate_ram. + +A register-file spec (KEYS below) is translated to +generate_ram_netlist's options, and the generated RAM, a block named +_ram, stands in for the RTL module through a wrapper written in +the module's place: its ports, from the design's yosys JSON, connected +to generate_ram's (clk, rst_n, D0, we0, addr_w0, addr_r0, Q0, ...), an +active-high reset inverted for an active-low flop. The wrapper is +always inlined; the RAM is + +- inlined: its netlist follows the wrapper in .v; +- mode netlist: a macro with its periphery unplaced, which + regfile_dissolve.tcl dissolves after macro placement from + _ram.v (one instance a line) and _ram.place; +- mode macro: a macro kept to the end. + +The flops take the RTL's names where the spec gives them (store_name, +read_reg_name), for equivalence checking: renamed in the database from +generate_ram's own. With `periphery verilog` generate_ram writes the +periphery as a Verilog module, _ram, around the core, +_ram_core, which is then what is inlined or the macro. A macro +kept to the end (mode macro) gets its pins from OpenROAD's pin placer on +the spec's pin layers, its liberty from write_timing_model and its +power from rails on its rows and straps with the VDD and VSS pins +(power_rails, power_layer, power_width, power_pitch, power_offset; +asap7's by default). +""" + +from __future__ import annotations + +import json +import math +import os +import re +import subprocess +from pathlib import Path + +# the longest a word's bits may run in a row before it is folded, um +WORD_SPAN_UM = 150 + +# the keys a spec may have: a misspelt one is refused, not ignored +KEYS = { + "module", + "mode", + "words", + "bits", + "clock", + "read", + "read_banked", + "write", + "write_priority", + "write_style", + "zero_word", + "banks", + "bank_columns", + "bank_order", + "bank_column_layout", + "read_latency", + "bit_folds", + "async_reset", + "reset", + "unused", + "store_name", + "read_reg_name", + "cell", + "periphery", + "pin_layer", + "pin_layer_h", + "pin_layer_v", + "tap_columns", + "service_sites", + "power_rails", + "power_rail_width", + "power_layer", + "power_width", + "power_pitch", + "power_offset", +} + +# a spec's `cell ` roles, as generate_ram's -cells names them +CELL_ROLES = { + "inv": "inv", + "and2": "and2", + "or2": "or2", + "ao22": "ao22", + "aoi22": "aoi22", + "nand2": "nand2", + "nor2": "nor2", + "icg": "clock_gate", + "tie_hi": "tie", + "buffer": "buffer", +} + + +# AUTO_MEMORIES is asap7's +DEFAULT_CELLS = { + "aoi22": "AOI22xp5_ASAP7_75t_R", + "nand2": "NAND2xp5_ASAP7_75t_R", + "nor2": "NOR2x1_ASAP7_75t_R", + "buffer": "BUFx2_ASAP7_75t_R", +} + + +def parse(spec: Path) -> list[list[str]]: + """The spec's lines as [key, value, ...], comments and blanks out.""" + lines = [] + for line in spec.read_text().splitlines(): + words = line.split("#", 1)[0].split() + if words: + lines.append(words) + return lines + + +def _values(lines: list[list[str]], key: str) -> list[list[str]]: + return [line[1:] for line in lines if line[0] == key] + + +def _one(lines: list[list[str]], key: str, default: str = "") -> str: + values = _values(lines, key) + return values[-1][0] if values and values[-1] else default + + +def check(spec: Path) -> None: + """Refuse a spec with a key this translation does not read.""" + for line in parse(spec): + if line[0] not in KEYS: + raise SystemExit(f"regfile_ram: {spec}: unknown key `{line[0]}`") + + +def _address_bits(words: int) -> int: + return max(1, math.ceil(math.log2(words))) + + +def _args(lines: list[list[str]], block: str, shape: str) -> list[str]: + """generate_ram_netlist's options for the spec.""" + words = int(_one(lines, "words")) + bits = int(_one(lines, "bits")) + folds = int(_one(lines, "bit_folds", "1")) + cells = {line[1]: line[2] for line in lines if line[0] == "cell"} + async_reset = _values(lines, "async_reset") + storage = cells.get("flop_r" if async_reset else "flop") + args = [ + "-name", + block, + "-mask_size", + str(-(-bits // folds)), + "-word_size", + str(bits), + "-num_words", + str(words), + "-r_ports", + str(len(_values(lines, "read"))), + "-w_ports", + str(len(_values(lines, "write"))), + "-write_style", + _one(lines, "write_style", "mux"), + # a balanced AND2 tree per word: the row decoder's chain is + # slower on a register file's read path + "-decoder", + "word", + ] + if len(_values(lines, "write")) > 1: + # two ports writing one word in a cycle: OR their data by + # default, as firtool's register files do + args += ["-write_priority", _one(lines, "write_priority", "or")] + if int(_one(lines, "bank_columns", "1")) > 1 and not _values( + lines, "bank_column_layout" + ): + # a row's words each contiguous: interleaved, a word's selects and + # write enables run the whole row (XiangShan's RobEntryFile: 6,483 + # slew violations in a parent, against 608) + args += ["-bank_column_layout", "contiguous"] + if storage: + args += ["-storage_cell", storage] + if folds > 1: + # a word's bits in folds rows, a slice each + args += ["-bit_folds", str(folds)] + if _values(lines, "read_banked"): + args += ["-rb_ports", str(len(_values(lines, "read_banked")))] + for key in ( + "zero_word", + "banks", + "bank_columns", + "bank_order", + "bank_column_layout", + ): + if _values(lines, key): + args += [f"-{key}", _one(lines, key)] + # the spec's read_latency, a key shared with structured_gen's specs, + # is generate_ram's read address register + if _values(lines, "read_latency"): + args += ["-register_read_address", _one(lines, "read_latency")] + if async_reset: + args += ["-reset_value", "0"] + # asap7 cells where the spec names none, and a buffer for the select + # buffers (the smallest asap7 buffer is the hold buffer HB1xp67) + cells = DEFAULT_CELLS | cells + roles = [ + f"{CELL_ROLES[role]} {master}" + for role, master in cells.items() + if role in CELL_ROLES + ] + if roles: + args += ["-cells", "{" + " ".join(roles) + "}"] + # service columns: `service_sites` empty sites after + # every `tap_columns` storage columns, room for a parent's buffers in + # the array; 40 by default in a macro kept to the end, else none + sites = int(_one(lines, "service_sites", "40" if shape == "macro" else "0")) + if sites > 0: + every = _one(lines, "tap_columns", "8") + args += ["-service_columns", f"{{{every} {sites}}}"] + if _one(lines, "periphery") == "verilog": + args += ["-periphery", "verilog", "-pin_layer", _one(lines, "pin_layer", "M4")] + elif shape == "netlist": + args += ["-periphery", "unplaced", "-pin_layer", _one(lines, "pin_layer", "M4")] + return args + + +# The second session's Tcl: the generated block's ports, and for a macro +# its views, from its database. +_VIEWS_TCL = r""" +set block [ord::get_db_block] +set f [open {out}/{block}.ports w] +foreach term [$block getBTerms] {{ + if {{[$term getSigType] in {{POWER GROUND}}}} {{ continue }} + puts $f "[$term getName] [$term getIoType]" +}} +close $f +""" + +_MACRO_TCL = r""" +# the netlist, one instance a line, as regfile_dissolve.tcl reads it +set f [open {out}/{block}.v w] +foreach inst [$block getInsts] {{ + set conns {{}} + foreach it [$inst getITerms] {{ + set net [$it getNet] + if {{$net eq "NULL" || [$net getSigType] in {{POWER GROUND}}}} {{ continue }} + lappend conns ".[[$it getMTerm] getName](\\[$net getName] )" + }} + puts $f "[[$inst getMaster] getName] \\[$inst getName] ([join $conns {{, }}]);" +}} +close $f +# where each placed cell is, as the generator laid it out +set f [open {out}/{block}.place w] +foreach inst [$block getInsts] {{ + if {{![$inst isPlaced]}} {{ continue }} + lassign [$inst getLocation] x y + puts $f "[$inst getName] $x $y [$inst getOrient]" +}} +close $f +write_abstract_lef {out}/{block}.lef +# a liberty of its area and pins: a blackbox to synthesis +set dbu [[ord::get_db_tech] getDbUnitsPerMicron] +set die [$block getDieArea] +set area [expr {{double([$die dx]) / $dbu * [$die dy] / $dbu}}] +set f [open {out}/{block}.lib w] +puts $f "library({block}) {{" +puts $f " delay_model : table_lookup;" +puts $f " time_unit : \"1ns\";" +puts $f " voltage_unit : \"1V\";" +puts $f " current_unit : \"1uA\";" +puts $f " leakage_power_unit : \"1uW\";" +puts $f " capacitive_load_unit (1,pf);" +puts $f " pulling_resistance_unit : \"1kohm\";" +set buses [dict create] +foreach term [$block getBTerms] {{ + if {{[$term getSigType] in {{POWER GROUND}}}} {{ continue }} + set name [$term getName] + set dir [expr {{[$term getIoType] eq "INPUT" ? "input" : "output"}}] + if {{[regexp {{^(.*)\[(\d+)\]$}} $name -> base index]}} {{ + set hi [expr {{[dict exists $buses $base] ? max([lindex [dict get $buses $base] 1], $index) : $index}}] + dict set buses $base [list $dir $hi] + }} else {{ + dict set buses $name [list $dir -1] + }} +}} +set widths {{}} +dict for {{name info}} $buses {{ + set hi [lindex $info 1] + if {{$hi >= 0 && [lsearch $widths [expr {{$hi + 1}}]] < 0}} {{ lappend widths [expr {{$hi + 1}}] }} +}} +foreach w $widths {{ + puts $f " type ({block}_bus_$w) {{ base_type : array; data_type : bit; bit_width : $w; bit_from : [expr {{$w - 1}}]; bit_to : 0; downto : true; }}" +}} +puts $f " cell({block}) {{" +puts $f " area : $area;" +puts $f " is_macro_cell : true;" +puts $f " dont_touch : true;" +dict for {{name info}} $buses {{ + lassign $info dir hi + if {{$hi < 0}} {{ + puts $f " pin($name) {{ direction : $dir; capacitance : 0.001; }}" + }} else {{ + puts $f " bus($name) {{ bus_type : {block}_bus_[expr {{$hi + 1}}]; direction : $dir; capacitance : 0.001; }}" + }} +}} +puts $f " }}" +puts $f "}}" +close $f +""" + + +def _word_at(lines: list[list[str]], row: int, w: int) -> int: + """The word generate_ram (-decoder word) puts at (row, word in the + row): RamGen::wordAt.""" + words = int(_one(lines, "words")) + banks = int(_one(lines, "banks", "1")) + columns = int(_one(lines, "bank_columns", "1")) + per_bank = words // banks + bank = (row // per_bank) * columns + w + i = row % per_bank + if _one(lines, "bank_order", "contiguous") == "interleaved": + return i * banks + bank + return bank * per_bank + i + + +def _renames(lines: list[list[str]]) -> list[tuple[str, str]]: + """generate_ram's flop names to the spec's store_name and + read_reg_name, the RTL's names for equivalence checking.""" + renames = [] + words = int(_one(lines, "words")) + bits = int(_one(lines, "bits")) + columns = int(_one(lines, "bank_columns", "1")) + store = _one(lines, "store_name") + per_fold = bits // int(_one(lines, "bit_folds", "1")) + if store: + for row in range(words // columns): + for w in range(columns): + word = _word_at(lines, row, w) + if word == int(_one(lines, "zero_word", "-1")): + continue + for bit in range(bits): + renames.append( + ( + f"storage_{row}_{w}_{bit // per_fold * per_fold}" + f".bit{bit}.bit", + store.replace("{word}", str(word)).replace( + "{bit}", str(bit) + ), + ) + ) + reg = _one(lines, "read_reg_name") + # (with the periphery as Verilog the address registers are in the + # wrapper, under generate_ram's names) + if ( + reg + and _one(lines, "read_latency", "0") != "0" + and _one(lines, "periphery") != "verilog" + ): + banks = int(_one(lines, "banks", "1")) + a = _address_bits(words) + ab = _address_bits(words // banks) + # generate_ram's ports: writes, then plain reads, then each banked + # read port's banks; the spec's read ports, plain and banked, in + # the order it lists them + first_read = len(_values(lines, "write")) + plain = len(_values(lines, "read")) + spec_port = 0 + plain_seen = 0 + banked_seen = 0 + for line in lines: + if line[0] == "read": + p = first_read + plain_seen + plain_seen += 1 + for i in range(a): + renames.append( + ( + f"decoder_p{p}.addr_reg_p{p}_a{i}", + reg.replace("{port}", str(spec_port)) + .replace("{bank}", "0") + .replace("{bit}", str(i)), + ) + ) + spec_port += 1 + elif line[0] == "read_banked": + for b in range((len(line) - 1) // 2): + p = first_read + plain + banked_seen * banks + b + for i in range(ab): + renames.append( + ( + f"decoder_p{p}.addr_reg_p{p}_a{i}", + reg.replace("{port}", str(spec_port)) + .replace("{bank}", str(b)) + .replace("{bit}", str(i)), + ) + ) + banked_seen += 1 + spec_port += 1 + return renames + + +def _module_ports(yosys_json: Path, module: str) -> dict[str, tuple[str, int]]: + """The RTL module's ports, name -> (direction, width), from the + design's yosys JSON; empty where it does not have the module.""" + if not yosys_json.exists(): + return {} + modules = json.loads(yosys_json.read_text()).get("modules", {}) + for name, body in modules.items(): + if name.lstrip("\\") == module: + return { + port: (info["direction"], len(info["bits"])) + for port, info in body.get("ports", {}).items() + } + return {} + + +def _buses(port_lines: list[str]) -> dict[str, tuple[str, int]]: + """generate_ram's ports, base name -> (direction, width).""" + buses: dict[str, tuple[str, int]] = {} + for line in port_lines: + name, io = line.split() + base, width = name, 1 + if name.endswith("]") and "[" in name: + base = name[: name.rindex("[")] + width = int(name[name.rindex("[") + 1 : -1]) + 1 + direction = "input" if io == "INPUT" else "output" + old = buses.get(base, (direction, 0))[1] + buses[base] = (direction, max(old, width)) + return buses + + +def _wrapper( + lines: list[list[str]], + module: str, + block: str, + ram_ports: dict[str, tuple[str, int]], + rtl_ports: dict[str, tuple[str, int]], +) -> str: + """The module the RTL's stands in for: its ports to generate_ram's.""" + words = int(_one(lines, "words")) + bits = int(_one(lines, "bits")) + banks = int(_one(lines, "banks", "1")) + conns: dict[str, str] = {} + widths: dict[str, tuple[str, int]] = {} + + def port(name: str, direction: str, width: int) -> str: + widths.setdefault(name, rtl_ports.get(name, (direction, width))) + return name + + def fit(name: str, width: int) -> str: + """An RTL address as wide as generate_ram's.""" + have = widths[name][1] + if have == width: + return name + if have > width: + return f"{name}[{width - 1}:0]" + return f"{{{width - have}'b0, {name}}}" + + conns["clk"] = port(_one(lines, "clock", "clock"), "input", 1) + # ports the RTL has and the array ignores, any number a line + for key in ("reset", "unused"): + for values in _values(lines, key): + for name in values: + port(name, "input", 1) + for values in _values(lines, "async_reset"): + name = port(values[0], "input", 1) + low = values[1] == "low" if len(values) > 1 else True + if "rst_n" in ram_ports: + conns["rst_n"] = name if low else f"~{name}" + else: + conns["rst"] = f"~{name}" if low else name + reads = _values(lines, "read") + a = _address_bits(words) + for i, (addr, data) in enumerate(reads): + conns[f"addr_r{i}"] = fit(port(addr, "input", a), a) + conns["Q" if len(reads) == 1 else f"Q{i}"] = port(data, "output", bits) + writes = _values(lines, "write") + for w, values in enumerate(writes): + suffix = "" if len(writes) == 1 else str(w) + conns[f"addr_w{suffix}"] = fit(port(values[0], "input", a), a) + conns[f"D{suffix}"] = port(values[1], "input", bits) + conns[f"we{suffix}"] = ( + port(values[2], "input", 1) if len(values) > 2 else "1'b1" + ) + ab = _address_bits(words // banks) + for k, values in enumerate(_values(lines, "read_banked")): + for b in range(len(values) // 2): + conns[f"addr_rb{k}_b{b}"] = fit(port(values[2 * b], "input", ab), ab) + conns[f"Qrb{k}_b{b}"] = port(values[2 * b + 1], "output", bits) + for name in ram_ports: + if name not in conns: + raise SystemExit( + f"regfile_ram: {module}: generate_ram's port {name} has no " + "counterpart in the spec" + ) + # the spec's ports are the module's: a stray or missing one would be + # left unconnected in the parent, not refused + if rtl_ports: + stray = sorted(set(widths) - set(rtl_ports)) + missing = sorted(set(rtl_ports) - set(widths)) + if stray or missing: + raise SystemExit( + f"regfile_ram: {module}: the spec's ports are not the " + f"module's: not in the module {stray}, not in the spec " + f"{missing} (list ports the array ignores with `unused`)" + ) + data = [values[1] for values in reads + writes] + [ + name for values in _values(lines, "read_banked") for name in values[1::2] + ] + for name in data: + if rtl_ports[name][1] != bits: + raise SystemExit( + f"regfile_ram: {module}: {name} is " + f"{rtl_ports[name][1]} bits, the spec's words {bits}" + ) + # the RTL's ports in its own order where the JSON has them + order = list(rtl_ports) or list(widths) + for name in widths: + if name not in order: + order.append(name) + decl = [] + for name in order: + direction, width = widths[name] if name in widths else rtl_ports[name] + decl.append(f" {direction} {'' if width == 1 else f'[{width - 1}:0] '}{name}") + body = ",\n".join(decl) + inst = ",\n".join(f" .{p}({c})" for p, c in conns.items()) + return ( + f"// generated by regfile_ram.py: {module} as generate_ram's {block}\n" + f"module {module} (\n{body}\n);\n {block} ram (\n{inst}\n );\nendmodule\n" + ) + + +def _module_header_ports(verilog: str, module: str) -> dict[str, tuple[str, int]]: + """A module's ports, name -> (direction, width), from its header.""" + body = verilog[verilog.index(f"module {module} (") :] + body = body[: body.index(");")] + ports = {} + for line in body.splitlines(): + words = line.strip().rstrip(",").split() + if words and words[0] in ("input", "output"): + width = 1 + if len(words) == 3 and words[1].startswith("["): + width = int(words[1][1 : words[1].index(":")]) + 1 + ports[words[-1]] = (words[0], width) + return ports + + +def generate( + spec: Path, + module: str, + shape: str, + openroad: str, + lefs: list[Path], + out_dir: Path, +) -> dict: + """Build the spec's RAM, shape inline, netlist or macro; return what + the flow lists: the block, and whether it is a macro and dissolves.""" + lines = parse(spec) + ram = f"{module}_ram" + # -periphery verilog: the block is the core, the periphery a module + verilog_periphery = _one(lines, "periphery") == "verilog" + block = f"{ram}_core" if verilog_periphery else ram + periphery_v = out_dir / f"{ram}.periphery.v" + libs = os.environ.get("LIB_FILES", "").split() + if not libs: + raise SystemExit("regfile_ram: generate_ram needs LIB_FILES") + reads = "".join(f"read_liberty {lib}\n" for lib in libs) + gen = out_dir / f"{module}.generate.tcl" + outline = out_dir / f"{block}.outline" + + def build(spec_lines: list[list[str]]) -> tuple[float, float]: + gen.write_text( + reads + + "".join(f"read_lef {lef}\n" for lef in lefs) + + "generate_ram_netlist " + + " ".join(_args(spec_lines, ram, shape)) + + (f" -wrapper_verilog {periphery_v}" if verilog_periphery else "") + + f"\nwrite_db {out_dir / f'{block}.odb'}\n" + + "set die [[ord::get_db_block] getDieArea]\n" + + f"set f [open {outline} w]\n" + + 'puts $f "[$die dx] [$die dy] [[ord::get_db_tech] getDbUnitsPerMicron]"\n' + + "close $f\n" + ) + subprocess.check_call([openroad, "-exit", "-no_init", "-no_splash", str(gen)]) + width, height, _ = outline.read_text().split() + return float(width), float(height) + + width, height = build(lines) + # where the spec names no folds, fold a word into a power of two of + # rows while + # + # - the array is more than 8 times as wide as tall, toward the square + # (XiangShan's IntRegFile, 12 reads and 9 writes, 48 to one); a strip + # of a few to one can be the shape that fits (riscv32i's, 6, sits + # under its FakeRAMs), so that alone does not fold; + # - or one word's bits span more than WORD_SPAN_UM: its selects and + # write enables, driven from one cell, are that long, and a parent + # buffers them inside the full array, where nothing legalizes + # (XiangShan's RenameBufferFile, a word a row 258 um wide, failed; + # RobEntryFile at 74 um and IntRegFile at 96 um a word did not). + # + # A spec names bit_folds to choose. + bits = int(_one(lines, "bits")) + dbu = float(outline.read_text().split()[2]) + # the words side by side in a row, each contiguous (see _args) unless + # the spec interleaves them, when a word spans the row + row_words = ( + int(_one(lines, "bank_columns", "1")) + if _one(lines, "bank_column_layout", "contiguous") == "contiguous" + else 1 + ) + span_um = width / dbu / row_words + if not _values(lines, "bit_folds"): + folds = 1 + # a short last fold is allowed, an empty one is not + while ( + folds * 2 <= bits + and (folds * 2 - 1) * -(-bits // (folds * 2)) < bits + and ( + (width > 8 * height and (folds * 2) ** 2 <= 2 * width / height) + or span_um / folds > WORD_SPAN_UM + ) + ): + folds *= 2 + if folds > 1: + lines = lines + [["bit_folds", str(folds)]] + build(lines) + views = out_dir / f"{module}.views.tcl" + tcl = reads + f"read_db {out_dir / f'{block}.odb'}\n" + # the RTL's flop names, for equivalence checking + renames = _renames(lines) + if renames: + (out_dir / f"{block}.renames").write_text( + "".join(f"{{{old}}} {{{new}}}\n" for old, new in renames) + ) + tcl += ( + f"set f [open {out_dir / f'{block}.renames'} r]\n" + "while {[gets $f line] >= 0} {\n" + " lassign $line old new\n" + " set inst [[ord::get_db_block] findInst $old]\n" + ' if {$inst eq "NULL"} { error "regfile_ram: no $old to name $new" }\n' + " $inst rename $new\n" + "}\n" + "close $f\n" + ) + tcl += _VIEWS_TCL.format(out=out_dir, block=block) + if shape == "inline": + tcl += f"write_verilog {out_dir / f'{block}.netlist.v'}\n" + else: + if shape == "macro": + # a macro kept to the end: its pins on its edges, by the pin + # placer + h = _one(lines, "pin_layer", _one(lines, "pin_layer_h", "M4")) + v = _one(lines, "pin_layer_v", "M5") + # tracks on the two pin layers, from their own pitch + for layer in (h, v): + tcl += ( + f"set l [[ord::get_db_tech] findLayer {layer}]\n" + "set u [[ord::get_db_tech] getDbUnitsPerMicron]\n" + "set p [expr {double([$l getPitch]) / $u}]\n" + "set o [expr {double([$l getOffset]) / $u}]\n" + f"make_tracks {layer} -x_offset $o -x_pitch $p" + " -y_offset $o -y_pitch $p\n" + ) + # its power, as a hardened block's: rails on the rows, straps + # with the VDD and VSS pins the parent's grid connects to + # (asap7's BLOCK_grid_strategy.tcl, without its ring) + rails = (_values(lines, "power_rails") or [["M1", "M2"]])[-1] + rail_w = _one(lines, "power_rail_width", "0.018") + strap = _one(lines, "power_layer", "M5") + strap_w = _one(lines, "power_width", "0.12") + pitch = _one(lines, "power_pitch", "2.976") + offset = _one(lines, "power_offset", "1.5") + tcl += ( + "set block [ord::get_db_block]\n" + "foreach {name type} {VDD POWER VSS GROUND} {\n" + " set net [$block findNet $name]\n" + ' if {$net eq "NULL"} { set net [odb::dbNet_create $block $name] }\n' + " $net setSpecial\n" + " $net setSigType $type\n" + "}\n" + "add_global_connection -net VDD -inst_pattern {.*}" + " -pin_pattern {^VDD$} -power\n" + "add_global_connection -net VSS -inst_pattern {.*}" + " -pin_pattern {^VSS$} -ground\n" + "global_connect\n" + "set_voltage_domain -name CORE -power VDD -ground VSS\n" + f"define_pdn_grid -name block -voltage_domains CORE -pins {strap}\n" + ) + for rail in rails: + tcl += ( + f"add_pdn_stripe -grid block -layer {rail} -width {rail_w}" + " -followpins\n" + ) + tcl += ( + f"add_pdn_stripe -grid block -layer {strap} -width {strap_w}" + f" -pitch {pitch} -offset {offset} -extend_to_boundary\n" + ) + for lo, hi in zip(rails + [strap], rails[1:] + [strap]): + if lo != hi: + tcl += f"add_pdn_connect -grid block -layers {{{lo} {hi}}}\n" + tcl += "pdngen\n" + tcl += f"place_pins -hor_layers {h} -ver_layers {v}\n" + tcl += _MACRO_TCL.format(out=out_dir, block=block) + if shape == "macro": + # and its timing, the block's own, for the parent's STA + clock = "clk" + tcl += ( + f"create_clock -name {clock} -period 1 [get_ports {clock}]\n" + "estimate_parasitics -placement\n" + f"write_timing_model {out_dir / f'{block}.lib'}\n" + ) + views.write_text(tcl) + subprocess.check_call([openroad, "-exit", "-no_init", "-no_splash", str(views)]) + if shape == "macro": + # write_timing_model states no area; the flow costs a macro by it + width, height, dbu = (float(v) for v in outline.read_text().split()) + lib = out_dir / f"{block}.lib" + text = lib.read_text() + text = re.sub( + r"(cell\s*\(\s*\\?\"?" + re.escape(block) + r"\"?\s*\)\s*\{)", + lambda m: m.group(1) + f"\n area : {width * height / dbu / dbu:.4f};", + text, + count=1, + ) + lib.write_text(text) + core_ports = _buses((out_dir / f"{block}.ports").read_text().splitlines()) + ram_ports = core_ports + periphery = "" + if verilog_periphery: + periphery = periphery_v.read_text() + ram_ports = _module_header_ports(periphery, ram) + rtl_ports = _module_ports(out_dir.parent / "memories_inferred.json", module) + wrapper = _wrapper(lines, module, ram, ram_ports, rtl_ports) + if periphery: + wrapper += "\n" + periphery + if shape == "inline": + wrapper += "\n" + (out_dir / f"{block}.netlist.v").read_text() + else: + # the macro, a blackbox to synthesis + decl = ",\n".join( + f" {d} {'' if w == 1 else f'[{w - 1}:0] '}{n}" + for n, (d, w) in core_ports.items() + ) + wrapper += f"\n(* blackbox *)\nmodule {block} (\n{decl}\n);\nendmodule\n" + (out_dir / f"{module}.v").write_text(wrapper) + return { + "block": block, + "macro": shape != "inline", + "dissolve": shape == "netlist", + } diff --git a/flow/scripts/memories/schema.py b/flow/scripts/memories/schema.py index 754ae8373c..9141b9cc76 100644 --- a/flow/scripts/memories/schema.py +++ b/flow/scripts/memories/schema.py @@ -61,10 +61,19 @@ class Memory: pins: list[Pin] = field(default_factory=list) # The module whose RTL body simulates this memory: {"file", "module"}. behavioral_model: dict | None = None - # True when the memory is converted to a macro (.lib/.lef emitted and - # the module blackboxed); False leaves it to synthesize as flops. + # True when FakeRAM converts the memory to an SRAM macro (.lib/.lef + # emitted and the module blackboxed); see `kind` for what the flow + # does with the memory in the end. idiomatic: bool = False reason: str = "" + # What the memory becomes: "fakeram" (an SRAM macro), "regfile" (a + # register file generate_ram builds from `spec`) or "flops". + kind: str = "flops" + # "detected" (yosys inferred it), "listed" (AUTO_MEMORIES_REGFILES + # names it) or "override" (an ADDITIONAL_MEMORIES file). + source: str = "detected" + # The register-file spec, for kind "regfile". + spec: str = "" def total_ports(self) -> int: return self.read_ports + self.write_ports + self.rw_ports @@ -129,6 +138,9 @@ def memory_from_dict(d: dict) -> Memory: mem.idiomatic = bool(d["idiomatic"]) if "reason" in d: mem.reason = str(d["reason"]) + for key in ("kind", "source", "spec"): + if key in d: + setattr(mem, key, str(d[key])) return mem diff --git a/flow/scripts/regfile_dissolve.tcl b/flow/scripts/regfile_dissolve.tcl new file mode 100644 index 0000000000..a797461fbe --- /dev/null +++ b/flow/scripts/regfile_dissolve.tcl @@ -0,0 +1,352 @@ +# Register files in `mode netlist` (AUTO_MEMORIES_REGFILES) dissolve into +# their cells here, right after macro placement: to synthesis and to the +# macro placer each was a macro, its abstract's pins where its wires +# connect, so the placer chose its location and flip; from here on it is +# standard cells in the parent's rows. Before tapcells and the power grid, +# which see only cells. +# +# For each macro instance of a listed module, in the instance's module: +# every cell of the generator's structural netlist (memories/.v) is +# created as /, the nets between them as +# /, and each port's net is the net the macro's pin was +# on; the macro goes. The core -- the cells memories/.place lists -- +# is placed FIRM where the generator laid it out, through the macro's +# location and flip; the rest, the periphery (address decode), is left +# unplaced for global placement to place and the resizer to size. +# eliminate_dead_logic then removes what the parent never reads, as the +# synthesis ODB step does for every other cell. + +proc regfile_netlist { file } { + # one instance per line, as regfile_ram.py writes it: + # MASTER \name (.PIN(net), .PIN(\net ), ...); + set cells {} + set f [open $file r] + while { [gets $f line] >= 0 } { + if { ![regexp {^\s*(\S+)\s+\\?(\S+)\s*\((.*)\);\s*$} $line -> master name body] } { + continue + } + set conns {} + foreach {- pin net} [regexp -all -inline {\.(\w+)\(\s*\\?([^ )]+)\s*\)} $body] { + lappend conns $pin $net + } + lappend cells [list $master $name $conns] + } + close $f + return $cells +} + +proc regfile_place_file { file } { + set place [dict create] + set f [open $file r] + while { [gets $f line] >= 0 } { + lassign $line name x y orient + if { $name ne "" } { dict set place $name [list $x $y $orient] } + } + close $f + return $place +} + +proc regfile_flip_x { o } { return [dict get {R0 MX MX R0 MY R180 R180 MY} $o] } +proc regfile_flip_y { o } { return [dict get {R0 MY MY R0 MX R180 R180 MX} $o] } +proc regfile_row_kind { o } { return [expr { $o in {R0 MY} ? "R0" : "MX" }] } + +# A cell is on the core's boundary when one of its nets reaches a port or +# a cell outside the core; a net is the core's own when every terminal of +# it is a placed cell of the core. +proc regfile_boundary_cell { inst placed } { + foreach it [$inst getITerms] { + set net [$it getNet] + if { $net eq "NULL" } { continue } + if { [llength [$net getBTerms]] > 0 } { return 1 } + foreach other [$net getITerms] { + if { ![dict exists $placed [[$other getInst] getName]] } { return 1 } + } + } + return 0 +} +proc regfile_internal_net { net placed } { + if { [llength [$net getBTerms]] > 0 } { return 0 } + foreach it [$net getITerms] { + if { ![dict exists $placed [[$it getInst] getName]] } { return 0 } + } + return 1 +} + +set regfile_list "$::env(RESULTS_DIR)/memories/regfiles.txt" +set regfile_modules {} +if { [env_var_equals AUTO_MEMORIES 1] && [file exists $regfile_list] } { + set f [open $regfile_list r] + set regfile_modules [split [string trim [read $f]] "\n"] + close $f + set regfile_modules [lsearch -all -inline -not -exact $regfile_modules ""] +} +if { [llength $regfile_modules] > 0 } { + set block [ord::get_db_block] + set db [ord::get_db] + set core [$block getCoreArea] + set dbu [[ord::get_db_tech] getDbUnitsPerMicron] + # the parent's rows by their bottom, for the parity check + set row_orient [dict create] + set row_h 0 + set site_w 0 + foreach row [$block getRows] { + set bb [$row getBBox] + dict set row_orient [$bb yMin] [$row getOrient] + set row_h [expr { [$bb yMax] - [$bb yMin] }] + set site_w [[$row getSite] getWidth] + } + set dissolved 0 + set fixups {} + foreach module $regfile_modules { + set macros {} + foreach inst [$block getInsts] { + if { [[$inst getMaster] getName] eq $module } { lappend macros $inst } + } + if { [llength $macros] == 0 } { + utl::info FLW 9 "register file $module: no instance in the design (removed as dead logic)" + continue + } + set cells [regfile_netlist "$::env(RESULTS_DIR)/memories/$module.v"] + set place [regfile_place_file "$::env(RESULTS_DIR)/memories/$module.place"] + foreach macro $macros { + set path [$macro getName] + set parent [$macro getModule] + set master [$macro getMaster] + set W [$master getWidth] + set H [$master getHeight] + set bb [$macro getBBox] + set flip [$macro getOrient] + if { $flip ni {R0 MX MY R180} } { + utl::error FLW 10 "register file $path is placed $flip;\ + a register file flips, it does not rotate" + } + # snap the corner to the site and row grid of the core + set X [expr { + [$core xMin] + + int(round(([$bb xMin] - [$core xMin]) / double($site_w))) * $site_w + }] + set Y [expr { + [$core yMin] + + int(round(([$bb yMin] - [$core yMin]) / double($row_h))) * $row_h + }] + # the macro's pins are the module's port bits; the nets they were on, + # flat and in the macro's module. A cell on the flat net alone is + # cut off from its module's net: STA propagates the clock through + # the hierarchy and never reaches it. + set ports [dict create] + foreach mt [$master getMTerms] { dict set ports [$mt getName] 1 } + set port_net [dict create] + set port_modnet [dict create] + foreach it [$macro getITerms] { + set net [$it getNet] + if { $net ne "NULL" } { dict set port_net [[$it getMTerm] getName] $net } + set modnet [$it getModNet] + if { $modnet ne "NULL" } { dict set port_modnet [[$it getMTerm] getName] $modnet } + } + # The macro placer's halo is a blockage tied to the macro; destroyed + # with it, its instance id goes to one of the new cells and global + # placement refuses a blockage on a movable cell (GPL-0003). + foreach bl [$block getBlockages] { + set owner [$bl getInstance] + if { $owner ne "NULL" && [$owner getId] == [$macro getId] } { + odb::dbBlockage_destroy $bl + } + } + odb::dbInst_destroy $macro + set placed [dict create] + set placed_insts {} + foreach cell $cells { + lassign $cell mname name conns + set m [$db findMaster $mname] + if { $m eq "NULL" } { + utl::error FLW 11 "register file $module: no master $mname for $name" + } + set inst [odb::dbInst_create $block $m "$path/$name" 0 $parent] + foreach {pin netname} $conns { + if { [dict exists $port_net $netname] } { + set net [dict get $port_net $netname] + } elseif { [dict exists $ports $netname] } { + # a port bit the parent leaves unconnected + continue + } else { + set full "$path/$netname" + set net [$block findNet $full] + if { $net eq "NULL" } { set net [odb::dbNet_create $block $full] } + } + set it [$inst findITerm $pin] + if { $it eq "NULL" } { + continue + } elseif { [dict exists $port_modnet $netname] } { + $it connect $net [dict get $port_modnet $netname] + } else { + $it connect $net + } + } + if { [dict exists $place $name] } { + lassign [dict get $place $name] cx cy o + set w [$m getWidth] + set h [$m getHeight] + set x [expr { $cx }] + set y [expr { $cy }] + if { $flip in {MX R180} } { + set y [expr { $H - $cy - $h }] + set o [regfile_flip_x $o] + } + if { $flip in {MY R180} } { + set x [expr { $W - $cx - $w }] + set o [regfile_flip_y $o] + } + $inst setOrient $o + $inst setLocation [expr { $X + $x }] [expr { $Y + $y }] + dict set placed [$inst getName] 1 + lappend placed_insts $inst + } + } + # Row parity: a core row lands on a parent row of its own kind, or + # the whole core moves up one row. + if { [llength $placed_insts] > 0 } { + set probe [lindex $placed_insts 0] + set py [[$probe getBBox] yMin] + if { + [dict exists $row_orient $py] + && [regfile_row_kind [dict get $row_orient $py]] ne [regfile_row_kind [$probe getOrient]] + } { + foreach inst $placed_insts { + set l [$inst getLocation] + $inst setLocation [lindex $l 0] [expr { [lindex $l 1] + $row_h }] + } + set Y [expr { $Y + $row_h }] + } + } + if { + $X < [$core xMin] || $Y < [$core yMin] + || $X + $W > [$core xMax] || $Y + $H > [$core yMax] + } { + set w_um [expr { $W / double($dbu) }] + set h_um [expr { $H / double($dbu) }] + set x_um [expr { $X / double($dbu) }] + set y_um [expr { $Y / double($dbu) }] + utl::error FLW 4 "register file $path ($module, $w_um x $h_um um)\ + at $x_um $y_um um leaves the core" + } + set placed_names {} + foreach inst $placed_insts { lappend placed_names [$inst getName] } + lappend fixups [list $module $path $flip $X $Y [llength $cells] $placed $placed_names] + incr dissolved + } + } + if { $dissolved > 0 } { + # What the parent never reads or writes, as at the synthesis ODB: a + # bit no one reads takes its column of the core with it. Before the + # core is fixed, which the elimination would respect. + log_cmd eliminate_dead_logic + # Cut the rows around the macros now, as tapcell would: cut_rows + # leaves a row that holds a fixed cell uncut (ODB-0386), so once the + # core is FIRM a row it shares with a macro would run on under the + # macro and take an endcap there. + set cut_args {} + if { [env_var_exists_and_non_empty TAP_CELL_NAME] } { + lappend cut_args -endcap_master $::env(TAP_CELL_NAME) + } + if { [env_var_exists_and_non_empty MACRO_ROWS_HALO_X] } { + lappend cut_args -halo_width_x $::env(MACRO_ROWS_HALO_X) + } + if { [env_var_exists_and_non_empty MACRO_ROWS_HALO_Y] } { + lappend cut_args -halo_width_y $::env(MACRO_ROWS_HALO_Y) + } + log_cmd cut_rows {*}$cut_args + } + set row_boxes {} + foreach row [$block getRows] { lappend row_boxes [$row getBBox] } + foreach fixup $fixups { + lassign $fixup module path flip X Y ncells placed placed_names + set placed_insts {} + foreach name $placed_names { + set inst [$block findInst $name] + if { $inst eq "NULL" } { + dict unset placed $name + } else { + lappend placed_insts $inst + } + } + foreach inst $placed_insts { + set bb [$inst getBBox] + set on_row 0 + foreach rb $row_boxes { + if { + [$bb xMin] >= [$rb xMin] && [$bb xMax] <= [$rb xMax] + && [$bb yMin] == [$rb yMin] + } { + set on_row 1 + break + } + } + if { !$on_row } { + utl::error FLW 14 "register file $module at $path: [$inst getName]\ + is on no row once the rows are cut around the macros" + } + $inst setPlacementStatus FIRM + } + # The core is final: FIRM keeps the legaliser off it, dont_touch + # keeps the resizer off it. Two kinds of cell are excepted. The + # flops: CTS has to rewire their clock pins and a dont_touch + # instance refuses (ODB-0370). The boundary cells, any with a pin on + # a net that leaves the core: the parent's repair_design has to + # buffer the nets that reach the core and cannot reconnect a + # dont_touch load (RSZ-3006). They stay FIRM, so nothing resizes + # them: OpenROAD keeps a fixed cell's footprint. + foreach inst $placed_insts { + if { ![[$inst getMaster] isSequential] && ![regfile_boundary_cell $inst $placed] } { + $inst setDoNotTouch 1 + } + } + # The wires between the core's own cells are the generator's too: + # repair_design buffers a net by inserting a cell before its loads, + # and a dont_touch load refuses (ODB-1211, then RSZ-3006 fails the + # stage). A net that leaves the core stays repairable. A violation + # left inside is the generator's to fix. + # Each net once: a net that leaves the core would otherwise be + # rechecked from every one of its pins (the reset, the clock). + set internal_nets 0 + set seen_nets [dict create] + foreach inst $placed_insts { + foreach it [$inst getITerms] { + set net [$it getNet] + if { $net eq "NULL" || [dict exists $seen_nets $net] } { continue } + dict set seen_nets $net 1 + if { [$net isDoNotTouch] } { continue } + if { [regfile_internal_net $net $placed] } { + $net setDoNotTouch 1 + incr internal_nets + } + } + } + set dead [expr { [llength $placed_names] - [llength $placed_insts] }] + set at_x [expr { $X / double($dbu) }] + set at_y [expr { $Y / double($dbu) }] + utl::info FLW 6 "register file $module at $path: $ncells cells,\ + [llength $placed_insts] FIRM ($flip at $at_x $at_y um), $dead dead,\ + $internal_nets internal nets dont_touch" + } + # Every flop of a dissolved core is one STA sees clocked: an unclocked + # one is no timing endpoint, and placement and repair would work blind + # to the paths through the array until CTS rewires its clock. + if { $dissolved > 0 && [llength [all_clocks]] > 0 } { + set clocked [dict create] + foreach cell [all_registers -cells -clock [all_clocks]] { + dict set clocked [[sta::sta_to_db_inst $cell] getName] 1 + } + foreach fixup $fixups { + lassign $fixup module path + foreach name [lindex $fixup 7] { + set inst [$block findInst $name] + if { + $inst ne "NULL" && [[$inst getMaster] isSequential] + && ![dict exists $clocked $name] + } { + utl::error FLW 13 "register file $module at $path: STA sees no clock on $name" + } + } + } + } +} diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 268f5cd9da..3a1872c8c7 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -83,6 +83,55 @@ proc auto_memories_blackboxes { } { return [dict keys [auto_memories_areas]] } +# AUTO_MEMORIES: register files inlined (AUTO_MEMORIES_REGFILES not in +# AUTO_MEMORIES_MACRO_PLACE): the RTL module is read as a blackbox and its +# generated netlist of standard cells is read in its place. +proc auto_memories_inline { } { + if { ![env_var_equals AUTO_MEMORIES 1] } { + return {} + } + set f "$::env(RESULTS_DIR)/memories/inline.txt" + if { ![file exists $f] } { + return {} + } + set fh [open $f r] + set content [read $fh] + close $fh + return [regexp -all -inline {\S+} $content] +} + +# AUTO_MEMORIES: the RAMs the register file wrappers instantiate as +# macros. They are in blackboxes.txt but are no module of the sources: +# they arrive with the wrappers' netlists, after read_slang. +proc auto_memories_regfile_cores { } { + if { ![env_var_equals AUTO_MEMORIES 1] } { + return {} + } + set f "$::env(RESULTS_DIR)/memories/regfile_cores.txt" + if { ![file exists $f] } { + return {} + } + set fh [open $f r] + set content [read $fh] + close $fh + return [regexp -all -inline {\S+} $content] +} + +proc read_auto_memories_inline { } { + foreach m [auto_memories_inline] { + # A parameterized RTL module (ibex_register_file_ff #(...)) is + # instantiated with parameters the generated netlist has no + # declaration for, which hierarchy refuses. The netlist is that module + # at the instance's widths, as regfile_ram.py's port check has + # confirmed: drop the parameters from its instances. + set dump [tee -q -s result.string dump t:$m] + foreach {- name} [regexp -all -inline -- {parameter \\(\S+)} $dump] { + setparam -unset $name t:$m + } + read_verilog -overwrite "$::env(RESULTS_DIR)/memories/$m.v" + } +} + proc read_design_sources { } { # We are reading Verilog sources source $::env(SCRIPTS_DIR)/synth_stdcells.tcl @@ -136,7 +185,7 @@ proc read_design_sources { } { # Blackbox AUTO_MEMORIES-detected memory modules so their generated # liberty view wins over their behavioral bodies. - foreach m [auto_memories_blackboxes] { + foreach m [concat [auto_memories_blackboxes] [auto_memories_inline]] { lappend slang_args --blackboxed-module "$m" } @@ -144,7 +193,15 @@ proc read_design_sources { } { lappend slang_args {*}$::env(SYNTH_SLANG_ARGS) yosys read_slang {*}$slang_args - auto_memories_check_blackboxed [auto_memories_blackboxes] + set cores [auto_memories_regfile_cores] + set sourced {} + foreach m [auto_memories_blackboxes] { + if { [lsearch -exact $cores $m] < 0 } { + lappend sourced $m + } + } + auto_memories_check_blackboxed $sourced + read_auto_memories_inline # Workaround for yosys-slang#119 setattr -unset init @@ -166,7 +223,7 @@ proc read_design_sources { } { if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { error "Non-empty SYNTH_BLACKBOXES unsupported with HDL frontend \"verific\"" } - if { [llength [auto_memories_blackboxes]] > 0 } { + if { [llength [concat [auto_memories_blackboxes] [auto_memories_inline]]] > 0 } { error "AUTO_MEMORIES unsupported with HDL frontend \"$::env(SYNTH_HDL_FRONTEND)\"" } } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { @@ -202,6 +259,10 @@ proc read_design_sources { } { } hierarchy -check -top $::env(DESIGN_NAME) } + if { [llength [auto_memories_inline]] > 0 } { + read_auto_memories_inline + hierarchy -check -top $::env(DESIGN_NAME) + } if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { hierarchy -check -top $::env(DESIGN_NAME) foreach m $::env(SYNTH_BLACKBOXES) { diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 2810d1ec80..dbc839a393 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -74,6 +74,18 @@ "default": 0, "description": "Experimental. When set to 1, memories that yosys infers in the RTL (`$mem_v2` cells, module boundary only) are detected pre-synthesis, inventoried in `$(RESULTS_DIR)/memories.json`, and \u2014 when idiomatic as an SRAM macro \u2014 given generated .lib/.lef views under `$(RESULTS_DIR)/memories/`. Synthesis blackboxes those modules and all later stages read the generated views, so an existing design gets macro-based results without a memory compiler. Supported for the asap7 platform only. See docs/user/AutoMemories.md.\n" }, + "AUTO_MEMORIES_MACRO_PLACE": { + "description": "Experimental. Space-separated list of module names of AUTO_MEMORIES_REGFILES register files to place as macros, blackboxed in synthesis and placed by the macro placer (and, in `mode netlist`, dissolved after macro placement). A register file not listed is inlined: its generated netlist of standard cells replaces the module's body in synthesis, and its cells are placed, sized and buffered with the rest of the design -- the better shape for a small design, where a macro's outline and channels cost more core than the array saves. A name no spec builds stops the build. Requires AUTO_MEMORIES=1.\n", + "stages": [ + "synth" + ] + }, + "AUTO_MEMORIES_REGFILES": { + "description": "Experimental. Space-separated list of register-file spec files, one per RTL module to build as a register file of placed standard cells rather than synthesise to flops. Each spec names its module, words, bits, read and write ports by the RTL's own port names, and the cells. memories/regfile_ram.py checks the spec against the module's ports and has OpenROAD's generate_ram build it as `_ram`, under `$(RESULTS_DIR)/memories/`, with a wrapper in the module's place. A module named in AUTO_MEMORIES_MACRO_PLACE is blackboxed like an AUTO_MEMORIES macro and placed as one; any other is inlined as its generated netlist. A placed spec in `mode netlist` then dissolves into its cells after macro placement: its core FIRM where the macro was placed, in the macro's orientation, its periphery left to placement. Every register file appears in memories.json with kind `regfile`. Requires AUTO_MEMORIES=1.\n", + "stages": [ + "synth" + ] + }, "BALANCE_ROWS": { "default": 0, "description": "Balance rows during placement.\n", diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 4d71623a35..7911e3c87c 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -256,6 +256,37 @@ SYNTH_VERILOG_SURGERY_ARGS: Arguments to SYNTH_VERILOG_SURGERY, before the ones the flow adds. stages: - synth +AUTO_MEMORIES_REGFILES: + description: > + Experimental. Space-separated list of register-file spec files, one + per RTL module to build as a register file of placed standard cells + rather than synthesise to flops. Each spec names its module, words, + bits, read and write ports by the RTL's own port names, and the cells. + memories/regfile_ram.py checks the spec against the module's ports + and has OpenROAD's generate_ram build it as `_ram`, under + `$(RESULTS_DIR)/memories/`, with a wrapper in the module's place. A + module named in AUTO_MEMORIES_MACRO_PLACE is blackboxed like an + AUTO_MEMORIES macro and placed as one; any other is inlined as its + generated netlist. A placed spec in `mode netlist` then dissolves into + its cells after macro placement: its core FIRM where the macro was + placed, in the macro's orientation, its periphery left to placement. Every register + file appears in memories.json with kind `regfile`. Requires + AUTO_MEMORIES=1. + stages: + - synth +AUTO_MEMORIES_MACRO_PLACE: + description: > + Experimental. Space-separated list of module names of + AUTO_MEMORIES_REGFILES register files to place as macros, blackboxed + in synthesis and placed by the macro placer (and, in `mode netlist`, + dissolved after macro placement). A register file not listed is + inlined: its generated netlist of standard cells replaces the module's + body in synthesis, and its cells are placed, sized and buffered with + the rest of the design -- the better shape for a small design, where a + macro's outline and channels cost more core than the array saves. A + name no spec builds stops the build. Requires AUTO_MEMORIES=1. + stages: + - synth SYNTH_MEMORY_MAX_BITS: description: > Maximum number of bits for memory synthesis. From 6fc698ae3871b7937e740015fab4721ec8d838d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 26 Oct 2026 22:16:20 +0100 Subject: [PATCH 3/7] pdn: connect the supply pins of dont_touch instances regfile_dissolve.tcl marks the cores of dissolved register files dont_touch at the macro step, before the PDN step defines the global connections, and global_connect skips dont_touch instances (ODB-0383, deliberate in odb). Their VDD and VSS pins stayed on no net through final: 896 of riscv32i's 7,089 instances in test/regfile, 406,272 cells on XiangShan's XSTile parent. The M1 rails touch them, so timing and routing were unaffected; the netlist, LVS and power analysis saw them unpowered. Every dont_touch instance with a supply pin on no net has its dont_touch lifted while the platform's PDN script makes its global connections, and restored after: one connection, no ODB-0383 warning per instance (406,272 on XSTile). A supply pin already on a net is left alone. --- flow/scripts/pdn.tcl | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl index 1ffbadd9ba..7beb7ffae2 100644 --- a/flow/scripts/pdn.tcl +++ b/flow/scripts/pdn.tcl @@ -3,7 +3,42 @@ erase_non_stage_variables floorplan load_design 2_3_floorplan_tapcell.odb 2_1_floorplan.sdc source_step_tcl PRE PDN +# global_connect skips dont_touch instances (ODB-0383, a warning each), +# and the cores of dissolved register files are dont_touch by now +# (regfile_dissolve.tcl), so their supply pins were left on no net: in +# the netlist, LVS and power analysis they were unpowered. A supply pin on +# no net changes no logic when it is connected, so dont_touch is lifted +# from those instances for the platform's global connections and +# restored after. A supply pin already on a net is left alone. +proc dont_touch_unsupplied { } { + set insts {} + foreach inst [[ord::get_db_block] getInsts] { + if { ![$inst isDoNotTouch] } { + continue + } + foreach iterm [$inst getITerms] { + set type [[$iterm getMTerm] getSigType] + if { ($type eq "POWER" || $type eq "GROUND") && [$iterm getNet] eq "NULL" } { + lappend insts $inst + break + } + } + } + return $insts +} +set lifted [dont_touch_unsupplied] +foreach inst $lifted { + $inst setDoNotTouch 0 +} source $::env(PDN_TCL) +foreach inst $lifted { + $inst setDoNotTouch 1 +} +if { [llength $lifted] > 0 } { + utl::info FLW 18 "[llength $lifted] dont_touch instances had a supply pin\ + on no net; connected by the global connections" +} + pdngen source_step_tcl POST PDN From 0c75731a521c2b9052fed29bf9709a2cf8940bdb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Mon, 26 Oct 2026 22:16:20 +0100 Subject: [PATCH 4/7] memories: a register file in mode macro stops; mode netlist is the only mode mode macro wrote a register file's timing model (write_timing_model) from generate_ram's netlist before any clock tree was built, so the macro's clock pin was the whole unbuffered clock net: 8.5 pF for 64 words of 256 bits on asap7, 32 pF for XiangShan's 954-bit Ftq queue, whose clock then arrived 7.7 ns late in its parent and set the parent's whole clock tree. A register file wanted as a macro is a design of its own: run it through the flow, where CTS builds its clock tree, and give the parent its abstract as a macro. mode macro now stops with that advice; a spec without a mode line means mode netlist, which dissolves the register file into its parent after macro placement. --- docs/user/AutoMemories.md | 15 ++++++++++----- flow/scripts/memories/gen_memories.py | 24 +++++++++++++++++++----- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/docs/user/AutoMemories.md b/docs/user/AutoMemories.md index 3fe7a9c505..3b059a4e1b 100644 --- a/docs/user/AutoMemories.md +++ b/docs/user/AutoMemories.md @@ -164,16 +164,21 @@ to place as macros: - **Listed: a macro.** `_ram` is a macro to synthesis and macro placement: its abstract `_ram.lef` and a liberty of its area and pins land beside the FakeRAM views and it joins `blackboxes.txt`. In - `mode netlist` (the usual one) `generate_ram` places only the array's + `mode netlist` (the only one) `generate_ram` places only the array's core and leaves its periphery (decode, select and input buffers) to the parent, and the macro dissolves into its cells at the end of macro placement (`regfile_dissolve.tcl`): the core lands FIRM where the macro was placed, flipped as the macro was, on the parent's rows; the periphery is left to global placement and the resizer, and dead logic - is eliminated as at synthesis. `mode macro` keeps the macro to the - end, its pins placed on its edges, a power grid with `VDD`/`VSS` pins - and a timing model from `write_timing_model`. A large design whose - floorplan plans its register files lists them. + is eliminated as at synthesis. A large design whose floorplan plans + its register files lists them. +- **A macro of its own.** A register file wanted as a macro to the end + is a design of its own: run its module through the flow (in + bazel-orfs, its own `orfs_flow`, its spec listed and macro-placed so + it dissolves there) and give the parent its abstract as a macro. Its + clock tree is then built and its timing model is written from it. + `mode macro`, which wrote the model from `generate_ram`'s netlist + before any clock tree, stops with that advice. A word holds its value between writes either through a hold mux per bit (`write_style mux`, the default here) or through one integrated diff --git a/flow/scripts/memories/gen_memories.py b/flow/scripts/memories/gen_memories.py index 67f7bfc383..98067b5ac4 100644 --- a/flow/scripts/memories/gen_memories.py +++ b/flow/scripts/memories/gen_memories.py @@ -66,16 +66,30 @@ def _spec_value(spec: Path, key: str) -> list[list[str]]: def _spec_mode(spec: Path) -> str: - """`mode macro` (the default) or `mode netlist` of a register-file spec.""" + """`mode netlist`, the only mode, of a register-file spec. + + `mode macro` stops: it wrote the macro's timing model from + generate_ram's netlist before any clock tree was built, so its clock + pin was the whole unbuffered clock net (8.5 pF for 64 x 256 bits on + asap7). A register file wanted as a macro is a design of its own: + run it through the flow and give its abstract to the parent as a + macro.""" for line in spec.read_text().splitlines(): parts = line.split("#", 1)[0].split() if len(parts) == 2 and parts[0] == "mode": - if parts[1] not in ("macro", "netlist"): + if parts[1] == "macro": raise SystemExit( - f"gen_memories: {spec}: mode is macro or netlist, not {parts[1]}" + f"gen_memories: {spec}: mode macro is gone. A register file " + "wanted as a macro is a design of its own: run it through " + "the flow (in bazel-orfs, its own orfs_flow) and give the " + "parent its abstract as a macro. Here, mode netlist " + "dissolves it into this design." ) - return parts[1] - return "macro" + if parts[1] != "netlist": + raise SystemExit( + f"gen_memories: {spec}: mode is netlist, not {parts[1]}" + ) + return "netlist" def _lib_area(lib: Path) -> str: From 27f5c7a3f2ba164e516f68b0f742d6ab74c6ee15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 27 Oct 2026 02:10:04 +0100 Subject: [PATCH 5/7] memories: a parameterized module as a macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit AUTO_MEMORIES replaced a parameterized memory module (coralnpu's Sram #(NUM_ENTRIES, GLOBAL_BASE_ADDR)) by its macro with the instance's parameters still on it: yosys writes `Sram #(.NUM_ENTRIES(...)) ...` into 1_2_yosys.v, and OpenROAD's Verilog reader stops on it (STA-0171, syntax error). The macro is the module at the widths detection sized it, as the inlined register files already are: drop the parameters from the instances of both, through one proc. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- flow/scripts/synth_preamble.tcl | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index 3a1872c8c7..347edd7735 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -117,17 +117,22 @@ proc auto_memories_regfile_cores { } { return [regexp -all -inline {\S+} $content] } +# The instances of a parameterized RTL module (ibex_register_file_ff +# #(...), coralnpu's Sram #(NUM_ENTRIES)) carry parameters its generated +# view has no declaration for: hierarchy refuses them, and a netlist +# that writes them out is one OpenROAD cannot read. The view is that +# module at the instance's widths, as detection sized it: drop the +# parameters from its instances. +proc drop_auto_memories_parameters { m } { + set dump [tee -q -s result.string dump t:$m] + foreach {- name} [regexp -all -inline -- {parameter \\(\S+)} $dump] { + setparam -unset $name t:$m + } +} + proc read_auto_memories_inline { } { foreach m [auto_memories_inline] { - # A parameterized RTL module (ibex_register_file_ff #(...)) is - # instantiated with parameters the generated netlist has no - # declaration for, which hierarchy refuses. The netlist is that module - # at the instance's widths, as regfile_ram.py's port check has - # confirmed: drop the parameters from its instances. - set dump [tee -q -s result.string dump t:$m] - foreach {- name} [regexp -all -inline -- {parameter \\(\S+)} $dump] { - setparam -unset $name t:$m - } + drop_auto_memories_parameters $m read_verilog -overwrite "$::env(RESULTS_DIR)/memories/$m.v" } } @@ -201,6 +206,9 @@ proc read_design_sources { } { } } auto_memories_check_blackboxed $sourced + foreach m $sourced { + drop_auto_memories_parameters $m + } read_auto_memories_inline # Workaround for yosys-slang#119 From 5d956019142214727b0fd67c1406c0d425dee600 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 27 Oct 2026 02:19:57 +0100 Subject: [PATCH 6/7] src/coralnpu: a Bazel module that generates CoreMiniAxi.sv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit flow/designs/src/coralnpu/generate is a Bazel module that writes CoreMiniAxi.sv from coralnpu's Chisel source at a pinned commit: cd flow/designs/src/coralnpu/generate bazelisk run //:update It elaborates coralnpu's CoreAxi as upstream's CoreMiniAxi build configures it (128-bit fetch and load/store, float with Zfbfmin), in a wrapper that ties the test enable te to 0, so synthesis removes the test-mode reset bypasses and clock-gate overrides, and without the debug ports a synthesis build does not use. firtool runs without the verification layers and without register randomization. The dependency pins and coralnpu's patches to cvfpu are coralnpu's own. The module is in a directory of its own, so flow/designs/src/coralnpu holds no Bazel package. CoreMiniAxi.sv is regenerated in the next commit, with the design changes the new RTL needs. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- flow/designs/src/coralnpu/generate/.gitignore | 2 + .../designs/src/coralnpu/generate/BUILD.bazel | 57 ++++++++++ .../generate/CoreMiniAxiGenerator.scala | 43 ++++++++ .../src/coralnpu/generate/MODULE.bazel | 102 ++++++++++++++++++ .../coralnpu/generate/coralnpu.BUILD.bazel | 68 ++++++++++++ .../src/coralnpu/generate/resources.py | 25 +++++ .../coralnpu/generate/rocket_chip.BUILD.bazel | 1 + flow/designs/src/coralnpu/generate/update.sh | 7 ++ 8 files changed, 305 insertions(+) create mode 100644 flow/designs/src/coralnpu/generate/.gitignore create mode 100644 flow/designs/src/coralnpu/generate/BUILD.bazel create mode 100644 flow/designs/src/coralnpu/generate/CoreMiniAxiGenerator.scala create mode 100644 flow/designs/src/coralnpu/generate/MODULE.bazel create mode 100644 flow/designs/src/coralnpu/generate/coralnpu.BUILD.bazel create mode 100644 flow/designs/src/coralnpu/generate/resources.py create mode 100644 flow/designs/src/coralnpu/generate/rocket_chip.BUILD.bazel create mode 100755 flow/designs/src/coralnpu/generate/update.sh diff --git a/flow/designs/src/coralnpu/generate/.gitignore b/flow/designs/src/coralnpu/generate/.gitignore new file mode 100644 index 0000000000..0d4fed27c9 --- /dev/null +++ b/flow/designs/src/coralnpu/generate/.gitignore @@ -0,0 +1,2 @@ +bazel-* +MODULE.bazel.lock diff --git a/flow/designs/src/coralnpu/generate/BUILD.bazel b/flow/designs/src/coralnpu/generate/BUILD.bazel new file mode 100644 index 0000000000..d14732ddbf --- /dev/null +++ b/flow/designs/src/coralnpu/generate/BUILD.bazel @@ -0,0 +1,57 @@ +load("@rules_chisel//chisel:defs.bzl", "chisel_binary") +load("@rules_chisel//verilog:defs.bzl", "fir_library", "verilog_file") +load("@rules_java//java:java_import.bzl", "java_import") +load("@rules_shell//shell:sh_binary.bzl", "sh_binary") + +genrule( + name = "resources_jar", + srcs = [ + "@common_cells//:all_srcs", + "@coralnpu//:blackboxes", + "@cvfpu//:all_srcs", + "@fpu_div_sqrt_mvp//:all_srcs", + ], + outs = ["resources.jar"], + cmd = "python3 $(location resources.py) $@ $(SRCS)", + tools = ["resources.py"], +) + +java_import( + name = "resources", + jars = [":resources.jar"], +) + +chisel_binary( + name = "generator", + srcs = ["CoreMiniAxiGenerator.scala"], + main_class = "orfs.coralnpu.CoreMiniAxiGenerator", + deps = [ + ":resources", + "@coralnpu", + ], +) + +fir_library( + name = "CoreMiniAxi_hw", + generator = ":generator", + opts = [ + "--disable-all-randomization", + "--disable-layers=Verification", + ], +) + +verilog_file( + name = "CoreMiniAxi_generated.sv", + srcs = [":CoreMiniAxi_hw"], + opts = [ + "--disable-all-randomization", + "--disable-layers=Verification", + "--lowering-options=disallowLocalVariables,locationInfoStyle=none", + ], +) + +sh_binary( + name = "update", + srcs = ["update.sh"], + data = [":CoreMiniAxi_generated.sv"], +) diff --git a/flow/designs/src/coralnpu/generate/CoreMiniAxiGenerator.scala b/flow/designs/src/coralnpu/generate/CoreMiniAxiGenerator.scala new file mode 100644 index 0000000000..b8fc645aa6 --- /dev/null +++ b/flow/designs/src/coralnpu/generate/CoreMiniAxiGenerator.scala @@ -0,0 +1,43 @@ +package orfs.coralnpu + +import chisel3._ +import chisel3.reflect.DataMirror +import circt.stage.ChiselStage +import coralnpu._ +import scala.collection.immutable.SeqMap + +/** CoreMiniAxi for synthesis. + * + * coralnpu's core_mini_axi_cc_library configuration (128-bit fetch and + * load/store data, the float unit with Zfbfmin, AXI ports) without its + * debug ports, which only expose state to a testbench. The core is built + * as CoreMiniCoreAxi inside a CoreMiniAxi with the same ports except the + * test enable, which is tied low: in functional mode it only selects + * reset bypasses and opens clock gates, and as a constant synthesis + * removes that logic. + */ +class CoreMiniAxi(p: Parameters) extends RawModule { + val core = Module(new CoreAxi(p, "CoreMiniCore")) + + val io = IO(new Record { + val elements = SeqMap.from( + core.io.elements.toSeq.reverse.collect { + case (name, data) if name != "te" => name -> DataMirror.internal.chiselTypeClone(data) + } + ) + }) + core.io.te := false.B + for ((name, data) <- io.elements) { + data <> core.io.elements(name) + } +} + +object CoreMiniAxiGenerator extends App { + val p = new Parameters + p.fetchDataBits = 128 + p.lsuDataBits = 128 + p.enableFloat = true + p.enableZfbfmin = true + p.m = MemoryRegions.default + ChiselStage.emitHWDialect(new CoreMiniAxi(p), Array(), args) +} diff --git a/flow/designs/src/coralnpu/generate/MODULE.bazel b/flow/designs/src/coralnpu/generate/MODULE.bazel new file mode 100644 index 0000000000..ede40b347f --- /dev/null +++ b/flow/designs/src/coralnpu/generate/MODULE.bazel @@ -0,0 +1,102 @@ +"""CoreMiniAxi.sv generated from coralnpu's Chisel source. + + bazelisk run //:update + +writes ../CoreMiniAxi.sv: coralnpu's CoreMiniAxi as upstream's +core_mini_axi_cc_library configures it, through firtool, without the +verification layers, randomization or debug ports a synthesis build +does not use, and with the test enable tied low. To move to a newer +coralnpu, change the coralnpu archive below and run it again. +""" + +module(name = "orfs_coralnpu") + +bazel_dep(name = "rules_chisel", version = "0.4.2") +bazel_dep(name = "rules_java", version = "8.14.0") +bazel_dep(name = "rules_scala", version = "7.1.5") +bazel_dep(name = "rules_shell", version = "0.8.0") + +# coralnpu pins Chisel 7.0.0-RC1. rules_scala carries Scala 2.13.17, +# and Chisel's compiler plugin is published for it from 7.2.0 on. +chisel = use_extension("@rules_chisel//chisel:extensions.bzl", "chisel") +chisel.toolchain( + chisel_version = "7.2.0", + scala_version = "2.13.17", +) +use_repo(chisel, "chisel_firtool", "chisel_maven") + +scala_config = use_extension("@rules_scala//scala/extensions:config.bzl", "scala_config") +scala_config.settings(scala_version = "2.13.17") +use_repo(scala_config, "rules_scala_config") + +scala_deps = use_extension("@rules_scala//scala/extensions:deps.bzl", "scala_deps") +scala_deps.scala() +use_repo(scala_deps, "rules_scala_toolchains") + +http_archive = use_repo_rule("@bazel_tools//tools/build_defs/repo:http.bzl", "http_archive") + +http_archive( + name = "coralnpu", + build_file = "//:coralnpu.BUILD.bazel", + # coralnpu's own BUILD files load its rules and toolchains; this + # build compiles the sources with coralnpu.BUILD.bazel alone. + patch_cmds = ["find . -mindepth 2 \\( -name BUILD -o -name BUILD.bazel \\) -delete"], + sha256 = "86d5a9be2ca00d6ced6f2a2cd63fe35f7fd6e00443860c7855dc37cf0c793c63", + strip_prefix = "coralnpu-b50b85a96925576b907b6cdec110d9f4b0a08695", + urls = ["https://github.com/google-coral/coralnpu/archive/b50b85a96925576b907b6cdec110d9f4b0a08695.tar.gz"], +) + +# The rest at the commits coralnpu's rules/repo_defs.bzl and +# rules/repos.bzl pin, cvfpu with coralnpu's patches. +http_archive( + name = "rocket_chip", + build_file = "//:rocket_chip.BUILD.bazel", + sha256 = "76076a7e7538dd347074d7dc056cfa6219a6dfdeed58bb47c848b435f27c30f8", + strip_prefix = "rocket-chip-f517abbf41abb65cea37421d3559f9739efd00a9", + urls = ["https://github.com/chipsalliance/rocket-chip/archive/f517abbf41abb65cea37421d3559f9739efd00a9.tar.gz"], +) + +http_archive( + name = "diplomacy", + build_file_content = 'exports_files(glob(["**/*.scala"]))', + sha256 = "33a66aa60e565b9665dcfc93020f5acf64710a7dc4f2b164752544ec5a946256", + strip_prefix = "diplomacy-6590276fa4dac315ae7c7c01371b954c5687a473", + urls = ["https://github.com/chipsalliance/diplomacy/archive/6590276fa4dac315ae7c7c01371b954c5687a473.tar.gz"], +) + +http_archive( + name = "cvfpu", + build_file_content = 'filegroup(name = "all_srcs", srcs = glob(["**/*.sv", "**/*.svh", "**/*.v"], allow_empty = True), visibility = ["//visibility:public"])', + patch_args = ["-p1"], + patches = [ + "@coralnpu//:third_party/cvfpu/0001-Fix-max_num_lanes-issue-in-DC.patch", + "@coralnpu//:third_party/cvfpu/0002-Remove-SVH-includes.patch", + "@coralnpu//:third_party/cvfpu/0003-Fill-in-unreachable-state-in-fpnew_divsqrt_th_32-fsm.patch", + "@coralnpu//:third_party/cvfpu/0004-Remove-ternary-operator-from-pkg-causing-dc-crash.patch", + "@coralnpu//:third_party/cvfpu/0005-Fix-fsm-complete.patch", + "@coralnpu//:third_party/cvfpu/0006-Fix-syn-tool-compatibility-issues.patch", + "@coralnpu//:third_party/cvfpu/0007-Fix-nan-boxing-divsqrt.patch", + "@coralnpu//:third_party/cvfpu/0008-Fix-num-lanes-multifmt-slice.patch", + "@coralnpu//:third_party/cvfpu/0009-Rebalance-fpnew-fma-pipeline-stages.patch", + "@coralnpu//:third_party/cvfpu/0010-Move-LZA-leading-zero-counter-to-norm-stage.patch", + ], + sha256 = "42f7852a8df79cd08999a42ca338ef8017e87f513229a4e34aca754f8aedea26", + strip_prefix = "cvfpu-bb65bdedd07711dfd41c621382f940a5cbb93046", + urls = ["https://github.com/openhwgroup/cvfpu/archive/bb65bdedd07711dfd41c621382f940a5cbb93046.tar.gz"], +) + +http_archive( + name = "common_cells", + build_file_content = 'filegroup(name = "all_srcs", srcs = glob(["**/*.sv", "**/*.svh", "**/*.v"], allow_empty = True), visibility = ["//visibility:public"])', + sha256 = "ea112e598908b9cfd03254aeb676ff8b51196b186ab00bdb5e2ad90a73a3055e", + strip_prefix = "common_cells-6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea", + urls = ["https://github.com/pulp-platform/common_cells/archive/6aeee85d0a34fedc06c14f04fd6363c9f7b4eeea.tar.gz"], +) + +http_archive( + name = "fpu_div_sqrt_mvp", + build_file_content = 'filegroup(name = "all_srcs", srcs = glob(["**/*.sv", "**/*.svh", "**/*.v"], allow_empty = True), visibility = ["//visibility:public"])', + sha256 = "2647be453d3dbb7315d7018235ab64b9178ed387c3ff0d2f48d106bac6ab2ece", + strip_prefix = "fpu_div_sqrt_mvp-86e1f558b3c95e91577c41b2fc452c86b04e85ac", + urls = ["https://github.com/pulp-platform/fpu_div_sqrt_mvp/archive/86e1f558b3c95e91577c41b2fc452c86b04e85ac.tar.gz"], +) diff --git a/flow/designs/src/coralnpu/generate/coralnpu.BUILD.bazel b/flow/designs/src/coralnpu/generate/coralnpu.BUILD.bazel new file mode 100644 index 0000000000..64ecf67590 --- /dev/null +++ b/flow/designs/src/coralnpu/generate/coralnpu.BUILD.bazel @@ -0,0 +1,68 @@ +load("@rules_chisel//chisel:defs.bzl", "chisel_library") + +package(default_visibility = ["//visibility:public"]) + +exports_files(glob(["third_party/**/*.patch"])) + +# rocket-chip's AsyncQueue, which coralnpu's TileLink bridges use. +chisel_library( + name = "asyncqueue", + srcs = [ + "@diplomacy//:diplomacy/src/diplomacy/nodes/HeterogeneousBag.scala", + "@rocket_chip//:src/main/scala/util/AsyncQueue.scala", + "@rocket_chip//:src/main/scala/util/AsyncResetReg.scala", + "@rocket_chip//:src/main/scala/util/Counters.scala", + "@rocket_chip//:src/main/scala/util/Crossing.scala", + "@rocket_chip//:src/main/scala/util/ShiftReg.scala", + "@rocket_chip//:src/main/scala/util/SynchronizerReg.scala", + "@rocket_chip//:src/main/scala/util/package.scala", + ], + scalacopts = ["-Wconf:cat=deprecation:s"], +) + +# The revision the core reports in a CSR, which coralnpu's build stamps +# from git: here the commit this archive is. +genrule( + name = "scm_info", + outs = ["ScmInfo.scala"], + cmd = """cat > $@ <<'EOF' +package coralnpu + +class ScmInfo { + val revision = BigInt("b50b85a96925576b907b6cdec110d9f4b0a08695", 16) +} +EOF""", +) + +# common, bus and the core compiled together: the packages refer to +# each other. Tests, specs, simulation helpers and the SoC-only TCMs +# are left out. +chisel_library( + name = "coralnpu", + srcs = [":scm_info"] + glob( + [ + "hdl/chisel/src/common/*.scala", + "hdl/chisel/src/bus/*.scala", + "hdl/chisel/src/coralnpu/*.scala", + "hdl/chisel/src/coralnpu/float/*.scala", + "hdl/chisel/src/coralnpu/rvv/*.scala", + "hdl/chisel/src/coralnpu/scalar/*.scala", + ], + exclude = [ + "**/*Spec.scala", + "**/*Test*.scala", + "hdl/chisel/src/common/FpTestUtils.scala", + "hdl/chisel/src/common/SvGenerationUtils.scala", + "hdl/chisel/src/common/TestingUtils.scala", + "hdl/chisel/src/coralnpu/BankedDtcm.scala", + "hdl/chisel/src/coralnpu/BankedItcm.scala", + ], + ), + scalacopts = ["-Wconf:cat=deprecation:s"], + deps = [":asyncqueue"], +) + +filegroup( + name = "blackboxes", + srcs = glob(["hdl/verilog/**/*.sv", "hdl/verilog/**/*.svh", "hdl/verilog/**/*.v"]), +) diff --git a/flow/designs/src/coralnpu/generate/resources.py b/flow/designs/src/coralnpu/generate/resources.py new file mode 100644 index 0000000000..4e000cabda --- /dev/null +++ b/flow/designs/src/coralnpu/generate/resources.py @@ -0,0 +1,25 @@ +"""A jar of the Verilog coralnpu's black boxes load from the classpath. + +The paths are the ones coralnpu's addResource calls name: its own files +at their path in its repository (hdl/verilog/rvv/...), those directly in +hdl/verilog (RstSync.sv, ClockGate.sv, Sram.v) at the root as well, and +a dependency's at external// (fpnew's, in FloatCore). +""" + +import re +import sys +import zipfile + +out = sys.argv[1] +with zipfile.ZipFile(out, "w") as jar: + for path in sys.argv[2:]: + m = re.search(r"external/[^/]*?([a-z_]+)/(.*)$", path) + if m is None: + sys.exit("resources: %s is not in an external repository" % path) + repo, rest = m.groups() + if repo != "coralnpu": + jar.write(path, "external/%s/%s" % (repo, rest)) + continue + jar.write(path, rest) + if rest.count("/") == 2: + jar.write(path, rest.split("/")[-1]) diff --git a/flow/designs/src/coralnpu/generate/rocket_chip.BUILD.bazel b/flow/designs/src/coralnpu/generate/rocket_chip.BUILD.bazel new file mode 100644 index 0000000000..b3a8f30238 --- /dev/null +++ b/flow/designs/src/coralnpu/generate/rocket_chip.BUILD.bazel @@ -0,0 +1 @@ +exports_files(glob(["src/main/scala/**/*.scala"])) diff --git a/flow/designs/src/coralnpu/generate/update.sh b/flow/designs/src/coralnpu/generate/update.sh new file mode 100755 index 0000000000..60e9f6b81d --- /dev/null +++ b/flow/designs/src/coralnpu/generate/update.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +# Copies the generated CoreMiniAxi.sv into flow/designs/src/coralnpu. +set -euo pipefail +src="$PWD/CoreMiniAxi_generated.sv" +dst="$BUILD_WORKSPACE_DIRECTORY/../CoreMiniAxi.sv" +cp "$src" "$dst" +chmod u+w "$dst" From 818b99e26ff53fa08349971ef8868c74b332bc65 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 27 Oct 2026 06:39:06 +0100 Subject: [PATCH 7/7] asap7/coralnpu: coralnpu's current RTL, its memories generated MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CoreMiniAxi.sv is regenerated from coralnpu b50b85a9 by src/coralnpu/generate, and the design is configured for it: - The five TCM banks (ITCM one, DTCM four) are coralnpu's Sram, 512 x 128 with one read-write port and a 16-lane byte mask. sram.memories names its pins (ADDITIONAL_MEMORIES) and AUTO_MEMORIES replaces it with a generated macro, write mask and all. The previous build swapped in USE_ASAP7 fakerams, which have no write mask, so a masked write wrote all 16 bytes. - Regfile and FRegfile keep their words as separate registers, with no array for yosys to infer. surgery.py (SYNTH_VERILOG_SURGERY) moves them into Regfile_rf and FRegfile_rf, which AUTO_MEMORIES_REGFILES has generate_ram build as standard cells, every word with its asynchronous reset: Regfile 32 x 32 with x0 reading zero, nine reads and six writes; FRegfile 32 x 32, four reads and two writes. - The clock is 1,900 ps in the platform's picoseconds (it was 10.00), with the platform's set_max_delay IO budgets; the asynchronous reset is not timed. The kept hierarchy is coralnpu's units by name, with OPENROAD_HIERARCHICAL=1. - The divider's 128 x 83 SRT table is a ROM yosys maps to logic. SYNTH_MEMORY_MAX_BITS counts ROMs today and stops synthesis on it; the design builds once a ROM is no longer counted, a separate change. surgery.py recognises each register file token for token and stops the build on anything else. Each was simulated before and after the surgery, and generate_ram's netlists against the behavioural modules the surgery writes, on the same random inputs, every output compared every cycle, with a negative control for each that is caught. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- docs/user/AutoMemories.md | 9 +- .../asap7/coralnpu/FRegfile_rf.regfile | 19 + flow/designs/asap7/coralnpu/README.md | 78 + .../designs/asap7/coralnpu/Regfile_rf.regfile | 28 + flow/designs/asap7/coralnpu/config.mk | 33 +- flow/designs/asap7/coralnpu/constraint.sdc | 17 +- flow/designs/asap7/coralnpu/sram.memories | 66 + flow/designs/asap7/coralnpu/surgery.py | 478 + flow/designs/src/coralnpu/CoreMiniAxi.sv | 45502 +++++++++------- 9 files changed, 27295 insertions(+), 18935 deletions(-) create mode 100644 flow/designs/asap7/coralnpu/FRegfile_rf.regfile create mode 100644 flow/designs/asap7/coralnpu/README.md create mode 100644 flow/designs/asap7/coralnpu/Regfile_rf.regfile create mode 100644 flow/designs/asap7/coralnpu/sram.memories create mode 100644 flow/designs/asap7/coralnpu/surgery.py diff --git a/docs/user/AutoMemories.md b/docs/user/AutoMemories.md index 3b059a4e1b..3e48a52424 100644 --- a/docs/user/AutoMemories.md +++ b/docs/user/AutoMemories.md @@ -213,10 +213,11 @@ own module, the seam a spec needs, measured as flops against | asap7/cva6 | `ariane_regfile` (`ariane_regfile_ff.sv`) | flip-flops: cv32a65x has `FpgaEn` 0 | 32 x 32, 2R1W | Not yet: the ports are packed arrays (`raddr_i[1:0][4:0]`), one port per slice, which a spec cannot yet address; asynchronous reset as ibex. | | asap7/swerv_wrapper | `dec_gpr_ctl_*` | flip-flops | 32 x 32, 4R3W | Not yet: read enables, bank ids and scan ports around the array need a seam in the RTL. | -coralnpu's `Regfile` (8R4W) and `FRegfile` (3R2W) carry their -scoreboard and bypass logic in the same module, and picorv32 and -tinyRocket keep their register file inside the CPU module: those need a -seam in their RTL first. +coralnpu's `Regfile` (9R6W) and `FRegfile` (4R2W) carry their +scoreboard and bypass logic in the same module; asap7/coralnpu gives +their words modules of their own with `SYNTH_VERILOG_SURGERY` and +generates both. picorv32 and tinyRocket keep their register file inside +the CPU module: those need a seam in their RTL first. ### Status: at parity on riscv32i, on a smaller core diff --git a/flow/designs/asap7/coralnpu/FRegfile_rf.regfile b/flow/designs/asap7/coralnpu/FRegfile_rf.regfile new file mode 100644 index 0000000000..9c8e1268f0 --- /dev/null +++ b/flow/designs/asap7/coralnpu/FRegfile_rf.regfile @@ -0,0 +1,19 @@ +# coralnpu's floating-point register file, FRegfile_rf, the module +# surgery.py moves FRegfile's words into: 32 x 32 (sign, exponent, +# mantissa from the top), four combinational reads (FRegfile's three +# read ports and its bus port), two writes of which the later +# (FRegfile's write port 0) wins a word both write, every word reset to +# zero while reset is high, a clock gate per word. +module FRegfile_rf +words 32 +bits 32 +clock clock +async_reset reset high +read raddr0 rdata0 +read raddr1 rdata1 +read raddr2 rdata2 +read raddr3 rdata3 +write waddr0 wdata0 we0 +write waddr1 wdata1 we1 +write_priority last +write_style clock_gate diff --git a/flow/designs/asap7/coralnpu/README.md b/flow/designs/asap7/coralnpu/README.md new file mode 100644 index 0000000000..5443f89968 --- /dev/null +++ b/flow/designs/asap7/coralnpu/README.md @@ -0,0 +1,78 @@ +# coralnpu on asap7 + +[CoralNPU](https://github.com/google-coral/coralnpu) is Google's open +RISC-V core for edge machine learning: an in-order scalar core that +dispatches up to four instructions a cycle, with a float unit, an ITCM +and a DTCM, and AXI ports. The top is `CoreMiniAxi`. + +Its memories are generated: the five TCM banks as SRAM macros with +their byte write masks (`AUTO_MEMORIES`), and the integer and +floating-point register files as standard cells by OpenROAD's +`generate_ram` (`AUTO_MEMORIES_REGFILES`), every word with its +asynchronous reset. What is left as flip-flops is a handful of queues +of two or three entries. + +## Results + +The whole flow at a 1,900 ps clock, in about 90 minutes: + +| stage | worst setup slack | achieved period | +|---|---|---| +| CTS | +4.6 ps | 1,895 ps | +| global route | +6.2 ps | 1,894 ps | +| final, extracted parasitics | -108 ps | 2,008 ps | + +Standard cells take 19,411 µm² and the five SRAM macros 13,965 µm². +Detailed route ends with no DRC errors. CTS takes 2.7 minutes and +global route 9.1; detailed route takes an hour. + +The worst path at the end runs from the debug module's request queue +through the CSRs, the float core and the load/store unit to the +retirement buffer, in and out of the kept units. +The generated register files' write enables close with 36 ps to spare. + +## Where the RTL comes from + +`../../src/coralnpu/CoreMiniAxi.sv` is generated from coralnpu's source +at the commit pinned in `../../src/coralnpu/generate/MODULE.bazel`, by +Bazel from that directory: + + cd flow/designs/src/coralnpu/generate + bazelisk run //:update + +`generate/CoreMiniAxiGenerator.scala` elaborates coralnpu's `CoreAxi` with the +parameters of coralnpu's own `CoreMiniAxi` build (128-bit fetch and +load/store, float with Zfbfmin), in a wrapper that ties the test enable +`te` to 0, so synthesis removes the test-mode reset bypasses and clock +gate overrides. firtool runs without the verification layers and +without register randomization. To move to a newer coralnpu, change the +commit and its `sha256` in `MODULE.bazel` and run `//:update`. + +## Memories + +- The ITCM (one bank) and DTCM (four banks) are coralnpu's `Sram`, + 512 x 128, one read-write port and a 16-lane byte mask. + `sram.memories` names its pins (`ADDITIONAL_MEMORIES`), and + `AUTO_MEMORIES` replaces it with a generated macro. +- `Regfile` and `FRegfile` keep their words as separate registers, with + no array for yosys to infer. `surgery.py` (`SYNTH_VERILOG_SURGERY`) + moves them into modules of their own, `Regfile_rf` and `FRegfile_rf`, + and `generate_ram` builds those from `Regfile_rf.regfile` and + `FRegfile_rf.regfile`. The integer register file has nine + combinational reads (eight read ports and the debug port) and six + writes; the floating-point one four reads and two writes. +- The largest array left is a ROM, the divider's SRT bound table + (128 x 83), which yosys maps to logic. `SYNTH_MEMORY_MAX_BITS` counts + ROMs today and stops synthesis on it; the design builds once a ROM + is no longer counted, a separate change. + +## Surgery + +`surgery.py` recognises each register file token for token, comments +and whitespace aside, and anything else stops the build. It moves +storage and changes no function: each register file before and after +the surgery was simulated side by side on the same random inputs, +every output compared every cycle (200,000 cycles, resets included, +read and write addresses biased to collide), and a deliberate error in +the moved storage, a write port's mask dropped or the write priority +swapped, is caught within 20 cycles. diff --git a/flow/designs/asap7/coralnpu/Regfile_rf.regfile b/flow/designs/asap7/coralnpu/Regfile_rf.regfile new file mode 100644 index 0000000000..0600d722b4 --- /dev/null +++ b/flow/designs/asap7/coralnpu/Regfile_rf.regfile @@ -0,0 +1,28 @@ +# coralnpu's integer register file as standard cells, inlined in its +# place: Regfile_rf, the module surgery.py moves Regfile's storage into. +# 32 x 32 with x0 reading zero, nine combinational reads (the eight read +# ports and the debug port), six writes ORed when two write one word +# (Regfile's own data_N), a clock gate per word, every word reset to +# zero while reset is high. +module Regfile_rf +words 32 +bits 32 +clock clock +async_reset reset high +read raddr0 rdata0 +read raddr1 rdata1 +read raddr2 rdata2 +read raddr3 rdata3 +read raddr4 rdata4 +read raddr5 rdata5 +read raddr6 rdata6 +read raddr7 rdata7 +read raddr8 rdata8 +write waddr0 wdata0 we0 +write waddr1 wdata1 we1 +write waddr2 wdata2 we2 +write waddr3 wdata3 we3 +write waddr4 wdata4 we4 +write waddr5 wdata5 we5 +zero_word 0 +write_style clock_gate diff --git a/flow/designs/asap7/coralnpu/config.mk b/flow/designs/asap7/coralnpu/config.mk index abf9df8b25..7d49266d86 100644 --- a/flow/designs/asap7/coralnpu/config.mk +++ b/flow/designs/asap7/coralnpu/config.mk @@ -3,17 +3,24 @@ export PLATFORM = asap7 export DESIGN_NICKNAME = coralnpu export DESIGN_NAME = CoreMiniAxi -export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sv \ - $(PLATFORM_DIR)/verilog/fakeram_512x128.sv \ - $(PLATFORM_DIR)/verilog/fakeram_2048x128.sv +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sv -export VERILOG_DEFINES += -D USE_ASAP7 +# The integer and floating-point register files' words moved into +# modules of their own, Regfile_rf and FRegfile_rf. +export SYNTH_VERILOG_SURGERY = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/surgery.py -export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram_512x128.lef \ - $(PLATFORM_DIR)/lef/fakeram_2048x128.lef +# The five TCM banks (ITCM one, DTCM four) are coralnpu's Sram, 512 x +# 128, an array with one read-write port and a 16-lane byte mask; +# sram.memories names its pins, and AUTO_MEMORIES replaces it with a +# generated macro, mask and all. +export AUTO_MEMORIES = 1 +export ADDITIONAL_MEMORIES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram.memories -export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/NLDM/fakeram_512x128.lib \ - $(PLATFORM_DIR)/lib/NLDM/fakeram_2048x128.lib +# The integer and floating-point register files, moved by surgery.py +# into Regfile_rf and FRegfile_rf, built by generate_ram as standard +# cells inlined in their place. +export AUTO_MEMORIES_REGFILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/Regfile_rf.regfile \ + $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/FRegfile_rf.regfile export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc @@ -21,8 +28,14 @@ export SYNTH_HDL_FRONTEND ?= slang export CORE_UTILIZATION = 65 +# coralnpu's units, kept by name: the core, its fetch, dispatch, +# register files, load/store unit, CSRs and FPU, and the two AXI +# bridges. The ALUs, branch units, multiplier and divider are small and +# belong with the dispatch and writeback around them. The size +# threshold is out of reach so that the list alone decides. export SYNTH_HIERARCHICAL = 1 -export SYNTH_MINIMUM_KEEP_SIZE = 40000 +export SYNTH_KEEP_MODULES = SCore UncachedFetch DispatchV2 Regfile FRegfile LsuV3 Csr FloatCore AxiSlave DBus2AxiV2 +export SYNTH_MINIMUM_KEEP_SIZE = 1000000000 +export OPENROAD_HIERARCHICAL = 1 export RTLMP_MIN_CHANNEL_SIZE = 4 4 - diff --git a/flow/designs/asap7/coralnpu/constraint.sdc b/flow/designs/asap7/coralnpu/constraint.sdc index efcf203d0e..a3d957c0a6 100644 --- a/flow/designs/asap7/coralnpu/constraint.sdc +++ b/flow/designs/asap7/coralnpu/constraint.sdc @@ -2,8 +2,19 @@ current_design CoreMiniAxi set clk_name io_aclk set clk_port_name io_aclk -set clk_period 10.00 +# The period the flow closes at global route, with timing repair. +set clk_period 1900 -set clk_port [get_ports $clk_port_name] +# IO budgets as optimization targets, the platform's set_max_delay +# model: 0.8 of the period for a path with a register at one end, 0.6 +# for a combinational path straight through. +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -period $clk_period -name $clk_name $clk_port +# io_aresetn is asynchronous and reaches the core through RstSync's +# synchroniser; its recovery and removal are not what sets the core's +# frequency. +set_false_path -from [get_ports io_aresetn] + +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/coralnpu/sram.memories b/flow/designs/asap7/coralnpu/sram.memories new file mode 100644 index 0000000000..481a240059 --- /dev/null +++ b/flow/designs/asap7/coralnpu/sram.memories @@ -0,0 +1,66 @@ +{ + "version": 1, + "memories": [ + { + "name": "Sram", + "rows": 512, + "bits": 128, + "addr_w": 9, + "rw_ports": 1, + "mask_lanes": 16, + "idiomatic": true, + "reason": "the TCMs' SRAM, NUM_ENTRIES=512: one read-write port, byte mask", + "pins": [ + { + "name": "clock", + "direction": "input", + "width": 1, + "port_id": "RW0", + "function": "clk" + }, + { + "name": "enable", + "direction": "input", + "width": 1, + "port_id": "RW0", + "function": "en" + }, + { + "name": "write", + "direction": "input", + "width": 1, + "port_id": "RW0", + "function": "wmode" + }, + { + "name": "addr", + "direction": "input", + "width": 9, + "port_id": "RW0", + "function": "addr" + }, + { + "name": "wdata", + "direction": "input", + "width": 128, + "port_id": "RW0", + "function": "data_in" + }, + { + "name": "wmask", + "direction": "input", + "width": 16, + "port_id": "RW0", + "function": "mask" + }, + { + "name": "rdata", + "direction": "output", + "width": 128, + "port_id": "RW0", + "function": "data_out" + } + ] + } + ] +} diff --git a/flow/designs/asap7/coralnpu/surgery.py b/flow/designs/asap7/coralnpu/surgery.py new file mode 100644 index 0000000000..6142cc3315 --- /dev/null +++ b/flow/designs/asap7/coralnpu/surgery.py @@ -0,0 +1,478 @@ +"""SYNTH_VERILOG_SURGERY for coralnpu: the register files given modules. + +The two register files keep their words as separate registers, with no +array for yosys to infer. Regfile's 31 words move into Regfile_rf and +FRegfile's 32 into FRegfile_rf, modules of their own that +AUTO_MEMORIES_REGFILES has generate_ram build (Regfile_rf.regfile and +FRegfile_rf.regfile). Each keeps its scoreboard, bypasses and read +gating as they were. + +Each register file is recognised by its text, token for token, comments +and whitespace aside: anything else stops the build. Everything else is +copied unchanged. +""" + +import argparse +import os +import re +import sys + +# Regfile's eight read ports, its debug read and its six write ports; +# write ports 1, 2, 3 and 5 are masked by their io_writeMask_N_valid. +READS = 8 +DEBUG = READS +WRITES = 6 +MASKED = (1, 2, 3, 5) + + +def regfile_rf_module(): + ports = [" input clock", " input reset"] + for k in range(READS + 1): + ports += [" input [4:0] raddr%d" % k, " output [31:0] rdata%d" % k] + for p in range(WRITES): + ports += [ + " input [4:0] waddr%d" % p, + " input [31:0] wdata%d" % p, + " input we%d" % p, + ] + hit = lambda p: "(we%d && waddr%d == i)" % (p, p) + any_hit = " || ".join(hit(p) for p in range(WRITES)) + data = " | ".join("(%s ? wdata%d : 32'd0)" % (hit(p), p) for p in range(WRITES)) + reads = "\n".join( + " assign rdata%d = raddr%d == 5'd0 ? 32'd0 : mem[raddr%d];" % (k, k, k) + for k in range(READS + 1) + ) + return """ +// SYNTH_VERILOG_SURGERY (asap7/coralnpu/surgery.py): Regfile's +// storage, behavioural; AUTO_MEMORIES_REGFILES replaces it. Word 0 reads +// zero and keeps nothing; writes of one word in one cycle are ORed, as +// Regfile's data_N are; every word resets to zero while reset is high. +module Regfile_rf ( +%s +); + reg [31:0] mem [1:31]; + integer i; + always @(posedge clock or posedge reset) begin + if (reset) begin + for (i = 1; i < 32; i = i + 1) mem[i] <= 32'd0; + end else begin + for (i = 1; i < 32; i = i + 1) + if (%s) + mem[i] <= %s; + end + end +%s +endmodule +""" % (",\n".join(ports), any_hit, data, reads) + + +def regfile_instance(): + conns = [" .clock(clock)", " .reset(reset)"] + for k in range(READS): + conns += [ + " .raddr%d(io_readAddr_%d_addr)" % (k, k), + " .rdata%d(_rf_rdata_%d)" % (k, k), + ] + conns += [ + " .raddr%d(io_debugBusPort_idx)" % DEBUG, + " .rdata%d(_rf_rdata_%d)" % (DEBUG, DEBUG), + ] + for p in range(WRITES): + we = "io_writeData_%d_valid" % p + if p in MASKED: + we += " & ~io_writeMask_%d_valid" % p + conns += [ + " .waddr%d(io_writeData_%d_bits_addr)" % (p, p), + " .wdata%d(io_writeData_%d_bits_data)" % (p, p), + " .we%d(%s)" % (p, we), + ] + return " Regfile_rf rf (\n%s\n );\n" % ",\n".join(conns) + + +def addr_is(port_expr, word): + if word == 31: + return "(&%s)" % port_expr + return "%s == 5'h%X" % (port_expr, word) + + +def port_we(p): + we = "io_writeData_%d_valid" % p + if p in MASKED: + we += " & ~io_writeMask_%d_valid" % p + return we + + +def write_through(k): + """Port k's read of a word being written: compares of the write + ports' addresses, not a select over every word's decoded data.""" + lines = [] + for p in range(WRITES): + lines.append( + " wire _wt_%d_%d = %s & io_writeData_%d_bits_addr == io_readAddr_%d_addr" + " & (|io_readAddr_%d_addr);\n" % (k, p, port_we(p), p, k, k) + ) + lines.append( + " wire _wt_%d = %s;\n" + % (k, " | ".join("_wt_%d_%d" % (k, p) for p in range(WRITES))) + ) + lines.append( + " wire [31:0] _wt_%d_data =\n %s;\n" + % ( + k, + "\n | ".join( + "(_wt_%d_%d ? io_writeData_%d_bits_data : 32'h0)" % (k, p, p) + for p in range(WRITES) + ), + ) + ) + return "".join(lines) + + +def rwdata_expected(k, tail): + dname = lambda n: "data" if n == 1 else "data_%d" % (n - 1) + cond = ["io_readAddr_%d_addr == 5'h0" % k] + cond += [ + "_wdata_%d_value_%d_T & (|_writeValid_%d_T)" % (k, n, n) for n in range(1, 31) + ] + cond += ["(&io_readAddr_%d_addr) & (|_writeValid_31_T)" % k] + data = [ + "(_wdata_%d_value_%d_T ? %s : 32'h0)" % (k, n, dname(n)) for n in range(1, 31) + ] + data += ["((&io_readAddr_%d_addr) ? data_30 : 32'h0)" % k] + return "%s ? %s : %s" % (" | ".join(cond), " | ".join(data), tail) + + +def make_write_through(mod): + """Each read port's bypass, a select by read address over the 31 + words' decoded write data (data_N), as a compare of the read address + with each write port's: the same function (a read of x0 is zero, the + ports that write the word are ORed), and data_N is left to nothing.""" + decls = [] + for k in range(READS): + m = re.search( + r"^(\s*readDataBits_%d <=)(\s*io_readAddr_%d_addr == .*?);\n" % (k, k), + mod, + re.M | re.S, + ) + got = m and " ".join(m.group(2).split()) + if got != rwdata_expected(k, "rdata_%d" % k): + fail( + "Regfile: readDataBits_%d's bypass is not the one this rewrite knows" + % k + ) + mod = ( + mod[: m.start()] + + "%s\n _wt_%d ? _wt_%d_data : rdata_%d;\n" % (m.group(1), k, k, k) + + mod[m.end() :] + ) + decls.append(write_through(k)) + return mod, "".join(decls) + + +def make_regfile_seam(text, path): + found = list(re.finditer(r"^module Regfile\(.*?^endmodule\b", text, re.M | re.S)) + if len(found) != 1: + fail("%s defines Regfile %d times, not once" % (path, len(found))) + m = found[0] + mod = m.group(0) + + def wire(name): + hits = re.findall( + r"^\s*wire\s+(?:\[\d+:\d+\]\s+)?%s\s*=\s*(.*?);" % re.escape(name), + mod, + re.M | re.S, + ) + if len(hits) != 1: + fail("Regfile: wire %s defined %d times" % (name, len(hits))) + return " ".join(hits[0].split()) + + # Reads: the address compares, then each port's select over the words. + for k in range(READS): + for n in range(1, 31): + got = wire("_wdata_%d_value_%d_T" % (k, n)) + if got != addr_is("io_readAddr_%d_addr" % k, n): + fail("Regfile: _wdata_%d_value_%d_T is %s" % (k, n, got)) + terms = [ + r"\(_wdata_%d_value_%d_T \? regfile_%d : 32'h0\)" % (k, n, n) + for n in range(1, 31) + ] + terms.append(r"\(\(&io_readAddr_%d_addr\) \? regfile_31 : 32'h0\)" % k) + sel = re.compile(r"\s*\|\s*".join(terms)) + hits = list(sel.finditer(mod)) + if len(hits) != 1: + fail( + "Regfile: read port %d's select over the words found %d times" + % (k, len(hits)) + ) + mod = mod[: hits[0].start()] + "_rf_rdata_%d" % k + mod[hits[0].end() :] + terms = [ + r"\(io_debugBusPort_idx == 5'h%X \? regfile_%d : 32'h0\)" % (n, n) + for n in range(1, 31) + ] + terms.append(r"\(\(&io_debugBusPort_idx\) \? regfile_31 : 32'h0\)") + hits = list(re.finditer(r"\s*\|\s*".join(terms), mod)) + if len(hits) != 1: + fail("Regfile: the debug read's select found %d times" % len(hits)) + mod = mod[: hits[0].start()] + "_rf_rdata_%d" % DEBUG + mod[hits[0].end() :] + + # Writes: each word's data is the OR over the ports that write it. + for n in range(1, 32): + dname = "data" if n == 1 else "data_%d" % (n - 1) + terms = re.fullmatch( + r"\s*".join( + [ + r"\((\w+) \? io_writeData_%d_bits_data : 32'h0\)" % p + for p in range(WRITES) + ] + ).replace(r"\)\s*\(", r"\)\s*\|\s*\("), + wire(dname), + ) + if not terms: + fail("Regfile: %s is not the OR of the six write ports" % dname) + conds = list(terms.groups()) + if wire("_writeValid_%d_T" % n) != "{%s}" % ", ".join(conds): + fail("Regfile: _writeValid_%d_T is not {%s}" % (n, ", ".join(conds))) + for p, c in enumerate(conds): + want = "io_writeData_%d_valid & %s" % ( + p, + addr_is("io_writeData_%d_bits_addr" % p, n), + ) + if p in MASKED: + want += " & ~io_writeMask_%d_valid" % p + if wire(c) != want: + fail("Regfile: %s is %s, not %s" % (c, wire(c), want)) + removals = [ + r"^\s*reg\s+\[31:0\]\s+regfile_%d;\n" % n, + r"^\s*regfile_%d <= 32'h0;\n" % n, + r"^\s*if \(\|_writeValid_%d_T\)\s*regfile_%d <= %s;\n" % (n, n, dname), + ] + for r in removals: + hits = list(re.finditer(r, mod, re.M)) + if len(hits) != 1: + fail("Regfile: /%s/ matched %d times" % (r.strip(), len(hits))) + mod = mod[: hits[0].start()] + mod[hits[0].end() :] + # The simulation-only initial values (`ifdef ENABLE_INITIAL_REG_). + mod = re.sub(r"^\s*regfile_%d = [^;]*;\n" % n, "", mod, flags=re.M) + + left = re.findall(r"\bregfile_\d+\b", mod) + if left: + fail("Regfile still names %s" % left[0]) + head = re.search(r"^module Regfile\(.*?\);\n", mod, re.S | re.M) + if not re.search(r"^\s*input\s+clock,\s*$", head.group(0), re.M) or not re.search( + r"^\s*reset,\s*$", head.group(0), re.M + ): + fail("Regfile's ports are not clock and reset first") + decls = "".join(" wire [31:0] _rf_rdata_%d;\n" % k for k in range(READS + 1)) + mod, wt = make_write_through(mod) + decls += wt + mod = mod[: head.end()] + decls + mod[head.end() :] + end = mod.rindex("endmodule") + mod = mod[:end] + regfile_instance() + mod[end:] + return text[: m.start()] + mod + text[m.end() :] + regfile_rf_module() + + +FIELDS = (("mantissa", 23), ("exponent", 8), ("sign", 1)) +FREAD_PORTS = 3 + + +def fnorm(text): + return " ".join(text.split()) + + +def make_fregfile_seam(text, path): + """FRegfile's 32 words as fields, mantissa, exponent and sign, moved + into FRegfile_rf: 32 x 32 (sign, exponent, mantissa from the top), four + reads (the three read ports and the bus port), two writes of which + write port 0 wins a word both write (FRegfile_rf's last port), every + word reset to zero while reset is high. FRegfile keeps the rest as it + was: the read ports' valid gating and the scoreboard.""" + found = list(re.finditer(r"^module FRegfile\(.*?^endmodule\b", text, re.M | re.S)) + if len(found) != 1: + fail("%s defines FRegfile %d times, not once" % (path, len(found))) + m = found[0] + mod = m.group(0) + head_end = mod.index("\n);\n") + 4 + head, body = mod[:head_end], mod[head_end:] + regs = re.findall(r"^\s*reg\s+(?:\[(\d+):0\]\s+)?(\w+);", body, re.M) + want = [ + (str(w - 1) if w > 1 else "", "fregfile_%d_%s" % (n, f)) + for n in range(32) + for f, w in FIELDS + ] + [("31", "scoreboard")] + if regs != want: + fail( + "FRegfile: its registers are not the fields and scoreboard this surgery knows" + ) + nb = fnorm(body) + for n in range(32): + v = "valid_0" if n == 0 else "valid_0_%d" % n + + def hit(port): + # firtool writes the last word's compare as an AND reduction + if n == 31: + return "(&io_write_ports_%d_addr)" % port + return "io_write_ports_%d_addr == 5'h%X" % (port, n) + + if fnorm("wire %s = io_write_ports_0_valid & %s;" % (v, hit(0))) not in nb: + fail("FRegfile: %s is not the decode this surgery knows" % v) + block = "if (%s | io_write_ports_1_valid & %s) begin " % (v, hit(1)) + block += " ".join( + "fregfile_%d_%s <= %s ? io_write_ports_0_data_%s : io_write_ports_1_data_%s;" + % (n, f, v, f, f) + for f, _ in FIELDS + ) + block += " end" + if fnorm(block) not in nb: + fail("FRegfile: word %d's write is not the one this surgery knows" % n) + for f, w in FIELDS: + if fnorm("fregfile_%d_%s <= %d'h0;" % (n, f, w)) not in nb: + fail("FRegfile: word %d's %s does not reset to zero" % (n, f)) + for g, f, w in ( + ("_GEN", "mantissa", 23), + ("_GEN_0", "exponent", 8), + ("_GEN_1", "sign", 1), + ): + typ = "wire [31:0][%d:0] %s =" % (w - 1, g) if w > 1 else "wire [31:0] %s =" % g + cat = ", ".join("{fregfile_%d_%s}" % (n, f) for n in range(31, -1, -1)) + if fnorm("%s {%s};" % (typ, cat)) not in nb: + fail("FRegfile: %s is not the word select this surgery knows" % g) + for k in range(FREAD_PORTS): + for g, f, w in (("_GEN", "mantissa", 23), ("_GEN_0", "exponent", 8)): + want_rd = ( + "assign io_read_ports_%d_data_%s = io_read_ports_%d_valid ? %s[io_read_ports_%d_addr] : %d'h0;" + % (k, f, k, g, k, w) + ) + if fnorm(want_rd) not in nb: + fail( + "FRegfile: read port %d's %s is not the read this surgery knows" + % (k, f) + ) + if ( + fnorm( + "assign io_read_ports_%d_data_sign = io_read_ports_%d_valid & _GEN_1[io_read_ports_%d_addr];" + % (k, k, k) + ) + not in nb + ): + fail("FRegfile: read port %d's sign is not the read this surgery knows" % k) + bus = ( + "assign io_busPort_data_0 = " + "{_GEN_1[io_busPortAddr], _GEN_0[io_busPortAddr], _GEN[io_busPortAddr]};" + ) + if fnorm(bus) not in nb: + fail("FRegfile: the bus port is not the read this surgery knows") + score = ( + "scoreboard <= {32{~io_pipelineFlush}} & scoreboard " + "& ~((io_write_ports_0_valid ? 32'h1 << io_write_ports_0_addr : 32'h0) " + "| (io_write_ports_1_valid ? 32'h1 << io_write_ports_1_addr : 32'h0)) " + "| io_scoreboard_set;" + ) + if fnorm(score) not in nb: + fail("FRegfile: the scoreboard is not the one this surgery knows") + rd = [] + addrs = ["io_read_ports_%d_addr" % k for k in range(FREAD_PORTS)] + [ + "io_busPortAddr" + ] + for k in range(4): + rd.append(" wire [31:0] _frf_rdata_%d;\n" % k) + new = head + "".join(rd) + new += ( + " // surgery.py: FRegfile's words, moved into FRegfile_rf\n" + " FRegfile_rf rf (\n" + " .clock(clock),\n" + " .reset(reset),\n" + + "".join( + " .raddr%d(%s),\n .rdata%d(_frf_rdata_%d),\n" % (k, a, k, k) + for k, a in enumerate(addrs) + ) + + " .waddr0(io_write_ports_1_addr),\n" + " .wdata0({io_write_ports_1_data_sign, io_write_ports_1_data_exponent, io_write_ports_1_data_mantissa}),\n" + " .we0(io_write_ports_1_valid),\n" + " .waddr1(io_write_ports_0_addr),\n" + " .wdata1({io_write_ports_0_data_sign, io_write_ports_0_data_exponent, io_write_ports_0_data_mantissa}),\n" + " .we1(io_write_ports_0_valid)\n" + " );\n" + " reg [31:0] scoreboard;\n" + " always @(posedge clock or posedge reset) begin\n" + " if (reset) begin\n" + " scoreboard <= 32'h0;\n" + " end\n" + " else begin\n" + " scoreboard <=\n" + " {32{~io_pipelineFlush}} & scoreboard\n" + " & ~((io_write_ports_0_valid ? 32'h1 << io_write_ports_0_addr : 32'h0)\n" + " | (io_write_ports_1_valid ? 32'h1 << io_write_ports_1_addr : 32'h0))\n" + " | io_scoreboard_set;\n" + " end\n" + " end\n" + ) + for k in range(FREAD_PORTS): + new += ( + " assign io_read_ports_%d_data_mantissa = io_read_ports_%d_valid ? _frf_rdata_%d[22:0] : 23'h0;\n" + " assign io_read_ports_%d_data_exponent = io_read_ports_%d_valid ? _frf_rdata_%d[30:23] : 8'h0;\n" + " assign io_read_ports_%d_data_sign = io_read_ports_%d_valid & _frf_rdata_%d[31];\n" + % (k, k, k, k, k, k, k, k, k) + ) + new += ( + " assign io_scoreboard = scoreboard;\n" + " assign io_busPort_data_0 = _frf_rdata_3;\n" + "endmodule" + ) + rf = ( + "\n\n// FRegfile's storage, moved out of FRegfile by surgery.py:\n" + "// 32 x 32 (sign, exponent, mantissa), four combinational reads, two\n" + "// writes, the later port (write port 0 of FRegfile) winning a word\n" + "// both write, every word reset to zero while reset is high.\n" + "module FRegfile_rf(\n" + " input clock,\n" + " input reset,\n" + + "".join( + " input [4:0] raddr%d,\n output [31:0] rdata%d,\n" % (k, k) + for k in range(4) + ) + + " input [4:0] waddr0,\n input [31:0] wdata0,\n input we0,\n" + " input [4:0] waddr1,\n input [31:0] wdata1,\n input we1\n" + ");\n" + " reg [31:0] mem [0:31];\n" + + "".join(" assign rdata%d = mem[raddr%d];\n" % (k, k) for k in range(4)) + + " integer i;\n" + " always @(posedge clock or posedge reset) begin\n" + " if (reset) begin\n" + " for (i = 0; i < 32; i = i + 1) mem[i] <= 32'h0;\n" + " end else begin\n" + " if (we0) mem[waddr0] <= wdata0;\n" + " if (we1) mem[waddr1] <= wdata1;\n" + " end\n" + " end\n" + "endmodule\n" + ) + return text[: m.start()] + new + text[m.end() :] + rf + + +def fail(msg): + sys.exit("coralnpu surgery: " + msg) + + +def main(): + p = argparse.ArgumentParser() + p.add_argument("--out-dir", required=True) + p.add_argument("files", nargs="+") + a = p.parse_args() + done = 0 + for path in a.files: + with open(path, encoding="utf-8") as f: + text = f.read() + if re.search(r"^module Regfile\(", text, re.M): + text = make_regfile_seam(text, path) + text = make_fregfile_seam(text, path) + done += 1 + with open( + os.path.join(a.out_dir, os.path.basename(path)), "w", encoding="utf-8" + ) as f: + f.write(text) + if done != 1: + fail("the register files found in %d files, not one" % done) + + +if __name__ == "__main__": + main() diff --git a/flow/designs/src/coralnpu/CoreMiniAxi.sv b/flow/designs/src/coralnpu/CoreMiniAxi.sv index cbe4d16144..357908d302 100644 --- a/flow/designs/src/coralnpu/CoreMiniAxi.sv +++ b/flow/designs/src/coralnpu/CoreMiniAxi.sv @@ -1,48 +1,48 @@ -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Include register initializers in init blocks unless synthesis is set -`ifndef RANDOMIZE - `ifdef RANDOMIZE_REG_INIT - `define RANDOMIZE - `endif // RANDOMIZE_REG_INIT -`endif // not def RANDOMIZE -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_REG_ - `define ENABLE_INITIAL_REG_ - `endif // not def ENABLE_INITIAL_REG_ -`endif // not def SYNTHESIS - -// Standard header to adapt well known macros for register randomization. - -// RANDOM may be set to an expression that produces a 32-bit random unsigned value. -`ifndef RANDOM - `define RANDOM $random -`endif // not def RANDOM - -// Users can define INIT_RANDOM as general code that gets injected into the -// initializer block for modules with registers. -`ifndef INIT_RANDOM - `define INIT_RANDOM -`endif // not def INIT_RANDOM - -// If using random initialization, you can also define RANDOMIZE_DELAY to -// customize the delay used, otherwise 0.002 is used. -`ifndef RANDOMIZE_DELAY - `define RANDOMIZE_DELAY 0.002 -`endif // not def RANDOMIZE_DELAY - -// Define INIT_RANDOM_PROLOG_ for use in our modules below. -`ifndef INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE - `ifdef VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM - `else // VERILATOR - `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end - `endif // VERILATOR - `else // RANDOMIZE - `define INIT_RANDOM_PROLOG_ - `endif // RANDOMIZE -`endif // not def INIT_RANDOM_PROLOG_ +// Generated by CIRCT firtool-1.133.0 +module Queue1_DebugModuleRspIO( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [31:0] io_enq_bits_data, + input [1:0] io_enq_bits_op, + input io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits_data, + output [1:0] io_deq_bits_op +); + + reg [33:0] ram; + reg maybe_full; + wire do_enq = ~maybe_full & io_enq_valid; + always @(posedge clock or posedge reset) begin + if (reset) + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= {io_enq_bits_data, io_enq_bits_op}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + maybe_full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_enq_ready = ~maybe_full; + assign io_deq_valid = maybe_full; + assign io_deq_bits_data = ram[33:2]; + assign io_deq_bits_op = ram[1:0]; +endmodule + module CoreCSR( input clock, reset, @@ -56,6 +56,7 @@ module CoreCSR( io_reset, io_cg, output [31:0] io_pcStart, + input [31:0] io_bootAddr, input io_halted, io_fault, input [31:0] io_coralnpu_csr_value_0, @@ -65,84 +66,131 @@ module CoreCSR( io_coralnpu_csr_value_4, io_coralnpu_csr_value_5, io_coralnpu_csr_value_6, - io_coralnpu_csr_value_7 + io_coralnpu_csr_value_7, + io_coralnpu_csr_value_8, + input io_debug_req_ready, + output io_debug_req_valid, + output [31:0] io_debug_req_bits_address, + io_debug_req_bits_data, + output [1:0] io_debug_req_bits_op, + output io_debug_rsp_ready, + input io_debug_rsp_valid, + input [31:0] io_debug_rsp_bits_data, + input [1:0] io_debug_rsp_bits_op ); + wire _rsp_queue_io_deq_valid; + wire [31:0] _rsp_queue_io_deq_bits_data; + wire [1:0] _rsp_queue_io_deq_bits_op; reg [31:0] resetReg; reg [31:0] pcStartReg; + reg bootAddrCapture; reg [31:0] statusReg; + reg [31:0] debugReqAddrReg; + reg [31:0] debugReqDataReg; + reg [1:0] debugReqOpReg; + reg req_valid_pulse; + wire _io_fabric_writeResp_T_8 = io_fabric_writeDataAddr_bits == 32'h808; + wire _io_fabric_writeResp_T_6 = io_fabric_writeDataAddr_bits == 32'h814; wire readDataValid = - io_fabric_readDataAddr_bits == 32'h108 | io_fabric_readDataAddr_bits == 32'h118 - | io_fabric_readDataAddr_bits == 32'h104 | io_fabric_readDataAddr_bits == 32'h10C - | io_fabric_readDataAddr_bits == 32'h0 | io_fabric_readDataAddr_bits == 32'h110 - | io_fabric_readDataAddr_bits == 32'h114 | io_fabric_readDataAddr_bits == 32'h100 - | io_fabric_readDataAddr_bits == 32'h4 | io_fabric_readDataAddr_bits == 32'h11C - | io_fabric_readDataAddr_bits == 32'h8; + io_fabric_readDataAddr_bits == 32'h114 | io_fabric_readDataAddr_bits == 32'h100 + | io_fabric_readDataAddr_bits == 32'h8 | io_fabric_readDataAddr_bits == 32'h808 + | io_fabric_readDataAddr_bits == 32'h80C | io_fabric_readDataAddr_bits == 32'h810 + | io_fabric_readDataAddr_bits == 32'h110 | io_fabric_readDataAddr_bits == 32'h800 + | io_fabric_readDataAddr_bits == 32'h814 | io_fabric_readDataAddr_bits == 32'h120 + | io_fabric_readDataAddr_bits == 32'h11C | io_fabric_readDataAddr_bits == 32'h104 + | io_fabric_readDataAddr_bits == 32'h804 | io_fabric_readDataAddr_bits == 32'h108 + | io_fabric_readDataAddr_bits == 32'h118 | io_fabric_readDataAddr_bits == 32'h10C + | io_fabric_readDataAddr_bits == 32'h4 | io_fabric_readDataAddr_bits == 32'h0; reg readDataNext_pipe_v; reg [127:0] readDataNext_pipe_b; - wire _io_fabric_writeResp_T_1 = io_fabric_writeDataAddr_bits == 32'h0; - wire _io_fabric_writeResp_T_2 = io_fabric_writeDataAddr_bits == 32'h4; + wire _io_fabric_writeResp_T_2 = io_fabric_writeDataAddr_bits == 32'h0; + wire _io_fabric_writeResp_T_10 = io_fabric_writeDataAddr_bits == 32'h4; + wire _io_fabric_writeResp_T_4 = io_fabric_writeDataAddr_bits == 32'h800; + wire _io_fabric_writeResp_T_1 = io_fabric_writeDataAddr_bits == 32'h804; always @(posedge clock or posedge reset) begin if (reset) begin resetReg <= 32'h3; pcStartReg <= 32'h0; + bootAddrCapture <= 1'h1; statusReg <= 32'h0; + debugReqAddrReg <= 32'h0; + debugReqDataReg <= 32'h0; + debugReqOpReg <= 2'h0; + req_valid_pulse <= 1'h0; readDataNext_pipe_v <= 1'h0; end else begin - if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_1) - resetReg <= io_fabric_writeDataBits[31:0]; if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_2) + resetReg <= io_fabric_writeDataBits[31:0]; + if (bootAddrCapture) + pcStartReg <= io_bootAddr; + else if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_10) pcStartReg <= io_fabric_writeDataBits[63:32]; + bootAddrCapture <= 1'h0; statusReg <= {30'h0, io_fault, io_halted}; + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_4) + debugReqAddrReg <= io_fabric_writeDataBits[31:0]; + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_1) + debugReqDataReg <= io_fabric_writeDataBits[63:32]; + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_8) + debugReqOpReg <= io_fabric_writeDataBits[65:64]; + req_valid_pulse <= + io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_8 & io_debug_req_ready; readDataNext_pipe_v <= readDataValid; end end // always @(posedge, posedge) wire _GEN = io_fabric_readDataAddr_bits[31:4] == 28'h0; wire _GEN_0 = io_fabric_readDataAddr_bits[31:4] == 28'h10; - wire _GEN_1 = io_fabric_readDataAddr_bits[31:4] == 28'h11; + wire _GEN_1 = io_fabric_readDataAddr_bits[31:4] == 28'h80; + wire _GEN_2 = io_fabric_readDataAddr_bits[31:4] == 28'h81; + wire _GEN_3 = io_fabric_readDataAddr_bits[31:4] == 28'h11; always @(posedge clock) begin if (readDataValid) readDataNext_pipe_b <= - {_GEN_1 ? io_coralnpu_csr_value_7 : _GEN_0 ? io_coralnpu_csr_value_3 : 32'h0, - _GEN_1 + {_GEN_3 + ? io_coralnpu_csr_value_7 + : _GEN_1 + ? _rsp_queue_io_deq_bits_data + : _GEN_0 ? io_coralnpu_csr_value_3 : 32'h0, + _GEN_3 ? io_coralnpu_csr_value_6 - : _GEN_0 ? io_coralnpu_csr_value_2 : _GEN ? statusReg : 32'h0, - _GEN_1 + : _GEN_1 + ? {30'h0, debugReqOpReg} + : _GEN_0 ? io_coralnpu_csr_value_2 : _GEN ? statusReg : 32'h0, + _GEN_3 ? io_coralnpu_csr_value_5 - : _GEN_0 ? io_coralnpu_csr_value_1 : _GEN ? pcStartReg : 32'h0, - _GEN_1 + : _GEN_2 + ? {30'h0, _rsp_queue_io_deq_valid, io_debug_req_ready} + : _GEN_1 + ? debugReqDataReg + : _GEN_0 ? io_coralnpu_csr_value_1 : _GEN ? pcStartReg : 32'h0, + _GEN_3 ? io_coralnpu_csr_value_4 - : _GEN_0 ? io_coralnpu_csr_value_0 : _GEN ? resetReg : 32'h0}; + : _GEN_2 + ? {30'h0, _rsp_queue_io_deq_bits_op} + : _GEN_1 + ? debugReqAddrReg + : _GEN_0 + ? io_coralnpu_csr_value_0 + : io_fabric_readDataAddr_bits[31:4] == 28'h12 + ? io_coralnpu_csr_value_8 + : _GEN ? resetReg : 32'h0}; end // always @(posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:7]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin - _RANDOM[i[2:0]] = `RANDOM; - end - resetReg = _RANDOM[3'h0]; - pcStartReg = _RANDOM[3'h1]; - statusReg = _RANDOM[3'h2]; - readDataNext_pipe_v = _RANDOM[3'h3][0]; - readDataNext_pipe_b = - {_RANDOM[3'h3][31:1], - _RANDOM[3'h4], - _RANDOM[3'h5], - _RANDOM[3'h6], - _RANDOM[3'h7][0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin resetReg = 32'h3; pcStartReg = 32'h0; + bootAddrCapture = 1'h1; statusReg = 32'h0; + debugReqAddrReg = 32'h0; + debugReqDataReg = 32'h0; + debugReqOpReg = 2'h0; + req_valid_pulse = 1'h0; readDataNext_pipe_v = 1'h0; end end // initial @@ -150,13 +198,543 @@ module CoreCSR( `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ + Queue1_DebugModuleRspIO rsp_queue ( + .clock (clock), + .reset (reset), + .io_enq_ready (io_debug_rsp_ready), + .io_enq_valid (io_debug_rsp_valid), + .io_enq_bits_data (io_debug_rsp_bits_data), + .io_enq_bits_op (io_debug_rsp_bits_op), + .io_deq_ready (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_6), + .io_deq_valid (_rsp_queue_io_deq_valid), + .io_deq_bits_data (_rsp_queue_io_deq_bits_data), + .io_deq_bits_op (_rsp_queue_io_deq_bits_op) + ); assign io_fabric_readData_valid = readDataNext_pipe_v; assign io_fabric_readData_bits = readDataNext_pipe_b; assign io_fabric_writeResp = - io_fabric_writeDataAddr_valid & (_io_fabric_writeResp_T_2 | _io_fabric_writeResp_T_1); + io_fabric_writeDataAddr_valid + & (_io_fabric_writeResp_T_10 | _io_fabric_writeResp_T_8 | _io_fabric_writeResp_T_6 + | _io_fabric_writeResp_T_4 | _io_fabric_writeResp_T_2 | _io_fabric_writeResp_T_1); assign io_reset = resetReg[0]; assign io_cg = resetReg[1]; - assign io_pcStart = pcStartReg; + assign io_pcStart = bootAddrCapture ? io_bootAddr : pcStartReg; + assign io_debug_req_valid = req_valid_pulse; + assign io_debug_req_bits_address = debugReqAddrReg; + assign io_debug_req_bits_data = debugReqDataReg; + assign io_debug_req_bits_op = + debugReqOpReg == 2'h0 | debugReqOpReg == 2'h1 | debugReqOpReg == 2'h2 + ? debugReqOpReg + : 2'h0; +endmodule + +module Queue1_DebugModuleReqIO( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [31:0] io_enq_bits_address, + io_enq_bits_data, + input [1:0] io_enq_bits_op, + input io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits_address, + io_deq_bits_data, + output [1:0] io_deq_bits_op +); + + reg [65:0] ram; + reg maybe_full; + wire do_enq = ~maybe_full & io_enq_valid; + always @(posedge clock or posedge reset) begin + if (reset) + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= {io_enq_bits_address, io_enq_bits_data, io_enq_bits_op}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + maybe_full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_enq_ready = ~maybe_full; + assign io_deq_valid = maybe_full; + assign io_deq_bits_address = ram[65:34]; + assign io_deq_bits_data = ram[33:2]; + assign io_deq_bits_op = ram[1:0]; +endmodule + +module DebugModule( + input clock, + reset, + output io_ext_req_ready, + input io_ext_req_valid, + input [31:0] io_ext_req_bits_address, + io_ext_req_bits_data, + input [1:0] io_ext_req_bits_op, + input io_ext_rsp_ready, + output io_ext_rsp_valid, + output [31:0] io_ext_rsp_bits_data, + output [1:0] io_ext_rsp_bits_op, + output io_csr_valid, + output [4:0] io_csr_bits_addr, + output [11:0] io_csr_bits_index, + output [4:0] io_csr_bits_rs1, + output [1:0] io_csr_bits_op, + output [31:0] io_csr_rs1, + input io_csr_rd_valid, + input [31:0] io_csr_rd_bits, + input io_scalar_rd_ready, + output io_scalar_rd_valid, + output [4:0] io_scalar_rd_bits_addr, + output [31:0] io_scalar_rd_bits_data, + output [4:0] io_scalar_rs_idx, + input [31:0] io_scalar_rs_data, + output io_float_rd_valid, + output [4:0] io_float_rd_addr, + output [22:0] io_float_rd_data_mantissa, + output [7:0] io_float_rd_data_exponent, + output io_float_rd_data_sign, + io_float_rs_valid, + output [4:0] io_float_rs_addr, + input [22:0] io_float_rs_data_mantissa, + input [7:0] io_float_rs_data_exponent, + input io_float_rs_data_sign, + output io_itcm_readDataAddr_valid, + output [31:0] io_itcm_readDataAddr_bits, + input io_itcm_readData_valid, + input [127:0] io_itcm_readData_bits, + output io_itcm_writeDataAddr_valid, + output [31:0] io_itcm_writeDataAddr_bits, + output [127:0] io_itcm_writeDataBits, + output [15:0] io_itcm_writeDataStrb, + input io_itcm_writeResp, + output io_dtcm_readDataAddr_valid, + output [31:0] io_dtcm_readDataAddr_bits, + input io_dtcm_readData_valid, + input [127:0] io_dtcm_readData_bits, + output io_dtcm_writeDataAddr_valid, + output [31:0] io_dtcm_writeDataAddr_bits, + output [127:0] io_dtcm_writeDataBits, + output [15:0] io_dtcm_writeDataStrb, + input io_dtcm_writeResp, + output io_haltreq_0, + io_resumereq_0, + input io_resumeack_0, + output io_ndmreset, + input io_halted_0, + io_running_0, + io_havereset_0 +); + + wire io_float_rd_valid_0; + wire io_scalar_rd_valid_0; + wire _io_ext_rsp_q_io_enq_ready; + wire _req_q_io_deq_valid; + wire [31:0] _req_q_io_deq_bits_address; + wire [31:0] _req_q_io_deq_bits_data; + wire [1:0] _req_q_io_deq_bits_op; + reg haltreq_0; + reg resumereq_0; + reg resumeack_0; + reg [31:0] dmcontrol; + reg [31:0] data0; + reg [31:0] data1; + reg [31:0] cmderr; + wire _rsp_map_bits_rspBits_data_T_6 = _req_q_io_deq_bits_address == 32'h10; + wire _rsp_map_bits_rspBits_op_WIRE_8_1 = _req_q_io_deq_bits_op == 2'h2; + wire _rsp_map_bits_rspBits_data_T_21 = _req_q_io_deq_bits_address == 32'h17; + wire abstractCmdValid = + _req_q_io_deq_valid & _rsp_map_bits_rspBits_op_WIRE_8_1 + & _rsp_map_bits_rspBits_data_T_21; + wire cmdtypeIsAccessMemory = _req_q_io_deq_bits_data[31:24] == 8'h2; + wire regnoIsCsr = _req_q_io_deq_bits_data[15:0] < 16'h1000; + wire regnoIsScalar = + (|(_req_q_io_deq_bits_data[15:12])) & _req_q_io_deq_bits_data[15:0] < 16'h1020; + wire regnoIsFloat = + _req_q_io_deq_bits_data[15:0] > 16'h101F & _req_q_io_deq_bits_data[15:0] < 16'h1040; + wire regnoInvalid = + (|(_req_q_io_deq_bits_data[15:12])) & ~regnoIsScalar & ~regnoIsFloat; + wire itcm = data1 < 32'h2000; + wire dtcm = (|(data1[31:16])) & data1 < 32'h18000; + wire _cmderr_T_17 = itcm | dtcm; + wire _abstractCmdCompleteFloat_T_3 = + ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsFloat; + wire _abstractCmdComplete_T_8 = + ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsScalar; + wire abstractCmdComplete = + abstractCmdValid + & (~(|(_req_q_io_deq_bits_data[31:24])) & regnoInvalid + | ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsCsr & io_csr_rd_valid + | _abstractCmdComplete_T_8 & io_scalar_rd_ready & io_scalar_rd_valid_0 + | _abstractCmdComplete_T_8 & ~(_req_q_io_deq_bits_data[16]) | cmdtypeIsAccessMemory + & io_itcm_readData_valid | cmdtypeIsAccessMemory & io_dtcm_readData_valid + | cmdtypeIsAccessMemory & _req_q_io_deq_bits_data[16] | cmdtypeIsAccessMemory + & ~_cmderr_T_17 | _abstractCmdCompleteFloat_T_3 & io_float_rd_valid_0 + | _abstractCmdCompleteFloat_T_3 & ~(_req_q_io_deq_bits_data[16])) | ~io_halted_0; + wire _io_float_rs_valid_T = io_halted_0 & abstractCmdValid; + wire _rsp_map_bits_rspBits_data_T_15 = _req_q_io_deq_bits_address == 32'h16; + wire _rsp_map_bits_rspBits_op_WIRE_8_0 = _req_q_io_deq_bits_op == 2'h1; + assign io_scalar_rd_valid_0 = + _io_float_rs_valid_T & ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsScalar + & _req_q_io_deq_bits_data[16]; + assign io_float_rd_valid_0 = + _io_float_rs_valid_T & ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsFloat + & _req_q_io_deq_bits_data[16]; + wire _rsp_map_bits_rspBits_data_T = _req_q_io_deq_bits_address == 32'h4; + wire _rsp_map_bits_rspBits_data_T_3 = _req_q_io_deq_bits_address == 32'h5; + wire _rsp_map_bits_rspBits_data_T_9 = _req_q_io_deq_bits_address == 32'h11; + wire _rsp_map_bits_rspBits_data_T_12 = _req_q_io_deq_bits_address == 32'h12; + wire req_q_io_deq_ready = + _io_ext_rsp_q_io_enq_ready & (~abstractCmdValid | abstractCmdComplete); + wire _io_dtcm_writeDataAddr_valid_T = + abstractCmdValid & cmdtypeIsAccessMemory; + wire [16:0] _strobe_T_6 = 17'h3 << data1[3:0]; + wire [18:0] _strobe_T_9 = 19'hF << data1[3:0]; + wire [15:0] strobe = + _req_q_io_deq_bits_data[22:20] == 3'h0 + ? 16'h1 << data1[3:0] + : _req_q_io_deq_bits_data[22:20] == 3'h1 + ? _strobe_T_6[15:0] + : _req_q_io_deq_bits_data[22:20] == 3'h2 ? _strobe_T_9[15:0] : 16'hFFFF; + wire [382:0] writeDataBits = {351'h0, data0} << {376'h0, data1[3:0], 3'h0}; + wire [3:0][31:0] _GEN = + {{io_itcm_readData_bits[127:96]}, + {io_itcm_readData_bits[95:64]}, + {io_itcm_readData_bits[63:32]}, + {32'h0}}; + wire [3:0][31:0] _GEN_0 = + {{io_dtcm_readData_bits[127:96]}, + {io_dtcm_readData_bits[95:64]}, + {io_dtcm_readData_bits[63:32]}, + {32'h0}}; + wire _data0_T_63 = abstractCmdComplete & cmdtypeIsAccessMemory; + wire [31:0] data0ItcmReadData = + (|(data1[3:2])) ? _GEN[data1[3:2]] : io_itcm_readData_bits[31:0]; + wire [31:0] _data0_T_57 = + data1[0] ? {data0ItcmReadData[7:0], data0ItcmReadData[31:8]} : data0ItcmReadData; + wire [31:0] data0DtcmReadData = + (|(data1[3:2])) ? _GEN_0[data1[3:2]] : io_dtcm_readData_bits[31:0]; + wire [31:0] _data0_T_93 = + data1[0] ? {data0DtcmReadData[7:0], data0DtcmReadData[31:8]} : data0DtcmReadData; + wire _abstractcs_wvalid_T = req_q_io_deq_ready & _req_q_io_deq_valid; + wire dmcontrol_wvalid = + _abstractcs_wvalid_T & _rsp_map_bits_rspBits_data_T_6 + & _rsp_map_bits_rspBits_op_WIRE_8_1; + wire _data1_T_12 = + abstractCmdComplete & ~(|(_req_q_io_deq_bits_data[31:24])); + always @(posedge clock or posedge reset) begin + if (reset) begin + haltreq_0 <= 1'h0; + resumereq_0 <= 1'h0; + resumeack_0 <= 1'h0; + dmcontrol <= 32'h1; + data0 <= 32'h0; + data1 <= 32'h0; + cmderr <= 32'h0; + end + else begin + if (dmcontrol_wvalid) begin + haltreq_0 <= _req_q_io_deq_bits_data[31]; + dmcontrol <= + {dmcontrol[31:26], + _req_q_io_deq_bits_data[25:6] == 20'h0 ? _req_q_io_deq_bits_data[25:6] : 20'h1, + dmcontrol[5:2], + _req_q_io_deq_bits_data[1:0]}; + end + resumereq_0 <= + dmcontrol_wvalid ? _req_q_io_deq_bits_data[30] : ~io_resumeack_0 & resumereq_0; + resumeack_0 <= ~haltreq_0 & (io_resumeack_0 | resumeack_0); + if (_req_q_io_deq_valid & _rsp_map_bits_rspBits_data_T + & _rsp_map_bits_rspBits_op_WIRE_8_1) + data0 <= _req_q_io_deq_bits_data; + else if (_data1_T_12 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & regnoIsCsr & io_csr_rd_valid) + data0 <= io_csr_rd_bits; + else if (_data1_T_12 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & regnoIsScalar) + data0 <= io_scalar_rs_data; + else if (_data1_T_12 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & regnoIsFloat) + data0 <= + {io_float_rs_data_sign, io_float_rs_data_exponent, io_float_rs_data_mantissa}; + else if (_data0_T_63 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & io_itcm_readData_valid) + data0 <= data1[1] ? {_data0_T_57[15:0], _data0_T_57[31:16]} : _data0_T_57; + else if (_data0_T_63 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & io_dtcm_readData_valid) + data0 <= data1[1] ? {_data0_T_93[15:0], _data0_T_93[31:16]} : _data0_T_93; + else if (dmcontrol[0]) begin + end + else + data0 <= 32'h0; + if (_req_q_io_deq_valid & _rsp_map_bits_rspBits_data_T_3 + & _rsp_map_bits_rspBits_op_WIRE_8_1) + data1 <= _req_q_io_deq_bits_data; + else if (_data1_T_12 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & regnoIsCsr & io_csr_rd_valid + | _data1_T_12 & io_halted_0 & _req_q_io_deq_valid + & ~(_req_q_io_deq_bits_data[16]) & regnoIsScalar) + data1 <= 32'h0; + else if (_req_q_io_deq_valid & _req_q_io_deq_bits_data[19] & abstractCmdComplete + & cmdtypeIsAccessMemory & io_halted_0) + data1 <= data1 + {24'h0, 8'h1 << _req_q_io_deq_bits_data[22:20]}; + if (_abstractcs_wvalid_T & _rsp_map_bits_rspBits_data_T_15 + & _rsp_map_bits_rspBits_op_WIRE_8_1) + cmderr <= {29'h0, cmderr[2:0] & ~(_req_q_io_deq_bits_data[10:8])}; + else if (abstractCmdValid & ~io_halted_0) + cmderr <= 32'h4; + else if (abstractCmdValid & ~(|(_req_q_io_deq_bits_data[31:24])) + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + & _req_q_io_deq_bits_data[22:20] != 3'h2) + cmderr <= 32'h2; + else if (abstractCmdValid & cmdtypeIsAccessMemory & ~_cmderr_T_17) + cmderr <= 32'h5; + else if (dmcontrol[0]) begin + end + else + cmderr <= 32'h0; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + haltreq_0 = 1'h0; + resumereq_0 = 1'h0; + resumeack_0 = 1'h0; + dmcontrol = 32'h1; + data0 = 32'h0; + data1 = 32'h0; + cmderr = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Queue1_DebugModuleReqIO req_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (io_ext_req_ready), + .io_enq_valid (io_ext_req_valid), + .io_enq_bits_address (io_ext_req_bits_address), + .io_enq_bits_data (io_ext_req_bits_data), + .io_enq_bits_op (io_ext_req_bits_op), + .io_deq_ready (req_q_io_deq_ready), + .io_deq_valid (_req_q_io_deq_valid), + .io_deq_bits_address (_req_q_io_deq_bits_address), + .io_deq_bits_data (_req_q_io_deq_bits_data), + .io_deq_bits_op (_req_q_io_deq_bits_op) + ); + Queue1_DebugModuleRspIO io_ext_rsp_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (_io_ext_rsp_q_io_enq_ready), + .io_enq_valid (_req_q_io_deq_valid & (~abstractCmdValid | abstractCmdComplete)), + .io_enq_bits_data + (_rsp_map_bits_rspBits_data_T & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? data0 + : _rsp_map_bits_rspBits_data_T_3 & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? data1 + : _rsp_map_bits_rspBits_data_T_6 & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? dmcontrol + : _rsp_map_bits_rspBits_data_T_9 & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? {14'h0, + {2{resumeack_0}}, + 4'h0, + {2{io_running_0}}, + {2{io_halted_0}}, + 8'h83} + : _rsp_map_bits_rspBits_data_T_12 & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? 32'h2007B4 + : _rsp_map_bits_rspBits_data_T_15 + & _rsp_map_bits_rspBits_op_WIRE_8_0 + ? {cmderr[23:0], 8'h1} + : 32'h0), + .io_enq_bits_op + (_rsp_map_bits_rspBits_data_T + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_3 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_6 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_9 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_12 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_15 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _req_q_io_deq_bits_address == 32'h38 + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + ? 2'h0 + : _rsp_map_bits_rspBits_data_T_21 & ~(|(_req_q_io_deq_bits_data[31:24])) + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + & regnoInvalid + ? 2'h2 + : _rsp_map_bits_rspBits_data_T_21 & ~(|(_req_q_io_deq_bits_data[31:24])) + & (|{_rsp_map_bits_rspBits_op_WIRE_8_1, _rsp_map_bits_rspBits_op_WIRE_8_0}) + | _rsp_map_bits_rspBits_data_T_21 & cmdtypeIsAccessMemory + ? 2'h0 + : 2'h3), + .io_deq_ready (io_ext_rsp_ready), + .io_deq_valid (io_ext_rsp_valid), + .io_deq_bits_data (io_ext_rsp_bits_data), + .io_deq_bits_op (io_ext_rsp_bits_op) + ); + assign io_csr_valid = + _io_float_rs_valid_T & ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsCsr; + assign io_csr_bits_addr = 5'h0; + assign io_csr_bits_index = _req_q_io_deq_bits_data[11:0]; + assign io_csr_bits_rs1 = 5'h0; + assign io_csr_bits_op = {~(_req_q_io_deq_bits_data[16]), 1'h0}; + assign io_csr_rs1 = _req_q_io_deq_bits_data[16] ? data0 : 32'h0; + assign io_scalar_rd_valid = io_scalar_rd_valid_0; + assign io_scalar_rd_bits_addr = _req_q_io_deq_bits_data[4:0]; + assign io_scalar_rd_bits_data = data0; + assign io_scalar_rs_idx = + _io_float_rs_valid_T & ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsScalar + & ~(_req_q_io_deq_bits_data[16]) + ? _req_q_io_deq_bits_data[4:0] + : 5'h0; + assign io_float_rd_valid = io_float_rd_valid_0; + assign io_float_rd_addr = _req_q_io_deq_bits_data[4:0]; + assign io_float_rd_data_mantissa = data0[22:0]; + assign io_float_rd_data_exponent = data0[30:23]; + assign io_float_rd_data_sign = data0[31]; + assign io_float_rs_valid = + _io_float_rs_valid_T & ~(|(_req_q_io_deq_bits_data[31:24])) & regnoIsFloat + & ~(_req_q_io_deq_bits_data[16]); + assign io_float_rs_addr = _req_q_io_deq_bits_data[4:0]; + assign io_itcm_readDataAddr_valid = + _io_dtcm_writeDataAddr_valid_T & ~(_req_q_io_deq_bits_data[16]) & itcm; + assign io_itcm_readDataAddr_bits = data1; + assign io_itcm_writeDataAddr_valid = + _io_dtcm_writeDataAddr_valid_T & _req_q_io_deq_bits_data[16] & itcm; + assign io_itcm_writeDataAddr_bits = data1; + assign io_itcm_writeDataBits = writeDataBits[127:0]; + assign io_itcm_writeDataStrb = strobe; + assign io_dtcm_readDataAddr_valid = + _io_dtcm_writeDataAddr_valid_T & ~(_req_q_io_deq_bits_data[16]) & dtcm; + assign io_dtcm_readDataAddr_bits = data1; + assign io_dtcm_writeDataAddr_valid = + _io_dtcm_writeDataAddr_valid_T & _req_q_io_deq_bits_data[16] & dtcm; + assign io_dtcm_writeDataAddr_bits = data1; + assign io_dtcm_writeDataBits = writeDataBits[127:0]; + assign io_dtcm_writeDataStrb = strobe; + assign io_haltreq_0 = haltreq_0; + assign io_resumereq_0 = resumereq_0; + assign io_ndmreset = dmcontrol[1]; +endmodule + +module CoralNPURRArbiter( + input clock, + reset, + output io_in_0_ready, + input io_in_0_valid, + input [31:0] io_in_0_bits_address, + io_in_0_bits_data, + input [1:0] io_in_0_bits_op, + output io_in_1_ready, + input io_in_1_valid, + input [31:0] io_in_1_bits_address, + io_in_1_bits_data, + input [1:0] io_in_1_bits_op, + input io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_address, + io_out_bits_data, + output [1:0] io_out_bits_op, + output io_chosen +); + + wire io_chosen_choice; + wire io_out_valid_0 = io_chosen_choice ? io_in_1_valid : io_in_0_valid; + reg ctrl_validMask_grantMask_lastGrant; + wire ctrl_validMask_1 = io_in_1_valid & ~ctrl_validMask_grantMask_lastGrant; + assign io_chosen_choice = ctrl_validMask_1 | ~io_in_0_valid; + always @(posedge clock or posedge reset) begin + if (reset) + ctrl_validMask_grantMask_lastGrant <= 1'h0; + else if (io_out_ready & io_out_valid_0) + ctrl_validMask_grantMask_lastGrant <= io_chosen_choice; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + ctrl_validMask_grantMask_lastGrant = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_in_0_ready = ~ctrl_validMask_1 & io_out_ready; + assign io_in_1_ready = + (~ctrl_validMask_grantMask_lastGrant | ~(ctrl_validMask_1 | io_in_0_valid)) + & io_out_ready; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_address = + io_chosen_choice ? io_in_1_bits_address : io_in_0_bits_address; + assign io_out_bits_data = io_chosen_choice ? io_in_1_bits_data : io_in_0_bits_data; + assign io_out_bits_op = io_chosen_choice ? io_in_1_bits_op : io_in_0_bits_op; + assign io_chosen = io_chosen_choice; +endmodule + +module Queue1_UInt1( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + io_enq_bits, + io_deq_ready, + output io_deq_valid, + io_deq_bits +); + + reg maybe_full; + wire do_enq = ~maybe_full & io_enq_valid; + reg ram; + always @(posedge clock or posedge reset) begin + if (reset) + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= io_enq_bits; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + maybe_full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_enq_ready = ~maybe_full; + assign io_deq_valid = maybe_full; + assign io_deq_bits = ram; endmodule module Regfile( @@ -202,15 +780,10 @@ module Regfile( input [4:0] io_writeAddr_2_addr, input io_writeAddr_3_valid, input [4:0] io_writeAddr_3_addr, - input io_busAddr_0_bypass, - io_busAddr_0_immen, input [31:0] io_busAddr_0_immed, - input io_busAddr_1_bypass, - input [31:0] io_busAddr_1_immed, - input io_busAddr_2_bypass, - input [31:0] io_busAddr_2_immed, - input io_busAddr_3_bypass, - input [31:0] io_busAddr_3_immed, + io_busAddr_1_immed, + io_busAddr_2_immed, + io_busAddr_3_immed, output [31:0] io_target_0_data, io_target_1_data, io_target_2_data, @@ -223,22 +796,16 @@ module Regfile( io_busPort_data_1, io_busPort_data_2, io_busPort_data_3, - output io_readData_0_valid, - output [31:0] io_readData_0_data, - output io_readData_1_valid, - output [31:0] io_readData_1_data, - output io_readData_2_valid, - output [31:0] io_readData_2_data, - output io_readData_3_valid, - output [31:0] io_readData_3_data, - output io_readData_4_valid, - output [31:0] io_readData_4_data, - output io_readData_5_valid, - output [31:0] io_readData_5_data, - output io_readData_6_valid, - output [31:0] io_readData_6_data, - output io_readData_7_valid, - output [31:0] io_readData_7_data, + input [4:0] io_debugBusPort_idx, + output [31:0] io_debugBusPort_data, + io_readData_0_data, + io_readData_1_data, + io_readData_2_data, + io_readData_3_data, + io_readData_4_data, + io_readData_5_data, + io_readData_6_data, + io_readData_7_data, input io_writeData_0_valid, input [4:0] io_writeData_0_bits_addr, input [31:0] io_writeData_0_bits_data, @@ -260,9 +827,10 @@ module Regfile( input io_writeMask_1_valid, io_writeMask_2_valid, io_writeMask_3_valid, + io_writeMask_5_valid, + io_pipelineFlush, output [31:0] io_scoreboard_regd, - io_scoreboard_comb, - output [5:0] io_rfwriteCount + io_scoreboard_comb ); reg [31:0] regfile_1; @@ -310,14 +878,6 @@ module Regfile( | (io_writeData_3_valid ? _scoreboard_clr0_T_10[31:1] : 31'h0) | (io_writeData_4_valid ? _scoreboard_clr0_T_13[31:1] : 31'h0) | (io_writeData_5_valid ? _scoreboard_clr0_T_16[31:1] : 31'h0); - reg readDataReady_0; - reg readDataReady_1; - reg readDataReady_2; - reg readDataReady_3; - reg readDataReady_4; - reg readDataReady_5; - reg readDataReady_6; - reg readDataReady_7; reg [31:0] readDataBits_0; reg [31:0] readDataBits_1; reg [31:0] readDataBits_2; @@ -326,564 +886,6 @@ module Regfile( reg [31:0] readDataBits_5; reg [31:0] readDataBits_6; reg [31:0] readDataBits_7; - wire _valid_T = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1; - wire valid_1 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1 & ~io_writeMask_1_valid; - wire valid_2 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1 & ~io_writeMask_2_valid; - wire valid_3 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1 & ~io_writeMask_3_valid; - wire _valid_T_8 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1; - wire _valid_T_10 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1; - wire [31:0] data = - (_valid_T ? io_writeData_0_bits_data : 32'h0) - | (valid_1 ? io_writeData_1_bits_data : 32'h0) - | (valid_2 ? io_writeData_2_bits_data : 32'h0) - | (valid_3 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_8 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_10 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_1_T = - {_valid_T, valid_1, valid_2, valid_3, _valid_T_8, _valid_T_10}; - wire _valid_T_12 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h2; - wire valid_1_1 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h2 & ~io_writeMask_1_valid; - wire valid_2_1 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h2 & ~io_writeMask_2_valid; - wire valid_3_1 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h2 & ~io_writeMask_3_valid; - wire _valid_T_20 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h2; - wire _valid_T_22 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h2; - wire [31:0] data_1 = - (_valid_T_12 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_1 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_1 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_1 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_20 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_22 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_2_T = - {_valid_T_12, valid_1_1, valid_2_1, valid_3_1, _valid_T_20, _valid_T_22}; - wire _valid_T_24 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h3; - wire valid_1_2 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h3 & ~io_writeMask_1_valid; - wire valid_2_2 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h3 & ~io_writeMask_2_valid; - wire valid_3_2 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h3 & ~io_writeMask_3_valid; - wire _valid_T_32 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h3; - wire _valid_T_34 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h3; - wire [31:0] data_2 = - (_valid_T_24 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_2 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_2 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_2 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_32 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_34 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_3_T = - {_valid_T_24, valid_1_2, valid_2_2, valid_3_2, _valid_T_32, _valid_T_34}; - wire _valid_T_36 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h4; - wire valid_1_3 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h4 & ~io_writeMask_1_valid; - wire valid_2_3 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h4 & ~io_writeMask_2_valid; - wire valid_3_3 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h4 & ~io_writeMask_3_valid; - wire _valid_T_44 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h4; - wire _valid_T_46 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h4; - wire [31:0] data_3 = - (_valid_T_36 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_3 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_3 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_3 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_44 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_46 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_4_T = - {_valid_T_36, valid_1_3, valid_2_3, valid_3_3, _valid_T_44, _valid_T_46}; - wire _valid_T_48 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h5; - wire valid_1_4 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h5 & ~io_writeMask_1_valid; - wire valid_2_4 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h5 & ~io_writeMask_2_valid; - wire valid_3_4 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h5 & ~io_writeMask_3_valid; - wire _valid_T_56 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h5; - wire _valid_T_58 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h5; - wire [31:0] data_4 = - (_valid_T_48 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_4 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_4 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_4 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_56 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_58 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_5_T = - {_valid_T_48, valid_1_4, valid_2_4, valid_3_4, _valid_T_56, _valid_T_58}; - wire _valid_T_60 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h6; - wire valid_1_5 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h6 & ~io_writeMask_1_valid; - wire valid_2_5 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h6 & ~io_writeMask_2_valid; - wire valid_3_5 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h6 & ~io_writeMask_3_valid; - wire _valid_T_68 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h6; - wire _valid_T_70 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h6; - wire [31:0] data_5 = - (_valid_T_60 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_5 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_5 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_5 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_68 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_70 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_6_T = - {_valid_T_60, valid_1_5, valid_2_5, valid_3_5, _valid_T_68, _valid_T_70}; - wire _valid_T_72 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h7; - wire valid_1_6 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h7 & ~io_writeMask_1_valid; - wire valid_2_6 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h7 & ~io_writeMask_2_valid; - wire valid_3_6 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h7 & ~io_writeMask_3_valid; - wire _valid_T_80 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h7; - wire _valid_T_82 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h7; - wire [31:0] data_6 = - (_valid_T_72 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_6 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_6 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_6 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_80 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_82 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_7_T = - {_valid_T_72, valid_1_6, valid_2_6, valid_3_6, _valid_T_80, _valid_T_82}; - wire _valid_T_84 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h8; - wire valid_1_7 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h8 & ~io_writeMask_1_valid; - wire valid_2_7 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h8 & ~io_writeMask_2_valid; - wire valid_3_7 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h8 & ~io_writeMask_3_valid; - wire _valid_T_92 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h8; - wire _valid_T_94 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h8; - wire [31:0] data_7 = - (_valid_T_84 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_7 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_7 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_7 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_92 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_94 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_8_T = - {_valid_T_84, valid_1_7, valid_2_7, valid_3_7, _valid_T_92, _valid_T_94}; - wire _valid_T_96 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h9; - wire valid_1_8 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h9 & ~io_writeMask_1_valid; - wire valid_2_8 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h9 & ~io_writeMask_2_valid; - wire valid_3_8 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h9 & ~io_writeMask_3_valid; - wire _valid_T_104 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h9; - wire _valid_T_106 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h9; - wire [31:0] data_8 = - (_valid_T_96 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_8 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_8 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_8 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_104 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_106 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_9_T = - {_valid_T_96, valid_1_8, valid_2_8, valid_3_8, _valid_T_104, _valid_T_106}; - wire _valid_T_108 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hA; - wire valid_1_9 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hA & ~io_writeMask_1_valid; - wire valid_2_9 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hA & ~io_writeMask_2_valid; - wire valid_3_9 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hA & ~io_writeMask_3_valid; - wire _valid_T_116 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hA; - wire _valid_T_118 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hA; - wire [31:0] data_9 = - (_valid_T_108 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_9 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_9 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_9 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_116 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_118 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_10_T = - {_valid_T_108, valid_1_9, valid_2_9, valid_3_9, _valid_T_116, _valid_T_118}; - wire _valid_T_120 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hB; - wire valid_1_10 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hB & ~io_writeMask_1_valid; - wire valid_2_10 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hB & ~io_writeMask_2_valid; - wire valid_3_10 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hB & ~io_writeMask_3_valid; - wire _valid_T_128 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hB; - wire _valid_T_130 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hB; - wire [31:0] data_10 = - (_valid_T_120 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_10 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_10 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_10 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_128 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_130 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_11_T = - {_valid_T_120, valid_1_10, valid_2_10, valid_3_10, _valid_T_128, _valid_T_130}; - wire _valid_T_132 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hC; - wire valid_1_11 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hC & ~io_writeMask_1_valid; - wire valid_2_11 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hC & ~io_writeMask_2_valid; - wire valid_3_11 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hC & ~io_writeMask_3_valid; - wire _valid_T_140 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hC; - wire _valid_T_142 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hC; - wire [31:0] data_11 = - (_valid_T_132 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_11 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_11 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_11 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_140 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_142 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_12_T = - {_valid_T_132, valid_1_11, valid_2_11, valid_3_11, _valid_T_140, _valid_T_142}; - wire _valid_T_144 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hD; - wire valid_1_12 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hD & ~io_writeMask_1_valid; - wire valid_2_12 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hD & ~io_writeMask_2_valid; - wire valid_3_12 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hD & ~io_writeMask_3_valid; - wire _valid_T_152 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hD; - wire _valid_T_154 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hD; - wire [31:0] data_12 = - (_valid_T_144 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_12 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_12 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_12 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_152 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_154 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_13_T = - {_valid_T_144, valid_1_12, valid_2_12, valid_3_12, _valid_T_152, _valid_T_154}; - wire _valid_T_156 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hE; - wire valid_1_13 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hE & ~io_writeMask_1_valid; - wire valid_2_13 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hE & ~io_writeMask_2_valid; - wire valid_3_13 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hE & ~io_writeMask_3_valid; - wire _valid_T_164 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hE; - wire _valid_T_166 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hE; - wire [31:0] data_13 = - (_valid_T_156 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_13 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_13 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_13 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_164 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_166 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_14_T = - {_valid_T_156, valid_1_13, valid_2_13, valid_3_13, _valid_T_164, _valid_T_166}; - wire _valid_T_168 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hF; - wire valid_1_14 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'hF & ~io_writeMask_1_valid; - wire valid_2_14 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'hF & ~io_writeMask_2_valid; - wire valid_3_14 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'hF & ~io_writeMask_3_valid; - wire _valid_T_176 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hF; - wire _valid_T_178 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hF; - wire [31:0] data_14 = - (_valid_T_168 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_14 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_14 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_14 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_176 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_178 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_15_T = - {_valid_T_168, valid_1_14, valid_2_14, valid_3_14, _valid_T_176, _valid_T_178}; - wire _valid_T_180 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h10; - wire valid_1_15 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h10 & ~io_writeMask_1_valid; - wire valid_2_15 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h10 & ~io_writeMask_2_valid; - wire valid_3_15 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h10 & ~io_writeMask_3_valid; - wire _valid_T_188 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h10; - wire _valid_T_190 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h10; - wire [31:0] data_15 = - (_valid_T_180 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_15 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_15 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_15 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_188 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_190 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_16_T = - {_valid_T_180, valid_1_15, valid_2_15, valid_3_15, _valid_T_188, _valid_T_190}; - wire _valid_T_192 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h11; - wire valid_1_16 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h11 & ~io_writeMask_1_valid; - wire valid_2_16 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h11 & ~io_writeMask_2_valid; - wire valid_3_16 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h11 & ~io_writeMask_3_valid; - wire _valid_T_200 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h11; - wire _valid_T_202 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h11; - wire [31:0] data_16 = - (_valid_T_192 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_16 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_16 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_16 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_200 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_202 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_17_T = - {_valid_T_192, valid_1_16, valid_2_16, valid_3_16, _valid_T_200, _valid_T_202}; - wire _valid_T_204 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h12; - wire valid_1_17 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h12 & ~io_writeMask_1_valid; - wire valid_2_17 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h12 & ~io_writeMask_2_valid; - wire valid_3_17 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h12 & ~io_writeMask_3_valid; - wire _valid_T_212 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h12; - wire _valid_T_214 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h12; - wire [31:0] data_17 = - (_valid_T_204 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_17 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_17 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_17 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_212 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_214 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_18_T = - {_valid_T_204, valid_1_17, valid_2_17, valid_3_17, _valid_T_212, _valid_T_214}; - wire _valid_T_216 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h13; - wire valid_1_18 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h13 & ~io_writeMask_1_valid; - wire valid_2_18 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h13 & ~io_writeMask_2_valid; - wire valid_3_18 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h13 & ~io_writeMask_3_valid; - wire _valid_T_224 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h13; - wire _valid_T_226 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h13; - wire [31:0] data_18 = - (_valid_T_216 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_18 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_18 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_18 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_224 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_226 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_19_T = - {_valid_T_216, valid_1_18, valid_2_18, valid_3_18, _valid_T_224, _valid_T_226}; - wire _valid_T_228 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h14; - wire valid_1_19 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h14 & ~io_writeMask_1_valid; - wire valid_2_19 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h14 & ~io_writeMask_2_valid; - wire valid_3_19 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h14 & ~io_writeMask_3_valid; - wire _valid_T_236 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h14; - wire _valid_T_238 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h14; - wire [31:0] data_19 = - (_valid_T_228 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_19 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_19 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_19 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_236 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_238 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_20_T = - {_valid_T_228, valid_1_19, valid_2_19, valid_3_19, _valid_T_236, _valid_T_238}; - wire _valid_T_240 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h15; - wire valid_1_20 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h15 & ~io_writeMask_1_valid; - wire valid_2_20 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h15 & ~io_writeMask_2_valid; - wire valid_3_20 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h15 & ~io_writeMask_3_valid; - wire _valid_T_248 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h15; - wire _valid_T_250 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h15; - wire [31:0] data_20 = - (_valid_T_240 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_20 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_20 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_20 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_248 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_250 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_21_T = - {_valid_T_240, valid_1_20, valid_2_20, valid_3_20, _valid_T_248, _valid_T_250}; - wire _valid_T_252 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h16; - wire valid_1_21 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h16 & ~io_writeMask_1_valid; - wire valid_2_21 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h16 & ~io_writeMask_2_valid; - wire valid_3_21 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h16 & ~io_writeMask_3_valid; - wire _valid_T_260 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h16; - wire _valid_T_262 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h16; - wire [31:0] data_21 = - (_valid_T_252 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_21 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_21 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_21 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_260 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_262 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_22_T = - {_valid_T_252, valid_1_21, valid_2_21, valid_3_21, _valid_T_260, _valid_T_262}; - wire _valid_T_264 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h17; - wire valid_1_22 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h17 & ~io_writeMask_1_valid; - wire valid_2_22 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h17 & ~io_writeMask_2_valid; - wire valid_3_22 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h17 & ~io_writeMask_3_valid; - wire _valid_T_272 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h17; - wire _valid_T_274 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h17; - wire [31:0] data_22 = - (_valid_T_264 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_22 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_22 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_22 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_272 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_274 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_23_T = - {_valid_T_264, valid_1_22, valid_2_22, valid_3_22, _valid_T_272, _valid_T_274}; - wire _valid_T_276 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h18; - wire valid_1_23 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h18 & ~io_writeMask_1_valid; - wire valid_2_23 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h18 & ~io_writeMask_2_valid; - wire valid_3_23 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h18 & ~io_writeMask_3_valid; - wire _valid_T_284 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h18; - wire _valid_T_286 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h18; - wire [31:0] data_23 = - (_valid_T_276 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_23 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_23 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_23 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_284 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_286 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_24_T = - {_valid_T_276, valid_1_23, valid_2_23, valid_3_23, _valid_T_284, _valid_T_286}; - wire _valid_T_288 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h19; - wire valid_1_24 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h19 & ~io_writeMask_1_valid; - wire valid_2_24 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h19 & ~io_writeMask_2_valid; - wire valid_3_24 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h19 & ~io_writeMask_3_valid; - wire _valid_T_296 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h19; - wire _valid_T_298 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h19; - wire [31:0] data_24 = - (_valid_T_288 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_24 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_24 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_24 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_296 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_298 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_25_T = - {_valid_T_288, valid_1_24, valid_2_24, valid_3_24, _valid_T_296, _valid_T_298}; - wire _valid_T_300 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1A; - wire valid_1_25 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1A & ~io_writeMask_1_valid; - wire valid_2_25 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1A & ~io_writeMask_2_valid; - wire valid_3_25 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1A & ~io_writeMask_3_valid; - wire _valid_T_308 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1A; - wire _valid_T_310 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1A; - wire [31:0] data_25 = - (_valid_T_300 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_25 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_25 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_25 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_308 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_310 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_26_T = - {_valid_T_300, valid_1_25, valid_2_25, valid_3_25, _valid_T_308, _valid_T_310}; - wire _valid_T_312 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1B; - wire valid_1_26 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1B & ~io_writeMask_1_valid; - wire valid_2_26 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1B & ~io_writeMask_2_valid; - wire valid_3_26 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1B & ~io_writeMask_3_valid; - wire _valid_T_320 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1B; - wire _valid_T_322 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1B; - wire [31:0] data_26 = - (_valid_T_312 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_26 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_26 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_26 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_320 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_322 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_27_T = - {_valid_T_312, valid_1_26, valid_2_26, valid_3_26, _valid_T_320, _valid_T_322}; - wire _valid_T_324 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1C; - wire valid_1_27 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1C & ~io_writeMask_1_valid; - wire valid_2_27 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1C & ~io_writeMask_2_valid; - wire valid_3_27 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1C & ~io_writeMask_3_valid; - wire _valid_T_332 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1C; - wire _valid_T_334 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1C; - wire [31:0] data_27 = - (_valid_T_324 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_27 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_27 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_27 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_332 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_334 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_28_T = - {_valid_T_324, valid_1_27, valid_2_27, valid_3_27, _valid_T_332, _valid_T_334}; - wire _valid_T_336 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1D; - wire valid_1_28 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1D & ~io_writeMask_1_valid; - wire valid_2_28 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1D & ~io_writeMask_2_valid; - wire valid_3_28 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1D & ~io_writeMask_3_valid; - wire _valid_T_344 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1D; - wire _valid_T_346 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1D; - wire [31:0] data_28 = - (_valid_T_336 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_28 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_28 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_28 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_344 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_346 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_29_T = - {_valid_T_336, valid_1_28, valid_2_28, valid_3_28, _valid_T_344, _valid_T_346}; - wire _valid_T_348 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1E; - wire valid_1_29 = - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1E & ~io_writeMask_1_valid; - wire valid_2_29 = - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1E & ~io_writeMask_2_valid; - wire valid_3_29 = - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1E & ~io_writeMask_3_valid; - wire _valid_T_356 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1E; - wire _valid_T_358 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1E; - wire [31:0] data_29 = - (_valid_T_348 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_29 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_29 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_29 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_356 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_358 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_30_T = - {_valid_T_348, valid_1_29, valid_2_29, valid_3_29, _valid_T_356, _valid_T_358}; - wire _valid_T_360 = io_writeData_0_valid & (&io_writeData_0_bits_addr); - wire valid_1_30 = - io_writeData_1_valid & (&io_writeData_1_bits_addr) & ~io_writeMask_1_valid; - wire valid_2_30 = - io_writeData_2_valid & (&io_writeData_2_bits_addr) & ~io_writeMask_2_valid; - wire valid_3_30 = - io_writeData_3_valid & (&io_writeData_3_bits_addr) & ~io_writeMask_3_valid; - wire _valid_T_368 = io_writeData_4_valid & (&io_writeData_4_bits_addr); - wire _valid_T_370 = io_writeData_5_valid & (&io_writeData_5_bits_addr); - wire [31:0] data_30 = - (_valid_T_360 ? io_writeData_0_bits_data : 32'h0) - | (valid_1_30 ? io_writeData_1_bits_data : 32'h0) - | (valid_2_30 ? io_writeData_2_bits_data : 32'h0) - | (valid_3_30 ? io_writeData_3_bits_data : 32'h0) - | (_valid_T_368 ? io_writeData_4_bits_data : 32'h0) - | (_valid_T_370 ? io_writeData_5_bits_data : 32'h0); - wire [5:0] _writeValid_31_T = - {_valid_T_360, valid_1_30, valid_2_30, valid_3_30, _valid_T_368, _valid_T_370}; wire _wdata_0_value_1_T = io_readAddr_0_addr == 5'h1; wire _wdata_0_value_2_T = io_readAddr_0_addr == 5'h2; wire _wdata_0_value_3_T = io_readAddr_0_addr == 5'h3; @@ -914,7 +916,7 @@ module Regfile( wire _wdata_0_value_28_T = io_readAddr_0_addr == 5'h1C; wire _wdata_0_value_29_T = io_readAddr_0_addr == 5'h1D; wire _wdata_0_value_30_T = io_readAddr_0_addr == 5'h1E; - wire [31:0] rdata_0_value_5_0 = + wire [31:0] rdata_0 = (_wdata_0_value_1_T ? regfile_1 : 32'h0) | (_wdata_0_value_2_T ? regfile_2 : 32'h0) | (_wdata_0_value_3_T ? regfile_3 : 32'h0) | (_wdata_0_value_4_T ? regfile_4 : 32'h0) | (_wdata_0_value_5_T ? regfile_5 : 32'h0) | (_wdata_0_value_6_T ? regfile_6 : 32'h0) @@ -942,54 +944,6 @@ module Regfile( | (_wdata_0_value_29_T ? regfile_29 : 32'h0) | (_wdata_0_value_30_T ? regfile_30 : 32'h0) | ((&io_readAddr_0_addr) ? regfile_31 : 32'h0); - wire [31:0] rwdata_0 = - io_readAddr_0_addr == 5'h0 | _wdata_0_value_1_T & (|_writeValid_1_T) - | _wdata_0_value_2_T & (|_writeValid_2_T) | _wdata_0_value_3_T & (|_writeValid_3_T) - | _wdata_0_value_4_T & (|_writeValid_4_T) | _wdata_0_value_5_T & (|_writeValid_5_T) - | _wdata_0_value_6_T & (|_writeValid_6_T) | _wdata_0_value_7_T & (|_writeValid_7_T) - | _wdata_0_value_8_T & (|_writeValid_8_T) | _wdata_0_value_9_T & (|_writeValid_9_T) - | _wdata_0_value_10_T & (|_writeValid_10_T) | _wdata_0_value_11_T - & (|_writeValid_11_T) | _wdata_0_value_12_T & (|_writeValid_12_T) - | _wdata_0_value_13_T & (|_writeValid_13_T) | _wdata_0_value_14_T - & (|_writeValid_14_T) | _wdata_0_value_15_T & (|_writeValid_15_T) - | _wdata_0_value_16_T & (|_writeValid_16_T) | _wdata_0_value_17_T - & (|_writeValid_17_T) | _wdata_0_value_18_T & (|_writeValid_18_T) - | _wdata_0_value_19_T & (|_writeValid_19_T) | _wdata_0_value_20_T - & (|_writeValid_20_T) | _wdata_0_value_21_T & (|_writeValid_21_T) - | _wdata_0_value_22_T & (|_writeValid_22_T) | _wdata_0_value_23_T - & (|_writeValid_23_T) | _wdata_0_value_24_T & (|_writeValid_24_T) - | _wdata_0_value_25_T & (|_writeValid_25_T) | _wdata_0_value_26_T - & (|_writeValid_26_T) | _wdata_0_value_27_T & (|_writeValid_27_T) - | _wdata_0_value_28_T & (|_writeValid_28_T) | _wdata_0_value_29_T - & (|_writeValid_29_T) | _wdata_0_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_0_addr) & (|_writeValid_31_T) - ? (_wdata_0_value_1_T ? data : 32'h0) | (_wdata_0_value_2_T ? data_1 : 32'h0) - | (_wdata_0_value_3_T ? data_2 : 32'h0) | (_wdata_0_value_4_T ? data_3 : 32'h0) - | (_wdata_0_value_5_T ? data_4 : 32'h0) | (_wdata_0_value_6_T ? data_5 : 32'h0) - | (_wdata_0_value_7_T ? data_6 : 32'h0) | (_wdata_0_value_8_T ? data_7 : 32'h0) - | (_wdata_0_value_9_T ? data_8 : 32'h0) | (_wdata_0_value_10_T ? data_9 : 32'h0) - | (_wdata_0_value_11_T ? data_10 : 32'h0) - | (_wdata_0_value_12_T ? data_11 : 32'h0) - | (_wdata_0_value_13_T ? data_12 : 32'h0) - | (_wdata_0_value_14_T ? data_13 : 32'h0) - | (_wdata_0_value_15_T ? data_14 : 32'h0) - | (_wdata_0_value_16_T ? data_15 : 32'h0) - | (_wdata_0_value_17_T ? data_16 : 32'h0) - | (_wdata_0_value_18_T ? data_17 : 32'h0) - | (_wdata_0_value_19_T ? data_18 : 32'h0) - | (_wdata_0_value_20_T ? data_19 : 32'h0) - | (_wdata_0_value_21_T ? data_20 : 32'h0) - | (_wdata_0_value_22_T ? data_21 : 32'h0) - | (_wdata_0_value_23_T ? data_22 : 32'h0) - | (_wdata_0_value_24_T ? data_23 : 32'h0) - | (_wdata_0_value_25_T ? data_24 : 32'h0) - | (_wdata_0_value_26_T ? data_25 : 32'h0) - | (_wdata_0_value_27_T ? data_26 : 32'h0) - | (_wdata_0_value_28_T ? data_27 : 32'h0) - | (_wdata_0_value_29_T ? data_28 : 32'h0) - | (_wdata_0_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_0_addr) ? data_30 : 32'h0) - : rdata_0_value_5_0; wire _wdata_1_value_1_T = io_readAddr_1_addr == 5'h1; wire _wdata_1_value_2_T = io_readAddr_1_addr == 5'h2; wire _wdata_1_value_3_T = io_readAddr_1_addr == 5'h3; @@ -1020,84 +974,34 @@ module Regfile( wire _wdata_1_value_28_T = io_readAddr_1_addr == 5'h1C; wire _wdata_1_value_29_T = io_readAddr_1_addr == 5'h1D; wire _wdata_1_value_30_T = io_readAddr_1_addr == 5'h1E; - wire [31:0] rwdata_1 = - io_readAddr_1_addr == 5'h0 | _wdata_1_value_1_T & (|_writeValid_1_T) - | _wdata_1_value_2_T & (|_writeValid_2_T) | _wdata_1_value_3_T & (|_writeValid_3_T) - | _wdata_1_value_4_T & (|_writeValid_4_T) | _wdata_1_value_5_T & (|_writeValid_5_T) - | _wdata_1_value_6_T & (|_writeValid_6_T) | _wdata_1_value_7_T & (|_writeValid_7_T) - | _wdata_1_value_8_T & (|_writeValid_8_T) | _wdata_1_value_9_T & (|_writeValid_9_T) - | _wdata_1_value_10_T & (|_writeValid_10_T) | _wdata_1_value_11_T - & (|_writeValid_11_T) | _wdata_1_value_12_T & (|_writeValid_12_T) - | _wdata_1_value_13_T & (|_writeValid_13_T) | _wdata_1_value_14_T - & (|_writeValid_14_T) | _wdata_1_value_15_T & (|_writeValid_15_T) - | _wdata_1_value_16_T & (|_writeValid_16_T) | _wdata_1_value_17_T - & (|_writeValid_17_T) | _wdata_1_value_18_T & (|_writeValid_18_T) - | _wdata_1_value_19_T & (|_writeValid_19_T) | _wdata_1_value_20_T - & (|_writeValid_20_T) | _wdata_1_value_21_T & (|_writeValid_21_T) - | _wdata_1_value_22_T & (|_writeValid_22_T) | _wdata_1_value_23_T - & (|_writeValid_23_T) | _wdata_1_value_24_T & (|_writeValid_24_T) - | _wdata_1_value_25_T & (|_writeValid_25_T) | _wdata_1_value_26_T - & (|_writeValid_26_T) | _wdata_1_value_27_T & (|_writeValid_27_T) - | _wdata_1_value_28_T & (|_writeValid_28_T) | _wdata_1_value_29_T - & (|_writeValid_29_T) | _wdata_1_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_1_addr) & (|_writeValid_31_T) - ? (_wdata_1_value_1_T ? data : 32'h0) | (_wdata_1_value_2_T ? data_1 : 32'h0) - | (_wdata_1_value_3_T ? data_2 : 32'h0) | (_wdata_1_value_4_T ? data_3 : 32'h0) - | (_wdata_1_value_5_T ? data_4 : 32'h0) | (_wdata_1_value_6_T ? data_5 : 32'h0) - | (_wdata_1_value_7_T ? data_6 : 32'h0) | (_wdata_1_value_8_T ? data_7 : 32'h0) - | (_wdata_1_value_9_T ? data_8 : 32'h0) | (_wdata_1_value_10_T ? data_9 : 32'h0) - | (_wdata_1_value_11_T ? data_10 : 32'h0) - | (_wdata_1_value_12_T ? data_11 : 32'h0) - | (_wdata_1_value_13_T ? data_12 : 32'h0) - | (_wdata_1_value_14_T ? data_13 : 32'h0) - | (_wdata_1_value_15_T ? data_14 : 32'h0) - | (_wdata_1_value_16_T ? data_15 : 32'h0) - | (_wdata_1_value_17_T ? data_16 : 32'h0) - | (_wdata_1_value_18_T ? data_17 : 32'h0) - | (_wdata_1_value_19_T ? data_18 : 32'h0) - | (_wdata_1_value_20_T ? data_19 : 32'h0) - | (_wdata_1_value_21_T ? data_20 : 32'h0) - | (_wdata_1_value_22_T ? data_21 : 32'h0) - | (_wdata_1_value_23_T ? data_22 : 32'h0) - | (_wdata_1_value_24_T ? data_23 : 32'h0) - | (_wdata_1_value_25_T ? data_24 : 32'h0) - | (_wdata_1_value_26_T ? data_25 : 32'h0) - | (_wdata_1_value_27_T ? data_26 : 32'h0) - | (_wdata_1_value_28_T ? data_27 : 32'h0) - | (_wdata_1_value_29_T ? data_28 : 32'h0) - | (_wdata_1_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_1_addr) ? data_30 : 32'h0) - : (_wdata_1_value_1_T ? regfile_1 : 32'h0) - | (_wdata_1_value_2_T ? regfile_2 : 32'h0) - | (_wdata_1_value_3_T ? regfile_3 : 32'h0) - | (_wdata_1_value_4_T ? regfile_4 : 32'h0) - | (_wdata_1_value_5_T ? regfile_5 : 32'h0) - | (_wdata_1_value_6_T ? regfile_6 : 32'h0) - | (_wdata_1_value_7_T ? regfile_7 : 32'h0) - | (_wdata_1_value_8_T ? regfile_8 : 32'h0) - | (_wdata_1_value_9_T ? regfile_9 : 32'h0) - | (_wdata_1_value_10_T ? regfile_10 : 32'h0) - | (_wdata_1_value_11_T ? regfile_11 : 32'h0) - | (_wdata_1_value_12_T ? regfile_12 : 32'h0) - | (_wdata_1_value_13_T ? regfile_13 : 32'h0) - | (_wdata_1_value_14_T ? regfile_14 : 32'h0) - | (_wdata_1_value_15_T ? regfile_15 : 32'h0) - | (_wdata_1_value_16_T ? regfile_16 : 32'h0) - | (_wdata_1_value_17_T ? regfile_17 : 32'h0) - | (_wdata_1_value_18_T ? regfile_18 : 32'h0) - | (_wdata_1_value_19_T ? regfile_19 : 32'h0) - | (_wdata_1_value_20_T ? regfile_20 : 32'h0) - | (_wdata_1_value_21_T ? regfile_21 : 32'h0) - | (_wdata_1_value_22_T ? regfile_22 : 32'h0) - | (_wdata_1_value_23_T ? regfile_23 : 32'h0) - | (_wdata_1_value_24_T ? regfile_24 : 32'h0) - | (_wdata_1_value_25_T ? regfile_25 : 32'h0) - | (_wdata_1_value_26_T ? regfile_26 : 32'h0) - | (_wdata_1_value_27_T ? regfile_27 : 32'h0) - | (_wdata_1_value_28_T ? regfile_28 : 32'h0) - | (_wdata_1_value_29_T ? regfile_29 : 32'h0) - | (_wdata_1_value_30_T ? regfile_30 : 32'h0) - | ((&io_readAddr_1_addr) ? regfile_31 : 32'h0); + wire [31:0] rdata_1 = + (_wdata_1_value_1_T ? regfile_1 : 32'h0) | (_wdata_1_value_2_T ? regfile_2 : 32'h0) + | (_wdata_1_value_3_T ? regfile_3 : 32'h0) | (_wdata_1_value_4_T ? regfile_4 : 32'h0) + | (_wdata_1_value_5_T ? regfile_5 : 32'h0) | (_wdata_1_value_6_T ? regfile_6 : 32'h0) + | (_wdata_1_value_7_T ? regfile_7 : 32'h0) | (_wdata_1_value_8_T ? regfile_8 : 32'h0) + | (_wdata_1_value_9_T ? regfile_9 : 32'h0) + | (_wdata_1_value_10_T ? regfile_10 : 32'h0) + | (_wdata_1_value_11_T ? regfile_11 : 32'h0) + | (_wdata_1_value_12_T ? regfile_12 : 32'h0) + | (_wdata_1_value_13_T ? regfile_13 : 32'h0) + | (_wdata_1_value_14_T ? regfile_14 : 32'h0) + | (_wdata_1_value_15_T ? regfile_15 : 32'h0) + | (_wdata_1_value_16_T ? regfile_16 : 32'h0) + | (_wdata_1_value_17_T ? regfile_17 : 32'h0) + | (_wdata_1_value_18_T ? regfile_18 : 32'h0) + | (_wdata_1_value_19_T ? regfile_19 : 32'h0) + | (_wdata_1_value_20_T ? regfile_20 : 32'h0) + | (_wdata_1_value_21_T ? regfile_21 : 32'h0) + | (_wdata_1_value_22_T ? regfile_22 : 32'h0) + | (_wdata_1_value_23_T ? regfile_23 : 32'h0) + | (_wdata_1_value_24_T ? regfile_24 : 32'h0) + | (_wdata_1_value_25_T ? regfile_25 : 32'h0) + | (_wdata_1_value_26_T ? regfile_26 : 32'h0) + | (_wdata_1_value_27_T ? regfile_27 : 32'h0) + | (_wdata_1_value_28_T ? regfile_28 : 32'h0) + | (_wdata_1_value_29_T ? regfile_29 : 32'h0) + | (_wdata_1_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_1_addr) ? regfile_31 : 32'h0); wire _wdata_2_value_1_T = io_readAddr_2_addr == 5'h1; wire _wdata_2_value_2_T = io_readAddr_2_addr == 5'h2; wire _wdata_2_value_3_T = io_readAddr_2_addr == 5'h3; @@ -1128,7 +1032,7 @@ module Regfile( wire _wdata_2_value_28_T = io_readAddr_2_addr == 5'h1C; wire _wdata_2_value_29_T = io_readAddr_2_addr == 5'h1D; wire _wdata_2_value_30_T = io_readAddr_2_addr == 5'h1E; - wire [31:0] rdata_2_value_5_0 = + wire [31:0] rdata_2 = (_wdata_2_value_1_T ? regfile_1 : 32'h0) | (_wdata_2_value_2_T ? regfile_2 : 32'h0) | (_wdata_2_value_3_T ? regfile_3 : 32'h0) | (_wdata_2_value_4_T ? regfile_4 : 32'h0) | (_wdata_2_value_5_T ? regfile_5 : 32'h0) | (_wdata_2_value_6_T ? regfile_6 : 32'h0) @@ -1156,54 +1060,6 @@ module Regfile( | (_wdata_2_value_29_T ? regfile_29 : 32'h0) | (_wdata_2_value_30_T ? regfile_30 : 32'h0) | ((&io_readAddr_2_addr) ? regfile_31 : 32'h0); - wire [31:0] rwdata_2 = - io_readAddr_2_addr == 5'h0 | _wdata_2_value_1_T & (|_writeValid_1_T) - | _wdata_2_value_2_T & (|_writeValid_2_T) | _wdata_2_value_3_T & (|_writeValid_3_T) - | _wdata_2_value_4_T & (|_writeValid_4_T) | _wdata_2_value_5_T & (|_writeValid_5_T) - | _wdata_2_value_6_T & (|_writeValid_6_T) | _wdata_2_value_7_T & (|_writeValid_7_T) - | _wdata_2_value_8_T & (|_writeValid_8_T) | _wdata_2_value_9_T & (|_writeValid_9_T) - | _wdata_2_value_10_T & (|_writeValid_10_T) | _wdata_2_value_11_T - & (|_writeValid_11_T) | _wdata_2_value_12_T & (|_writeValid_12_T) - | _wdata_2_value_13_T & (|_writeValid_13_T) | _wdata_2_value_14_T - & (|_writeValid_14_T) | _wdata_2_value_15_T & (|_writeValid_15_T) - | _wdata_2_value_16_T & (|_writeValid_16_T) | _wdata_2_value_17_T - & (|_writeValid_17_T) | _wdata_2_value_18_T & (|_writeValid_18_T) - | _wdata_2_value_19_T & (|_writeValid_19_T) | _wdata_2_value_20_T - & (|_writeValid_20_T) | _wdata_2_value_21_T & (|_writeValid_21_T) - | _wdata_2_value_22_T & (|_writeValid_22_T) | _wdata_2_value_23_T - & (|_writeValid_23_T) | _wdata_2_value_24_T & (|_writeValid_24_T) - | _wdata_2_value_25_T & (|_writeValid_25_T) | _wdata_2_value_26_T - & (|_writeValid_26_T) | _wdata_2_value_27_T & (|_writeValid_27_T) - | _wdata_2_value_28_T & (|_writeValid_28_T) | _wdata_2_value_29_T - & (|_writeValid_29_T) | _wdata_2_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_2_addr) & (|_writeValid_31_T) - ? (_wdata_2_value_1_T ? data : 32'h0) | (_wdata_2_value_2_T ? data_1 : 32'h0) - | (_wdata_2_value_3_T ? data_2 : 32'h0) | (_wdata_2_value_4_T ? data_3 : 32'h0) - | (_wdata_2_value_5_T ? data_4 : 32'h0) | (_wdata_2_value_6_T ? data_5 : 32'h0) - | (_wdata_2_value_7_T ? data_6 : 32'h0) | (_wdata_2_value_8_T ? data_7 : 32'h0) - | (_wdata_2_value_9_T ? data_8 : 32'h0) | (_wdata_2_value_10_T ? data_9 : 32'h0) - | (_wdata_2_value_11_T ? data_10 : 32'h0) - | (_wdata_2_value_12_T ? data_11 : 32'h0) - | (_wdata_2_value_13_T ? data_12 : 32'h0) - | (_wdata_2_value_14_T ? data_13 : 32'h0) - | (_wdata_2_value_15_T ? data_14 : 32'h0) - | (_wdata_2_value_16_T ? data_15 : 32'h0) - | (_wdata_2_value_17_T ? data_16 : 32'h0) - | (_wdata_2_value_18_T ? data_17 : 32'h0) - | (_wdata_2_value_19_T ? data_18 : 32'h0) - | (_wdata_2_value_20_T ? data_19 : 32'h0) - | (_wdata_2_value_21_T ? data_20 : 32'h0) - | (_wdata_2_value_22_T ? data_21 : 32'h0) - | (_wdata_2_value_23_T ? data_22 : 32'h0) - | (_wdata_2_value_24_T ? data_23 : 32'h0) - | (_wdata_2_value_25_T ? data_24 : 32'h0) - | (_wdata_2_value_26_T ? data_25 : 32'h0) - | (_wdata_2_value_27_T ? data_26 : 32'h0) - | (_wdata_2_value_28_T ? data_27 : 32'h0) - | (_wdata_2_value_29_T ? data_28 : 32'h0) - | (_wdata_2_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_2_addr) ? data_30 : 32'h0) - : rdata_2_value_5_0; wire _wdata_3_value_1_T = io_readAddr_3_addr == 5'h1; wire _wdata_3_value_2_T = io_readAddr_3_addr == 5'h2; wire _wdata_3_value_3_T = io_readAddr_3_addr == 5'h3; @@ -1234,84 +1090,34 @@ module Regfile( wire _wdata_3_value_28_T = io_readAddr_3_addr == 5'h1C; wire _wdata_3_value_29_T = io_readAddr_3_addr == 5'h1D; wire _wdata_3_value_30_T = io_readAddr_3_addr == 5'h1E; - wire [31:0] rwdata_3 = - io_readAddr_3_addr == 5'h0 | _wdata_3_value_1_T & (|_writeValid_1_T) - | _wdata_3_value_2_T & (|_writeValid_2_T) | _wdata_3_value_3_T & (|_writeValid_3_T) - | _wdata_3_value_4_T & (|_writeValid_4_T) | _wdata_3_value_5_T & (|_writeValid_5_T) - | _wdata_3_value_6_T & (|_writeValid_6_T) | _wdata_3_value_7_T & (|_writeValid_7_T) - | _wdata_3_value_8_T & (|_writeValid_8_T) | _wdata_3_value_9_T & (|_writeValid_9_T) - | _wdata_3_value_10_T & (|_writeValid_10_T) | _wdata_3_value_11_T - & (|_writeValid_11_T) | _wdata_3_value_12_T & (|_writeValid_12_T) - | _wdata_3_value_13_T & (|_writeValid_13_T) | _wdata_3_value_14_T - & (|_writeValid_14_T) | _wdata_3_value_15_T & (|_writeValid_15_T) - | _wdata_3_value_16_T & (|_writeValid_16_T) | _wdata_3_value_17_T - & (|_writeValid_17_T) | _wdata_3_value_18_T & (|_writeValid_18_T) - | _wdata_3_value_19_T & (|_writeValid_19_T) | _wdata_3_value_20_T - & (|_writeValid_20_T) | _wdata_3_value_21_T & (|_writeValid_21_T) - | _wdata_3_value_22_T & (|_writeValid_22_T) | _wdata_3_value_23_T - & (|_writeValid_23_T) | _wdata_3_value_24_T & (|_writeValid_24_T) - | _wdata_3_value_25_T & (|_writeValid_25_T) | _wdata_3_value_26_T - & (|_writeValid_26_T) | _wdata_3_value_27_T & (|_writeValid_27_T) - | _wdata_3_value_28_T & (|_writeValid_28_T) | _wdata_3_value_29_T - & (|_writeValid_29_T) | _wdata_3_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_3_addr) & (|_writeValid_31_T) - ? (_wdata_3_value_1_T ? data : 32'h0) | (_wdata_3_value_2_T ? data_1 : 32'h0) - | (_wdata_3_value_3_T ? data_2 : 32'h0) | (_wdata_3_value_4_T ? data_3 : 32'h0) - | (_wdata_3_value_5_T ? data_4 : 32'h0) | (_wdata_3_value_6_T ? data_5 : 32'h0) - | (_wdata_3_value_7_T ? data_6 : 32'h0) | (_wdata_3_value_8_T ? data_7 : 32'h0) - | (_wdata_3_value_9_T ? data_8 : 32'h0) | (_wdata_3_value_10_T ? data_9 : 32'h0) - | (_wdata_3_value_11_T ? data_10 : 32'h0) - | (_wdata_3_value_12_T ? data_11 : 32'h0) - | (_wdata_3_value_13_T ? data_12 : 32'h0) - | (_wdata_3_value_14_T ? data_13 : 32'h0) - | (_wdata_3_value_15_T ? data_14 : 32'h0) - | (_wdata_3_value_16_T ? data_15 : 32'h0) - | (_wdata_3_value_17_T ? data_16 : 32'h0) - | (_wdata_3_value_18_T ? data_17 : 32'h0) - | (_wdata_3_value_19_T ? data_18 : 32'h0) - | (_wdata_3_value_20_T ? data_19 : 32'h0) - | (_wdata_3_value_21_T ? data_20 : 32'h0) - | (_wdata_3_value_22_T ? data_21 : 32'h0) - | (_wdata_3_value_23_T ? data_22 : 32'h0) - | (_wdata_3_value_24_T ? data_23 : 32'h0) - | (_wdata_3_value_25_T ? data_24 : 32'h0) - | (_wdata_3_value_26_T ? data_25 : 32'h0) - | (_wdata_3_value_27_T ? data_26 : 32'h0) - | (_wdata_3_value_28_T ? data_27 : 32'h0) - | (_wdata_3_value_29_T ? data_28 : 32'h0) - | (_wdata_3_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_3_addr) ? data_30 : 32'h0) - : (_wdata_3_value_1_T ? regfile_1 : 32'h0) - | (_wdata_3_value_2_T ? regfile_2 : 32'h0) - | (_wdata_3_value_3_T ? regfile_3 : 32'h0) - | (_wdata_3_value_4_T ? regfile_4 : 32'h0) - | (_wdata_3_value_5_T ? regfile_5 : 32'h0) - | (_wdata_3_value_6_T ? regfile_6 : 32'h0) - | (_wdata_3_value_7_T ? regfile_7 : 32'h0) - | (_wdata_3_value_8_T ? regfile_8 : 32'h0) - | (_wdata_3_value_9_T ? regfile_9 : 32'h0) - | (_wdata_3_value_10_T ? regfile_10 : 32'h0) - | (_wdata_3_value_11_T ? regfile_11 : 32'h0) - | (_wdata_3_value_12_T ? regfile_12 : 32'h0) - | (_wdata_3_value_13_T ? regfile_13 : 32'h0) - | (_wdata_3_value_14_T ? regfile_14 : 32'h0) - | (_wdata_3_value_15_T ? regfile_15 : 32'h0) - | (_wdata_3_value_16_T ? regfile_16 : 32'h0) - | (_wdata_3_value_17_T ? regfile_17 : 32'h0) - | (_wdata_3_value_18_T ? regfile_18 : 32'h0) - | (_wdata_3_value_19_T ? regfile_19 : 32'h0) - | (_wdata_3_value_20_T ? regfile_20 : 32'h0) - | (_wdata_3_value_21_T ? regfile_21 : 32'h0) - | (_wdata_3_value_22_T ? regfile_22 : 32'h0) - | (_wdata_3_value_23_T ? regfile_23 : 32'h0) - | (_wdata_3_value_24_T ? regfile_24 : 32'h0) - | (_wdata_3_value_25_T ? regfile_25 : 32'h0) - | (_wdata_3_value_26_T ? regfile_26 : 32'h0) - | (_wdata_3_value_27_T ? regfile_27 : 32'h0) - | (_wdata_3_value_28_T ? regfile_28 : 32'h0) - | (_wdata_3_value_29_T ? regfile_29 : 32'h0) - | (_wdata_3_value_30_T ? regfile_30 : 32'h0) - | ((&io_readAddr_3_addr) ? regfile_31 : 32'h0); + wire [31:0] rdata_3 = + (_wdata_3_value_1_T ? regfile_1 : 32'h0) | (_wdata_3_value_2_T ? regfile_2 : 32'h0) + | (_wdata_3_value_3_T ? regfile_3 : 32'h0) | (_wdata_3_value_4_T ? regfile_4 : 32'h0) + | (_wdata_3_value_5_T ? regfile_5 : 32'h0) | (_wdata_3_value_6_T ? regfile_6 : 32'h0) + | (_wdata_3_value_7_T ? regfile_7 : 32'h0) | (_wdata_3_value_8_T ? regfile_8 : 32'h0) + | (_wdata_3_value_9_T ? regfile_9 : 32'h0) + | (_wdata_3_value_10_T ? regfile_10 : 32'h0) + | (_wdata_3_value_11_T ? regfile_11 : 32'h0) + | (_wdata_3_value_12_T ? regfile_12 : 32'h0) + | (_wdata_3_value_13_T ? regfile_13 : 32'h0) + | (_wdata_3_value_14_T ? regfile_14 : 32'h0) + | (_wdata_3_value_15_T ? regfile_15 : 32'h0) + | (_wdata_3_value_16_T ? regfile_16 : 32'h0) + | (_wdata_3_value_17_T ? regfile_17 : 32'h0) + | (_wdata_3_value_18_T ? regfile_18 : 32'h0) + | (_wdata_3_value_19_T ? regfile_19 : 32'h0) + | (_wdata_3_value_20_T ? regfile_20 : 32'h0) + | (_wdata_3_value_21_T ? regfile_21 : 32'h0) + | (_wdata_3_value_22_T ? regfile_22 : 32'h0) + | (_wdata_3_value_23_T ? regfile_23 : 32'h0) + | (_wdata_3_value_24_T ? regfile_24 : 32'h0) + | (_wdata_3_value_25_T ? regfile_25 : 32'h0) + | (_wdata_3_value_26_T ? regfile_26 : 32'h0) + | (_wdata_3_value_27_T ? regfile_27 : 32'h0) + | (_wdata_3_value_28_T ? regfile_28 : 32'h0) + | (_wdata_3_value_29_T ? regfile_29 : 32'h0) + | (_wdata_3_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_3_addr) ? regfile_31 : 32'h0); wire _wdata_4_value_1_T = io_readAddr_4_addr == 5'h1; wire _wdata_4_value_2_T = io_readAddr_4_addr == 5'h2; wire _wdata_4_value_3_T = io_readAddr_4_addr == 5'h3; @@ -1342,7 +1148,7 @@ module Regfile( wire _wdata_4_value_28_T = io_readAddr_4_addr == 5'h1C; wire _wdata_4_value_29_T = io_readAddr_4_addr == 5'h1D; wire _wdata_4_value_30_T = io_readAddr_4_addr == 5'h1E; - wire [31:0] rdata_4_value_5_0 = + wire [31:0] rdata_4 = (_wdata_4_value_1_T ? regfile_1 : 32'h0) | (_wdata_4_value_2_T ? regfile_2 : 32'h0) | (_wdata_4_value_3_T ? regfile_3 : 32'h0) | (_wdata_4_value_4_T ? regfile_4 : 32'h0) | (_wdata_4_value_5_T ? regfile_5 : 32'h0) | (_wdata_4_value_6_T ? regfile_6 : 32'h0) @@ -1370,54 +1176,6 @@ module Regfile( | (_wdata_4_value_29_T ? regfile_29 : 32'h0) | (_wdata_4_value_30_T ? regfile_30 : 32'h0) | ((&io_readAddr_4_addr) ? regfile_31 : 32'h0); - wire [31:0] rwdata_4 = - io_readAddr_4_addr == 5'h0 | _wdata_4_value_1_T & (|_writeValid_1_T) - | _wdata_4_value_2_T & (|_writeValid_2_T) | _wdata_4_value_3_T & (|_writeValid_3_T) - | _wdata_4_value_4_T & (|_writeValid_4_T) | _wdata_4_value_5_T & (|_writeValid_5_T) - | _wdata_4_value_6_T & (|_writeValid_6_T) | _wdata_4_value_7_T & (|_writeValid_7_T) - | _wdata_4_value_8_T & (|_writeValid_8_T) | _wdata_4_value_9_T & (|_writeValid_9_T) - | _wdata_4_value_10_T & (|_writeValid_10_T) | _wdata_4_value_11_T - & (|_writeValid_11_T) | _wdata_4_value_12_T & (|_writeValid_12_T) - | _wdata_4_value_13_T & (|_writeValid_13_T) | _wdata_4_value_14_T - & (|_writeValid_14_T) | _wdata_4_value_15_T & (|_writeValid_15_T) - | _wdata_4_value_16_T & (|_writeValid_16_T) | _wdata_4_value_17_T - & (|_writeValid_17_T) | _wdata_4_value_18_T & (|_writeValid_18_T) - | _wdata_4_value_19_T & (|_writeValid_19_T) | _wdata_4_value_20_T - & (|_writeValid_20_T) | _wdata_4_value_21_T & (|_writeValid_21_T) - | _wdata_4_value_22_T & (|_writeValid_22_T) | _wdata_4_value_23_T - & (|_writeValid_23_T) | _wdata_4_value_24_T & (|_writeValid_24_T) - | _wdata_4_value_25_T & (|_writeValid_25_T) | _wdata_4_value_26_T - & (|_writeValid_26_T) | _wdata_4_value_27_T & (|_writeValid_27_T) - | _wdata_4_value_28_T & (|_writeValid_28_T) | _wdata_4_value_29_T - & (|_writeValid_29_T) | _wdata_4_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_4_addr) & (|_writeValid_31_T) - ? (_wdata_4_value_1_T ? data : 32'h0) | (_wdata_4_value_2_T ? data_1 : 32'h0) - | (_wdata_4_value_3_T ? data_2 : 32'h0) | (_wdata_4_value_4_T ? data_3 : 32'h0) - | (_wdata_4_value_5_T ? data_4 : 32'h0) | (_wdata_4_value_6_T ? data_5 : 32'h0) - | (_wdata_4_value_7_T ? data_6 : 32'h0) | (_wdata_4_value_8_T ? data_7 : 32'h0) - | (_wdata_4_value_9_T ? data_8 : 32'h0) | (_wdata_4_value_10_T ? data_9 : 32'h0) - | (_wdata_4_value_11_T ? data_10 : 32'h0) - | (_wdata_4_value_12_T ? data_11 : 32'h0) - | (_wdata_4_value_13_T ? data_12 : 32'h0) - | (_wdata_4_value_14_T ? data_13 : 32'h0) - | (_wdata_4_value_15_T ? data_14 : 32'h0) - | (_wdata_4_value_16_T ? data_15 : 32'h0) - | (_wdata_4_value_17_T ? data_16 : 32'h0) - | (_wdata_4_value_18_T ? data_17 : 32'h0) - | (_wdata_4_value_19_T ? data_18 : 32'h0) - | (_wdata_4_value_20_T ? data_19 : 32'h0) - | (_wdata_4_value_21_T ? data_20 : 32'h0) - | (_wdata_4_value_22_T ? data_21 : 32'h0) - | (_wdata_4_value_23_T ? data_22 : 32'h0) - | (_wdata_4_value_24_T ? data_23 : 32'h0) - | (_wdata_4_value_25_T ? data_24 : 32'h0) - | (_wdata_4_value_26_T ? data_25 : 32'h0) - | (_wdata_4_value_27_T ? data_26 : 32'h0) - | (_wdata_4_value_28_T ? data_27 : 32'h0) - | (_wdata_4_value_29_T ? data_28 : 32'h0) - | (_wdata_4_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_4_addr) ? data_30 : 32'h0) - : rdata_4_value_5_0; wire _wdata_5_value_1_T = io_readAddr_5_addr == 5'h1; wire _wdata_5_value_2_T = io_readAddr_5_addr == 5'h2; wire _wdata_5_value_3_T = io_readAddr_5_addr == 5'h3; @@ -1448,84 +1206,34 @@ module Regfile( wire _wdata_5_value_28_T = io_readAddr_5_addr == 5'h1C; wire _wdata_5_value_29_T = io_readAddr_5_addr == 5'h1D; wire _wdata_5_value_30_T = io_readAddr_5_addr == 5'h1E; - wire [31:0] rwdata_5 = - io_readAddr_5_addr == 5'h0 | _wdata_5_value_1_T & (|_writeValid_1_T) - | _wdata_5_value_2_T & (|_writeValid_2_T) | _wdata_5_value_3_T & (|_writeValid_3_T) - | _wdata_5_value_4_T & (|_writeValid_4_T) | _wdata_5_value_5_T & (|_writeValid_5_T) - | _wdata_5_value_6_T & (|_writeValid_6_T) | _wdata_5_value_7_T & (|_writeValid_7_T) - | _wdata_5_value_8_T & (|_writeValid_8_T) | _wdata_5_value_9_T & (|_writeValid_9_T) - | _wdata_5_value_10_T & (|_writeValid_10_T) | _wdata_5_value_11_T - & (|_writeValid_11_T) | _wdata_5_value_12_T & (|_writeValid_12_T) - | _wdata_5_value_13_T & (|_writeValid_13_T) | _wdata_5_value_14_T - & (|_writeValid_14_T) | _wdata_5_value_15_T & (|_writeValid_15_T) - | _wdata_5_value_16_T & (|_writeValid_16_T) | _wdata_5_value_17_T - & (|_writeValid_17_T) | _wdata_5_value_18_T & (|_writeValid_18_T) - | _wdata_5_value_19_T & (|_writeValid_19_T) | _wdata_5_value_20_T - & (|_writeValid_20_T) | _wdata_5_value_21_T & (|_writeValid_21_T) - | _wdata_5_value_22_T & (|_writeValid_22_T) | _wdata_5_value_23_T - & (|_writeValid_23_T) | _wdata_5_value_24_T & (|_writeValid_24_T) - | _wdata_5_value_25_T & (|_writeValid_25_T) | _wdata_5_value_26_T - & (|_writeValid_26_T) | _wdata_5_value_27_T & (|_writeValid_27_T) - | _wdata_5_value_28_T & (|_writeValid_28_T) | _wdata_5_value_29_T - & (|_writeValid_29_T) | _wdata_5_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_5_addr) & (|_writeValid_31_T) - ? (_wdata_5_value_1_T ? data : 32'h0) | (_wdata_5_value_2_T ? data_1 : 32'h0) - | (_wdata_5_value_3_T ? data_2 : 32'h0) | (_wdata_5_value_4_T ? data_3 : 32'h0) - | (_wdata_5_value_5_T ? data_4 : 32'h0) | (_wdata_5_value_6_T ? data_5 : 32'h0) - | (_wdata_5_value_7_T ? data_6 : 32'h0) | (_wdata_5_value_8_T ? data_7 : 32'h0) - | (_wdata_5_value_9_T ? data_8 : 32'h0) | (_wdata_5_value_10_T ? data_9 : 32'h0) - | (_wdata_5_value_11_T ? data_10 : 32'h0) - | (_wdata_5_value_12_T ? data_11 : 32'h0) - | (_wdata_5_value_13_T ? data_12 : 32'h0) - | (_wdata_5_value_14_T ? data_13 : 32'h0) - | (_wdata_5_value_15_T ? data_14 : 32'h0) - | (_wdata_5_value_16_T ? data_15 : 32'h0) - | (_wdata_5_value_17_T ? data_16 : 32'h0) - | (_wdata_5_value_18_T ? data_17 : 32'h0) - | (_wdata_5_value_19_T ? data_18 : 32'h0) - | (_wdata_5_value_20_T ? data_19 : 32'h0) - | (_wdata_5_value_21_T ? data_20 : 32'h0) - | (_wdata_5_value_22_T ? data_21 : 32'h0) - | (_wdata_5_value_23_T ? data_22 : 32'h0) - | (_wdata_5_value_24_T ? data_23 : 32'h0) - | (_wdata_5_value_25_T ? data_24 : 32'h0) - | (_wdata_5_value_26_T ? data_25 : 32'h0) - | (_wdata_5_value_27_T ? data_26 : 32'h0) - | (_wdata_5_value_28_T ? data_27 : 32'h0) - | (_wdata_5_value_29_T ? data_28 : 32'h0) - | (_wdata_5_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_5_addr) ? data_30 : 32'h0) - : (_wdata_5_value_1_T ? regfile_1 : 32'h0) - | (_wdata_5_value_2_T ? regfile_2 : 32'h0) - | (_wdata_5_value_3_T ? regfile_3 : 32'h0) - | (_wdata_5_value_4_T ? regfile_4 : 32'h0) - | (_wdata_5_value_5_T ? regfile_5 : 32'h0) - | (_wdata_5_value_6_T ? regfile_6 : 32'h0) - | (_wdata_5_value_7_T ? regfile_7 : 32'h0) - | (_wdata_5_value_8_T ? regfile_8 : 32'h0) - | (_wdata_5_value_9_T ? regfile_9 : 32'h0) - | (_wdata_5_value_10_T ? regfile_10 : 32'h0) - | (_wdata_5_value_11_T ? regfile_11 : 32'h0) - | (_wdata_5_value_12_T ? regfile_12 : 32'h0) - | (_wdata_5_value_13_T ? regfile_13 : 32'h0) - | (_wdata_5_value_14_T ? regfile_14 : 32'h0) - | (_wdata_5_value_15_T ? regfile_15 : 32'h0) - | (_wdata_5_value_16_T ? regfile_16 : 32'h0) - | (_wdata_5_value_17_T ? regfile_17 : 32'h0) - | (_wdata_5_value_18_T ? regfile_18 : 32'h0) - | (_wdata_5_value_19_T ? regfile_19 : 32'h0) - | (_wdata_5_value_20_T ? regfile_20 : 32'h0) - | (_wdata_5_value_21_T ? regfile_21 : 32'h0) - | (_wdata_5_value_22_T ? regfile_22 : 32'h0) - | (_wdata_5_value_23_T ? regfile_23 : 32'h0) - | (_wdata_5_value_24_T ? regfile_24 : 32'h0) - | (_wdata_5_value_25_T ? regfile_25 : 32'h0) - | (_wdata_5_value_26_T ? regfile_26 : 32'h0) - | (_wdata_5_value_27_T ? regfile_27 : 32'h0) - | (_wdata_5_value_28_T ? regfile_28 : 32'h0) - | (_wdata_5_value_29_T ? regfile_29 : 32'h0) - | (_wdata_5_value_30_T ? regfile_30 : 32'h0) - | ((&io_readAddr_5_addr) ? regfile_31 : 32'h0); + wire [31:0] rdata_5 = + (_wdata_5_value_1_T ? regfile_1 : 32'h0) | (_wdata_5_value_2_T ? regfile_2 : 32'h0) + | (_wdata_5_value_3_T ? regfile_3 : 32'h0) | (_wdata_5_value_4_T ? regfile_4 : 32'h0) + | (_wdata_5_value_5_T ? regfile_5 : 32'h0) | (_wdata_5_value_6_T ? regfile_6 : 32'h0) + | (_wdata_5_value_7_T ? regfile_7 : 32'h0) | (_wdata_5_value_8_T ? regfile_8 : 32'h0) + | (_wdata_5_value_9_T ? regfile_9 : 32'h0) + | (_wdata_5_value_10_T ? regfile_10 : 32'h0) + | (_wdata_5_value_11_T ? regfile_11 : 32'h0) + | (_wdata_5_value_12_T ? regfile_12 : 32'h0) + | (_wdata_5_value_13_T ? regfile_13 : 32'h0) + | (_wdata_5_value_14_T ? regfile_14 : 32'h0) + | (_wdata_5_value_15_T ? regfile_15 : 32'h0) + | (_wdata_5_value_16_T ? regfile_16 : 32'h0) + | (_wdata_5_value_17_T ? regfile_17 : 32'h0) + | (_wdata_5_value_18_T ? regfile_18 : 32'h0) + | (_wdata_5_value_19_T ? regfile_19 : 32'h0) + | (_wdata_5_value_20_T ? regfile_20 : 32'h0) + | (_wdata_5_value_21_T ? regfile_21 : 32'h0) + | (_wdata_5_value_22_T ? regfile_22 : 32'h0) + | (_wdata_5_value_23_T ? regfile_23 : 32'h0) + | (_wdata_5_value_24_T ? regfile_24 : 32'h0) + | (_wdata_5_value_25_T ? regfile_25 : 32'h0) + | (_wdata_5_value_26_T ? regfile_26 : 32'h0) + | (_wdata_5_value_27_T ? regfile_27 : 32'h0) + | (_wdata_5_value_28_T ? regfile_28 : 32'h0) + | (_wdata_5_value_29_T ? regfile_29 : 32'h0) + | (_wdata_5_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_5_addr) ? regfile_31 : 32'h0); wire _wdata_6_value_1_T = io_readAddr_6_addr == 5'h1; wire _wdata_6_value_2_T = io_readAddr_6_addr == 5'h2; wire _wdata_6_value_3_T = io_readAddr_6_addr == 5'h3; @@ -1556,7 +1264,7 @@ module Regfile( wire _wdata_6_value_28_T = io_readAddr_6_addr == 5'h1C; wire _wdata_6_value_29_T = io_readAddr_6_addr == 5'h1D; wire _wdata_6_value_30_T = io_readAddr_6_addr == 5'h1E; - wire [31:0] rdata_6_value_5_0 = + wire [31:0] rdata_6 = (_wdata_6_value_1_T ? regfile_1 : 32'h0) | (_wdata_6_value_2_T ? regfile_2 : 32'h0) | (_wdata_6_value_3_T ? regfile_3 : 32'h0) | (_wdata_6_value_4_T ? regfile_4 : 32'h0) | (_wdata_6_value_5_T ? regfile_5 : 32'h0) | (_wdata_6_value_6_T ? regfile_6 : 32'h0) @@ -1584,54 +1292,6 @@ module Regfile( | (_wdata_6_value_29_T ? regfile_29 : 32'h0) | (_wdata_6_value_30_T ? regfile_30 : 32'h0) | ((&io_readAddr_6_addr) ? regfile_31 : 32'h0); - wire [31:0] rwdata_6 = - io_readAddr_6_addr == 5'h0 | _wdata_6_value_1_T & (|_writeValid_1_T) - | _wdata_6_value_2_T & (|_writeValid_2_T) | _wdata_6_value_3_T & (|_writeValid_3_T) - | _wdata_6_value_4_T & (|_writeValid_4_T) | _wdata_6_value_5_T & (|_writeValid_5_T) - | _wdata_6_value_6_T & (|_writeValid_6_T) | _wdata_6_value_7_T & (|_writeValid_7_T) - | _wdata_6_value_8_T & (|_writeValid_8_T) | _wdata_6_value_9_T & (|_writeValid_9_T) - | _wdata_6_value_10_T & (|_writeValid_10_T) | _wdata_6_value_11_T - & (|_writeValid_11_T) | _wdata_6_value_12_T & (|_writeValid_12_T) - | _wdata_6_value_13_T & (|_writeValid_13_T) | _wdata_6_value_14_T - & (|_writeValid_14_T) | _wdata_6_value_15_T & (|_writeValid_15_T) - | _wdata_6_value_16_T & (|_writeValid_16_T) | _wdata_6_value_17_T - & (|_writeValid_17_T) | _wdata_6_value_18_T & (|_writeValid_18_T) - | _wdata_6_value_19_T & (|_writeValid_19_T) | _wdata_6_value_20_T - & (|_writeValid_20_T) | _wdata_6_value_21_T & (|_writeValid_21_T) - | _wdata_6_value_22_T & (|_writeValid_22_T) | _wdata_6_value_23_T - & (|_writeValid_23_T) | _wdata_6_value_24_T & (|_writeValid_24_T) - | _wdata_6_value_25_T & (|_writeValid_25_T) | _wdata_6_value_26_T - & (|_writeValid_26_T) | _wdata_6_value_27_T & (|_writeValid_27_T) - | _wdata_6_value_28_T & (|_writeValid_28_T) | _wdata_6_value_29_T - & (|_writeValid_29_T) | _wdata_6_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_6_addr) & (|_writeValid_31_T) - ? (_wdata_6_value_1_T ? data : 32'h0) | (_wdata_6_value_2_T ? data_1 : 32'h0) - | (_wdata_6_value_3_T ? data_2 : 32'h0) | (_wdata_6_value_4_T ? data_3 : 32'h0) - | (_wdata_6_value_5_T ? data_4 : 32'h0) | (_wdata_6_value_6_T ? data_5 : 32'h0) - | (_wdata_6_value_7_T ? data_6 : 32'h0) | (_wdata_6_value_8_T ? data_7 : 32'h0) - | (_wdata_6_value_9_T ? data_8 : 32'h0) | (_wdata_6_value_10_T ? data_9 : 32'h0) - | (_wdata_6_value_11_T ? data_10 : 32'h0) - | (_wdata_6_value_12_T ? data_11 : 32'h0) - | (_wdata_6_value_13_T ? data_12 : 32'h0) - | (_wdata_6_value_14_T ? data_13 : 32'h0) - | (_wdata_6_value_15_T ? data_14 : 32'h0) - | (_wdata_6_value_16_T ? data_15 : 32'h0) - | (_wdata_6_value_17_T ? data_16 : 32'h0) - | (_wdata_6_value_18_T ? data_17 : 32'h0) - | (_wdata_6_value_19_T ? data_18 : 32'h0) - | (_wdata_6_value_20_T ? data_19 : 32'h0) - | (_wdata_6_value_21_T ? data_20 : 32'h0) - | (_wdata_6_value_22_T ? data_21 : 32'h0) - | (_wdata_6_value_23_T ? data_22 : 32'h0) - | (_wdata_6_value_24_T ? data_23 : 32'h0) - | (_wdata_6_value_25_T ? data_24 : 32'h0) - | (_wdata_6_value_26_T ? data_25 : 32'h0) - | (_wdata_6_value_27_T ? data_26 : 32'h0) - | (_wdata_6_value_28_T ? data_27 : 32'h0) - | (_wdata_6_value_29_T ? data_28 : 32'h0) - | (_wdata_6_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_6_addr) ? data_30 : 32'h0) - : rdata_6_value_5_0; wire _wdata_7_value_1_T = io_readAddr_7_addr == 5'h1; wire _wdata_7_value_2_T = io_readAddr_7_addr == 5'h2; wire _wdata_7_value_3_T = io_readAddr_7_addr == 5'h3; @@ -1662,116 +1322,632 @@ module Regfile( wire _wdata_7_value_28_T = io_readAddr_7_addr == 5'h1C; wire _wdata_7_value_29_T = io_readAddr_7_addr == 5'h1D; wire _wdata_7_value_30_T = io_readAddr_7_addr == 5'h1E; - wire [31:0] rwdata_7 = - io_readAddr_7_addr == 5'h0 | _wdata_7_value_1_T & (|_writeValid_1_T) - | _wdata_7_value_2_T & (|_writeValid_2_T) | _wdata_7_value_3_T & (|_writeValid_3_T) - | _wdata_7_value_4_T & (|_writeValid_4_T) | _wdata_7_value_5_T & (|_writeValid_5_T) - | _wdata_7_value_6_T & (|_writeValid_6_T) | _wdata_7_value_7_T & (|_writeValid_7_T) - | _wdata_7_value_8_T & (|_writeValid_8_T) | _wdata_7_value_9_T & (|_writeValid_9_T) - | _wdata_7_value_10_T & (|_writeValid_10_T) | _wdata_7_value_11_T - & (|_writeValid_11_T) | _wdata_7_value_12_T & (|_writeValid_12_T) - | _wdata_7_value_13_T & (|_writeValid_13_T) | _wdata_7_value_14_T - & (|_writeValid_14_T) | _wdata_7_value_15_T & (|_writeValid_15_T) - | _wdata_7_value_16_T & (|_writeValid_16_T) | _wdata_7_value_17_T - & (|_writeValid_17_T) | _wdata_7_value_18_T & (|_writeValid_18_T) - | _wdata_7_value_19_T & (|_writeValid_19_T) | _wdata_7_value_20_T - & (|_writeValid_20_T) | _wdata_7_value_21_T & (|_writeValid_21_T) - | _wdata_7_value_22_T & (|_writeValid_22_T) | _wdata_7_value_23_T - & (|_writeValid_23_T) | _wdata_7_value_24_T & (|_writeValid_24_T) - | _wdata_7_value_25_T & (|_writeValid_25_T) | _wdata_7_value_26_T - & (|_writeValid_26_T) | _wdata_7_value_27_T & (|_writeValid_27_T) - | _wdata_7_value_28_T & (|_writeValid_28_T) | _wdata_7_value_29_T - & (|_writeValid_29_T) | _wdata_7_value_30_T & (|_writeValid_30_T) - | (&io_readAddr_7_addr) & (|_writeValid_31_T) - ? (_wdata_7_value_1_T ? data : 32'h0) | (_wdata_7_value_2_T ? data_1 : 32'h0) - | (_wdata_7_value_3_T ? data_2 : 32'h0) | (_wdata_7_value_4_T ? data_3 : 32'h0) - | (_wdata_7_value_5_T ? data_4 : 32'h0) | (_wdata_7_value_6_T ? data_5 : 32'h0) - | (_wdata_7_value_7_T ? data_6 : 32'h0) | (_wdata_7_value_8_T ? data_7 : 32'h0) - | (_wdata_7_value_9_T ? data_8 : 32'h0) | (_wdata_7_value_10_T ? data_9 : 32'h0) - | (_wdata_7_value_11_T ? data_10 : 32'h0) - | (_wdata_7_value_12_T ? data_11 : 32'h0) - | (_wdata_7_value_13_T ? data_12 : 32'h0) - | (_wdata_7_value_14_T ? data_13 : 32'h0) - | (_wdata_7_value_15_T ? data_14 : 32'h0) - | (_wdata_7_value_16_T ? data_15 : 32'h0) - | (_wdata_7_value_17_T ? data_16 : 32'h0) - | (_wdata_7_value_18_T ? data_17 : 32'h0) - | (_wdata_7_value_19_T ? data_18 : 32'h0) - | (_wdata_7_value_20_T ? data_19 : 32'h0) - | (_wdata_7_value_21_T ? data_20 : 32'h0) - | (_wdata_7_value_22_T ? data_21 : 32'h0) - | (_wdata_7_value_23_T ? data_22 : 32'h0) - | (_wdata_7_value_24_T ? data_23 : 32'h0) - | (_wdata_7_value_25_T ? data_24 : 32'h0) - | (_wdata_7_value_26_T ? data_25 : 32'h0) - | (_wdata_7_value_27_T ? data_26 : 32'h0) - | (_wdata_7_value_28_T ? data_27 : 32'h0) - | (_wdata_7_value_29_T ? data_28 : 32'h0) - | (_wdata_7_value_30_T ? data_29 : 32'h0) - | ((&io_readAddr_7_addr) ? data_30 : 32'h0) - : (_wdata_7_value_1_T ? regfile_1 : 32'h0) - | (_wdata_7_value_2_T ? regfile_2 : 32'h0) - | (_wdata_7_value_3_T ? regfile_3 : 32'h0) - | (_wdata_7_value_4_T ? regfile_4 : 32'h0) - | (_wdata_7_value_5_T ? regfile_5 : 32'h0) - | (_wdata_7_value_6_T ? regfile_6 : 32'h0) - | (_wdata_7_value_7_T ? regfile_7 : 32'h0) - | (_wdata_7_value_8_T ? regfile_8 : 32'h0) - | (_wdata_7_value_9_T ? regfile_9 : 32'h0) - | (_wdata_7_value_10_T ? regfile_10 : 32'h0) - | (_wdata_7_value_11_T ? regfile_11 : 32'h0) - | (_wdata_7_value_12_T ? regfile_12 : 32'h0) - | (_wdata_7_value_13_T ? regfile_13 : 32'h0) - | (_wdata_7_value_14_T ? regfile_14 : 32'h0) - | (_wdata_7_value_15_T ? regfile_15 : 32'h0) - | (_wdata_7_value_16_T ? regfile_16 : 32'h0) - | (_wdata_7_value_17_T ? regfile_17 : 32'h0) - | (_wdata_7_value_18_T ? regfile_18 : 32'h0) - | (_wdata_7_value_19_T ? regfile_19 : 32'h0) - | (_wdata_7_value_20_T ? regfile_20 : 32'h0) - | (_wdata_7_value_21_T ? regfile_21 : 32'h0) - | (_wdata_7_value_22_T ? regfile_22 : 32'h0) - | (_wdata_7_value_23_T ? regfile_23 : 32'h0) - | (_wdata_7_value_24_T ? regfile_24 : 32'h0) - | (_wdata_7_value_25_T ? regfile_25 : 32'h0) - | (_wdata_7_value_26_T ? regfile_26 : 32'h0) - | (_wdata_7_value_27_T ? regfile_27 : 32'h0) - | (_wdata_7_value_28_T ? regfile_28 : 32'h0) - | (_wdata_7_value_29_T ? regfile_29 : 32'h0) - | (_wdata_7_value_30_T ? regfile_30 : 32'h0) - | ((&io_readAddr_7_addr) ? regfile_31 : 32'h0); - wire [31:0] busAddr_0 = - io_busAddr_0_bypass - ? rwdata_0 - : io_busAddr_0_immen ? rdata_0_value_5_0 + io_busAddr_0_immed : rdata_0_value_5_0; - wire [31:0] busAddr_1 = - io_busAddr_1_bypass ? rwdata_2 : rdata_2_value_5_0 + io_busAddr_1_immed; - wire [31:0] busAddr_2 = - io_busAddr_2_bypass ? rwdata_4 : rdata_4_value_5_0 + io_busAddr_2_immed; - wire [31:0] busAddr_3 = - io_busAddr_3_bypass ? rwdata_6 : rdata_6_value_5_0 + io_busAddr_3_immed; - reg write_fail; - reg write_fail_1; - reg write_fail_2; - reg write_fail_3; - reg write_fail_4; - reg write_fail_5; - reg write_fail_6; - reg write_fail_7; - reg write_fail_8; - reg write_fail_9; - reg write_fail_10; - reg write_fail_11; - reg write_fail_12; - reg write_fail_13; - reg write_fail_14; - reg scoreboard_error; + wire [31:0] rdata_7 = + (_wdata_7_value_1_T ? regfile_1 : 32'h0) | (_wdata_7_value_2_T ? regfile_2 : 32'h0) + | (_wdata_7_value_3_T ? regfile_3 : 32'h0) | (_wdata_7_value_4_T ? regfile_4 : 32'h0) + | (_wdata_7_value_5_T ? regfile_5 : 32'h0) | (_wdata_7_value_6_T ? regfile_6 : 32'h0) + | (_wdata_7_value_7_T ? regfile_7 : 32'h0) | (_wdata_7_value_8_T ? regfile_8 : 32'h0) + | (_wdata_7_value_9_T ? regfile_9 : 32'h0) + | (_wdata_7_value_10_T ? regfile_10 : 32'h0) + | (_wdata_7_value_11_T ? regfile_11 : 32'h0) + | (_wdata_7_value_12_T ? regfile_12 : 32'h0) + | (_wdata_7_value_13_T ? regfile_13 : 32'h0) + | (_wdata_7_value_14_T ? regfile_14 : 32'h0) + | (_wdata_7_value_15_T ? regfile_15 : 32'h0) + | (_wdata_7_value_16_T ? regfile_16 : 32'h0) + | (_wdata_7_value_17_T ? regfile_17 : 32'h0) + | (_wdata_7_value_18_T ? regfile_18 : 32'h0) + | (_wdata_7_value_19_T ? regfile_19 : 32'h0) + | (_wdata_7_value_20_T ? regfile_20 : 32'h0) + | (_wdata_7_value_21_T ? regfile_21 : 32'h0) + | (_wdata_7_value_22_T ? regfile_22 : 32'h0) + | (_wdata_7_value_23_T ? regfile_23 : 32'h0) + | (_wdata_7_value_24_T ? regfile_24 : 32'h0) + | (_wdata_7_value_25_T ? regfile_25 : 32'h0) + | (_wdata_7_value_26_T ? regfile_26 : 32'h0) + | (_wdata_7_value_27_T ? regfile_27 : 32'h0) + | (_wdata_7_value_28_T ? regfile_28 : 32'h0) + | (_wdata_7_value_29_T ? regfile_29 : 32'h0) + | (_wdata_7_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_7_addr) ? regfile_31 : 32'h0); + wire [31:0] _busAddr_0_T = rdata_0 + io_busAddr_0_immed; + wire [31:0] _busAddr_1_T = rdata_2 + io_busAddr_1_immed; + wire [31:0] _busAddr_2_T = rdata_4 + io_busAddr_2_immed; + wire [31:0] _busAddr_3_T = rdata_6 + io_busAddr_3_immed; wire [31:0] scoreboard_set = (io_writeAddr_0_valid ? 32'h1 << io_writeAddr_0_addr : 32'h0) | (io_writeAddr_1_valid ? 32'h1 << io_writeAddr_1_addr : 32'h0) | (io_writeAddr_2_valid ? 32'h1 << io_writeAddr_2_addr : 32'h0) | (io_writeAddr_3_valid ? 32'h1 << io_writeAddr_3_addr : 32'h0); - wire [31:0] scoreboard_clr = {scoreboard_clr0, 1'h0}; + wire _valid_T = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1; + wire valid_1 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1 & ~io_writeMask_1_valid; + wire valid_2 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1 & ~io_writeMask_2_valid; + wire valid_3 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1 & ~io_writeMask_3_valid; + wire _valid_T_8 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1; + wire valid_5 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1 & ~io_writeMask_5_valid; + wire [31:0] data = + (_valid_T ? io_writeData_0_bits_data : 32'h0) + | (valid_1 ? io_writeData_1_bits_data : 32'h0) + | (valid_2 ? io_writeData_2_bits_data : 32'h0) + | (valid_3 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_8 ? io_writeData_4_bits_data : 32'h0) + | (valid_5 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_1_T = + {_valid_T, valid_1, valid_2, valid_3, _valid_T_8, valid_5}; + wire _valid_T_12 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h2; + wire valid_1_1 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h2 & ~io_writeMask_1_valid; + wire valid_2_1 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h2 & ~io_writeMask_2_valid; + wire valid_3_1 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h2 & ~io_writeMask_3_valid; + wire _valid_T_20 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h2; + wire valid_5_1 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h2 & ~io_writeMask_5_valid; + wire [31:0] data_1 = + (_valid_T_12 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_1 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_1 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_1 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_20 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_1 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_2_T = + {_valid_T_12, valid_1_1, valid_2_1, valid_3_1, _valid_T_20, valid_5_1}; + wire _valid_T_24 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h3; + wire valid_1_2 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h3 & ~io_writeMask_1_valid; + wire valid_2_2 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h3 & ~io_writeMask_2_valid; + wire valid_3_2 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h3 & ~io_writeMask_3_valid; + wire _valid_T_32 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h3; + wire valid_5_2 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h3 & ~io_writeMask_5_valid; + wire [31:0] data_2 = + (_valid_T_24 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_2 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_2 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_2 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_32 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_2 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_3_T = + {_valid_T_24, valid_1_2, valid_2_2, valid_3_2, _valid_T_32, valid_5_2}; + wire _valid_T_36 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h4; + wire valid_1_3 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h4 & ~io_writeMask_1_valid; + wire valid_2_3 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h4 & ~io_writeMask_2_valid; + wire valid_3_3 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h4 & ~io_writeMask_3_valid; + wire _valid_T_44 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h4; + wire valid_5_3 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h4 & ~io_writeMask_5_valid; + wire [31:0] data_3 = + (_valid_T_36 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_3 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_3 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_3 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_44 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_3 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_4_T = + {_valid_T_36, valid_1_3, valid_2_3, valid_3_3, _valid_T_44, valid_5_3}; + wire _valid_T_48 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h5; + wire valid_1_4 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h5 & ~io_writeMask_1_valid; + wire valid_2_4 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h5 & ~io_writeMask_2_valid; + wire valid_3_4 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h5 & ~io_writeMask_3_valid; + wire _valid_T_56 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h5; + wire valid_5_4 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h5 & ~io_writeMask_5_valid; + wire [31:0] data_4 = + (_valid_T_48 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_4 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_4 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_4 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_56 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_4 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_5_T = + {_valid_T_48, valid_1_4, valid_2_4, valid_3_4, _valid_T_56, valid_5_4}; + wire _valid_T_60 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h6; + wire valid_1_5 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h6 & ~io_writeMask_1_valid; + wire valid_2_5 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h6 & ~io_writeMask_2_valid; + wire valid_3_5 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h6 & ~io_writeMask_3_valid; + wire _valid_T_68 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h6; + wire valid_5_5 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h6 & ~io_writeMask_5_valid; + wire [31:0] data_5 = + (_valid_T_60 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_5 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_5 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_5 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_68 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_5 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_6_T = + {_valid_T_60, valid_1_5, valid_2_5, valid_3_5, _valid_T_68, valid_5_5}; + wire _valid_T_72 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h7; + wire valid_1_6 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h7 & ~io_writeMask_1_valid; + wire valid_2_6 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h7 & ~io_writeMask_2_valid; + wire valid_3_6 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h7 & ~io_writeMask_3_valid; + wire _valid_T_80 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h7; + wire valid_5_6 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h7 & ~io_writeMask_5_valid; + wire [31:0] data_6 = + (_valid_T_72 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_6 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_6 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_6 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_80 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_6 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_7_T = + {_valid_T_72, valid_1_6, valid_2_6, valid_3_6, _valid_T_80, valid_5_6}; + wire _valid_T_84 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h8; + wire valid_1_7 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h8 & ~io_writeMask_1_valid; + wire valid_2_7 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h8 & ~io_writeMask_2_valid; + wire valid_3_7 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h8 & ~io_writeMask_3_valid; + wire _valid_T_92 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h8; + wire valid_5_7 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h8 & ~io_writeMask_5_valid; + wire [31:0] data_7 = + (_valid_T_84 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_7 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_7 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_7 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_92 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_7 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_8_T = + {_valid_T_84, valid_1_7, valid_2_7, valid_3_7, _valid_T_92, valid_5_7}; + wire _valid_T_96 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h9; + wire valid_1_8 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h9 & ~io_writeMask_1_valid; + wire valid_2_8 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h9 & ~io_writeMask_2_valid; + wire valid_3_8 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h9 & ~io_writeMask_3_valid; + wire _valid_T_104 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h9; + wire valid_5_8 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h9 & ~io_writeMask_5_valid; + wire [31:0] data_8 = + (_valid_T_96 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_8 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_8 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_8 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_104 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_8 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_9_T = + {_valid_T_96, valid_1_8, valid_2_8, valid_3_8, _valid_T_104, valid_5_8}; + wire _valid_T_108 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hA; + wire valid_1_9 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hA & ~io_writeMask_1_valid; + wire valid_2_9 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hA & ~io_writeMask_2_valid; + wire valid_3_9 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hA & ~io_writeMask_3_valid; + wire _valid_T_116 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hA; + wire valid_5_9 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hA & ~io_writeMask_5_valid; + wire [31:0] data_9 = + (_valid_T_108 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_9 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_9 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_9 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_116 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_9 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_10_T = + {_valid_T_108, valid_1_9, valid_2_9, valid_3_9, _valid_T_116, valid_5_9}; + wire _valid_T_120 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hB; + wire valid_1_10 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hB & ~io_writeMask_1_valid; + wire valid_2_10 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hB & ~io_writeMask_2_valid; + wire valid_3_10 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hB & ~io_writeMask_3_valid; + wire _valid_T_128 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hB; + wire valid_5_10 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hB & ~io_writeMask_5_valid; + wire [31:0] data_10 = + (_valid_T_120 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_10 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_10 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_10 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_128 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_10 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_11_T = + {_valid_T_120, valid_1_10, valid_2_10, valid_3_10, _valid_T_128, valid_5_10}; + wire _valid_T_132 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hC; + wire valid_1_11 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hC & ~io_writeMask_1_valid; + wire valid_2_11 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hC & ~io_writeMask_2_valid; + wire valid_3_11 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hC & ~io_writeMask_3_valid; + wire _valid_T_140 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hC; + wire valid_5_11 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hC & ~io_writeMask_5_valid; + wire [31:0] data_11 = + (_valid_T_132 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_11 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_11 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_11 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_140 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_11 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_12_T = + {_valid_T_132, valid_1_11, valid_2_11, valid_3_11, _valid_T_140, valid_5_11}; + wire _valid_T_144 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hD; + wire valid_1_12 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hD & ~io_writeMask_1_valid; + wire valid_2_12 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hD & ~io_writeMask_2_valid; + wire valid_3_12 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hD & ~io_writeMask_3_valid; + wire _valid_T_152 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hD; + wire valid_5_12 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hD & ~io_writeMask_5_valid; + wire [31:0] data_12 = + (_valid_T_144 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_12 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_12 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_12 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_152 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_12 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_13_T = + {_valid_T_144, valid_1_12, valid_2_12, valid_3_12, _valid_T_152, valid_5_12}; + wire _valid_T_156 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hE; + wire valid_1_13 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hE & ~io_writeMask_1_valid; + wire valid_2_13 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hE & ~io_writeMask_2_valid; + wire valid_3_13 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hE & ~io_writeMask_3_valid; + wire _valid_T_164 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hE; + wire valid_5_13 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hE & ~io_writeMask_5_valid; + wire [31:0] data_13 = + (_valid_T_156 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_13 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_13 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_13 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_164 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_13 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_14_T = + {_valid_T_156, valid_1_13, valid_2_13, valid_3_13, _valid_T_164, valid_5_13}; + wire _valid_T_168 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hF; + wire valid_1_14 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hF & ~io_writeMask_1_valid; + wire valid_2_14 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hF & ~io_writeMask_2_valid; + wire valid_3_14 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hF & ~io_writeMask_3_valid; + wire _valid_T_176 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hF; + wire valid_5_14 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'hF & ~io_writeMask_5_valid; + wire [31:0] data_14 = + (_valid_T_168 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_14 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_14 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_14 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_176 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_14 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_15_T = + {_valid_T_168, valid_1_14, valid_2_14, valid_3_14, _valid_T_176, valid_5_14}; + wire _valid_T_180 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h10; + wire valid_1_15 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h10 & ~io_writeMask_1_valid; + wire valid_2_15 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h10 & ~io_writeMask_2_valid; + wire valid_3_15 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h10 & ~io_writeMask_3_valid; + wire _valid_T_188 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h10; + wire valid_5_15 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h10 & ~io_writeMask_5_valid; + wire [31:0] data_15 = + (_valid_T_180 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_15 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_15 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_15 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_188 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_15 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_16_T = + {_valid_T_180, valid_1_15, valid_2_15, valid_3_15, _valid_T_188, valid_5_15}; + wire _valid_T_192 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h11; + wire valid_1_16 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h11 & ~io_writeMask_1_valid; + wire valid_2_16 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h11 & ~io_writeMask_2_valid; + wire valid_3_16 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h11 & ~io_writeMask_3_valid; + wire _valid_T_200 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h11; + wire valid_5_16 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h11 & ~io_writeMask_5_valid; + wire [31:0] data_16 = + (_valid_T_192 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_16 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_16 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_16 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_200 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_16 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_17_T = + {_valid_T_192, valid_1_16, valid_2_16, valid_3_16, _valid_T_200, valid_5_16}; + wire _valid_T_204 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h12; + wire valid_1_17 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h12 & ~io_writeMask_1_valid; + wire valid_2_17 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h12 & ~io_writeMask_2_valid; + wire valid_3_17 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h12 & ~io_writeMask_3_valid; + wire _valid_T_212 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h12; + wire valid_5_17 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h12 & ~io_writeMask_5_valid; + wire [31:0] data_17 = + (_valid_T_204 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_17 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_17 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_17 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_212 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_17 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_18_T = + {_valid_T_204, valid_1_17, valid_2_17, valid_3_17, _valid_T_212, valid_5_17}; + wire _valid_T_216 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h13; + wire valid_1_18 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h13 & ~io_writeMask_1_valid; + wire valid_2_18 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h13 & ~io_writeMask_2_valid; + wire valid_3_18 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h13 & ~io_writeMask_3_valid; + wire _valid_T_224 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h13; + wire valid_5_18 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h13 & ~io_writeMask_5_valid; + wire [31:0] data_18 = + (_valid_T_216 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_18 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_18 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_18 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_224 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_18 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_19_T = + {_valid_T_216, valid_1_18, valid_2_18, valid_3_18, _valid_T_224, valid_5_18}; + wire _valid_T_228 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h14; + wire valid_1_19 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h14 & ~io_writeMask_1_valid; + wire valid_2_19 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h14 & ~io_writeMask_2_valid; + wire valid_3_19 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h14 & ~io_writeMask_3_valid; + wire _valid_T_236 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h14; + wire valid_5_19 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h14 & ~io_writeMask_5_valid; + wire [31:0] data_19 = + (_valid_T_228 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_19 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_19 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_19 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_236 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_19 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_20_T = + {_valid_T_228, valid_1_19, valid_2_19, valid_3_19, _valid_T_236, valid_5_19}; + wire _valid_T_240 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h15; + wire valid_1_20 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h15 & ~io_writeMask_1_valid; + wire valid_2_20 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h15 & ~io_writeMask_2_valid; + wire valid_3_20 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h15 & ~io_writeMask_3_valid; + wire _valid_T_248 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h15; + wire valid_5_20 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h15 & ~io_writeMask_5_valid; + wire [31:0] data_20 = + (_valid_T_240 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_20 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_20 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_20 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_248 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_20 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_21_T = + {_valid_T_240, valid_1_20, valid_2_20, valid_3_20, _valid_T_248, valid_5_20}; + wire _valid_T_252 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h16; + wire valid_1_21 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h16 & ~io_writeMask_1_valid; + wire valid_2_21 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h16 & ~io_writeMask_2_valid; + wire valid_3_21 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h16 & ~io_writeMask_3_valid; + wire _valid_T_260 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h16; + wire valid_5_21 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h16 & ~io_writeMask_5_valid; + wire [31:0] data_21 = + (_valid_T_252 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_21 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_21 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_21 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_260 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_21 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_22_T = + {_valid_T_252, valid_1_21, valid_2_21, valid_3_21, _valid_T_260, valid_5_21}; + wire _valid_T_264 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h17; + wire valid_1_22 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h17 & ~io_writeMask_1_valid; + wire valid_2_22 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h17 & ~io_writeMask_2_valid; + wire valid_3_22 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h17 & ~io_writeMask_3_valid; + wire _valid_T_272 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h17; + wire valid_5_22 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h17 & ~io_writeMask_5_valid; + wire [31:0] data_22 = + (_valid_T_264 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_22 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_22 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_22 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_272 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_22 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_23_T = + {_valid_T_264, valid_1_22, valid_2_22, valid_3_22, _valid_T_272, valid_5_22}; + wire _valid_T_276 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h18; + wire valid_1_23 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h18 & ~io_writeMask_1_valid; + wire valid_2_23 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h18 & ~io_writeMask_2_valid; + wire valid_3_23 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h18 & ~io_writeMask_3_valid; + wire _valid_T_284 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h18; + wire valid_5_23 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h18 & ~io_writeMask_5_valid; + wire [31:0] data_23 = + (_valid_T_276 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_23 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_23 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_23 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_284 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_23 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_24_T = + {_valid_T_276, valid_1_23, valid_2_23, valid_3_23, _valid_T_284, valid_5_23}; + wire _valid_T_288 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h19; + wire valid_1_24 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h19 & ~io_writeMask_1_valid; + wire valid_2_24 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h19 & ~io_writeMask_2_valid; + wire valid_3_24 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h19 & ~io_writeMask_3_valid; + wire _valid_T_296 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h19; + wire valid_5_24 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h19 & ~io_writeMask_5_valid; + wire [31:0] data_24 = + (_valid_T_288 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_24 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_24 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_24 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_296 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_24 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_25_T = + {_valid_T_288, valid_1_24, valid_2_24, valid_3_24, _valid_T_296, valid_5_24}; + wire _valid_T_300 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1A; + wire valid_1_25 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1A & ~io_writeMask_1_valid; + wire valid_2_25 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1A & ~io_writeMask_2_valid; + wire valid_3_25 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1A & ~io_writeMask_3_valid; + wire _valid_T_308 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1A; + wire valid_5_25 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1A & ~io_writeMask_5_valid; + wire [31:0] data_25 = + (_valid_T_300 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_25 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_25 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_25 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_308 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_25 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_26_T = + {_valid_T_300, valid_1_25, valid_2_25, valid_3_25, _valid_T_308, valid_5_25}; + wire _valid_T_312 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1B; + wire valid_1_26 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1B & ~io_writeMask_1_valid; + wire valid_2_26 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1B & ~io_writeMask_2_valid; + wire valid_3_26 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1B & ~io_writeMask_3_valid; + wire _valid_T_320 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1B; + wire valid_5_26 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1B & ~io_writeMask_5_valid; + wire [31:0] data_26 = + (_valid_T_312 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_26 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_26 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_26 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_320 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_26 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_27_T = + {_valid_T_312, valid_1_26, valid_2_26, valid_3_26, _valid_T_320, valid_5_26}; + wire _valid_T_324 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1C; + wire valid_1_27 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1C & ~io_writeMask_1_valid; + wire valid_2_27 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1C & ~io_writeMask_2_valid; + wire valid_3_27 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1C & ~io_writeMask_3_valid; + wire _valid_T_332 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1C; + wire valid_5_27 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1C & ~io_writeMask_5_valid; + wire [31:0] data_27 = + (_valid_T_324 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_27 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_27 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_27 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_332 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_27 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_28_T = + {_valid_T_324, valid_1_27, valid_2_27, valid_3_27, _valid_T_332, valid_5_27}; + wire _valid_T_336 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1D; + wire valid_1_28 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1D & ~io_writeMask_1_valid; + wire valid_2_28 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1D & ~io_writeMask_2_valid; + wire valid_3_28 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1D & ~io_writeMask_3_valid; + wire _valid_T_344 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1D; + wire valid_5_28 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1D & ~io_writeMask_5_valid; + wire [31:0] data_28 = + (_valid_T_336 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_28 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_28 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_28 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_344 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_28 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_29_T = + {_valid_T_336, valid_1_28, valid_2_28, valid_3_28, _valid_T_344, valid_5_28}; + wire _valid_T_348 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1E; + wire valid_1_29 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1E & ~io_writeMask_1_valid; + wire valid_2_29 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1E & ~io_writeMask_2_valid; + wire valid_3_29 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1E & ~io_writeMask_3_valid; + wire _valid_T_356 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1E; + wire valid_5_29 = + io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1E & ~io_writeMask_5_valid; + wire [31:0] data_29 = + (_valid_T_348 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_29 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_29 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_29 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_356 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_29 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_30_T = + {_valid_T_348, valid_1_29, valid_2_29, valid_3_29, _valid_T_356, valid_5_29}; + wire _valid_T_360 = io_writeData_0_valid & (&io_writeData_0_bits_addr); + wire valid_1_30 = + io_writeData_1_valid & (&io_writeData_1_bits_addr) & ~io_writeMask_1_valid; + wire valid_2_30 = + io_writeData_2_valid & (&io_writeData_2_bits_addr) & ~io_writeMask_2_valid; + wire valid_3_30 = + io_writeData_3_valid & (&io_writeData_3_bits_addr) & ~io_writeMask_3_valid; + wire _valid_T_368 = io_writeData_4_valid & (&io_writeData_4_bits_addr); + wire valid_5_30 = + io_writeData_5_valid & (&io_writeData_5_bits_addr) & ~io_writeMask_5_valid; + wire [31:0] data_30 = + (_valid_T_360 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_30 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_30 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_30 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_368 ? io_writeData_4_bits_data : 32'h0) + | (valid_5_30 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_31_T = + {_valid_T_360, valid_1_30, valid_2_30, valid_3_30, _valid_T_368, valid_5_30}; always @(posedge clock or posedge reset) begin if (reset) begin regfile_1 <= 32'h0; @@ -1806,14 +1982,6 @@ module Regfile( regfile_30 <= 32'h0; regfile_31 <= 32'h0; scoreboard <= 32'h0; - readDataReady_0 <= 1'h0; - readDataReady_1 <= 1'h0; - readDataReady_2 <= 1'h0; - readDataReady_3 <= 1'h0; - readDataReady_4 <= 1'h0; - readDataReady_5 <= 1'h0; - readDataReady_6 <= 1'h0; - readDataReady_7 <= 1'h0; readDataBits_0 <= 32'h0; readDataBits_1 <= 32'h0; readDataBits_2 <= 32'h0; @@ -1822,22 +1990,6 @@ module Regfile( readDataBits_5 <= 32'h0; readDataBits_6 <= 32'h0; readDataBits_7 <= 32'h0; - write_fail <= 1'h0; - write_fail_1 <= 1'h0; - write_fail_2 <= 1'h0; - write_fail_3 <= 1'h0; - write_fail_4 <= 1'h0; - write_fail_5 <= 1'h0; - write_fail_6 <= 1'h0; - write_fail_7 <= 1'h0; - write_fail_8 <= 1'h0; - write_fail_9 <= 1'h0; - write_fail_10 <= 1'h0; - write_fail_11 <= 1'h0; - write_fail_12 <= 1'h0; - write_fail_13 <= 1'h0; - write_fail_14 <= 1'h0; - scoreboard_error <= 1'h0; end else begin if (|_writeValid_1_T) @@ -1902,189 +2054,465 @@ module Regfile( regfile_30 <= data_29; if (|_writeValid_31_T) regfile_31 <= data_30; - if (|{scoreboard_set, scoreboard_clr0}) + if (io_pipelineFlush) + scoreboard <= {scoreboard_set[31:1], 1'h0}; + else if (|{scoreboard_set, scoreboard_clr0}) scoreboard <= {scoreboard[31:1] & ~scoreboard_clr0 | scoreboard_set[31:1], 1'h0}; - readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid; - readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid; - readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid; - readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid; - readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid; - readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid; - readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid; - readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid; if (io_readSet_0_valid) readDataBits_0 <= io_readSet_0_value; else if (io_readAddr_0_valid) - readDataBits_0 <= rwdata_0; + readDataBits_0 <= + io_readAddr_0_addr == 5'h0 | _wdata_0_value_1_T & (|_writeValid_1_T) + | _wdata_0_value_2_T & (|_writeValid_2_T) | _wdata_0_value_3_T + & (|_writeValid_3_T) | _wdata_0_value_4_T & (|_writeValid_4_T) + | _wdata_0_value_5_T & (|_writeValid_5_T) | _wdata_0_value_6_T + & (|_writeValid_6_T) | _wdata_0_value_7_T & (|_writeValid_7_T) + | _wdata_0_value_8_T & (|_writeValid_8_T) | _wdata_0_value_9_T + & (|_writeValid_9_T) | _wdata_0_value_10_T & (|_writeValid_10_T) + | _wdata_0_value_11_T & (|_writeValid_11_T) | _wdata_0_value_12_T + & (|_writeValid_12_T) | _wdata_0_value_13_T & (|_writeValid_13_T) + | _wdata_0_value_14_T & (|_writeValid_14_T) | _wdata_0_value_15_T + & (|_writeValid_15_T) | _wdata_0_value_16_T & (|_writeValid_16_T) + | _wdata_0_value_17_T & (|_writeValid_17_T) | _wdata_0_value_18_T + & (|_writeValid_18_T) | _wdata_0_value_19_T & (|_writeValid_19_T) + | _wdata_0_value_20_T & (|_writeValid_20_T) | _wdata_0_value_21_T + & (|_writeValid_21_T) | _wdata_0_value_22_T & (|_writeValid_22_T) + | _wdata_0_value_23_T & (|_writeValid_23_T) | _wdata_0_value_24_T + & (|_writeValid_24_T) | _wdata_0_value_25_T & (|_writeValid_25_T) + | _wdata_0_value_26_T & (|_writeValid_26_T) | _wdata_0_value_27_T + & (|_writeValid_27_T) | _wdata_0_value_28_T & (|_writeValid_28_T) + | _wdata_0_value_29_T & (|_writeValid_29_T) | _wdata_0_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_0_addr) & (|_writeValid_31_T) + ? (_wdata_0_value_1_T ? data : 32'h0) | (_wdata_0_value_2_T ? data_1 : 32'h0) + | (_wdata_0_value_3_T ? data_2 : 32'h0) + | (_wdata_0_value_4_T ? data_3 : 32'h0) + | (_wdata_0_value_5_T ? data_4 : 32'h0) + | (_wdata_0_value_6_T ? data_5 : 32'h0) + | (_wdata_0_value_7_T ? data_6 : 32'h0) + | (_wdata_0_value_8_T ? data_7 : 32'h0) + | (_wdata_0_value_9_T ? data_8 : 32'h0) + | (_wdata_0_value_10_T ? data_9 : 32'h0) + | (_wdata_0_value_11_T ? data_10 : 32'h0) + | (_wdata_0_value_12_T ? data_11 : 32'h0) + | (_wdata_0_value_13_T ? data_12 : 32'h0) + | (_wdata_0_value_14_T ? data_13 : 32'h0) + | (_wdata_0_value_15_T ? data_14 : 32'h0) + | (_wdata_0_value_16_T ? data_15 : 32'h0) + | (_wdata_0_value_17_T ? data_16 : 32'h0) + | (_wdata_0_value_18_T ? data_17 : 32'h0) + | (_wdata_0_value_19_T ? data_18 : 32'h0) + | (_wdata_0_value_20_T ? data_19 : 32'h0) + | (_wdata_0_value_21_T ? data_20 : 32'h0) + | (_wdata_0_value_22_T ? data_21 : 32'h0) + | (_wdata_0_value_23_T ? data_22 : 32'h0) + | (_wdata_0_value_24_T ? data_23 : 32'h0) + | (_wdata_0_value_25_T ? data_24 : 32'h0) + | (_wdata_0_value_26_T ? data_25 : 32'h0) + | (_wdata_0_value_27_T ? data_26 : 32'h0) + | (_wdata_0_value_28_T ? data_27 : 32'h0) + | (_wdata_0_value_29_T ? data_28 : 32'h0) + | (_wdata_0_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_0_addr) ? data_30 : 32'h0) + : rdata_0; if (io_readSet_1_valid) readDataBits_1 <= io_readSet_1_value; else if (io_readAddr_1_valid) - readDataBits_1 <= rwdata_1; + readDataBits_1 <= + io_readAddr_1_addr == 5'h0 | _wdata_1_value_1_T & (|_writeValid_1_T) + | _wdata_1_value_2_T & (|_writeValid_2_T) | _wdata_1_value_3_T + & (|_writeValid_3_T) | _wdata_1_value_4_T & (|_writeValid_4_T) + | _wdata_1_value_5_T & (|_writeValid_5_T) | _wdata_1_value_6_T + & (|_writeValid_6_T) | _wdata_1_value_7_T & (|_writeValid_7_T) + | _wdata_1_value_8_T & (|_writeValid_8_T) | _wdata_1_value_9_T + & (|_writeValid_9_T) | _wdata_1_value_10_T & (|_writeValid_10_T) + | _wdata_1_value_11_T & (|_writeValid_11_T) | _wdata_1_value_12_T + & (|_writeValid_12_T) | _wdata_1_value_13_T & (|_writeValid_13_T) + | _wdata_1_value_14_T & (|_writeValid_14_T) | _wdata_1_value_15_T + & (|_writeValid_15_T) | _wdata_1_value_16_T & (|_writeValid_16_T) + | _wdata_1_value_17_T & (|_writeValid_17_T) | _wdata_1_value_18_T + & (|_writeValid_18_T) | _wdata_1_value_19_T & (|_writeValid_19_T) + | _wdata_1_value_20_T & (|_writeValid_20_T) | _wdata_1_value_21_T + & (|_writeValid_21_T) | _wdata_1_value_22_T & (|_writeValid_22_T) + | _wdata_1_value_23_T & (|_writeValid_23_T) | _wdata_1_value_24_T + & (|_writeValid_24_T) | _wdata_1_value_25_T & (|_writeValid_25_T) + | _wdata_1_value_26_T & (|_writeValid_26_T) | _wdata_1_value_27_T + & (|_writeValid_27_T) | _wdata_1_value_28_T & (|_writeValid_28_T) + | _wdata_1_value_29_T & (|_writeValid_29_T) | _wdata_1_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_1_addr) & (|_writeValid_31_T) + ? (_wdata_1_value_1_T ? data : 32'h0) | (_wdata_1_value_2_T ? data_1 : 32'h0) + | (_wdata_1_value_3_T ? data_2 : 32'h0) + | (_wdata_1_value_4_T ? data_3 : 32'h0) + | (_wdata_1_value_5_T ? data_4 : 32'h0) + | (_wdata_1_value_6_T ? data_5 : 32'h0) + | (_wdata_1_value_7_T ? data_6 : 32'h0) + | (_wdata_1_value_8_T ? data_7 : 32'h0) + | (_wdata_1_value_9_T ? data_8 : 32'h0) + | (_wdata_1_value_10_T ? data_9 : 32'h0) + | (_wdata_1_value_11_T ? data_10 : 32'h0) + | (_wdata_1_value_12_T ? data_11 : 32'h0) + | (_wdata_1_value_13_T ? data_12 : 32'h0) + | (_wdata_1_value_14_T ? data_13 : 32'h0) + | (_wdata_1_value_15_T ? data_14 : 32'h0) + | (_wdata_1_value_16_T ? data_15 : 32'h0) + | (_wdata_1_value_17_T ? data_16 : 32'h0) + | (_wdata_1_value_18_T ? data_17 : 32'h0) + | (_wdata_1_value_19_T ? data_18 : 32'h0) + | (_wdata_1_value_20_T ? data_19 : 32'h0) + | (_wdata_1_value_21_T ? data_20 : 32'h0) + | (_wdata_1_value_22_T ? data_21 : 32'h0) + | (_wdata_1_value_23_T ? data_22 : 32'h0) + | (_wdata_1_value_24_T ? data_23 : 32'h0) + | (_wdata_1_value_25_T ? data_24 : 32'h0) + | (_wdata_1_value_26_T ? data_25 : 32'h0) + | (_wdata_1_value_27_T ? data_26 : 32'h0) + | (_wdata_1_value_28_T ? data_27 : 32'h0) + | (_wdata_1_value_29_T ? data_28 : 32'h0) + | (_wdata_1_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_1_addr) ? data_30 : 32'h0) + : rdata_1; if (io_readSet_2_valid) readDataBits_2 <= io_readSet_2_value; else if (io_readAddr_2_valid) - readDataBits_2 <= rwdata_2; + readDataBits_2 <= + io_readAddr_2_addr == 5'h0 | _wdata_2_value_1_T & (|_writeValid_1_T) + | _wdata_2_value_2_T & (|_writeValid_2_T) | _wdata_2_value_3_T + & (|_writeValid_3_T) | _wdata_2_value_4_T & (|_writeValid_4_T) + | _wdata_2_value_5_T & (|_writeValid_5_T) | _wdata_2_value_6_T + & (|_writeValid_6_T) | _wdata_2_value_7_T & (|_writeValid_7_T) + | _wdata_2_value_8_T & (|_writeValid_8_T) | _wdata_2_value_9_T + & (|_writeValid_9_T) | _wdata_2_value_10_T & (|_writeValid_10_T) + | _wdata_2_value_11_T & (|_writeValid_11_T) | _wdata_2_value_12_T + & (|_writeValid_12_T) | _wdata_2_value_13_T & (|_writeValid_13_T) + | _wdata_2_value_14_T & (|_writeValid_14_T) | _wdata_2_value_15_T + & (|_writeValid_15_T) | _wdata_2_value_16_T & (|_writeValid_16_T) + | _wdata_2_value_17_T & (|_writeValid_17_T) | _wdata_2_value_18_T + & (|_writeValid_18_T) | _wdata_2_value_19_T & (|_writeValid_19_T) + | _wdata_2_value_20_T & (|_writeValid_20_T) | _wdata_2_value_21_T + & (|_writeValid_21_T) | _wdata_2_value_22_T & (|_writeValid_22_T) + | _wdata_2_value_23_T & (|_writeValid_23_T) | _wdata_2_value_24_T + & (|_writeValid_24_T) | _wdata_2_value_25_T & (|_writeValid_25_T) + | _wdata_2_value_26_T & (|_writeValid_26_T) | _wdata_2_value_27_T + & (|_writeValid_27_T) | _wdata_2_value_28_T & (|_writeValid_28_T) + | _wdata_2_value_29_T & (|_writeValid_29_T) | _wdata_2_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_2_addr) & (|_writeValid_31_T) + ? (_wdata_2_value_1_T ? data : 32'h0) | (_wdata_2_value_2_T ? data_1 : 32'h0) + | (_wdata_2_value_3_T ? data_2 : 32'h0) + | (_wdata_2_value_4_T ? data_3 : 32'h0) + | (_wdata_2_value_5_T ? data_4 : 32'h0) + | (_wdata_2_value_6_T ? data_5 : 32'h0) + | (_wdata_2_value_7_T ? data_6 : 32'h0) + | (_wdata_2_value_8_T ? data_7 : 32'h0) + | (_wdata_2_value_9_T ? data_8 : 32'h0) + | (_wdata_2_value_10_T ? data_9 : 32'h0) + | (_wdata_2_value_11_T ? data_10 : 32'h0) + | (_wdata_2_value_12_T ? data_11 : 32'h0) + | (_wdata_2_value_13_T ? data_12 : 32'h0) + | (_wdata_2_value_14_T ? data_13 : 32'h0) + | (_wdata_2_value_15_T ? data_14 : 32'h0) + | (_wdata_2_value_16_T ? data_15 : 32'h0) + | (_wdata_2_value_17_T ? data_16 : 32'h0) + | (_wdata_2_value_18_T ? data_17 : 32'h0) + | (_wdata_2_value_19_T ? data_18 : 32'h0) + | (_wdata_2_value_20_T ? data_19 : 32'h0) + | (_wdata_2_value_21_T ? data_20 : 32'h0) + | (_wdata_2_value_22_T ? data_21 : 32'h0) + | (_wdata_2_value_23_T ? data_22 : 32'h0) + | (_wdata_2_value_24_T ? data_23 : 32'h0) + | (_wdata_2_value_25_T ? data_24 : 32'h0) + | (_wdata_2_value_26_T ? data_25 : 32'h0) + | (_wdata_2_value_27_T ? data_26 : 32'h0) + | (_wdata_2_value_28_T ? data_27 : 32'h0) + | (_wdata_2_value_29_T ? data_28 : 32'h0) + | (_wdata_2_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_2_addr) ? data_30 : 32'h0) + : rdata_2; if (io_readSet_3_valid) readDataBits_3 <= io_readSet_3_value; else if (io_readAddr_3_valid) - readDataBits_3 <= rwdata_3; + readDataBits_3 <= + io_readAddr_3_addr == 5'h0 | _wdata_3_value_1_T & (|_writeValid_1_T) + | _wdata_3_value_2_T & (|_writeValid_2_T) | _wdata_3_value_3_T + & (|_writeValid_3_T) | _wdata_3_value_4_T & (|_writeValid_4_T) + | _wdata_3_value_5_T & (|_writeValid_5_T) | _wdata_3_value_6_T + & (|_writeValid_6_T) | _wdata_3_value_7_T & (|_writeValid_7_T) + | _wdata_3_value_8_T & (|_writeValid_8_T) | _wdata_3_value_9_T + & (|_writeValid_9_T) | _wdata_3_value_10_T & (|_writeValid_10_T) + | _wdata_3_value_11_T & (|_writeValid_11_T) | _wdata_3_value_12_T + & (|_writeValid_12_T) | _wdata_3_value_13_T & (|_writeValid_13_T) + | _wdata_3_value_14_T & (|_writeValid_14_T) | _wdata_3_value_15_T + & (|_writeValid_15_T) | _wdata_3_value_16_T & (|_writeValid_16_T) + | _wdata_3_value_17_T & (|_writeValid_17_T) | _wdata_3_value_18_T + & (|_writeValid_18_T) | _wdata_3_value_19_T & (|_writeValid_19_T) + | _wdata_3_value_20_T & (|_writeValid_20_T) | _wdata_3_value_21_T + & (|_writeValid_21_T) | _wdata_3_value_22_T & (|_writeValid_22_T) + | _wdata_3_value_23_T & (|_writeValid_23_T) | _wdata_3_value_24_T + & (|_writeValid_24_T) | _wdata_3_value_25_T & (|_writeValid_25_T) + | _wdata_3_value_26_T & (|_writeValid_26_T) | _wdata_3_value_27_T + & (|_writeValid_27_T) | _wdata_3_value_28_T & (|_writeValid_28_T) + | _wdata_3_value_29_T & (|_writeValid_29_T) | _wdata_3_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_3_addr) & (|_writeValid_31_T) + ? (_wdata_3_value_1_T ? data : 32'h0) | (_wdata_3_value_2_T ? data_1 : 32'h0) + | (_wdata_3_value_3_T ? data_2 : 32'h0) + | (_wdata_3_value_4_T ? data_3 : 32'h0) + | (_wdata_3_value_5_T ? data_4 : 32'h0) + | (_wdata_3_value_6_T ? data_5 : 32'h0) + | (_wdata_3_value_7_T ? data_6 : 32'h0) + | (_wdata_3_value_8_T ? data_7 : 32'h0) + | (_wdata_3_value_9_T ? data_8 : 32'h0) + | (_wdata_3_value_10_T ? data_9 : 32'h0) + | (_wdata_3_value_11_T ? data_10 : 32'h0) + | (_wdata_3_value_12_T ? data_11 : 32'h0) + | (_wdata_3_value_13_T ? data_12 : 32'h0) + | (_wdata_3_value_14_T ? data_13 : 32'h0) + | (_wdata_3_value_15_T ? data_14 : 32'h0) + | (_wdata_3_value_16_T ? data_15 : 32'h0) + | (_wdata_3_value_17_T ? data_16 : 32'h0) + | (_wdata_3_value_18_T ? data_17 : 32'h0) + | (_wdata_3_value_19_T ? data_18 : 32'h0) + | (_wdata_3_value_20_T ? data_19 : 32'h0) + | (_wdata_3_value_21_T ? data_20 : 32'h0) + | (_wdata_3_value_22_T ? data_21 : 32'h0) + | (_wdata_3_value_23_T ? data_22 : 32'h0) + | (_wdata_3_value_24_T ? data_23 : 32'h0) + | (_wdata_3_value_25_T ? data_24 : 32'h0) + | (_wdata_3_value_26_T ? data_25 : 32'h0) + | (_wdata_3_value_27_T ? data_26 : 32'h0) + | (_wdata_3_value_28_T ? data_27 : 32'h0) + | (_wdata_3_value_29_T ? data_28 : 32'h0) + | (_wdata_3_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_3_addr) ? data_30 : 32'h0) + : rdata_3; if (io_readSet_4_valid) readDataBits_4 <= io_readSet_4_value; else if (io_readAddr_4_valid) - readDataBits_4 <= rwdata_4; + readDataBits_4 <= + io_readAddr_4_addr == 5'h0 | _wdata_4_value_1_T & (|_writeValid_1_T) + | _wdata_4_value_2_T & (|_writeValid_2_T) | _wdata_4_value_3_T + & (|_writeValid_3_T) | _wdata_4_value_4_T & (|_writeValid_4_T) + | _wdata_4_value_5_T & (|_writeValid_5_T) | _wdata_4_value_6_T + & (|_writeValid_6_T) | _wdata_4_value_7_T & (|_writeValid_7_T) + | _wdata_4_value_8_T & (|_writeValid_8_T) | _wdata_4_value_9_T + & (|_writeValid_9_T) | _wdata_4_value_10_T & (|_writeValid_10_T) + | _wdata_4_value_11_T & (|_writeValid_11_T) | _wdata_4_value_12_T + & (|_writeValid_12_T) | _wdata_4_value_13_T & (|_writeValid_13_T) + | _wdata_4_value_14_T & (|_writeValid_14_T) | _wdata_4_value_15_T + & (|_writeValid_15_T) | _wdata_4_value_16_T & (|_writeValid_16_T) + | _wdata_4_value_17_T & (|_writeValid_17_T) | _wdata_4_value_18_T + & (|_writeValid_18_T) | _wdata_4_value_19_T & (|_writeValid_19_T) + | _wdata_4_value_20_T & (|_writeValid_20_T) | _wdata_4_value_21_T + & (|_writeValid_21_T) | _wdata_4_value_22_T & (|_writeValid_22_T) + | _wdata_4_value_23_T & (|_writeValid_23_T) | _wdata_4_value_24_T + & (|_writeValid_24_T) | _wdata_4_value_25_T & (|_writeValid_25_T) + | _wdata_4_value_26_T & (|_writeValid_26_T) | _wdata_4_value_27_T + & (|_writeValid_27_T) | _wdata_4_value_28_T & (|_writeValid_28_T) + | _wdata_4_value_29_T & (|_writeValid_29_T) | _wdata_4_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_4_addr) & (|_writeValid_31_T) + ? (_wdata_4_value_1_T ? data : 32'h0) | (_wdata_4_value_2_T ? data_1 : 32'h0) + | (_wdata_4_value_3_T ? data_2 : 32'h0) + | (_wdata_4_value_4_T ? data_3 : 32'h0) + | (_wdata_4_value_5_T ? data_4 : 32'h0) + | (_wdata_4_value_6_T ? data_5 : 32'h0) + | (_wdata_4_value_7_T ? data_6 : 32'h0) + | (_wdata_4_value_8_T ? data_7 : 32'h0) + | (_wdata_4_value_9_T ? data_8 : 32'h0) + | (_wdata_4_value_10_T ? data_9 : 32'h0) + | (_wdata_4_value_11_T ? data_10 : 32'h0) + | (_wdata_4_value_12_T ? data_11 : 32'h0) + | (_wdata_4_value_13_T ? data_12 : 32'h0) + | (_wdata_4_value_14_T ? data_13 : 32'h0) + | (_wdata_4_value_15_T ? data_14 : 32'h0) + | (_wdata_4_value_16_T ? data_15 : 32'h0) + | (_wdata_4_value_17_T ? data_16 : 32'h0) + | (_wdata_4_value_18_T ? data_17 : 32'h0) + | (_wdata_4_value_19_T ? data_18 : 32'h0) + | (_wdata_4_value_20_T ? data_19 : 32'h0) + | (_wdata_4_value_21_T ? data_20 : 32'h0) + | (_wdata_4_value_22_T ? data_21 : 32'h0) + | (_wdata_4_value_23_T ? data_22 : 32'h0) + | (_wdata_4_value_24_T ? data_23 : 32'h0) + | (_wdata_4_value_25_T ? data_24 : 32'h0) + | (_wdata_4_value_26_T ? data_25 : 32'h0) + | (_wdata_4_value_27_T ? data_26 : 32'h0) + | (_wdata_4_value_28_T ? data_27 : 32'h0) + | (_wdata_4_value_29_T ? data_28 : 32'h0) + | (_wdata_4_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_4_addr) ? data_30 : 32'h0) + : rdata_4; if (io_readSet_5_valid) readDataBits_5 <= io_readSet_5_value; else if (io_readAddr_5_valid) - readDataBits_5 <= rwdata_5; + readDataBits_5 <= + io_readAddr_5_addr == 5'h0 | _wdata_5_value_1_T & (|_writeValid_1_T) + | _wdata_5_value_2_T & (|_writeValid_2_T) | _wdata_5_value_3_T + & (|_writeValid_3_T) | _wdata_5_value_4_T & (|_writeValid_4_T) + | _wdata_5_value_5_T & (|_writeValid_5_T) | _wdata_5_value_6_T + & (|_writeValid_6_T) | _wdata_5_value_7_T & (|_writeValid_7_T) + | _wdata_5_value_8_T & (|_writeValid_8_T) | _wdata_5_value_9_T + & (|_writeValid_9_T) | _wdata_5_value_10_T & (|_writeValid_10_T) + | _wdata_5_value_11_T & (|_writeValid_11_T) | _wdata_5_value_12_T + & (|_writeValid_12_T) | _wdata_5_value_13_T & (|_writeValid_13_T) + | _wdata_5_value_14_T & (|_writeValid_14_T) | _wdata_5_value_15_T + & (|_writeValid_15_T) | _wdata_5_value_16_T & (|_writeValid_16_T) + | _wdata_5_value_17_T & (|_writeValid_17_T) | _wdata_5_value_18_T + & (|_writeValid_18_T) | _wdata_5_value_19_T & (|_writeValid_19_T) + | _wdata_5_value_20_T & (|_writeValid_20_T) | _wdata_5_value_21_T + & (|_writeValid_21_T) | _wdata_5_value_22_T & (|_writeValid_22_T) + | _wdata_5_value_23_T & (|_writeValid_23_T) | _wdata_5_value_24_T + & (|_writeValid_24_T) | _wdata_5_value_25_T & (|_writeValid_25_T) + | _wdata_5_value_26_T & (|_writeValid_26_T) | _wdata_5_value_27_T + & (|_writeValid_27_T) | _wdata_5_value_28_T & (|_writeValid_28_T) + | _wdata_5_value_29_T & (|_writeValid_29_T) | _wdata_5_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_5_addr) & (|_writeValid_31_T) + ? (_wdata_5_value_1_T ? data : 32'h0) | (_wdata_5_value_2_T ? data_1 : 32'h0) + | (_wdata_5_value_3_T ? data_2 : 32'h0) + | (_wdata_5_value_4_T ? data_3 : 32'h0) + | (_wdata_5_value_5_T ? data_4 : 32'h0) + | (_wdata_5_value_6_T ? data_5 : 32'h0) + | (_wdata_5_value_7_T ? data_6 : 32'h0) + | (_wdata_5_value_8_T ? data_7 : 32'h0) + | (_wdata_5_value_9_T ? data_8 : 32'h0) + | (_wdata_5_value_10_T ? data_9 : 32'h0) + | (_wdata_5_value_11_T ? data_10 : 32'h0) + | (_wdata_5_value_12_T ? data_11 : 32'h0) + | (_wdata_5_value_13_T ? data_12 : 32'h0) + | (_wdata_5_value_14_T ? data_13 : 32'h0) + | (_wdata_5_value_15_T ? data_14 : 32'h0) + | (_wdata_5_value_16_T ? data_15 : 32'h0) + | (_wdata_5_value_17_T ? data_16 : 32'h0) + | (_wdata_5_value_18_T ? data_17 : 32'h0) + | (_wdata_5_value_19_T ? data_18 : 32'h0) + | (_wdata_5_value_20_T ? data_19 : 32'h0) + | (_wdata_5_value_21_T ? data_20 : 32'h0) + | (_wdata_5_value_22_T ? data_21 : 32'h0) + | (_wdata_5_value_23_T ? data_22 : 32'h0) + | (_wdata_5_value_24_T ? data_23 : 32'h0) + | (_wdata_5_value_25_T ? data_24 : 32'h0) + | (_wdata_5_value_26_T ? data_25 : 32'h0) + | (_wdata_5_value_27_T ? data_26 : 32'h0) + | (_wdata_5_value_28_T ? data_27 : 32'h0) + | (_wdata_5_value_29_T ? data_28 : 32'h0) + | (_wdata_5_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_5_addr) ? data_30 : 32'h0) + : rdata_5; if (io_readSet_6_valid) readDataBits_6 <= io_readSet_6_value; else if (io_readAddr_6_valid) - readDataBits_6 <= rwdata_6; + readDataBits_6 <= + io_readAddr_6_addr == 5'h0 | _wdata_6_value_1_T & (|_writeValid_1_T) + | _wdata_6_value_2_T & (|_writeValid_2_T) | _wdata_6_value_3_T + & (|_writeValid_3_T) | _wdata_6_value_4_T & (|_writeValid_4_T) + | _wdata_6_value_5_T & (|_writeValid_5_T) | _wdata_6_value_6_T + & (|_writeValid_6_T) | _wdata_6_value_7_T & (|_writeValid_7_T) + | _wdata_6_value_8_T & (|_writeValid_8_T) | _wdata_6_value_9_T + & (|_writeValid_9_T) | _wdata_6_value_10_T & (|_writeValid_10_T) + | _wdata_6_value_11_T & (|_writeValid_11_T) | _wdata_6_value_12_T + & (|_writeValid_12_T) | _wdata_6_value_13_T & (|_writeValid_13_T) + | _wdata_6_value_14_T & (|_writeValid_14_T) | _wdata_6_value_15_T + & (|_writeValid_15_T) | _wdata_6_value_16_T & (|_writeValid_16_T) + | _wdata_6_value_17_T & (|_writeValid_17_T) | _wdata_6_value_18_T + & (|_writeValid_18_T) | _wdata_6_value_19_T & (|_writeValid_19_T) + | _wdata_6_value_20_T & (|_writeValid_20_T) | _wdata_6_value_21_T + & (|_writeValid_21_T) | _wdata_6_value_22_T & (|_writeValid_22_T) + | _wdata_6_value_23_T & (|_writeValid_23_T) | _wdata_6_value_24_T + & (|_writeValid_24_T) | _wdata_6_value_25_T & (|_writeValid_25_T) + | _wdata_6_value_26_T & (|_writeValid_26_T) | _wdata_6_value_27_T + & (|_writeValid_27_T) | _wdata_6_value_28_T & (|_writeValid_28_T) + | _wdata_6_value_29_T & (|_writeValid_29_T) | _wdata_6_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_6_addr) & (|_writeValid_31_T) + ? (_wdata_6_value_1_T ? data : 32'h0) | (_wdata_6_value_2_T ? data_1 : 32'h0) + | (_wdata_6_value_3_T ? data_2 : 32'h0) + | (_wdata_6_value_4_T ? data_3 : 32'h0) + | (_wdata_6_value_5_T ? data_4 : 32'h0) + | (_wdata_6_value_6_T ? data_5 : 32'h0) + | (_wdata_6_value_7_T ? data_6 : 32'h0) + | (_wdata_6_value_8_T ? data_7 : 32'h0) + | (_wdata_6_value_9_T ? data_8 : 32'h0) + | (_wdata_6_value_10_T ? data_9 : 32'h0) + | (_wdata_6_value_11_T ? data_10 : 32'h0) + | (_wdata_6_value_12_T ? data_11 : 32'h0) + | (_wdata_6_value_13_T ? data_12 : 32'h0) + | (_wdata_6_value_14_T ? data_13 : 32'h0) + | (_wdata_6_value_15_T ? data_14 : 32'h0) + | (_wdata_6_value_16_T ? data_15 : 32'h0) + | (_wdata_6_value_17_T ? data_16 : 32'h0) + | (_wdata_6_value_18_T ? data_17 : 32'h0) + | (_wdata_6_value_19_T ? data_18 : 32'h0) + | (_wdata_6_value_20_T ? data_19 : 32'h0) + | (_wdata_6_value_21_T ? data_20 : 32'h0) + | (_wdata_6_value_22_T ? data_21 : 32'h0) + | (_wdata_6_value_23_T ? data_22 : 32'h0) + | (_wdata_6_value_24_T ? data_23 : 32'h0) + | (_wdata_6_value_25_T ? data_24 : 32'h0) + | (_wdata_6_value_26_T ? data_25 : 32'h0) + | (_wdata_6_value_27_T ? data_26 : 32'h0) + | (_wdata_6_value_28_T ? data_27 : 32'h0) + | (_wdata_6_value_29_T ? data_28 : 32'h0) + | (_wdata_6_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_6_addr) ? data_30 : 32'h0) + : rdata_6; if (io_readSet_7_valid) readDataBits_7 <= io_readSet_7_value; else if (io_readAddr_7_valid) - readDataBits_7 <= rwdata_7; - write_fail <= - io_writeData_0_valid & io_writeData_1_valid - & io_writeData_0_bits_addr == io_writeData_1_bits_addr - & (|io_writeData_0_bits_addr); - write_fail_1 <= - io_writeData_0_valid & io_writeData_2_valid - & io_writeData_0_bits_addr == io_writeData_2_bits_addr - & (|io_writeData_0_bits_addr); - write_fail_2 <= - io_writeData_0_valid & io_writeData_3_valid - & io_writeData_0_bits_addr == io_writeData_3_bits_addr - & (|io_writeData_0_bits_addr); - write_fail_3 <= - io_writeData_0_valid & io_writeData_4_valid - & io_writeData_0_bits_addr == io_writeData_4_bits_addr - & (|io_writeData_0_bits_addr); - write_fail_4 <= - io_writeData_0_valid & io_writeData_5_valid - & io_writeData_0_bits_addr == io_writeData_5_bits_addr - & (|io_writeData_0_bits_addr); - write_fail_5 <= - io_writeData_1_valid & io_writeData_2_valid - & io_writeData_1_bits_addr == io_writeData_2_bits_addr - & (|io_writeData_1_bits_addr); - write_fail_6 <= - io_writeData_1_valid & io_writeData_3_valid - & io_writeData_1_bits_addr == io_writeData_3_bits_addr - & (|io_writeData_1_bits_addr); - write_fail_7 <= - io_writeData_1_valid & io_writeData_4_valid - & io_writeData_1_bits_addr == io_writeData_4_bits_addr - & (|io_writeData_1_bits_addr); - write_fail_8 <= - io_writeData_1_valid & io_writeData_5_valid - & io_writeData_1_bits_addr == io_writeData_5_bits_addr - & (|io_writeData_1_bits_addr); - write_fail_9 <= - io_writeData_2_valid & io_writeData_3_valid - & io_writeData_2_bits_addr == io_writeData_3_bits_addr - & (|io_writeData_2_bits_addr); - write_fail_10 <= - io_writeData_2_valid & io_writeData_4_valid - & io_writeData_2_bits_addr == io_writeData_4_bits_addr - & (|io_writeData_2_bits_addr); - write_fail_11 <= - io_writeData_2_valid & io_writeData_5_valid - & io_writeData_2_bits_addr == io_writeData_5_bits_addr - & (|io_writeData_2_bits_addr); - write_fail_12 <= - io_writeData_3_valid & io_writeData_4_valid - & io_writeData_3_bits_addr == io_writeData_4_bits_addr - & (|io_writeData_3_bits_addr); - write_fail_13 <= - io_writeData_3_valid & io_writeData_5_valid - & io_writeData_3_bits_addr == io_writeData_5_bits_addr - & (|io_writeData_3_bits_addr); - write_fail_14 <= - io_writeData_4_valid & io_writeData_5_valid - & io_writeData_4_bits_addr == io_writeData_5_bits_addr - & (|io_writeData_4_bits_addr); - scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + readDataBits_7 <= + io_readAddr_7_addr == 5'h0 | _wdata_7_value_1_T & (|_writeValid_1_T) + | _wdata_7_value_2_T & (|_writeValid_2_T) | _wdata_7_value_3_T + & (|_writeValid_3_T) | _wdata_7_value_4_T & (|_writeValid_4_T) + | _wdata_7_value_5_T & (|_writeValid_5_T) | _wdata_7_value_6_T + & (|_writeValid_6_T) | _wdata_7_value_7_T & (|_writeValid_7_T) + | _wdata_7_value_8_T & (|_writeValid_8_T) | _wdata_7_value_9_T + & (|_writeValid_9_T) | _wdata_7_value_10_T & (|_writeValid_10_T) + | _wdata_7_value_11_T & (|_writeValid_11_T) | _wdata_7_value_12_T + & (|_writeValid_12_T) | _wdata_7_value_13_T & (|_writeValid_13_T) + | _wdata_7_value_14_T & (|_writeValid_14_T) | _wdata_7_value_15_T + & (|_writeValid_15_T) | _wdata_7_value_16_T & (|_writeValid_16_T) + | _wdata_7_value_17_T & (|_writeValid_17_T) | _wdata_7_value_18_T + & (|_writeValid_18_T) | _wdata_7_value_19_T & (|_writeValid_19_T) + | _wdata_7_value_20_T & (|_writeValid_20_T) | _wdata_7_value_21_T + & (|_writeValid_21_T) | _wdata_7_value_22_T & (|_writeValid_22_T) + | _wdata_7_value_23_T & (|_writeValid_23_T) | _wdata_7_value_24_T + & (|_writeValid_24_T) | _wdata_7_value_25_T & (|_writeValid_25_T) + | _wdata_7_value_26_T & (|_writeValid_26_T) | _wdata_7_value_27_T + & (|_writeValid_27_T) | _wdata_7_value_28_T & (|_writeValid_28_T) + | _wdata_7_value_29_T & (|_writeValid_29_T) | _wdata_7_value_30_T + & (|_writeValid_30_T) | (&io_readAddr_7_addr) & (|_writeValid_31_T) + ? (_wdata_7_value_1_T ? data : 32'h0) | (_wdata_7_value_2_T ? data_1 : 32'h0) + | (_wdata_7_value_3_T ? data_2 : 32'h0) + | (_wdata_7_value_4_T ? data_3 : 32'h0) + | (_wdata_7_value_5_T ? data_4 : 32'h0) + | (_wdata_7_value_6_T ? data_5 : 32'h0) + | (_wdata_7_value_7_T ? data_6 : 32'h0) + | (_wdata_7_value_8_T ? data_7 : 32'h0) + | (_wdata_7_value_9_T ? data_8 : 32'h0) + | (_wdata_7_value_10_T ? data_9 : 32'h0) + | (_wdata_7_value_11_T ? data_10 : 32'h0) + | (_wdata_7_value_12_T ? data_11 : 32'h0) + | (_wdata_7_value_13_T ? data_12 : 32'h0) + | (_wdata_7_value_14_T ? data_13 : 32'h0) + | (_wdata_7_value_15_T ? data_14 : 32'h0) + | (_wdata_7_value_16_T ? data_15 : 32'h0) + | (_wdata_7_value_17_T ? data_16 : 32'h0) + | (_wdata_7_value_18_T ? data_17 : 32'h0) + | (_wdata_7_value_19_T ? data_18 : 32'h0) + | (_wdata_7_value_20_T ? data_19 : 32'h0) + | (_wdata_7_value_21_T ? data_20 : 32'h0) + | (_wdata_7_value_22_T ? data_21 : 32'h0) + | (_wdata_7_value_23_T ? data_22 : 32'h0) + | (_wdata_7_value_24_T ? data_23 : 32'h0) + | (_wdata_7_value_25_T ? data_24 : 32'h0) + | (_wdata_7_value_26_T ? data_25 : 32'h0) + | (_wdata_7_value_27_T ? data_26 : 32'h0) + | (_wdata_7_value_28_T ? data_27 : 32'h0) + | (_wdata_7_value_29_T ? data_28 : 32'h0) + | (_wdata_7_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_7_addr) ? data_30 : 32'h0) + : rdata_7; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:41]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [5:0] i = 6'h0; i < 6'h2A; i += 6'h1) begin - _RANDOM[i] = `RANDOM; - end - regfile_1 = _RANDOM[6'h1]; - regfile_2 = _RANDOM[6'h2]; - regfile_3 = _RANDOM[6'h3]; - regfile_4 = _RANDOM[6'h4]; - regfile_5 = _RANDOM[6'h5]; - regfile_6 = _RANDOM[6'h6]; - regfile_7 = _RANDOM[6'h7]; - regfile_8 = _RANDOM[6'h8]; - regfile_9 = _RANDOM[6'h9]; - regfile_10 = _RANDOM[6'hA]; - regfile_11 = _RANDOM[6'hB]; - regfile_12 = _RANDOM[6'hC]; - regfile_13 = _RANDOM[6'hD]; - regfile_14 = _RANDOM[6'hE]; - regfile_15 = _RANDOM[6'hF]; - regfile_16 = _RANDOM[6'h10]; - regfile_17 = _RANDOM[6'h11]; - regfile_18 = _RANDOM[6'h12]; - regfile_19 = _RANDOM[6'h13]; - regfile_20 = _RANDOM[6'h14]; - regfile_21 = _RANDOM[6'h15]; - regfile_22 = _RANDOM[6'h16]; - regfile_23 = _RANDOM[6'h17]; - regfile_24 = _RANDOM[6'h18]; - regfile_25 = _RANDOM[6'h19]; - regfile_26 = _RANDOM[6'h1A]; - regfile_27 = _RANDOM[6'h1B]; - regfile_28 = _RANDOM[6'h1C]; - regfile_29 = _RANDOM[6'h1D]; - regfile_30 = _RANDOM[6'h1E]; - regfile_31 = _RANDOM[6'h1F]; - scoreboard = _RANDOM[6'h20]; - readDataReady_0 = _RANDOM[6'h21][0]; - readDataReady_1 = _RANDOM[6'h21][1]; - readDataReady_2 = _RANDOM[6'h21][2]; - readDataReady_3 = _RANDOM[6'h21][3]; - readDataReady_4 = _RANDOM[6'h21][4]; - readDataReady_5 = _RANDOM[6'h21][5]; - readDataReady_6 = _RANDOM[6'h21][6]; - readDataReady_7 = _RANDOM[6'h21][7]; - readDataBits_0 = {_RANDOM[6'h21][31:8], _RANDOM[6'h22][7:0]}; - readDataBits_1 = {_RANDOM[6'h22][31:8], _RANDOM[6'h23][7:0]}; - readDataBits_2 = {_RANDOM[6'h23][31:8], _RANDOM[6'h24][7:0]}; - readDataBits_3 = {_RANDOM[6'h24][31:8], _RANDOM[6'h25][7:0]}; - readDataBits_4 = {_RANDOM[6'h25][31:8], _RANDOM[6'h26][7:0]}; - readDataBits_5 = {_RANDOM[6'h26][31:8], _RANDOM[6'h27][7:0]}; - readDataBits_6 = {_RANDOM[6'h27][31:8], _RANDOM[6'h28][7:0]}; - readDataBits_7 = {_RANDOM[6'h28][31:8], _RANDOM[6'h29][7:0]}; - write_fail = _RANDOM[6'h29][8]; - write_fail_1 = _RANDOM[6'h29][9]; - write_fail_2 = _RANDOM[6'h29][10]; - write_fail_3 = _RANDOM[6'h29][11]; - write_fail_4 = _RANDOM[6'h29][12]; - write_fail_5 = _RANDOM[6'h29][13]; - write_fail_6 = _RANDOM[6'h29][14]; - write_fail_7 = _RANDOM[6'h29][15]; - write_fail_8 = _RANDOM[6'h29][16]; - write_fail_9 = _RANDOM[6'h29][17]; - write_fail_10 = _RANDOM[6'h29][18]; - write_fail_11 = _RANDOM[6'h29][19]; - write_fail_12 = _RANDOM[6'h29][20]; - write_fail_13 = _RANDOM[6'h29][21]; - write_fail_14 = _RANDOM[6'h29][22]; - scoreboard_error = _RANDOM[6'h29][23]; - `endif // RANDOMIZE_REG_INIT if (reset) begin regfile_1 = 32'h0; regfile_2 = 32'h0; @@ -2118,14 +2546,6 @@ module Regfile( regfile_30 = 32'h0; regfile_31 = 32'h0; scoreboard = 32'h0; - readDataReady_0 = 1'h0; - readDataReady_1 = 1'h0; - readDataReady_2 = 1'h0; - readDataReady_3 = 1'h0; - readDataReady_4 = 1'h0; - readDataReady_5 = 1'h0; - readDataReady_6 = 1'h0; - readDataReady_7 = 1'h0; readDataBits_0 = 32'h0; readDataBits_1 = 32'h0; readDataBits_2 = 32'h0; @@ -2134,120 +2554,91 @@ module Regfile( readDataBits_5 = 32'h0; readDataBits_6 = 32'h0; readDataBits_7 = 32'h0; - write_fail = 1'h0; - write_fail_1 = 1'h0; - write_fail_2 = 1'h0; - write_fail_3 = 1'h0; - write_fail_4 = 1'h0; - write_fail_5 = 1'h0; - write_fail_6 = 1'h0; - write_fail_7 = 1'h0; - write_fail_8 = 1'h0; - write_fail_9 = 1'h0; - write_fail_10 = 1'h0; - write_fail_11 = 1'h0; - write_fail_12 = 1'h0; - write_fail_13 = 1'h0; - write_fail_14 = 1'h0; - scoreboard_error = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_target_0_data = busAddr_0; - assign io_target_1_data = busAddr_1; - assign io_target_2_data = busAddr_2; - assign io_target_3_data = busAddr_3; - assign io_busPort_addr_0 = busAddr_0; - assign io_busPort_addr_1 = busAddr_1; - assign io_busPort_addr_2 = busAddr_2; - assign io_busPort_addr_3 = busAddr_3; - assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; - assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; - assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; - assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; - assign io_readData_0_valid = readDataReady_0; + assign io_target_0_data = _busAddr_0_T; + assign io_target_1_data = _busAddr_1_T; + assign io_target_2_data = _busAddr_2_T; + assign io_target_3_data = _busAddr_3_T; + assign io_busPort_addr_0 = _busAddr_0_T; + assign io_busPort_addr_1 = _busAddr_1_T; + assign io_busPort_addr_2 = _busAddr_2_T; + assign io_busPort_addr_3 = _busAddr_3_T; + assign io_busPort_data_0 = rdata_1; + assign io_busPort_data_1 = rdata_3; + assign io_busPort_data_2 = rdata_5; + assign io_busPort_data_3 = rdata_7; + assign io_debugBusPort_data = + (io_debugBusPort_idx == 5'h1 ? regfile_1 : 32'h0) + | (io_debugBusPort_idx == 5'h2 ? regfile_2 : 32'h0) + | (io_debugBusPort_idx == 5'h3 ? regfile_3 : 32'h0) + | (io_debugBusPort_idx == 5'h4 ? regfile_4 : 32'h0) + | (io_debugBusPort_idx == 5'h5 ? regfile_5 : 32'h0) + | (io_debugBusPort_idx == 5'h6 ? regfile_6 : 32'h0) + | (io_debugBusPort_idx == 5'h7 ? regfile_7 : 32'h0) + | (io_debugBusPort_idx == 5'h8 ? regfile_8 : 32'h0) + | (io_debugBusPort_idx == 5'h9 ? regfile_9 : 32'h0) + | (io_debugBusPort_idx == 5'hA ? regfile_10 : 32'h0) + | (io_debugBusPort_idx == 5'hB ? regfile_11 : 32'h0) + | (io_debugBusPort_idx == 5'hC ? regfile_12 : 32'h0) + | (io_debugBusPort_idx == 5'hD ? regfile_13 : 32'h0) + | (io_debugBusPort_idx == 5'hE ? regfile_14 : 32'h0) + | (io_debugBusPort_idx == 5'hF ? regfile_15 : 32'h0) + | (io_debugBusPort_idx == 5'h10 ? regfile_16 : 32'h0) + | (io_debugBusPort_idx == 5'h11 ? regfile_17 : 32'h0) + | (io_debugBusPort_idx == 5'h12 ? regfile_18 : 32'h0) + | (io_debugBusPort_idx == 5'h13 ? regfile_19 : 32'h0) + | (io_debugBusPort_idx == 5'h14 ? regfile_20 : 32'h0) + | (io_debugBusPort_idx == 5'h15 ? regfile_21 : 32'h0) + | (io_debugBusPort_idx == 5'h16 ? regfile_22 : 32'h0) + | (io_debugBusPort_idx == 5'h17 ? regfile_23 : 32'h0) + | (io_debugBusPort_idx == 5'h18 ? regfile_24 : 32'h0) + | (io_debugBusPort_idx == 5'h19 ? regfile_25 : 32'h0) + | (io_debugBusPort_idx == 5'h1A ? regfile_26 : 32'h0) + | (io_debugBusPort_idx == 5'h1B ? regfile_27 : 32'h0) + | (io_debugBusPort_idx == 5'h1C ? regfile_28 : 32'h0) + | (io_debugBusPort_idx == 5'h1D ? regfile_29 : 32'h0) + | (io_debugBusPort_idx == 5'h1E ? regfile_30 : 32'h0) + | ((&io_debugBusPort_idx) ? regfile_31 : 32'h0); assign io_readData_0_data = readDataBits_0; - assign io_readData_1_valid = readDataReady_1; assign io_readData_1_data = readDataBits_1; - assign io_readData_2_valid = readDataReady_2; assign io_readData_2_data = readDataBits_2; - assign io_readData_3_valid = readDataReady_3; assign io_readData_3_data = readDataBits_3; - assign io_readData_4_valid = readDataReady_4; assign io_readData_4_data = readDataBits_4; - assign io_readData_5_valid = readDataReady_5; assign io_readData_5_data = readDataBits_5; - assign io_readData_6_valid = readDataReady_6; assign io_readData_6_data = readDataBits_6; - assign io_readData_7_valid = readDataReady_7; assign io_readData_7_data = readDataBits_7; assign io_scoreboard_regd = scoreboard; assign io_scoreboard_comb = scoreboard & {~scoreboard_clr0, 1'h1}; - assign io_rfwriteCount = - {1'h0, - {1'h0, - {1'h0, - {1'h0, {1'h0, |_writeValid_1_T} + 2'h1} - + {1'h0, {1'h0, |_writeValid_2_T} + {1'h0, |_writeValid_3_T}}} - + {1'h0, - {1'h0, {1'h0, |_writeValid_4_T} + {1'h0, |_writeValid_5_T}} - + {1'h0, {1'h0, |_writeValid_6_T} + {1'h0, |_writeValid_7_T}}}} - + {1'h0, - {1'h0, - {1'h0, {1'h0, |_writeValid_8_T} + {1'h0, |_writeValid_9_T}} - + {1'h0, {1'h0, |_writeValid_10_T} + {1'h0, |_writeValid_11_T}}} - + {1'h0, - {1'h0, {1'h0, |_writeValid_12_T} + {1'h0, |_writeValid_13_T}} - + {1'h0, {1'h0, |_writeValid_14_T} + {1'h0, |_writeValid_15_T}}}}} - + {1'h0, - {1'h0, - {1'h0, - {1'h0, {1'h0, |_writeValid_16_T} + {1'h0, |_writeValid_17_T}} - + {1'h0, {1'h0, |_writeValid_18_T} + {1'h0, |_writeValid_19_T}}} - + {1'h0, - {1'h0, {1'h0, |_writeValid_20_T} + {1'h0, |_writeValid_21_T}} - + {1'h0, {1'h0, |_writeValid_22_T} + {1'h0, |_writeValid_23_T}}}} - + {1'h0, - {1'h0, - {1'h0, {1'h0, |_writeValid_24_T} + {1'h0, |_writeValid_25_T}} - + {1'h0, {1'h0, |_writeValid_26_T} + {1'h0, |_writeValid_27_T}}} - + {1'h0, - {1'h0, {1'h0, |_writeValid_28_T} + {1'h0, |_writeValid_29_T}} - + {1'h0, {1'h0, |_writeValid_30_T} + {1'h0, |_writeValid_31_T}}}}} - + {3'h0, - {1'h0, - {1'h0, io_writeData_0_valid & io_writeData_0_bits_addr == 5'h0} - + {1'h0, - io_writeData_1_valid & io_writeData_1_bits_addr == 5'h0 - & ~io_writeMask_1_valid}} - + {1'h0, - {1'h0, - io_writeData_2_valid & io_writeData_2_bits_addr == 5'h0 - & ~io_writeMask_2_valid} - + {1'h0, - io_writeData_3_valid & io_writeData_3_bits_addr == 5'h0 - & ~io_writeMask_3_valid}}} - 6'h1; endmodule module FetchControl( input clock, reset, + output io_fetchFault_valid, + output [31:0] io_fetchFault_bits, input [31:0] io_csr_value_0, input io_iflush_valid, input [31:0] io_iflush_bits, input io_branch_valid, input [31:0] io_branch_bits, + output io_fetchData_ready, input io_fetchData_valid, input [31:0] io_fetchData_bits_addr, io_fetchData_bits_inst_0, io_fetchData_bits_inst_1, io_fetchData_bits_inst_2, io_fetchData_bits_inst_3, + input io_fetchData_bits_fault, + io_fetchAddr_ready, output io_fetchAddr_valid, output [31:0] io_fetchAddr_bits, + output io_flushTx, + input [2:0] io_bufferRequest_nReady, output [2:0] io_bufferRequest_nValid, output [31:0] io_bufferRequest_bits_0_addr, io_bufferRequest_bits_0_inst, @@ -2260,3276 +2651,2660 @@ module FetchControl( output io_bufferRequest_bits_2_brchFwd, output [31:0] io_bufferRequest_bits_3_addr, io_bufferRequest_bits_3_inst, - output io_bufferRequest_bits_3_brchFwd, - input [3:0] io_bufferSpaces + output io_bufferRequest_bits_3_brchFwd ); - wire [31:0] _GEN = {io_fetchData_bits_addr[31:4], 4'h0}; - wire jumped_3 = - io_fetchData_bits_inst_3[6:0] == 7'h6F | io_fetchData_bits_inst_3[6:0] == 7'h63 - & io_fetchData_bits_inst_3[31] & io_fetchData_bits_inst_3[14:13] != 2'h1; - wire jumped_0 = - io_fetchData_bits_addr[3:2] == 2'h0 - & (io_fetchData_bits_inst_0[6:0] == 7'h6F | io_fetchData_bits_inst_0[6:0] == 7'h63 - & io_fetchData_bits_inst_0[31] & io_fetchData_bits_inst_0[14:13] != 2'h1); - wire jumped_1 = - ~(io_fetchData_bits_addr[3]) - & (io_fetchData_bits_inst_1[6:0] == 7'h6F | io_fetchData_bits_inst_1[6:0] == 7'h63 - & io_fetchData_bits_inst_1[31] & io_fetchData_bits_inst_1[14:13] != 2'h1); - wire jumped_2 = - io_fetchData_bits_addr[3:2] != 2'h3 - & (io_fetchData_bits_inst_2[6:0] == 7'h6F | io_fetchData_bits_inst_2[6:0] == 7'h63 - & io_fetchData_bits_inst_2[31] & io_fetchData_bits_inst_2[14:13] != 2'h1); - wire [2:0] lastInstIdx = - jumped_0 ? 3'h0 : jumped_1 ? 3'h1 : jumped_2 ? 3'h2 : jumped_3 ? 3'h3 : 3'h4; - wire [31:0] nextFetchPc = - jumped_0 - ? _GEN - + {{12{io_fetchData_bits_inst_0[31]}}, - io_fetchData_bits_inst_0[2] - ? {io_fetchData_bits_inst_0[19:12], - io_fetchData_bits_inst_0[20], - io_fetchData_bits_inst_0[30:21]} - : {{8{io_fetchData_bits_inst_0[31]}}, - io_fetchData_bits_inst_0[7], - io_fetchData_bits_inst_0[30:25], - io_fetchData_bits_inst_0[11:8]}, - 1'h0} - : jumped_1 - ? {io_fetchData_bits_addr[31:4], 4'h4} - + {{12{io_fetchData_bits_inst_1[31]}}, - io_fetchData_bits_inst_1[2] - ? {io_fetchData_bits_inst_1[19:12], - io_fetchData_bits_inst_1[20], - io_fetchData_bits_inst_1[30:21]} - : {{8{io_fetchData_bits_inst_1[31]}}, - io_fetchData_bits_inst_1[7], - io_fetchData_bits_inst_1[30:25], - io_fetchData_bits_inst_1[11:8]}, - 1'h0} - : jumped_2 - ? {io_fetchData_bits_addr[31:4], 4'h8} - + {{12{io_fetchData_bits_inst_2[31]}}, - io_fetchData_bits_inst_2[2] - ? {io_fetchData_bits_inst_2[19:12], - io_fetchData_bits_inst_2[20], - io_fetchData_bits_inst_2[30:21]} - : {{8{io_fetchData_bits_inst_2[31]}}, - io_fetchData_bits_inst_2[7], - io_fetchData_bits_inst_2[30:25], - io_fetchData_bits_inst_2[11:8]}, - 1'h0} - : jumped_3 - ? {io_fetchData_bits_addr[31:4], 4'hC} - + {{12{io_fetchData_bits_inst_3[31]}}, - io_fetchData_bits_inst_3[2] - ? {io_fetchData_bits_inst_3[19:12], - io_fetchData_bits_inst_3[20], - io_fetchData_bits_inst_3[30:21]} - : {{8{io_fetchData_bits_inst_3[31]}}, - io_fetchData_bits_inst_3[7], - io_fetchData_bits_inst_3[30:25], - io_fetchData_bits_inst_3[11:8]}, - 1'h0} - : {io_fetchData_bits_addr[31:4] + 28'h1, 4'h0}; - wire [2:0] predecode_startIdx = {1'h0, io_fetchData_bits_addr[3:2]}; - wire [2:0] _GEN_0 = {1'h0, io_fetchData_bits_addr[3:2]}; - wire [2:0] _result_count_T_7 = - lastInstIdx == 3'h4 ? lastInstIdx - _GEN_0 : lastInstIdx + 3'h1 - _GEN_0; - wire [4:0] _predecodeValids_T_10 = - {3'h0, io_fetchData_bits_addr[3:2]} + {2'h0, _result_count_T_7}; - wire selectHot_0 = - io_fetchData_bits_addr[3:2] == 2'h0 & (|_predecodeValids_T_10); - wire predecodeValids_1 = - predecode_startIdx < 3'h2 & (|(_predecodeValids_T_10[4:1])); - wire predecodeValids_2 = - predecode_startIdx < 3'h3 & _predecodeValids_T_10 > 5'h2; - wire selectHot_seenValid_2 = selectHot_0 | predecodeValids_1; - wire selectHot_1 = predecodeValids_1 & ~selectHot_0; - wire selectHot_2 = predecodeValids_2 & ~selectHot_seenValid_2; - wire selectHot_3 = - (|(_predecodeValids_T_10[4:2])) & ~(selectHot_seenValid_2 | predecodeValids_2); - wire [31:0] _io_bufferRequest_bits_3_addr_T_2 = _GEN + 32'h4; - wire [31:0] _io_bufferRequest_bits_3_addr_T_4 = _GEN + 32'h8; - wire [31:0] _io_bufferRequest_bits_3_addr_T_6 = _GEN + 32'hC; - wire selectHot_1_1 = predecodeValids_1 & ~selectHot_1; - wire _GEN_1 = predecodeValids_2 & ~selectHot_2; - wire _GEN_2 = (|(_predecodeValids_T_10[4:2])) & ~selectHot_3; - wire selectHot_1_2 = _GEN_1 & ~selectHot_1_1; - wire selectHot_1_3 = _GEN_2 & ~(selectHot_1_1 | _GEN_1); - wire selectHot_2_2 = _GEN_1 & ~selectHot_1_2; - wire _GEN_3 = _GEN_2 & ~selectHot_1_3; - wire selectHot_2_3 = _GEN_3 & ~selectHot_2_2; - wire selectHot_3_3 = _GEN_3 & ~selectHot_2_3; - reg pastBranchOrFlush; - wire currentBranchOrFlush = io_iflush_valid | io_branch_valid; - wire ongoingBranchOrFlush = pastBranchOrFlush | currentBranchOrFlush; - wire writeToBuffer = io_fetchData_valid & ~ongoingBranchOrFlush; - wire [3:0] nValid = writeToBuffer ? {1'h0, _result_count_T_7} : 4'h0; - reg pc_valid; - reg [31:0] pc_bits; - wire [31:0] _pcNext_T_2 = {io_csr_value_0[31:2], 2'h0}; - wire blockNewFetch = - ~pc_valid | currentBranchOrFlush | {1'h0, io_bufferSpaces} < {1'h0, nValid} + 5'h4; + wire [127:0] predecode_insts_shifted = + {io_fetchData_bits_inst_3, + io_fetchData_bits_inst_2, + io_fetchData_bits_inst_1, + io_fetchData_bits_inst_0} >> {121'h0, io_fetchData_bits_addr[3:2], 5'h0}; + wire [31:0] _predecode_addrs_T_2 = io_fetchData_bits_addr + 32'h4; + wire [31:0] _predecode_addrs_T_4 = io_fetchData_bits_addr + 32'h8; + wire [31:0] _predecode_addrs_T_6 = io_fetchData_bits_addr + 32'hC; + wire [2:0] _predecode_validsIn_T_9 = 3'h4 - {1'h0, io_fetchData_bits_addr[3:2]}; + wire predecode_validsIn_2 = _predecode_validsIn_T_9 > 3'h2; + wire predecode_jumped_0 = + (|_predecode_validsIn_T_9) + & (predecode_insts_shifted[6:0] == 7'h6F | predecode_insts_shifted[6:0] == 7'h63 + & predecode_insts_shifted[31] & predecode_insts_shifted[14:13] != 2'h1); + wire predecode_jumped_1 = + (|(_predecode_validsIn_T_9[2:1])) + & (predecode_insts_shifted[38:32] == 7'h6F | predecode_insts_shifted[38:32] == 7'h63 + & predecode_insts_shifted[63] & predecode_insts_shifted[46:45] != 2'h1); + wire predecode_jumped_2 = + predecode_validsIn_2 + & (predecode_insts_shifted[70:64] == 7'h6F | predecode_insts_shifted[70:64] == 7'h63 + & predecode_insts_shifted[95] & predecode_insts_shifted[78:77] != 2'h1); + wire predecode_jumped_3 = + _predecode_validsIn_T_9[2] + & (predecode_insts_shifted[102:96] == 7'h6F | predecode_insts_shifted[102:96] == 7'h63 + & predecode_insts_shifted[127] & predecode_insts_shifted[110:109] != 2'h1); + wire [3:0] predecode_firstJumpOH_enc = + predecode_jumped_0 + ? 4'h1 + : predecode_jumped_1 + ? 4'h2 + : predecode_jumped_2 ? 4'h4 : {predecode_jumped_3, 3'h0}; + wire predecode_hasJumpedBefore_2 = predecode_jumped_0 | predecode_jumped_1; + wire [31:0] predecode_nextPc = + (predecode_firstJumpOH_enc[0] + ? io_fetchData_bits_addr + + {{12{predecode_insts_shifted[31]}}, + predecode_insts_shifted[2] + ? {predecode_insts_shifted[19:12], + predecode_insts_shifted[20], + predecode_insts_shifted[30:21]} + : {{8{predecode_insts_shifted[31]}}, + predecode_insts_shifted[7], + predecode_insts_shifted[30:25], + predecode_insts_shifted[11:8]}, + 1'h0} + : 32'h0) + | (predecode_firstJumpOH_enc[1] + ? _predecode_addrs_T_2 + + {{12{predecode_insts_shifted[63]}}, + predecode_insts_shifted[34] + ? {predecode_insts_shifted[51:44], + predecode_insts_shifted[52], + predecode_insts_shifted[62:53]} + : {{8{predecode_insts_shifted[63]}}, + predecode_insts_shifted[39], + predecode_insts_shifted[62:57], + predecode_insts_shifted[43:40]}, + 1'h0} + : 32'h0) + | (predecode_firstJumpOH_enc[2] + ? _predecode_addrs_T_4 + + {{12{predecode_insts_shifted[95]}}, + predecode_insts_shifted[66] + ? {predecode_insts_shifted[83:76], + predecode_insts_shifted[84], + predecode_insts_shifted[94:85]} + : {{8{predecode_insts_shifted[95]}}, + predecode_insts_shifted[71], + predecode_insts_shifted[94:89], + predecode_insts_shifted[75:72]}, + 1'h0} + : 32'h0) + | (predecode_firstJumpOH_enc[3] + ? _predecode_addrs_T_6 + + {{12{predecode_insts_shifted[127]}}, + predecode_insts_shifted[98] + ? {predecode_insts_shifted[115:108], + predecode_insts_shifted[116], + predecode_insts_shifted[126:117]} + : {{8{predecode_insts_shifted[127]}}, + predecode_insts_shifted[103], + predecode_insts_shifted[126:121], + predecode_insts_shifted[107:104]}, + 1'h0} + : 32'h0) + | (predecode_firstJumpOH_enc == 4'h0 + ? {io_fetchData_bits_addr[31:4] + 28'h1, 4'h0} + : 32'h0); + wire [2:0] predecode_result_y_1 = + {1'h0, + {1'h0, |_predecode_validsIn_T_9} + + {1'h0, (|(_predecode_validsIn_T_9[2:1])) & ~predecode_jumped_0}} + + {1'h0, + {1'h0, predecode_validsIn_2 & ~predecode_hasJumpedBefore_2} + + {1'h0, + _predecode_validsIn_T_9[2] + & ~(predecode_hasJumpedBefore_2 | predecode_jumped_2)}}; + reg pastBranchOrFlush; + wire currentBranchOrFlush = io_iflush_valid | io_branch_valid; + wire ongoingBranchOrFlush = pastBranchOrFlush | currentBranchOrFlush; + reg faulted; + wire fetchFaultValid = + (faulted | io_fetchData_valid & io_fetchData_bits_fault) & ~io_branch_valid; + wire io_fetchData_ready_0 = + io_bufferRequest_nReady >= predecode_result_y_1 | fetchFaultValid; + wire writeToBuffer = + io_fetchData_ready_0 & io_fetchData_valid & ~fetchFaultValid & ~ongoingBranchOrFlush; + reg ongoingFetch_valid; + reg [31:0] ongoingFetch_bits; + reg pc_valid; + reg [31:0] pc_bits; + wire blockNewFetch = + ~pc_valid | currentBranchOrFlush | ongoingFetch_valid | fetchFaultValid; + reg pcFetched; + wire newJump = + writeToBuffer + & (predecode_jumped_0 | predecode_jumped_1 | predecode_jumped_2 | predecode_jumped_3); + wire [31:0] _pcNext_T_2 = {io_csr_value_0[31:2], 2'h0}; + wire _pcNext_T_5 = ~blockNewFetch & pcFetched; + wire [31:0] _pcNext_T_9 = {pc_bits[31:4] + 28'h1, 4'h0}; + wire [31:0] fetch_bits = + (ongoingFetch_valid ? ongoingFetch_bits : 32'h0) + | (blockNewFetch + ? 32'h0 + : pc_valid + ? (io_iflush_valid + ? io_iflush_bits + : io_branch_valid + ? io_branch_bits + : newJump ? predecode_nextPc : _pcNext_T_5 ? _pcNext_T_9 : pc_bits) + : _pcNext_T_2); + wire fetch_valid = ongoingFetch_valid | ~blockNewFetch; + reg pendingJump; + wire newFetchInitiated = fetch_valid & ~ongoingFetch_valid; always @(posedge clock or posedge reset) begin if (reset) begin pastBranchOrFlush <= 1'h0; + faulted <= 1'h0; + ongoingFetch_valid <= 1'h0; + ongoingFetch_bits <= 32'h0; pc_valid <= 1'h0; pc_bits <= 32'h0; + pcFetched <= 1'h0; + pendingJump <= 1'h0; end else begin - pastBranchOrFlush <= ongoingBranchOrFlush & blockNewFetch; + pastBranchOrFlush <= ongoingBranchOrFlush & ~newFetchInitiated; + faulted <= fetchFaultValid; + ongoingFetch_valid <= ~io_fetchAddr_ready & fetch_valid; + ongoingFetch_bits <= io_fetchAddr_ready ? 32'h0 : fetch_bits; pc_valid <= 1'h1; if (pc_valid) begin - if (io_iflush_valid) - pc_bits <= io_iflush_bits; - else if (io_branch_valid) - pc_bits <= io_branch_bits; - else if (writeToBuffer) - pc_bits <= nextFetchPc; - end - else - pc_bits <= _pcNext_T_2; - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ - `ifdef FIRRTL_BEFORE_INITIAL - `FIRRTL_BEFORE_INITIAL - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; - initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; - end - pastBranchOrFlush = _RANDOM[1'h0][0]; - pc_valid = _RANDOM[1'h0][1]; - pc_bits = {_RANDOM[1'h0][31:2], _RANDOM[1'h1][1:0]}; - `endif // RANDOMIZE_REG_INIT - if (reset) begin - pastBranchOrFlush = 1'h0; - pc_valid = 1'h0; - pc_bits = 32'h0; - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_fetchAddr_valid = ~blockNewFetch; - assign io_fetchAddr_bits = - blockNewFetch - ? 32'h0 - : pc_valid - ? (io_iflush_valid - ? io_iflush_bits - : io_branch_valid ? io_branch_bits : writeToBuffer ? nextFetchPc : pc_bits) - : _pcNext_T_2; - assign io_bufferRequest_nValid = nValid[2:0]; - assign io_bufferRequest_bits_0_addr = - selectHot_0 - ? {io_fetchData_bits_addr[31:4], 4'h0} - : selectHot_1 - ? _io_bufferRequest_bits_3_addr_T_2 - : selectHot_2 - ? _io_bufferRequest_bits_3_addr_T_4 - : selectHot_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; - assign io_bufferRequest_bits_0_inst = - selectHot_0 - ? io_fetchData_bits_inst_0 - : selectHot_1 - ? io_fetchData_bits_inst_1 - : selectHot_2 - ? io_fetchData_bits_inst_2 - : selectHot_3 ? io_fetchData_bits_inst_3 : 32'h0; - assign io_bufferRequest_bits_0_brchFwd = - selectHot_0 - ? jumped_0 - : selectHot_1 ? jumped_1 : selectHot_2 ? jumped_2 : selectHot_3 & jumped_3; - assign io_bufferRequest_bits_1_addr = - selectHot_1_1 - ? _io_bufferRequest_bits_3_addr_T_2 - : selectHot_1_2 - ? _io_bufferRequest_bits_3_addr_T_4 - : selectHot_1_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; - assign io_bufferRequest_bits_1_inst = - selectHot_1_1 - ? io_fetchData_bits_inst_1 - : selectHot_1_2 - ? io_fetchData_bits_inst_2 - : selectHot_1_3 ? io_fetchData_bits_inst_3 : 32'h0; - assign io_bufferRequest_bits_1_brchFwd = - selectHot_1_1 ? jumped_1 : selectHot_1_2 ? jumped_2 : selectHot_1_3 & jumped_3; - assign io_bufferRequest_bits_2_addr = - selectHot_2_2 - ? _io_bufferRequest_bits_3_addr_T_4 - : selectHot_2_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; - assign io_bufferRequest_bits_2_inst = - selectHot_2_2 - ? io_fetchData_bits_inst_2 - : selectHot_2_3 ? io_fetchData_bits_inst_3 : 32'h0; - assign io_bufferRequest_bits_2_brchFwd = - selectHot_2_2 ? jumped_2 : selectHot_2_3 & jumped_3; - assign io_bufferRequest_bits_3_addr = - selectHot_3_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; - assign io_bufferRequest_bits_3_inst = selectHot_3_3 ? io_fetchData_bits_inst_3 : 32'h0; - assign io_bufferRequest_bits_3_brchFwd = selectHot_3_3 & jumped_3; -endmodule - -module Fetcher( - input clock, - reset, - io_ctrl_valid, - input [31:0] io_ctrl_bits, - output io_fetch_valid, - output [31:0] io_fetch_bits_addr, - io_fetch_bits_inst_0, - io_fetch_bits_inst_1, - io_fetch_bits_inst_2, - io_fetch_bits_inst_3, - output io_ibus_valid, - input io_ibus_ready, - output [31:0] io_ibus_addr, - input [127:0] io_ibus_rdata -); - - reg ibusCmd_valid; - reg [31:0] ibusCmd_bits; - wire ibusFired = io_ctrl_valid & io_ibus_ready; - always @(posedge clock or posedge reset) begin - if (reset) begin - ibusCmd_valid <= 1'h0; - ibusCmd_bits <= 32'h0; - end - else begin - ibusCmd_valid <= ibusFired; - ibusCmd_bits <= ibusFired ? io_ctrl_bits : 32'h0; - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ - `ifdef FIRRTL_BEFORE_INITIAL - `FIRRTL_BEFORE_INITIAL - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; - initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; - end - ibusCmd_valid = _RANDOM[1'h0][0]; - ibusCmd_bits = {_RANDOM[1'h0][31:1], _RANDOM[1'h1][0]}; - `endif // RANDOMIZE_REG_INIT - if (reset) begin - ibusCmd_valid = 1'h0; - ibusCmd_bits = 32'h0; - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_fetch_valid = ibusCmd_valid; - assign io_fetch_bits_addr = ibusCmd_bits; - assign io_fetch_bits_inst_0 = io_ibus_rdata[31:0]; - assign io_fetch_bits_inst_1 = io_ibus_rdata[63:32]; - assign io_fetch_bits_inst_2 = io_ibus_rdata[95:64]; - assign io_fetch_bits_inst_3 = io_ibus_rdata[127:96]; - assign io_ibus_valid = io_ctrl_valid; - assign io_ibus_addr = {io_ctrl_bits[31:4], 4'h0}; -endmodule - -module CircularBufferMulti( - input clock, - reset, - input [2:0] io_enqValid, - input [31:0] io_enqData_0_addr, - io_enqData_0_inst, - input io_enqData_0_brchFwd, - input [31:0] io_enqData_1_addr, - io_enqData_1_inst, - input io_enqData_1_brchFwd, - input [31:0] io_enqData_2_addr, - io_enqData_2_inst, - input io_enqData_2_brchFwd, - input [31:0] io_enqData_3_addr, - io_enqData_3_inst, - input io_enqData_3_brchFwd, - output [3:0] io_nEnqueued, - io_nSpace, - output [31:0] io_dataOut_0_addr, - io_dataOut_0_inst, - output io_dataOut_0_brchFwd, - output [31:0] io_dataOut_1_addr, - io_dataOut_1_inst, - output io_dataOut_1_brchFwd, - output [31:0] io_dataOut_2_addr, - io_dataOut_2_inst, - output io_dataOut_2_brchFwd, - output [31:0] io_dataOut_3_addr, - io_dataOut_3_inst, - output io_dataOut_3_brchFwd, - input [2:0] io_deqReady, - input io_flush -); - - reg [31:0] buffer_0_addr; - reg [31:0] buffer_0_inst; - reg buffer_0_brchFwd; - reg [31:0] buffer_1_addr; - reg [31:0] buffer_1_inst; - reg buffer_1_brchFwd; - reg [31:0] buffer_2_addr; - reg [31:0] buffer_2_inst; - reg buffer_2_brchFwd; - reg [31:0] buffer_3_addr; - reg [31:0] buffer_3_inst; - reg buffer_3_brchFwd; - reg [31:0] buffer_4_addr; - reg [31:0] buffer_4_inst; - reg buffer_4_brchFwd; - reg [31:0] buffer_5_addr; - reg [31:0] buffer_5_inst; - reg buffer_5_brchFwd; - reg [31:0] buffer_6_addr; - reg [31:0] buffer_6_inst; - reg buffer_6_brchFwd; - reg [31:0] buffer_7_addr; - reg [31:0] buffer_7_inst; - reg buffer_7_brchFwd; - reg [2:0] enqPtr; - reg [2:0] deqPtr; - reg [3:0] nEnqueued; - wire [9:0] _outputBufferView_rotated_T_9 = {7'h0, deqPtr} * 10'h41; - wire [519:0] _outputBufferView_rotated_T_23 = - _outputBufferView_rotated_T_9[0] - ? {buffer_0_brchFwd, - buffer_7_addr, - buffer_7_inst, - buffer_7_brchFwd, - buffer_6_addr, - buffer_6_inst, - buffer_6_brchFwd, - buffer_5_addr, - buffer_5_inst, - buffer_5_brchFwd, - buffer_4_addr, - buffer_4_inst, - buffer_4_brchFwd, - buffer_3_addr, - buffer_3_inst, - buffer_3_brchFwd, - buffer_2_addr, - buffer_2_inst, - buffer_2_brchFwd, - buffer_1_addr, - buffer_1_inst, - buffer_1_brchFwd, - buffer_0_addr, - buffer_0_inst} - : {buffer_7_addr, - buffer_7_inst, - buffer_7_brchFwd, - buffer_6_addr, - buffer_6_inst, - buffer_6_brchFwd, - buffer_5_addr, - buffer_5_inst, - buffer_5_brchFwd, - buffer_4_addr, - buffer_4_inst, - buffer_4_brchFwd, - buffer_3_addr, - buffer_3_inst, - buffer_3_brchFwd, - buffer_2_addr, - buffer_2_inst, - buffer_2_brchFwd, - buffer_1_addr, - buffer_1_inst, - buffer_1_brchFwd, - buffer_0_addr, - buffer_0_inst, - buffer_0_brchFwd}; - wire [519:0] _outputBufferView_rotated_T_27 = - _outputBufferView_rotated_T_9[1] - ? {_outputBufferView_rotated_T_23[1:0], _outputBufferView_rotated_T_23[519:2]} - : _outputBufferView_rotated_T_23; - wire [519:0] _outputBufferView_rotated_T_31 = - _outputBufferView_rotated_T_9[2] - ? {_outputBufferView_rotated_T_27[3:0], _outputBufferView_rotated_T_27[519:4]} - : _outputBufferView_rotated_T_27; - wire [519:0] _outputBufferView_rotated_T_35 = - _outputBufferView_rotated_T_9[3] - ? {_outputBufferView_rotated_T_31[7:0], _outputBufferView_rotated_T_31[519:8]} - : _outputBufferView_rotated_T_31; - wire [519:0] _outputBufferView_rotated_T_39 = - _outputBufferView_rotated_T_9[4] - ? {_outputBufferView_rotated_T_35[15:0], _outputBufferView_rotated_T_35[519:16]} - : _outputBufferView_rotated_T_35; - wire [519:0] _outputBufferView_rotated_T_43 = - _outputBufferView_rotated_T_9[5] - ? {_outputBufferView_rotated_T_39[31:0], _outputBufferView_rotated_T_39[519:32]} - : _outputBufferView_rotated_T_39; - wire [519:0] _outputBufferView_rotated_T_47 = - _outputBufferView_rotated_T_9[6] - ? {_outputBufferView_rotated_T_43[63:0], _outputBufferView_rotated_T_43[519:64]} - : _outputBufferView_rotated_T_43; - wire [519:0] _outputBufferView_rotated_T_51 = - _outputBufferView_rotated_T_9[7] - ? {_outputBufferView_rotated_T_47[127:0], _outputBufferView_rotated_T_47[519:128]} - : _outputBufferView_rotated_T_47; - wire [519:0] _outputBufferView_rotated_T_55 = - _outputBufferView_rotated_T_9[8] - ? {_outputBufferView_rotated_T_51[255:0], _outputBufferView_rotated_T_51[519:256]} - : _outputBufferView_rotated_T_51; - wire [259:0] outputBufferView_rotated = - _outputBufferView_rotated_T_9[9] - ? {_outputBufferView_rotated_T_55[251:0], _outputBufferView_rotated_T_55[519:512]} - : _outputBufferView_rotated_T_55[259:0]; - wire expandedInput_2_ret_valid = io_enqValid > 3'h2; - wire [9:0] _rotatedInput_rotated_T_17 = {7'h0, enqPtr} * 10'h42; - wire [527:0] _rotatedInput_rotated_T_31 = - _rotatedInput_rotated_T_17[0] - ? {263'h0, - io_enqValid[2], - io_enqData_3_addr, - io_enqData_3_inst, - io_enqData_3_brchFwd, - expandedInput_2_ret_valid, - io_enqData_2_addr, - io_enqData_2_inst, - io_enqData_2_brchFwd, - |(io_enqValid[2:1]), - io_enqData_1_addr, - io_enqData_1_inst, - io_enqData_1_brchFwd, - |io_enqValid, - io_enqData_0_addr, - io_enqData_0_inst, - io_enqData_0_brchFwd, - 1'h0} - : {264'h0, - io_enqValid[2], - io_enqData_3_addr, - io_enqData_3_inst, - io_enqData_3_brchFwd, - expandedInput_2_ret_valid, - io_enqData_2_addr, - io_enqData_2_inst, - io_enqData_2_brchFwd, - |(io_enqValid[2:1]), - io_enqData_1_addr, - io_enqData_1_inst, - io_enqData_1_brchFwd, - |io_enqValid, - io_enqData_0_addr, - io_enqData_0_inst, - io_enqData_0_brchFwd}; - wire [527:0] _rotatedInput_rotated_T_35 = - _rotatedInput_rotated_T_17[1] - ? {_rotatedInput_rotated_T_31[525:0], _rotatedInput_rotated_T_31[527:526]} - : _rotatedInput_rotated_T_31; - wire [527:0] _rotatedInput_rotated_T_39 = - _rotatedInput_rotated_T_17[2] - ? {_rotatedInput_rotated_T_35[523:0], _rotatedInput_rotated_T_35[527:524]} - : _rotatedInput_rotated_T_35; - wire [527:0] _rotatedInput_rotated_T_43 = - _rotatedInput_rotated_T_17[3] - ? {_rotatedInput_rotated_T_39[519:0], _rotatedInput_rotated_T_39[527:520]} - : _rotatedInput_rotated_T_39; - wire [527:0] _rotatedInput_rotated_T_47 = - _rotatedInput_rotated_T_17[4] - ? {_rotatedInput_rotated_T_43[511:0], _rotatedInput_rotated_T_43[527:512]} - : _rotatedInput_rotated_T_43; - wire [527:0] _rotatedInput_rotated_T_51 = - _rotatedInput_rotated_T_17[5] - ? {_rotatedInput_rotated_T_47[495:0], _rotatedInput_rotated_T_47[527:496]} - : _rotatedInput_rotated_T_47; - wire [527:0] _rotatedInput_rotated_T_55 = - _rotatedInput_rotated_T_17[6] - ? {_rotatedInput_rotated_T_51[463:0], _rotatedInput_rotated_T_51[527:464]} - : _rotatedInput_rotated_T_51; - wire [527:0] _rotatedInput_rotated_T_59 = - _rotatedInput_rotated_T_17[7] - ? {_rotatedInput_rotated_T_55[399:0], _rotatedInput_rotated_T_55[527:400]} - : _rotatedInput_rotated_T_55; - wire [527:0] _rotatedInput_rotated_T_63 = - _rotatedInput_rotated_T_17[8] - ? {_rotatedInput_rotated_T_59[271:0], _rotatedInput_rotated_T_59[527:272]} - : _rotatedInput_rotated_T_59; - wire [527:0] rotatedInput_rotated = - _rotatedInput_rotated_T_17[9] - ? {_rotatedInput_rotated_T_63[15:0], _rotatedInput_rotated_T_63[527:16]} - : _rotatedInput_rotated_T_63; - always @(posedge clock or posedge reset) begin - if (reset) begin - buffer_0_addr <= 32'h0; - buffer_0_inst <= 32'h0; - buffer_0_brchFwd <= 1'h0; - buffer_1_addr <= 32'h0; - buffer_1_inst <= 32'h0; - buffer_1_brchFwd <= 1'h0; - buffer_2_addr <= 32'h0; - buffer_2_inst <= 32'h0; - buffer_2_brchFwd <= 1'h0; - buffer_3_addr <= 32'h0; - buffer_3_inst <= 32'h0; - buffer_3_brchFwd <= 1'h0; - buffer_4_addr <= 32'h0; - buffer_4_inst <= 32'h0; - buffer_4_brchFwd <= 1'h0; - buffer_5_addr <= 32'h0; - buffer_5_inst <= 32'h0; - buffer_5_brchFwd <= 1'h0; - buffer_6_addr <= 32'h0; - buffer_6_inst <= 32'h0; - buffer_6_brchFwd <= 1'h0; - buffer_7_addr <= 32'h0; - buffer_7_inst <= 32'h0; - buffer_7_brchFwd <= 1'h0; - enqPtr <= 3'h0; - deqPtr <= 3'h0; - nEnqueued <= 4'h0; - end - else begin - if (rotatedInput_rotated[65]) begin - buffer_0_addr <= rotatedInput_rotated[64:33]; - buffer_0_inst <= rotatedInput_rotated[32:1]; - buffer_0_brchFwd <= rotatedInput_rotated[0]; - end - if (rotatedInput_rotated[131]) begin - buffer_1_addr <= rotatedInput_rotated[130:99]; - buffer_1_inst <= rotatedInput_rotated[98:67]; - buffer_1_brchFwd <= rotatedInput_rotated[66]; - end - if (rotatedInput_rotated[197]) begin - buffer_2_addr <= rotatedInput_rotated[196:165]; - buffer_2_inst <= rotatedInput_rotated[164:133]; - buffer_2_brchFwd <= rotatedInput_rotated[132]; - end - if (rotatedInput_rotated[263]) begin - buffer_3_addr <= rotatedInput_rotated[262:231]; - buffer_3_inst <= rotatedInput_rotated[230:199]; - buffer_3_brchFwd <= rotatedInput_rotated[198]; - end - if (rotatedInput_rotated[329]) begin - buffer_4_addr <= rotatedInput_rotated[328:297]; - buffer_4_inst <= rotatedInput_rotated[296:265]; - buffer_4_brchFwd <= rotatedInput_rotated[264]; - end - if (rotatedInput_rotated[395]) begin - buffer_5_addr <= rotatedInput_rotated[394:363]; - buffer_5_inst <= rotatedInput_rotated[362:331]; - buffer_5_brchFwd <= rotatedInput_rotated[330]; - end - if (rotatedInput_rotated[461]) begin - buffer_6_addr <= rotatedInput_rotated[460:429]; - buffer_6_inst <= rotatedInput_rotated[428:397]; - buffer_6_brchFwd <= rotatedInput_rotated[396]; - end - if (rotatedInput_rotated[527]) begin - buffer_7_addr <= rotatedInput_rotated[526:495]; - buffer_7_inst <= rotatedInput_rotated[494:463]; - buffer_7_brchFwd <= rotatedInput_rotated[462]; + if (io_iflush_valid) + pc_bits <= io_iflush_bits; + else if (io_branch_valid) + pc_bits <= io_branch_bits; + else if (newJump) + pc_bits <= predecode_nextPc; + else if (_pcNext_T_5) + pc_bits <= _pcNext_T_9; end - enqPtr <= io_flush ? 3'h0 : enqPtr + io_enqValid; - deqPtr <= io_flush ? 3'h0 : deqPtr + io_deqReady; - nEnqueued <= - io_flush ? 4'h0 : nEnqueued + {1'h0, io_enqValid} - {1'h0, io_deqReady}; + else + pc_bits <= _pcNext_T_2; + pcFetched <= + pc_valid + ? ~currentBranchOrFlush & (~newJump & pcFetched | ~blockNewFetch) + : ~blockNewFetch; + pendingJump <= (pendingJump | newJump) & ~newFetchInitiated; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:16]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin - _RANDOM[i] = `RANDOM; - end - buffer_0_addr = _RANDOM[5'h0]; - buffer_0_inst = _RANDOM[5'h1]; - buffer_0_brchFwd = _RANDOM[5'h2][0]; - buffer_1_addr = {_RANDOM[5'h2][31:1], _RANDOM[5'h3][0]}; - buffer_1_inst = {_RANDOM[5'h3][31:1], _RANDOM[5'h4][0]}; - buffer_1_brchFwd = _RANDOM[5'h4][1]; - buffer_2_addr = {_RANDOM[5'h4][31:2], _RANDOM[5'h5][1:0]}; - buffer_2_inst = {_RANDOM[5'h5][31:2], _RANDOM[5'h6][1:0]}; - buffer_2_brchFwd = _RANDOM[5'h6][2]; - buffer_3_addr = {_RANDOM[5'h6][31:3], _RANDOM[5'h7][2:0]}; - buffer_3_inst = {_RANDOM[5'h7][31:3], _RANDOM[5'h8][2:0]}; - buffer_3_brchFwd = _RANDOM[5'h8][3]; - buffer_4_addr = {_RANDOM[5'h8][31:4], _RANDOM[5'h9][3:0]}; - buffer_4_inst = {_RANDOM[5'h9][31:4], _RANDOM[5'hA][3:0]}; - buffer_4_brchFwd = _RANDOM[5'hA][4]; - buffer_5_addr = {_RANDOM[5'hA][31:5], _RANDOM[5'hB][4:0]}; - buffer_5_inst = {_RANDOM[5'hB][31:5], _RANDOM[5'hC][4:0]}; - buffer_5_brchFwd = _RANDOM[5'hC][5]; - buffer_6_addr = {_RANDOM[5'hC][31:6], _RANDOM[5'hD][5:0]}; - buffer_6_inst = {_RANDOM[5'hD][31:6], _RANDOM[5'hE][5:0]}; - buffer_6_brchFwd = _RANDOM[5'hE][6]; - buffer_7_addr = {_RANDOM[5'hE][31:7], _RANDOM[5'hF][6:0]}; - buffer_7_inst = {_RANDOM[5'hF][31:7], _RANDOM[5'h10][6:0]}; - buffer_7_brchFwd = _RANDOM[5'h10][7]; - enqPtr = _RANDOM[5'h10][10:8]; - deqPtr = _RANDOM[5'h10][13:11]; - nEnqueued = _RANDOM[5'h10][17:14]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - buffer_0_addr = 32'h0; - buffer_0_inst = 32'h0; - buffer_0_brchFwd = 1'h0; - buffer_1_addr = 32'h0; - buffer_1_inst = 32'h0; - buffer_1_brchFwd = 1'h0; - buffer_2_addr = 32'h0; - buffer_2_inst = 32'h0; - buffer_2_brchFwd = 1'h0; - buffer_3_addr = 32'h0; - buffer_3_inst = 32'h0; - buffer_3_brchFwd = 1'h0; - buffer_4_addr = 32'h0; - buffer_4_inst = 32'h0; - buffer_4_brchFwd = 1'h0; - buffer_5_addr = 32'h0; - buffer_5_inst = 32'h0; - buffer_5_brchFwd = 1'h0; - buffer_6_addr = 32'h0; - buffer_6_inst = 32'h0; - buffer_6_brchFwd = 1'h0; - buffer_7_addr = 32'h0; - buffer_7_inst = 32'h0; - buffer_7_brchFwd = 1'h0; - enqPtr = 3'h0; - deqPtr = 3'h0; - nEnqueued = 4'h0; + pastBranchOrFlush = 1'h0; + faulted = 1'h0; + ongoingFetch_valid = 1'h0; + ongoingFetch_bits = 32'h0; + pc_valid = 1'h0; + pc_bits = 32'h0; + pcFetched = 1'h0; + pendingJump = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_nEnqueued = nEnqueued; - assign io_nSpace = 4'h8 - nEnqueued; - assign io_dataOut_0_addr = outputBufferView_rotated[64:33]; - assign io_dataOut_0_inst = outputBufferView_rotated[32:1]; - assign io_dataOut_0_brchFwd = outputBufferView_rotated[0]; - assign io_dataOut_1_addr = outputBufferView_rotated[129:98]; - assign io_dataOut_1_inst = outputBufferView_rotated[97:66]; - assign io_dataOut_1_brchFwd = outputBufferView_rotated[65]; - assign io_dataOut_2_addr = outputBufferView_rotated[194:163]; - assign io_dataOut_2_inst = outputBufferView_rotated[162:131]; - assign io_dataOut_2_brchFwd = outputBufferView_rotated[130]; - assign io_dataOut_3_addr = outputBufferView_rotated[259:228]; - assign io_dataOut_3_inst = outputBufferView_rotated[227:196]; - assign io_dataOut_3_brchFwd = outputBufferView_rotated[195]; + assign io_fetchFault_valid = fetchFaultValid; + assign io_fetchFault_bits = io_fetchData_bits_addr; + assign io_fetchData_ready = io_fetchData_ready_0; + assign io_fetchAddr_valid = fetch_valid; + assign io_fetchAddr_bits = fetch_bits; + assign io_flushTx = ongoingBranchOrFlush | pendingJump | newJump; + assign io_bufferRequest_nValid = writeToBuffer ? predecode_result_y_1 : 3'h0; + assign io_bufferRequest_bits_0_addr = io_fetchData_bits_addr; + assign io_bufferRequest_bits_0_inst = predecode_insts_shifted[31:0]; + assign io_bufferRequest_bits_0_brchFwd = predecode_jumped_0; + assign io_bufferRequest_bits_1_addr = _predecode_addrs_T_2; + assign io_bufferRequest_bits_1_inst = predecode_insts_shifted[63:32]; + assign io_bufferRequest_bits_1_brchFwd = predecode_jumped_1; + assign io_bufferRequest_bits_2_addr = _predecode_addrs_T_4; + assign io_bufferRequest_bits_2_inst = predecode_insts_shifted[95:64]; + assign io_bufferRequest_bits_2_brchFwd = predecode_jumped_2; + assign io_bufferRequest_bits_3_addr = _predecode_addrs_T_6; + assign io_bufferRequest_bits_3_inst = predecode_insts_shifted[127:96]; + assign io_bufferRequest_bits_3_brchFwd = predecode_jumped_3; endmodule -module InstructionBuffer( - input clock, - reset, - output [2:0] io_feedIn_nReady, - input [2:0] io_feedIn_nValid, - input [31:0] io_feedIn_bits_0_addr, - io_feedIn_bits_0_inst, - input io_feedIn_bits_0_brchFwd, - input [31:0] io_feedIn_bits_1_addr, - io_feedIn_bits_1_inst, - input io_feedIn_bits_1_brchFwd, - input [31:0] io_feedIn_bits_2_addr, - io_feedIn_bits_2_inst, - input io_feedIn_bits_2_brchFwd, - input [31:0] io_feedIn_bits_3_addr, - io_feedIn_bits_3_inst, - input io_feedIn_bits_3_brchFwd, - io_out_0_ready, - output io_out_0_valid, - output [31:0] io_out_0_bits_addr, - io_out_0_bits_inst, - output io_out_0_bits_brchFwd, - input io_out_1_ready, - output io_out_1_valid, - output [31:0] io_out_1_bits_addr, - io_out_1_bits_inst, - output io_out_1_bits_brchFwd, - input io_out_2_ready, - output io_out_2_valid, - output [31:0] io_out_2_bits_addr, - io_out_2_bits_inst, - output io_out_2_bits_brchFwd, - input io_out_3_ready, - output io_out_3_valid, - output [31:0] io_out_3_bits_addr, - io_out_3_bits_inst, - output io_out_3_bits_brchFwd, - input io_flush, - output [3:0] io_nEnqueued, - io_nSpace +module IndexAllocatorShifting( + input clock, + reset, + io_alloc_ready, + output io_alloc_valid, + io_alloc_bits, + input io_free_valid, + io_free_bits ); - wire [3:0] _circularBuffer_io_nEnqueued; - wire [3:0] _circularBuffer_io_nSpace; - wire io_out_0_valid_0 = (|_circularBuffer_io_nEnqueued) & ~io_flush; - wire io_out_1_valid_0 = (|(_circularBuffer_io_nEnqueued[3:1])) & ~io_flush; - wire io_out_2_valid_0 = _circularBuffer_io_nEnqueued > 4'h2 & ~io_flush; - wire io_out_3_valid_0 = (|(_circularBuffer_io_nEnqueued[3:2])) & ~io_flush; - wire _nReady_T = io_out_0_ready & io_out_0_valid_0; - wire _nReady_T_1 = io_out_1_ready & io_out_1_valid_0; - wire _nReady_T_2 = io_out_2_ready & io_out_2_valid_0; - wire _nReady_T_3 = io_out_3_ready & io_out_3_valid_0; - CircularBufferMulti circularBuffer ( - .clock (clock), - .reset (reset), - .io_enqValid (io_feedIn_nValid), - .io_enqData_0_addr (io_feedIn_bits_0_addr), - .io_enqData_0_inst (io_feedIn_bits_0_inst), - .io_enqData_0_brchFwd (io_feedIn_bits_0_brchFwd), - .io_enqData_1_addr (io_feedIn_bits_1_addr), - .io_enqData_1_inst (io_feedIn_bits_1_inst), - .io_enqData_1_brchFwd (io_feedIn_bits_1_brchFwd), - .io_enqData_2_addr (io_feedIn_bits_2_addr), - .io_enqData_2_inst (io_feedIn_bits_2_inst), - .io_enqData_2_brchFwd (io_feedIn_bits_2_brchFwd), - .io_enqData_3_addr (io_feedIn_bits_3_addr), - .io_enqData_3_inst (io_feedIn_bits_3_inst), - .io_enqData_3_brchFwd (io_feedIn_bits_3_brchFwd), - .io_nEnqueued (_circularBuffer_io_nEnqueued), - .io_nSpace (_circularBuffer_io_nSpace), - .io_dataOut_0_addr (io_out_0_bits_addr), - .io_dataOut_0_inst (io_out_0_bits_inst), - .io_dataOut_0_brchFwd (io_out_0_bits_brchFwd), - .io_dataOut_1_addr (io_out_1_bits_addr), - .io_dataOut_1_inst (io_out_1_bits_inst), - .io_dataOut_1_brchFwd (io_out_1_bits_brchFwd), - .io_dataOut_2_addr (io_out_2_bits_addr), - .io_dataOut_2_inst (io_out_2_bits_inst), - .io_dataOut_2_brchFwd (io_out_2_bits_brchFwd), - .io_dataOut_3_addr (io_out_3_bits_addr), - .io_dataOut_3_inst (io_out_3_bits_inst), - .io_dataOut_3_brchFwd (io_out_3_bits_brchFwd), - .io_deqReady - ({1'h0, {1'h0, _nReady_T} + {1'h0, _nReady_T_1}} - + {1'h0, {1'h0, _nReady_T_2} + {1'h0, _nReady_T_3}}), - .io_flush (io_flush) - ); - assign io_feedIn_nReady = - _circularBuffer_io_nSpace < 4'h4 ? _circularBuffer_io_nSpace[2:0] : 3'h4; - assign io_out_0_valid = io_out_0_valid_0; - assign io_out_1_valid = io_out_1_valid_0; - assign io_out_2_valid = io_out_2_valid_0; - assign io_out_3_valid = io_out_3_valid_0; - assign io_nEnqueued = _circularBuffer_io_nEnqueued; - assign io_nSpace = _circularBuffer_io_nSpace; + reg state_regs_0; + reg state_regs_1; + reg [1:0] state_nAvail; + reg state_isNonEmpty; + wire io_alloc_valid_0 = state_isNonEmpty | io_free_valid; + wire _state_T_16 = io_alloc_ready & io_alloc_valid_0; + wire _state_T_17 = ~(state_nAvail[1]) & io_free_valid; + wire _state_T_3 = _state_T_16 & ~_state_T_17; + wire _state_T_12 = ~_state_T_16 & _state_T_17; + wire _state_T_19 = _state_T_16 & _state_T_17 & state_isNonEmpty; + wire _state_defaultSel_T_2 = + _state_T_3 | _state_T_12 | _state_T_19 | state_nAvail[1] & io_free_valid; + wire _GEN = _state_T_3 & state_isNonEmpty & state_nAvail != 2'h3; + wire _GEN_0 = _state_T_19 & ~(state_nAvail[1]); + wire _GEN_1 = _state_T_12 & ~(state_nAvail[1]); + always @(posedge clock or posedge reset) begin + if (reset) begin + state_regs_0 <= 1'h0; + state_regs_1 <= 1'h1; + state_nAvail <= 2'h2; + state_isNonEmpty <= 1'h1; + end + else begin + state_regs_0 <= + _GEN & (state_nAvail[1] ? state_regs_1 : state_regs_0) | _GEN_1 + & (state_nAvail[0] ? state_regs_0 : io_free_bits) | _GEN_0 & io_free_bits + | ~_state_defaultSel_T_2 & state_regs_0; + state_regs_1 <= + _GEN & state_regs_1 | _GEN_1 & (state_nAvail[0] ? io_free_bits : state_regs_1) + | _GEN_0 & state_regs_1 | ~_state_defaultSel_T_2 & state_regs_1; + state_nAvail <= + (_GEN ? state_nAvail - 2'h1 : 2'h0) | (_GEN_1 ? state_nAvail + 2'h1 : 2'h0) + | (_GEN_0 ? state_nAvail : 2'h0) | (_state_defaultSel_T_2 ? 2'h0 : state_nAvail); + state_isNonEmpty <= + _GEN & state_nAvail[1] | _state_T_12 & ~(state_nAvail[1]) | _GEN_0 + & state_isNonEmpty | ~_state_defaultSel_T_2 & state_isNonEmpty; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + state_regs_0 = 1'h0; + state_regs_1 = 1'h1; + state_nAvail = 2'h2; + state_isNonEmpty = 1'h1; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_alloc_valid = io_alloc_valid_0; + assign io_alloc_bits = state_isNonEmpty ? state_regs_0 : io_free_bits; endmodule -module UncachedFetch( +module FetchReorderBuffer( input clock, reset, - input [31:0] io_csr_value_0, - output io_ibus_valid, - input io_ibus_ready, - output [31:0] io_ibus_addr, - input [127:0] io_ibus_rdata, - input io_inst_lanes_0_ready, - output io_inst_lanes_0_valid, - output [31:0] io_inst_lanes_0_bits_addr, - io_inst_lanes_0_bits_inst, - output io_inst_lanes_0_bits_brchFwd, - input io_inst_lanes_1_ready, - output io_inst_lanes_1_valid, - output [31:0] io_inst_lanes_1_bits_addr, - io_inst_lanes_1_bits_inst, - output io_inst_lanes_1_bits_brchFwd, - input io_inst_lanes_2_ready, - output io_inst_lanes_2_valid, - output [31:0] io_inst_lanes_2_bits_addr, - io_inst_lanes_2_bits_inst, - output io_inst_lanes_2_bits_brchFwd, - input io_inst_lanes_3_ready, - output io_inst_lanes_3_valid, - output [31:0] io_inst_lanes_3_bits_addr, - io_inst_lanes_3_bits_inst, - output io_inst_lanes_3_bits_brchFwd, - input io_branch_0_valid, - input [31:0] io_branch_0_value, - input io_branch_1_valid, - input [31:0] io_branch_1_value, - input io_branch_2_valid, - input [31:0] io_branch_2_value, - input io_branch_3_valid, - input [31:0] io_branch_3_value, - input io_iflush_valid, - input [31:0] io_iflush_pcNext, - output [31:0] io_pc + output io_newTx_ready, + input io_newTx_valid, + io_newTx_bits_txid, + input [31:0] io_newTx_bits_addr, + input io_busResp_valid, + io_busResp_bits_txid, + input [127:0] io_busResp_bits_resp_data, + input io_busResp_bits_resp_fault, + io_commit_ready, + output io_commit_valid, + output [31:0] io_commit_bits_addr, + output [127:0] io_commit_bits_resp_data, + output io_commit_bits_resp_fault, + io_freeTxid_valid, + io_freeTxid_bits, + input io_flush ); - wire _instructionBuffer_io_out_0_valid; - wire [31:0] _instructionBuffer_io_out_0_bits_addr; - wire [3:0] _instructionBuffer_io_nSpace; - wire _fetcher_io_fetch_valid; - wire [31:0] _fetcher_io_fetch_bits_addr; - wire [31:0] _fetcher_io_fetch_bits_inst_0; - wire [31:0] _fetcher_io_fetch_bits_inst_1; - wire [31:0] _fetcher_io_fetch_bits_inst_2; - wire [31:0] _fetcher_io_fetch_bits_inst_3; - wire _ctrl_io_fetchAddr_valid; - wire [31:0] _ctrl_io_fetchAddr_bits; - wire [2:0] _ctrl_io_bufferRequest_nValid; - wire [31:0] _ctrl_io_bufferRequest_bits_0_addr; - wire [31:0] _ctrl_io_bufferRequest_bits_0_inst; - wire _ctrl_io_bufferRequest_bits_0_brchFwd; - wire [31:0] _ctrl_io_bufferRequest_bits_1_addr; - wire [31:0] _ctrl_io_bufferRequest_bits_1_inst; - wire _ctrl_io_bufferRequest_bits_1_brchFwd; - wire [31:0] _ctrl_io_bufferRequest_bits_2_addr; - wire [31:0] _ctrl_io_bufferRequest_bits_2_inst; - wire _ctrl_io_bufferRequest_bits_2_brchFwd; - wire [31:0] _ctrl_io_bufferRequest_bits_3_addr; - wire [31:0] _ctrl_io_bufferRequest_bits_3_inst; - wire _ctrl_io_bufferRequest_bits_3_brchFwd; - wire branch_valid = - io_branch_0_valid | io_branch_1_valid | io_branch_2_valid | io_branch_3_valid; - reg [31:0] pc; + reg state_queue_0_txid; + reg [31:0] state_queue_0_addr; + reg state_queue_0_resp_valid; + reg [127:0] state_queue_0_resp_bits_data; + reg state_queue_0_resp_bits_fault; + reg state_queue_1_txid; + reg [31:0] state_queue_1_addr; + reg state_queue_1_resp_valid; + reg [127:0] state_queue_1_resp_bits_data; + reg state_queue_1_resp_bits_fault; + reg [1:0] state_nElem; + reg [1:0] state_nCancelled; + wire _founds_T_2 = state_queue_0_txid == io_busResp_bits_txid; + wire _founds_T_6 = state_queue_1_txid == io_busResp_bits_txid; + wire _s2Precondition_dontNeedTrim_T = state_nCancelled == 2'h0; + wire precondition_noOverflow = state_nElem != 2'h3; + wire precondition_nCancelledReasonable = state_nCancelled <= state_nElem; + wire _noDuplicateTxid_T_22 = state_queue_0_txid == state_queue_1_txid; + wire s1Precondition = + precondition_noOverflow & precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s2Precondition_dontNeedTrim_T | state_queue_0_resp_valid) + & ~(io_busResp_valid + & ((|state_nElem) & state_queue_0_resp_valid & _founds_T_2 | state_nElem[1] + & state_queue_1_resp_valid & _founds_T_6)); + wire founds_0 = (|state_nElem) & _founds_T_2; + wire founds_1 = state_nElem[1] & _founds_T_6; + wire [1:0] _duplicateTxid_T_1 = {1'h0, founds_0} + {1'h0, founds_1}; + wire precondition = + precondition_noOverflow & precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s2Precondition_dontNeedTrim_T | state_queue_0_resp_valid) + & ~(_duplicateTxid_T_1[1]) + & ~(founds_0 & state_queue_0_resp_valid | founds_1 & state_queue_1_resp_valid); + wire respFound = precondition & (founds_0 | founds_1); + wire _GEN = respFound & founds_0; + wire _GEN_0 = respFound & ~founds_0; + wire s1Reject = io_busResp_valid & ~respFound; + wire _GEN_1 = ~io_busResp_valid | precondition; + wire _s1State_T_queue_1_txid = _GEN_1 & state_queue_1_txid; + wire _s1State_T_queue_1_resp_valid = + io_busResp_valid + ? precondition & (_GEN_0 | state_queue_1_resp_valid) + : state_queue_1_resp_valid; + wire s1State_queue_0_txid = s1Precondition & _GEN_1 & state_queue_0_txid; + wire _GEN_2 = s1Precondition & _GEN_1; + wire s1State_queue_0_resp_valid = + s1Precondition + & (io_busResp_valid + ? precondition & (_GEN | state_queue_0_resp_valid) + : state_queue_0_resp_valid); + wire s2State_y_1_txid = s1Precondition & _s1State_T_queue_1_txid; + wire s2State_y_1_resp_valid = s1Precondition & _s1State_T_queue_1_resp_valid; + wire [1:0] s1State_nElem = _GEN_2 ? state_nElem : 2'h0; + wire [1:0] s1State_nCancelled = _GEN_2 ? state_nCancelled : 2'h0; + wire s2Valid = + ~s1Reject & (|state_nElem) & _s2Precondition_dontNeedTrim_T + & state_queue_0_resp_valid; + wire s2Commit = io_commit_ready & s2Valid; + wire s2Precondition = + precondition_noOverflow & precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s2Precondition_dontNeedTrim_T | state_queue_0_resp_valid) & (~s2Commit | s2Valid); + wire s2State_precondition = + s1State_nElem != 2'h3 & s1State_nCancelled <= s1State_nElem + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (s1State_nCancelled == 2'h0 | s1State_queue_0_resp_valid) & (|s1State_nElem); + wire _GEN_3 = s2State_precondition & s1Precondition; + wire [1:0] _s2State_T_6_nElem = s2State_precondition ? s1State_nElem - 2'h1 : 2'h0; + wire [1:0] _s2State_T_6_nCancelled = + s2State_precondition & (|s1State_nCancelled) ? s1State_nCancelled - 2'h1 : 2'h0; + wire _s2State_T_7_queue_0_txid = + s2Commit + ? s2State_precondition + & (s1State_nElem[1] ? s2State_y_1_txid : s1State_queue_0_txid) + : s1State_queue_0_txid; + wire _s2State_T_7_queue_0_resp_valid = + s2Commit + ? s2State_precondition + & (s1State_nElem[1] ? s2State_y_1_resp_valid : s1State_queue_0_resp_valid) + : s1State_queue_0_resp_valid; + wire _s2State_T_7_queue_1_txid = + s2Commit ? _GEN_3 & _s1State_T_queue_1_txid : s2State_y_1_txid; + wire _s2State_T_7_queue_1_resp_valid = + s2Commit ? _GEN_3 & _s1State_T_queue_1_resp_valid : s2State_y_1_resp_valid; + wire [1:0] _s2State_T_7_nElem = s2Commit ? _s2State_T_6_nElem : s1State_nElem; + wire s2State_queue_0_resp_valid = + s2Precondition & _s2State_T_7_queue_0_resp_valid; + wire [1:0] s2State_nElem = s2Precondition ? _s2State_T_7_nElem : 2'h0; + wire [1:0] s2State_nCancelled = + s2Precondition ? (s2Commit ? _s2State_T_6_nCancelled : s1State_nCancelled) : 2'h0; + wire _s3State_dontNeedTrim_T = s2State_nCancelled == 2'h0; + wire s3State_noOverflow = s2State_nElem != 2'h3; + wire s3State_nCancelledReasonable = s2State_nCancelled <= s2State_nElem; + wire s3Precondition = + s3State_noOverflow & s3State_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s3State_dontNeedTrim_T | s2State_queue_0_resp_valid); + wire _GEN_4 = + s3State_noOverflow & s3State_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s3State_dontNeedTrim_T | s2State_queue_0_resp_valid) & s2Precondition; + wire _s3State_T_3_queue_0_txid = _GEN_4 & _s2State_T_7_queue_0_txid; + wire _s3State_T_3_queue_0_resp_valid = _GEN_4 & _s2State_T_7_queue_0_resp_valid; + wire _s3State_T_3_queue_1_txid = _GEN_4 & _s2State_T_7_queue_1_txid; + wire _s3State_T_3_queue_1_resp_valid = _GEN_4 & _s2State_T_7_queue_1_resp_valid; + wire [1:0] _s3State_T_3_nElem = _GEN_4 ? _s2State_T_7_nElem : 2'h0; + wire [1:0] _s3State_T_3_nCancelled = _GEN_4 ? _s2State_T_7_nElem : 2'h0; + wire s3State_keepCancelled_0 = + (|_s3State_T_3_nCancelled) & _s3State_T_3_queue_0_resp_valid; + wire [1:0] s3State_offset = + s3State_keepCancelled_0 | _s3State_T_3_nCancelled[1] & _s3State_T_3_queue_1_resp_valid + ? {1'h0, ~s3State_keepCancelled_0} + : _s3State_T_3_nCancelled; + wire _s3State_T_5 = + _s3State_T_3_nElem != 2'h3 & _s3State_T_3_nCancelled <= _s3State_T_3_nElem + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22); + wire [1:0] _s3State_T_20 = _s3State_T_3_nElem - s3State_offset; + wire _GEN_5 = (|_s3State_T_20) & s3State_offset[0]; + wire _GEN_6 = ~(_s3State_T_20[1]) | s3State_offset[0] - 1'h1; + wire [1:0] _s3State_T_22_nElem = _s3State_T_5 ? _s3State_T_20 : 2'h0; + wire [1:0] _s3State_T_22_nCancelled = + _s3State_T_5 ? _s3State_T_3_nCancelled - s3State_offset : 2'h0; + wire _s3State_T_23_queue_0_txid = + io_flush + ? _s3State_T_5 & (_GEN_5 ? _s3State_T_3_queue_1_txid : _s3State_T_3_queue_0_txid) + : s2Precondition & _s2State_T_7_queue_0_txid; + wire _s3State_T_23_queue_1_resp_valid = + io_flush + ? _s3State_T_5 + & (_GEN_6 ? _s3State_T_3_queue_1_resp_valid : _s3State_T_3_queue_0_resp_valid) + : s2Precondition & _s2State_T_7_queue_1_resp_valid; + wire s3State_queue_0_resp_valid = + s3Precondition + & (io_flush + ? _s3State_T_5 + & (_GEN_5 ? _s3State_T_3_queue_1_resp_valid : _s3State_T_3_queue_0_resp_valid) + : s2State_queue_0_resp_valid); + wire s4State_y_1_resp_valid = s3Precondition & _s3State_T_23_queue_1_resp_valid; + wire [1:0] s3State_nElem = + s3Precondition ? (io_flush ? _s3State_T_22_nElem : s2State_nElem) : 2'h0; + wire [1:0] s3State_nCancelled = + s3Precondition ? (io_flush ? _s3State_T_22_nCancelled : s2State_nCancelled) : 2'h0; + wire s4Discard = + ~s1Reject & ~s2Commit & (|s3State_nElem) & (|s3State_nCancelled); + wire _s4State_precondition_dontNeedTrim_T = s3State_nCancelled == 2'h0; + wire s4Precondition_noOverflow = s3State_nElem != 2'h3; + wire s4Precondition_nCancelledReasonable = s3State_nCancelled <= s3State_nElem; + wire s4Precondition = + s4Precondition_noOverflow & s4Precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s4State_precondition_dontNeedTrim_T | s3State_queue_0_resp_valid) + & (~s4Discard | s3State_queue_0_resp_valid); + wire s4State_precondition = + s4Precondition_noOverflow & s4Precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s4State_precondition_dontNeedTrim_T | s3State_queue_0_resp_valid) + & (|s3State_nElem); + wire _s4State_T_6_queue_0_resp_valid = + s4State_precondition + & (s3State_nElem[1] ? s4State_y_1_resp_valid : s3State_queue_0_resp_valid); + wire _GEN_7 = s4State_precondition & s3Precondition; + wire _s4State_T_6_queue_1_resp_valid = + _GEN_7 & _s3State_T_23_queue_1_resp_valid; + wire [1:0] _s4State_T_6_nElem = s4State_precondition ? s3State_nElem - 2'h1 : 2'h0; + wire [1:0] _s4State_T_6_nCancelled = + s4State_precondition & (|s3State_nCancelled) ? s3State_nCancelled - 2'h1 : 2'h0; + wire s4State_keepCancelled_0 = + (|_s4State_T_6_nCancelled) & _s4State_T_6_queue_0_resp_valid; + wire [1:0] s4State_offset = + s4State_keepCancelled_0 | _s4State_T_6_nCancelled[1] & _s4State_T_6_queue_1_resp_valid + ? {1'h0, ~s4State_keepCancelled_0} + : _s4State_T_6_nCancelled; + wire _s4State_T_8 = + _s4State_T_6_nElem != 2'h3 & _s4State_T_6_nCancelled <= _s4State_T_6_nElem + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22); + wire [1:0] _s4State_T_23 = _s4State_T_6_nElem - s4State_offset; + wire [1:0] _s4State_T_25_nElem = _s4State_T_8 ? _s4State_T_23 : 2'h0; + wire [1:0] s4State_nElem = + s4Precondition ? (s4Discard ? _s4State_T_25_nElem : s3State_nElem) : 2'h0; + wire [31:0] s1State_queue_0_addr = _GEN_2 ? state_queue_0_addr : 32'h0; + wire [31:0] _GEN_8 = s1State_nElem[1] ? state_queue_1_addr : state_queue_0_addr; + wire _GEN_9 = s2State_precondition & _GEN_2; + wire [31:0] _s2State_T_7_queue_0_addr = + s2Commit ? (_GEN_9 ? _GEN_8 : 32'h0) : s1State_queue_0_addr; + wire _GEN_10 = s2Commit ? _GEN_3 & _GEN_1 : _GEN_2; + wire _GEN_11 = s2Precondition & _GEN_10; + wire [31:0] s2State_queue_1_addr = _GEN_11 ? state_queue_1_addr : 32'h0; + wire [31:0] _s3State_T_3_queue_0_addr = _GEN_4 ? _s2State_T_7_queue_0_addr : 32'h0; + wire _GEN_12 = _GEN_4 & _GEN_10; + wire [31:0] _s3State_T_3_queue_1_addr = _GEN_12 ? state_queue_1_addr : 32'h0; + wire [31:0] _GEN_13 = + s3State_nElem[1] + ? (io_flush + ? (_s3State_T_5 + ? (_GEN_6 ? _s3State_T_3_queue_1_addr : _s3State_T_3_queue_0_addr) + : 32'h0) + : s2State_queue_1_addr) + : io_flush + ? (_s3State_T_5 + ? (_GEN_5 ? _s3State_T_3_queue_1_addr : _s3State_T_3_queue_0_addr) + : 32'h0) + : s2Precondition ? _s2State_T_7_queue_0_addr : 32'h0; + wire [127:0] _s1State_T_queue_0_resp_bits_data = + io_busResp_valid + ? (precondition + ? (_GEN ? io_busResp_bits_resp_data : state_queue_0_resp_bits_data) + : 128'h0) + : state_queue_0_resp_bits_data; + wire [127:0] _s1State_T_queue_1_resp_bits_data = + io_busResp_valid + ? (precondition + ? (_GEN_0 ? io_busResp_bits_resp_data : state_queue_1_resp_bits_data) + : 128'h0) + : state_queue_1_resp_bits_data; + wire [127:0] s1State_queue_0_resp_bits_data = + s1Precondition ? _s1State_T_queue_0_resp_bits_data : 128'h0; + wire [127:0] _GEN_14 = + s1State_nElem[1] + ? _s1State_T_queue_1_resp_bits_data + : _s1State_T_queue_0_resp_bits_data; + wire _GEN_15 = s2State_precondition & s1Precondition; + wire _GEN_16 = (~s2Commit | s2State_precondition) & s1Precondition; + wire _GEN_17 = s2Precondition & _GEN_16; + wire _GEN_18 = _GEN_4 & _GEN_16; + wire [127:0] _s3State_T_3_queue_1_resp_bits_data = + _GEN_18 ? _s1State_T_queue_1_resp_bits_data : 128'h0; + wire [127:0] _s2State_T_7_queue_0_resp_bits_data = + s2Commit ? (_GEN_15 ? _GEN_14 : 128'h0) : s1State_queue_0_resp_bits_data; + wire [127:0] s2State_queue_1_resp_bits_data = + _GEN_17 ? _s1State_T_queue_1_resp_bits_data : 128'h0; + wire [127:0] _s3State_T_3_queue_0_resp_bits_data = + _GEN_4 ? _s2State_T_7_queue_0_resp_bits_data : 128'h0; + wire [127:0] _GEN_19 = + s3State_nElem[1] + ? (io_flush + ? (_s3State_T_5 + ? (_GEN_6 + ? _s3State_T_3_queue_1_resp_bits_data + : _s3State_T_3_queue_0_resp_bits_data) + : 128'h0) + : s2State_queue_1_resp_bits_data) + : io_flush + ? (_s3State_T_5 + ? (_GEN_5 + ? _s3State_T_3_queue_1_resp_bits_data + : _s3State_T_3_queue_0_resp_bits_data) + : 128'h0) + : s2Precondition ? _s2State_T_7_queue_0_resp_bits_data : 128'h0; + wire _s1State_T_queue_1_resp_bits_fault = + io_busResp_valid + ? precondition + & (_GEN_0 ? io_busResp_bits_resp_fault : state_queue_1_resp_bits_fault) + : state_queue_1_resp_bits_fault; + wire s1State_queue_0_resp_bits_fault = + s1Precondition + & (io_busResp_valid + ? precondition + & (_GEN ? io_busResp_bits_resp_fault : state_queue_0_resp_bits_fault) + : state_queue_0_resp_bits_fault); + wire s2State_y_1_resp_bits_fault = + s1Precondition & _s1State_T_queue_1_resp_bits_fault; + wire _s2State_T_7_queue_0_resp_bits_fault = + s2Commit + ? s2State_precondition + & (s1State_nElem[1] + ? s2State_y_1_resp_bits_fault + : s1State_queue_0_resp_bits_fault) + : s1State_queue_0_resp_bits_fault; + wire _s2State_T_7_queue_1_resp_bits_fault = + s2Commit ? _GEN_3 & _s1State_T_queue_1_resp_bits_fault : s2State_y_1_resp_bits_fault; + wire _s3State_T_3_queue_0_resp_bits_fault = + _GEN_4 & _s2State_T_7_queue_0_resp_bits_fault; + wire _s3State_T_3_queue_1_resp_bits_fault = + _GEN_4 & _s2State_T_7_queue_1_resp_bits_fault; + wire _s3State_T_23_queue_1_txid = + io_flush + ? _s3State_T_5 & (_GEN_6 ? _s3State_T_3_queue_1_txid : _s3State_T_3_queue_0_txid) + : s2Precondition & _s2State_T_7_queue_1_txid; + wire _s3State_T_23_queue_1_resp_bits_fault = + io_flush + ? _s3State_T_5 + & (_GEN_6 + ? _s3State_T_3_queue_1_resp_bits_fault + : _s3State_T_3_queue_0_resp_bits_fault) + : s2Precondition & _s2State_T_7_queue_1_resp_bits_fault; + wire s3State_queue_0_txid = s3Precondition & _s3State_T_23_queue_0_txid; + wire s3State_queue_0_resp_bits_fault = + s3Precondition + & (io_flush + ? _s3State_T_5 + & (_GEN_5 + ? _s3State_T_3_queue_1_resp_bits_fault + : _s3State_T_3_queue_0_resp_bits_fault) + : s2Precondition & _s2State_T_7_queue_0_resp_bits_fault); + wire s4State_y_1_txid = s3Precondition & _s3State_T_23_queue_1_txid; + wire s4State_y_1_resp_bits_fault = + s3Precondition & _s3State_T_23_queue_1_resp_bits_fault; + wire _s4State_T_6_queue_0_txid = + s4State_precondition & (s3State_nElem[1] ? s4State_y_1_txid : s3State_queue_0_txid); + wire _GEN_20 = s4State_precondition & s3Precondition; + wire _s4State_T_6_queue_0_resp_bits_fault = + s4State_precondition + & (s3State_nElem[1] ? s4State_y_1_resp_bits_fault : s3State_queue_0_resp_bits_fault); + wire _s4State_T_6_queue_1_txid = _GEN_7 & _s3State_T_23_queue_1_txid; + wire _s4State_T_6_queue_1_resp_bits_fault = + _GEN_7 & _s3State_T_23_queue_1_resp_bits_fault; + wire _GEN_21 = (|_s4State_T_23) & s4State_offset[0]; + wire _GEN_22 = ~(_s4State_T_23[1]) | s4State_offset[0] - 1'h1; + wire [1:0] _s4State_T_25_nCancelled = + _s4State_T_8 ? _s4State_T_6_nCancelled - s4State_offset : 2'h0; + wire _s4State_T_26_queue_0_resp_bits_fault = + s4Discard + ? _s4State_T_8 + & (_GEN_21 + ? _s4State_T_6_queue_1_resp_bits_fault + : _s4State_T_6_queue_0_resp_bits_fault) + : s3State_queue_0_resp_bits_fault; + wire _s4State_T_26_queue_1_resp_bits_fault = + s4Discard + ? _s4State_T_8 + & (_GEN_22 + ? _s4State_T_6_queue_1_resp_bits_fault + : _s4State_T_6_queue_0_resp_bits_fault) + : s4State_y_1_resp_bits_fault; + wire s4State_queue_0_txid = + s4Precondition + & (s4Discard + ? _s4State_T_8 + & (_GEN_21 ? _s4State_T_6_queue_1_txid : _s4State_T_6_queue_0_txid) + : s3State_queue_0_txid); + wire s4State_queue_0_resp_valid = + s4Precondition + & (s4Discard + ? _s4State_T_8 + & (_GEN_21 ? _s4State_T_6_queue_1_resp_valid : _s4State_T_6_queue_0_resp_valid) + : s3State_queue_0_resp_valid); + wire s4State_queue_1_txid = + s4Precondition + & (s4Discard + ? _s4State_T_8 + & (_GEN_22 ? _s4State_T_6_queue_1_txid : _s4State_T_6_queue_0_txid) + : s4State_y_1_txid); + wire [1:0] s4State_nCancelled = + s4Precondition ? (s4Discard ? _s4State_T_25_nCancelled : s3State_nCancelled) : 2'h0; + wire s5Fire = ~(s4State_nElem[1]) & io_newTx_valid; + wire _s5State_precondition_dontNeedTrim_T = s4State_nCancelled == 2'h0; + wire s5Precondition_noOverflow = s4State_nElem != 2'h3; + wire s5Precondition_nCancelledReasonable = s4State_nCancelled <= s4State_nElem; + wire s5Precondition = + s5Precondition_noOverflow & s5Precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s5State_precondition_dontNeedTrim_T | s4State_queue_0_resp_valid) + & (~s5Fire | ~(s4State_nElem[1])); + wire s5State_precondition = + s5Precondition_noOverflow & s5Precondition_nCancelledReasonable + & ~((|state_nElem) & state_nElem[1] & _noDuplicateTxid_T_22 | state_nElem[1] + & (|state_nElem) & _noDuplicateTxid_T_22) + & (_s5State_precondition_dontNeedTrim_T | s4State_queue_0_resp_valid) + & ~(s4State_nElem[1]); + wire _GEN_23 = s5State_precondition & s4Precondition; + always @(posedge clock or posedge reset) begin + if (reset) begin + state_queue_0_txid <= 1'h0; + state_queue_0_addr <= 32'h0; + state_queue_0_resp_valid <= 1'h0; + state_queue_0_resp_bits_data <= 128'h0; + state_queue_0_resp_bits_fault <= 1'h0; + state_queue_1_txid <= 1'h0; + state_queue_1_addr <= 32'h0; + state_queue_1_resp_valid <= 1'h0; + state_queue_1_resp_bits_data <= 128'h0; + state_queue_1_resp_bits_fault <= 1'h0; + state_nElem <= 2'h0; + state_nCancelled <= 2'h0; + end + else begin + state_queue_0_txid <= + s5Precondition + & (s5Fire + ? s5State_precondition + & (s4State_nElem[0] ? s4State_queue_0_txid : io_newTx_bits_txid) + : s4State_queue_0_txid); + if (s5Precondition) begin + if (s5Fire) begin + if (s5State_precondition) begin + if (s4State_nElem[0]) begin + if (s4Precondition) begin + if (s4Discard) begin + if (_s4State_T_8) begin + if (_GEN_21) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) + state_queue_0_addr <= _s3State_T_3_queue_1_addr; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_2) begin + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= s2State_queue_1_addr; + end + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_20) + state_queue_0_addr <= _GEN_13; + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else if (s3Precondition) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_5) + state_queue_0_addr <= _s3State_T_3_queue_1_addr; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_2) begin + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else if (s2Precondition) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_2) begin + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= io_newTx_bits_addr; + end + else begin + state_queue_0_addr <= io_newTx_bits_addr; + if (s4Precondition) begin + if (s4Discard) begin + if (_s4State_T_8) begin + if (_GEN_22) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) begin + if (_GEN_12) begin + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_1_addr <= _GEN_8; + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= s1State_queue_0_addr; + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_11) begin + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_20) + state_queue_1_addr <= _GEN_13; + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (s3Precondition) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) begin + if (_GEN_12) begin + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_1_addr <= _GEN_8; + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= s1State_queue_0_addr; + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_11) begin + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + end + state_nElem <= s5State_precondition ? s4State_nElem + 2'h1 : 2'h0; + end + else if (s4Precondition) begin + if (s4Discard) begin + if (_s4State_T_8) begin + if (_GEN_21) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) + state_queue_0_addr <= _s3State_T_3_queue_1_addr; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_2) begin + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= s2State_queue_1_addr; + end + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_20) + state_queue_0_addr <= _GEN_13; + else + state_queue_0_addr <= 32'h0; + if (_GEN_22) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) begin + if (_GEN_12) begin + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_1_addr <= _GEN_8; + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= s1State_queue_0_addr; + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_11) begin + end + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_20) + state_queue_1_addr <= _GEN_13; + else + state_queue_1_addr <= 32'h0; + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + end + state_nElem <= _s4State_T_25_nElem; + end + else if (s3Precondition) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_5) + state_queue_0_addr <= _s3State_T_3_queue_1_addr; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + end + else if (_GEN_2) begin + end + else + state_queue_0_addr <= 32'h0; + end + else + state_queue_0_addr <= 32'h0; + if (_GEN_6) begin + if (_GEN_12) begin + end + else + state_queue_1_addr <= 32'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_1_addr <= _GEN_8; + else + state_queue_1_addr <= 32'h0; + end + else + state_queue_1_addr <= s1State_queue_0_addr; + end + else + state_queue_1_addr <= 32'h0; + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + end + state_nElem <= _s3State_T_22_nElem; + end + else begin + if (s2Precondition) begin + if (s2Commit) begin + if (_GEN_9) + state_queue_0_addr <= _GEN_8; + else + state_queue_0_addr <= 32'h0; + state_nElem <= _s2State_T_6_nElem; + end + else if (_GEN_2) begin + end + else begin + state_queue_0_addr <= 32'h0; + state_nElem <= 2'h0; + end + end + else begin + state_queue_0_addr <= 32'h0; + state_nElem <= 2'h0; + end + if (_GEN_11) begin + end + else + state_queue_1_addr <= 32'h0; + end + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + state_nElem <= 2'h0; + end + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + state_nElem <= 2'h0; + end + end + else begin + state_queue_0_addr <= 32'h0; + state_queue_1_addr <= 32'h0; + state_nElem <= 2'h0; + end + state_queue_0_resp_valid <= + s5Precondition & (~s5Fire | s5State_precondition & s4State_nElem[0]) + & s4State_queue_0_resp_valid; + if (s5Precondition & (~s5Fire | s5State_precondition) & s4Precondition) begin + if (s4Discard) begin + if (_s4State_T_8) begin + if (_GEN_21) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) + state_queue_0_resp_bits_data <= _s3State_T_3_queue_1_resp_bits_data; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_15) + state_queue_0_resp_bits_data <= _GEN_14; + else + state_queue_0_resp_bits_data <= 128'h0; + end + else if (s1Precondition) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN) + state_queue_0_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + else + state_queue_0_resp_bits_data <= s2State_queue_1_resp_bits_data; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + else if (_GEN_20) + state_queue_0_resp_bits_data <= _GEN_19; + else + state_queue_0_resp_bits_data <= 128'h0; + if (_GEN_22) begin + if (_GEN_7) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_6) begin + if (_GEN_18) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN_0) + state_queue_1_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_15) + state_queue_1_resp_bits_data <= _GEN_14; + else + state_queue_1_resp_bits_data <= 128'h0; + end + else + state_queue_1_resp_bits_data <= s1State_queue_0_resp_bits_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else if (_GEN_17) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN_0) + state_queue_1_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else if (_GEN_20) + state_queue_1_resp_bits_data <= _GEN_19; + else + state_queue_1_resp_bits_data <= 128'h0; + end + else begin + state_queue_0_resp_bits_data <= 128'h0; + state_queue_1_resp_bits_data <= 128'h0; + end + state_nCancelled <= _s4State_T_25_nCancelled; + end + else if (s3Precondition) begin + if (io_flush) begin + if (_s3State_T_5) begin + if (_GEN_5) + state_queue_0_resp_bits_data <= _s3State_T_3_queue_1_resp_bits_data; + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_15) + state_queue_0_resp_bits_data <= _GEN_14; + else + state_queue_0_resp_bits_data <= 128'h0; + end + else if (s1Precondition) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN) + state_queue_0_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + else + state_queue_0_resp_bits_data <= 128'h0; + if (_GEN_6) begin + if (_GEN_18) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN_0) + state_queue_1_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else if (_GEN_4) begin + if (s2Commit) begin + if (_GEN_15) + state_queue_1_resp_bits_data <= _GEN_14; + else + state_queue_1_resp_bits_data <= 128'h0; + end + else + state_queue_1_resp_bits_data <= s1State_queue_0_resp_bits_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + else begin + state_queue_0_resp_bits_data <= 128'h0; + state_queue_1_resp_bits_data <= 128'h0; + end + state_nCancelled <= _s3State_T_22_nCancelled; + end + else begin + if (s2Precondition) begin + if (s2Commit) begin + if (_GEN_15) + state_queue_0_resp_bits_data <= _GEN_14; + else + state_queue_0_resp_bits_data <= 128'h0; + state_nCancelled <= _s2State_T_6_nCancelled; + end + else begin + if (s1Precondition) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN) + state_queue_0_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_0_resp_bits_data <= 128'h0; + end + end + else + state_queue_0_resp_bits_data <= 128'h0; + if (_GEN_2) begin + end + else + state_nCancelled <= 2'h0; + end + end + else begin + state_queue_0_resp_bits_data <= 128'h0; + state_nCancelled <= 2'h0; + end + if (_GEN_17) begin + if (io_busResp_valid) begin + if (precondition) begin + if (_GEN_0) + state_queue_1_resp_bits_data <= io_busResp_bits_resp_data; + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + end + else + state_queue_1_resp_bits_data <= 128'h0; + end + end + else begin + state_queue_0_resp_bits_data <= 128'h0; + state_queue_1_resp_bits_data <= 128'h0; + state_nCancelled <= 2'h0; + end + end + else begin + state_queue_0_resp_bits_data <= 128'h0; + state_queue_1_resp_bits_data <= 128'h0; + state_nCancelled <= 2'h0; + end + state_queue_0_resp_bits_fault <= + s5Precondition + & (s5Fire + ? _GEN_23 & _s4State_T_26_queue_0_resp_bits_fault + : s4Precondition & _s4State_T_26_queue_0_resp_bits_fault); + state_queue_1_txid <= + s5Precondition + & (s5Fire + ? s5State_precondition + & (s4State_nElem[0] ? io_newTx_bits_txid : s4State_queue_1_txid) + : s4State_queue_1_txid); + state_queue_1_resp_valid <= + s5Precondition & (~s5Fire | s5State_precondition & ~(s4State_nElem[0])) + & s4Precondition + & (s4Discard + ? _s4State_T_8 + & (_GEN_22 + ? _s4State_T_6_queue_1_resp_valid + : _s4State_T_6_queue_0_resp_valid) + : s4State_y_1_resp_valid); + state_queue_1_resp_bits_fault <= + s5Precondition + & (s5Fire + ? _GEN_23 & _s4State_T_26_queue_1_resp_bits_fault + : s4Precondition & _s4State_T_26_queue_1_resp_bits_fault); + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + state_queue_0_txid = 1'h0; + state_queue_0_addr = 32'h0; + state_queue_0_resp_valid = 1'h0; + state_queue_0_resp_bits_data = 128'h0; + state_queue_0_resp_bits_fault = 1'h0; + state_queue_1_txid = 1'h0; + state_queue_1_addr = 32'h0; + state_queue_1_resp_valid = 1'h0; + state_queue_1_resp_bits_data = 128'h0; + state_queue_1_resp_bits_fault = 1'h0; + state_nElem = 2'h0; + state_nCancelled = 2'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_newTx_ready = ~(s4State_nElem[1]); + assign io_commit_valid = s2Valid; + assign io_commit_bits_addr = state_queue_0_addr; + assign io_commit_bits_resp_data = state_queue_0_resp_bits_data; + assign io_commit_bits_resp_fault = state_queue_0_resp_bits_fault; + assign io_freeTxid_valid = s1Reject | s2Commit | s4Discard; + assign io_freeTxid_bits = + s1Reject & io_busResp_bits_txid | s2Commit & state_queue_0_txid | s4Discard + & s3Precondition & _s3State_T_23_queue_0_txid; +endmodule + +module Fetcher( + input clock, + reset, + output io_ctrl_ready, + input io_ctrl_valid, + input [31:0] io_ctrl_bits, + input io_flushTx, + io_fetch_ready, + output io_fetch_valid, + output [31:0] io_fetch_bits_addr, + io_fetch_bits_inst_0, + io_fetch_bits_inst_1, + io_fetch_bits_inst_2, + io_fetch_bits_inst_3, + output io_fetch_bits_fault, + io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + input io_ibus_fault_valid +); + + wire _reorderBuffer_io_newTx_ready; + wire [127:0] _reorderBuffer_io_commit_bits_resp_data; + wire _reorderBuffer_io_freeTxid_valid; + wire _reorderBuffer_io_freeTxid_bits; + wire _txidAllocator_io_alloc_valid; + wire _txidAllocator_io_alloc_bits; + wire canStartFetch = + io_ctrl_valid & _reorderBuffer_io_newTx_ready & _txidAllocator_io_alloc_valid; + wire ibusAddrFire = canStartFetch & io_ibus_ready; + reg reorderBuffer_io_busResp_valid_REG; + reg reorderBuffer_io_busResp_bits_txid_REG; + reg reorderBuffer_io_busResp_bits_resp_fault_REG; always @(posedge clock or posedge reset) begin if (reset) - pc <= 32'h0; - else if (_instructionBuffer_io_out_0_valid) - pc <= _instructionBuffer_io_out_0_bits_addr; + reorderBuffer_io_busResp_valid_REG <= 1'h0; + else + reorderBuffer_io_busResp_valid_REG <= ibusAddrFire; end // always @(posedge, posedge) + always @(posedge clock) begin + reorderBuffer_io_busResp_bits_txid_REG <= _txidAllocator_io_alloc_bits; + reorderBuffer_io_busResp_bits_resp_fault_REG <= io_ibus_fault_valid; + end // always @(posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - pc = _RANDOM[/*Zero width*/ 1'b0]; - `endif // RANDOMIZE_REG_INIT if (reset) - pc = 32'h0; + reorderBuffer_io_busResp_valid_REG = 1'h0; end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FetchControl ctrl ( - .clock (clock), - .reset (reset), - .io_csr_value_0 (io_csr_value_0), - .io_iflush_valid (io_iflush_valid), - .io_iflush_bits (io_iflush_pcNext), - .io_branch_valid (branch_valid), - .io_branch_bits - (io_branch_0_valid - ? io_branch_0_value - : io_branch_1_valid - ? io_branch_1_value - : io_branch_2_valid - ? io_branch_2_value - : io_branch_3_valid ? io_branch_3_value : 32'h0), - .io_fetchData_valid (_fetcher_io_fetch_valid), - .io_fetchData_bits_addr (_fetcher_io_fetch_bits_addr), - .io_fetchData_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), - .io_fetchData_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), - .io_fetchData_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), - .io_fetchData_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), - .io_fetchAddr_valid (_ctrl_io_fetchAddr_valid), - .io_fetchAddr_bits (_ctrl_io_fetchAddr_bits), - .io_bufferRequest_nValid (_ctrl_io_bufferRequest_nValid), - .io_bufferRequest_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), - .io_bufferRequest_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), - .io_bufferRequest_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), - .io_bufferRequest_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), - .io_bufferRequest_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), - .io_bufferRequest_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), - .io_bufferRequest_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), - .io_bufferRequest_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), - .io_bufferRequest_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), - .io_bufferRequest_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), - .io_bufferRequest_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), - .io_bufferRequest_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd), - .io_bufferSpaces (_instructionBuffer_io_nSpace) - ); - Fetcher fetcher ( - .clock (clock), - .reset (reset), - .io_ctrl_valid (_ctrl_io_fetchAddr_valid), - .io_ctrl_bits (_ctrl_io_fetchAddr_bits), - .io_fetch_valid (_fetcher_io_fetch_valid), - .io_fetch_bits_addr (_fetcher_io_fetch_bits_addr), - .io_fetch_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), - .io_fetch_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), - .io_fetch_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), - .io_fetch_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), - .io_ibus_valid (io_ibus_valid), - .io_ibus_ready (io_ibus_ready), - .io_ibus_addr (io_ibus_addr), - .io_ibus_rdata (io_ibus_rdata) + IndexAllocatorShifting txidAllocator ( + .clock (clock), + .reset (reset), + .io_alloc_ready (ibusAddrFire), + .io_alloc_valid (_txidAllocator_io_alloc_valid), + .io_alloc_bits (_txidAllocator_io_alloc_bits), + .io_free_valid (_reorderBuffer_io_freeTxid_valid), + .io_free_bits (_reorderBuffer_io_freeTxid_bits) ); - InstructionBuffer instructionBuffer ( - .clock (clock), - .reset (reset), - .io_feedIn_nReady (/* unused */), - .io_feedIn_nValid (_ctrl_io_bufferRequest_nValid), - .io_feedIn_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), - .io_feedIn_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), - .io_feedIn_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), - .io_feedIn_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), - .io_feedIn_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), - .io_feedIn_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), - .io_feedIn_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), - .io_feedIn_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), - .io_feedIn_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), - .io_feedIn_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), - .io_feedIn_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), - .io_feedIn_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd), - .io_out_0_ready (io_inst_lanes_0_ready), - .io_out_0_valid (_instructionBuffer_io_out_0_valid), - .io_out_0_bits_addr (_instructionBuffer_io_out_0_bits_addr), - .io_out_0_bits_inst (io_inst_lanes_0_bits_inst), - .io_out_0_bits_brchFwd (io_inst_lanes_0_bits_brchFwd), - .io_out_1_ready (io_inst_lanes_1_ready), - .io_out_1_valid (io_inst_lanes_1_valid), - .io_out_1_bits_addr (io_inst_lanes_1_bits_addr), - .io_out_1_bits_inst (io_inst_lanes_1_bits_inst), - .io_out_1_bits_brchFwd (io_inst_lanes_1_bits_brchFwd), - .io_out_2_ready (io_inst_lanes_2_ready), - .io_out_2_valid (io_inst_lanes_2_valid), - .io_out_2_bits_addr (io_inst_lanes_2_bits_addr), - .io_out_2_bits_inst (io_inst_lanes_2_bits_inst), - .io_out_2_bits_brchFwd (io_inst_lanes_2_bits_brchFwd), - .io_out_3_ready (io_inst_lanes_3_ready), - .io_out_3_valid (io_inst_lanes_3_valid), - .io_out_3_bits_addr (io_inst_lanes_3_bits_addr), - .io_out_3_bits_inst (io_inst_lanes_3_bits_inst), - .io_out_3_bits_brchFwd (io_inst_lanes_3_bits_brchFwd), - .io_flush (io_iflush_valid | branch_valid), - .io_nEnqueued (/* unused */), - .io_nSpace (_instructionBuffer_io_nSpace) + FetchReorderBuffer reorderBuffer ( + .clock (clock), + .reset (reset), + .io_newTx_ready (_reorderBuffer_io_newTx_ready), + .io_newTx_valid (ibusAddrFire), + .io_newTx_bits_txid (_txidAllocator_io_alloc_bits), + .io_newTx_bits_addr (io_ctrl_bits), + .io_busResp_valid (reorderBuffer_io_busResp_valid_REG), + .io_busResp_bits_txid (reorderBuffer_io_busResp_bits_txid_REG), + .io_busResp_bits_resp_data (io_ibus_rdata), + .io_busResp_bits_resp_fault (reorderBuffer_io_busResp_bits_resp_fault_REG), + .io_commit_ready (io_fetch_ready), + .io_commit_valid (io_fetch_valid), + .io_commit_bits_addr (io_fetch_bits_addr), + .io_commit_bits_resp_data (_reorderBuffer_io_commit_bits_resp_data), + .io_commit_bits_resp_fault (io_fetch_bits_fault), + .io_freeTxid_valid (_reorderBuffer_io_freeTxid_valid), + .io_freeTxid_bits (_reorderBuffer_io_freeTxid_bits), + .io_flush (io_flushTx) ); - assign io_inst_lanes_0_valid = _instructionBuffer_io_out_0_valid; - assign io_inst_lanes_0_bits_addr = _instructionBuffer_io_out_0_bits_addr; - assign io_pc = pc; + assign io_ctrl_ready = ibusAddrFire; + assign io_fetch_bits_inst_0 = _reorderBuffer_io_commit_bits_resp_data[31:0]; + assign io_fetch_bits_inst_1 = _reorderBuffer_io_commit_bits_resp_data[63:32]; + assign io_fetch_bits_inst_2 = _reorderBuffer_io_commit_bits_resp_data[95:64]; + assign io_fetch_bits_inst_3 = _reorderBuffer_io_commit_bits_resp_data[127:96]; + assign io_ibus_valid = canStartFetch; + assign io_ibus_addr = {io_ctrl_bits[31:4], 4'h0}; endmodule -module Csr( +module CircularBufferMulti( input clock, reset, - input [31:0] io_csr_in_value_12, - output [31:0] io_csr_out_value_0, - io_csr_out_value_1, - io_csr_out_value_2, - io_csr_out_value_3, - io_csr_out_value_4, - io_csr_out_value_5, - io_csr_out_value_6, - io_csr_out_value_7, - input io_req_valid, - input [4:0] io_req_bits_addr, - input [11:0] io_req_bits_index, - input [1:0] io_req_bits_op, - input io_rs1_valid, - input [31:0] io_rs1_data, - output io_rd_valid, - output [4:0] io_rd_bits_addr, - output [31:0] io_rd_bits_data, - input io_bru_in_mode_valid, - input [1:0] io_bru_in_mode_bits, - input io_bru_in_mcause_valid, - input [31:0] io_bru_in_mcause_bits, - input io_bru_in_mepc_valid, - input [31:0] io_bru_in_mepc_bits, - input io_bru_in_mtval_valid, - input [31:0] io_bru_in_mtval_bits, - input io_bru_in_halt, - io_bru_in_fault, - io_bru_in_wfi, - output [1:0] io_bru_out_mode, - output [31:0] io_bru_out_mepc, - io_bru_out_mtvec, - input io_float_in_fflags_valid, - input [4:0] io_float_in_fflags_bits, - output [2:0] io_float_out_frm, - input [2:0] io_counters_rfwriteCount, - input [1:0] io_counters_storeCount, - input io_counters_branchCount, - output io_halted, - io_fault, - io_wfi, - input io_irq + input [2:0] io_enqValid, + input [31:0] io_enqData_0_addr, + io_enqData_0_inst, + input io_enqData_0_brchFwd, + input [31:0] io_enqData_1_addr, + io_enqData_1_inst, + input io_enqData_1_brchFwd, + input [31:0] io_enqData_2_addr, + io_enqData_2_inst, + input io_enqData_2_brchFwd, + input [31:0] io_enqData_3_addr, + io_enqData_3_inst, + input io_enqData_3_brchFwd, + output [3:0] io_nEnqueued, + io_nSpace, + output [31:0] io_dataOut_0_addr, + io_dataOut_0_inst, + output io_dataOut_0_brchFwd, + output [31:0] io_dataOut_1_addr, + io_dataOut_1_inst, + output io_dataOut_1_brchFwd, + output [31:0] io_dataOut_2_addr, + io_dataOut_2_inst, + output io_dataOut_2_brchFwd, + output [31:0] io_dataOut_3_addr, + io_dataOut_3_inst, + output io_dataOut_3_brchFwd, + input [2:0] io_deqReady, + input io_flush ); - reg req_pipe_v; - reg [4:0] req_pipe_b_addr; - reg [11:0] req_pipe_b_index; - reg [1:0] req_pipe_b_op; - reg halted; - reg fault; - reg wfi; - reg [1:0] mode; - reg [31:0] mpc; - reg [31:0] msp; - reg [31:0] mcause; - reg [31:0] mtval; - reg [31:0] mcontext0; - reg [31:0] mcontext1; - reg [31:0] mcontext2; - reg [31:0] mcontext3; - reg [31:0] mcontext4; - reg [31:0] mcontext5; - reg [31:0] mcontext6; - reg [31:0] mcontext7; - reg [4:0] fflags; - reg [2:0] frm; - reg mie; - reg [31:0] mtvec; - reg [31:0] mscratch; - reg [31:0] mepc; - reg [1:0] mpp; - reg [63:0] mcycle; - reg [63:0] minstret; - wire fflagsEn = req_pipe_b_index == 12'h1; - wire frmEn = req_pipe_b_index == 12'h2; - wire fcsrEn = req_pipe_b_index == 12'h3; - wire mstatusEn = req_pipe_b_index == 12'h300; - wire misaEn = req_pipe_b_index == 12'h301; - wire mieEn = req_pipe_b_index == 12'h304; - wire mtvecEn = req_pipe_b_index == 12'h305; - wire mscratchEn = req_pipe_b_index == 12'h340; - wire mepcEn = req_pipe_b_index == 12'h341; - wire mcauseEn = req_pipe_b_index == 12'h342; - wire mtvalEn = req_pipe_b_index == 12'h343; - wire mcontext0En = req_pipe_b_index == 12'h7C0; - wire mcontext1En = req_pipe_b_index == 12'h7C1; - wire mcontext2En = req_pipe_b_index == 12'h7C2; - wire mcontext3En = req_pipe_b_index == 12'h7C3; - wire mcontext4En = req_pipe_b_index == 12'h7C4; - wire mcontext5En = req_pipe_b_index == 12'h7C5; - wire mcontext6En = req_pipe_b_index == 12'h7C6; - wire mcontext7En = req_pipe_b_index == 12'h7C7; - wire mpcEn = req_pipe_b_index == 12'h7E0; - wire mspEn = req_pipe_b_index == 12'h7E1; - wire mcycleEn = req_pipe_b_index == 12'hB00; - wire minstretEn = req_pipe_b_index == 12'hB02; - wire mcyclehEn = req_pipe_b_index == 12'hB80; - wire minstrethEn = req_pipe_b_index == 12'hB82; - wire mvendoridEn = req_pipe_b_index == 12'hF11; - wire marchidEn = req_pipe_b_index == 12'hF12; - wire mimpidEn = req_pipe_b_index == 12'hF13; - wire mhartidEn = req_pipe_b_index == 12'hF14; - wire kisaEn = req_pipe_b_index == 12'hFC0; - wire kscm0En = req_pipe_b_index == 12'hFC4; - wire kscm1En = req_pipe_b_index == 12'hFC8; - wire kscm2En = req_pipe_b_index == 12'hFCC; - wire kscm3En = req_pipe_b_index == 12'hFD0; - wire kscm4En = req_pipe_b_index == 12'hFD4; - wire [31:0] rdata = - fflagsEn - ? {27'h0, fflags} - : frmEn - ? {29'h0, frm} - : fcsrEn - ? {24'h0, frm, fflags} - : mstatusEn - ? {19'h0, mpp, 11'h0} - : misaEn - ? 32'h40001120 - : mieEn - ? {31'h0, mie} - : mtvecEn - ? mtvec - : mscratchEn - ? mscratch - : mepcEn - ? mepc - : mcauseEn - ? mcause - : mtvalEn - ? mtval - : mcontext0En - ? mcontext0 - : mcontext1En - ? mcontext1 - : mcontext2En - ? mcontext2 - : mcontext3En - ? mcontext3 - : mcontext4En - ? mcontext4 - : mcontext5En - ? mcontext5 - : mcontext6En - ? mcontext6 - : mcontext7En - ? mcontext7 - : mpcEn - ? mpc - : mspEn - ? msp - : mcycleEn - ? mcycle[31:0] - : mcyclehEn - ? mcycle[63:32] - : minstretEn - ? minstret[31:0] - : minstrethEn - ? minstret[63:32] - : mvendoridEn - ? 32'h426 - : marchidEn - | mimpidEn - | mhartidEn - | kisaEn - ? 32'h0 - : kscm0En - ? 32'hE25C2997 - : kscm1En - ? 32'hA8C4C694 - : kscm2En - ? 32'hF9845884 - : kscm3En - ? 32'h8522A4D6 - : kscm4En - ? 32'hF3300946 - : 32'h0; - wire [3:0][31:0] _GEN = - {{32'h0}, {rdata & ~io_rs1_data}, {rdata | io_rs1_data}, {io_rs1_data}}; - wire [31:0] wdata = _GEN[req_pipe_b_op]; - wire [2:0] _minstretThisCycle_T_2 = - io_counters_rfwriteCount + {1'h0, io_counters_storeCount} - + {2'h0, io_counters_branchCount}; + reg [31:0] buffer_0_addr; + reg [31:0] buffer_0_inst; + reg buffer_0_brchFwd; + reg [31:0] buffer_1_addr; + reg [31:0] buffer_1_inst; + reg buffer_1_brchFwd; + reg [31:0] buffer_2_addr; + reg [31:0] buffer_2_inst; + reg buffer_2_brchFwd; + reg [31:0] buffer_3_addr; + reg [31:0] buffer_3_inst; + reg buffer_3_brchFwd; + reg [31:0] buffer_4_addr; + reg [31:0] buffer_4_inst; + reg buffer_4_brchFwd; + reg [31:0] buffer_5_addr; + reg [31:0] buffer_5_inst; + reg buffer_5_brchFwd; + reg [31:0] buffer_6_addr; + reg [31:0] buffer_6_inst; + reg buffer_6_brchFwd; + reg [31:0] buffer_7_addr; + reg [31:0] buffer_7_inst; + reg buffer_7_brchFwd; + reg [2:0] enqPtr; + reg [2:0] deqPtr; + reg [3:0] nEnqueued; + wire [31:0] _shifted_T_7_addr = deqPtr[2] ? buffer_6_addr : buffer_2_addr; + wire [31:0] _shifted_T_7_inst = deqPtr[2] ? buffer_6_inst : buffer_2_inst; + wire _shifted_T_7_brchFwd = deqPtr[2] ? buffer_6_brchFwd : buffer_2_brchFwd; + wire [31:0] _shifted_T_10_addr = deqPtr[2] ? buffer_7_addr : buffer_3_addr; + wire [31:0] _shifted_T_10_inst = deqPtr[2] ? buffer_7_inst : buffer_3_inst; + wire _shifted_T_10_brchFwd = deqPtr[2] ? buffer_7_brchFwd : buffer_3_brchFwd; + wire [31:0] _shifted_WIRE_1_addr = + deqPtr[1] ? _shifted_T_10_addr : deqPtr[2] ? buffer_5_addr : buffer_1_addr; + wire [31:0] _shifted_WIRE_1_inst = + deqPtr[1] ? _shifted_T_10_inst : deqPtr[2] ? buffer_5_inst : buffer_1_inst; + wire _shifted_WIRE_1_brchFwd = + deqPtr[1] ? _shifted_T_10_brchFwd : deqPtr[2] ? buffer_5_brchFwd : buffer_1_brchFwd; + wire [31:0] _shifted_T_13_addr = deqPtr[2] ? buffer_0_addr : buffer_4_addr; + wire [31:0] _shifted_T_13_inst = deqPtr[2] ? buffer_0_inst : buffer_4_inst; + wire _shifted_T_13_brchFwd = deqPtr[2] ? buffer_0_brchFwd : buffer_4_brchFwd; + wire [31:0] _shifted_WIRE_2_addr = deqPtr[1] ? _shifted_T_13_addr : _shifted_T_7_addr; + wire [31:0] _shifted_WIRE_2_inst = deqPtr[1] ? _shifted_T_13_inst : _shifted_T_7_inst; + wire _shifted_WIRE_2_brchFwd = + deqPtr[1] ? _shifted_T_13_brchFwd : _shifted_T_7_brchFwd; + wire [31:0] _shifted_WIRE_3_addr = + deqPtr[1] ? (deqPtr[2] ? buffer_1_addr : buffer_5_addr) : _shifted_T_10_addr; + wire [31:0] _shifted_WIRE_3_inst = + deqPtr[1] ? (deqPtr[2] ? buffer_1_inst : buffer_5_inst) : _shifted_T_10_inst; + wire _shifted_WIRE_3_brchFwd = + deqPtr[1] ? (deqPtr[2] ? buffer_1_brchFwd : buffer_5_brchFwd) : _shifted_T_10_brchFwd; + wire matches_isTargetSlot = enqPtr == 3'h0; + wire matches_0 = (|io_enqValid) & matches_isTargetSlot; + wire matches_1 = (|(io_enqValid[2:1])) & (&enqPtr); + wire matches_isTargetSlot_2 = enqPtr == 3'h6; + wire _matches_T_60 = io_enqValid > 3'h2; + wire matches_2 = _matches_T_60 & matches_isTargetSlot_2; + wire matches_isTargetSlot_3 = enqPtr == 3'h5; + wire matches_3 = io_enqValid[2] & matches_isTargetSlot_3; + wire matches_isTargetSlot_4 = enqPtr == 3'h1; + wire matches_1_0 = (|io_enqValid) & matches_isTargetSlot_4; + wire matches_1_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot; + wire matches_1_2 = _matches_T_60 & (&enqPtr); + wire matches_1_3 = io_enqValid[2] & matches_isTargetSlot_2; + wire matches_isTargetSlot_8 = enqPtr == 3'h2; + wire matches_2_0 = (|io_enqValid) & matches_isTargetSlot_8; + wire matches_2_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_4; + wire matches_2_2 = _matches_T_60 & matches_isTargetSlot; + wire matches_2_3 = io_enqValid[2] & (&enqPtr); + wire matches_isTargetSlot_12 = enqPtr == 3'h3; + wire matches_3_0 = (|io_enqValid) & matches_isTargetSlot_12; + wire matches_3_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_8; + wire matches_3_2 = _matches_T_60 & matches_isTargetSlot_4; + wire matches_3_3 = io_enqValid[2] & matches_isTargetSlot; + wire matches_isTargetSlot_16 = enqPtr == 3'h4; + wire matches_4_0 = (|io_enqValid) & matches_isTargetSlot_16; + wire matches_4_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_12; + wire matches_4_2 = _matches_T_60 & matches_isTargetSlot_8; + wire matches_4_3 = io_enqValid[2] & matches_isTargetSlot_4; + wire matches_5_0 = (|io_enqValid) & matches_isTargetSlot_3; + wire matches_5_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_16; + wire matches_5_2 = _matches_T_60 & matches_isTargetSlot_12; + wire matches_5_3 = io_enqValid[2] & matches_isTargetSlot_8; + wire matches_6_0 = (|io_enqValid) & matches_isTargetSlot_2; + wire matches_6_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_3; + wire matches_6_2 = _matches_T_60 & matches_isTargetSlot_16; + wire matches_6_3 = io_enqValid[2] & matches_isTargetSlot_12; + wire matches_7_0 = (|io_enqValid) & (&enqPtr); + wire matches_7_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_2; + wire matches_7_2 = _matches_T_60 & matches_isTargetSlot_3; + wire matches_7_3 = io_enqValid[2] & matches_isTargetSlot_16; always @(posedge clock or posedge reset) begin if (reset) begin - req_pipe_v <= 1'h0; - halted <= 1'h0; - fault <= 1'h0; - wfi <= 1'h0; - mode <= 2'h0; - mpc <= 32'h0; - msp <= 32'h0; - mcause <= 32'h0; - mtval <= 32'h0; - mcontext0 <= 32'h0; - mcontext1 <= 32'h0; - mcontext2 <= 32'h0; - mcontext3 <= 32'h0; - mcontext4 <= 32'h0; - mcontext5 <= 32'h0; - mcontext6 <= 32'h0; - mcontext7 <= 32'h0; - fflags <= 5'h0; - frm <= 3'h0; - mie <= 1'h0; - mtvec <= 32'h0; - mscratch <= 32'h0; - mepc <= 32'h0; - mpp <= 2'h0; - mcycle <= 64'h0; - minstret <= 64'h0; - end - else begin - req_pipe_v <= io_req_valid; - halted <= io_bru_in_halt | halted; - fault <= io_bru_in_fault | fault; - if (wfi) - wfi <= ~io_irq; - else - wfi <= io_bru_in_wfi; - if (io_bru_in_mode_valid) - mode <= io_bru_in_mode_bits; - if (req_pipe_v & mpcEn) - mpc <= wdata; - if (req_pipe_v & mspEn) - msp <= wdata; - if (io_bru_in_mcause_valid) - mcause <= io_bru_in_mcause_bits; - else if (req_pipe_v & mcauseEn) - mcause <= wdata; - if (io_bru_in_mtval_valid) - mtval <= io_bru_in_mtval_bits; - else if (req_pipe_v & mtvalEn) - mtval <= wdata; - if (req_pipe_v & mcontext0En) - mcontext0 <= wdata; - if (req_pipe_v & mcontext1En) - mcontext1 <= wdata; - if (req_pipe_v & mcontext2En) - mcontext2 <= wdata; - if (req_pipe_v & mcontext3En) - mcontext3 <= wdata; - if (req_pipe_v & mcontext4En) - mcontext4 <= wdata; - if (req_pipe_v & mcontext5En) - mcontext5 <= wdata; - if (req_pipe_v & mcontext6En) - mcontext6 <= wdata; - if (req_pipe_v & mcontext7En) - mcontext7 <= wdata; - if (io_float_in_fflags_valid) - fflags <= io_float_in_fflags_bits | fflags; - else if (req_pipe_v) begin - if (fcsrEn) - fflags <= wdata[4:0]; - else if (fflagsEn) - fflags <= wdata[4:0]; + buffer_0_addr <= 32'h0; + buffer_0_inst <= 32'h0; + buffer_0_brchFwd <= 1'h0; + buffer_1_addr <= 32'h0; + buffer_1_inst <= 32'h0; + buffer_1_brchFwd <= 1'h0; + buffer_2_addr <= 32'h0; + buffer_2_inst <= 32'h0; + buffer_2_brchFwd <= 1'h0; + buffer_3_addr <= 32'h0; + buffer_3_inst <= 32'h0; + buffer_3_brchFwd <= 1'h0; + buffer_4_addr <= 32'h0; + buffer_4_inst <= 32'h0; + buffer_4_brchFwd <= 1'h0; + buffer_5_addr <= 32'h0; + buffer_5_inst <= 32'h0; + buffer_5_brchFwd <= 1'h0; + buffer_6_addr <= 32'h0; + buffer_6_inst <= 32'h0; + buffer_6_brchFwd <= 1'h0; + buffer_7_addr <= 32'h0; + buffer_7_inst <= 32'h0; + buffer_7_brchFwd <= 1'h0; + enqPtr <= 3'h0; + deqPtr <= 3'h0; + nEnqueued <= 4'h0; + end + else begin + if (|{matches_3, matches_2, matches_1, matches_0}) begin + buffer_0_addr <= + (matches_0 ? io_enqData_0_addr : 32'h0) + | (matches_1 ? io_enqData_1_addr : 32'h0) + | (matches_2 ? io_enqData_2_addr : 32'h0) + | (matches_3 ? io_enqData_3_addr : 32'h0); + buffer_0_inst <= + (matches_0 ? io_enqData_0_inst : 32'h0) + | (matches_1 ? io_enqData_1_inst : 32'h0) + | (matches_2 ? io_enqData_2_inst : 32'h0) + | (matches_3 ? io_enqData_3_inst : 32'h0); + buffer_0_brchFwd <= + matches_0 & io_enqData_0_brchFwd | matches_1 & io_enqData_1_brchFwd | matches_2 + & io_enqData_2_brchFwd | matches_3 & io_enqData_3_brchFwd; end - if (req_pipe_v) begin - if (fcsrEn) - frm <= wdata[7:5]; - else if (frmEn) - frm <= wdata[2:0]; - minstret <= - {minstrethEn ? wdata : minstret[63:32], minstretEn ? wdata : minstret[31:0]}; + if (|{matches_1_3, matches_1_2, matches_1_1, matches_1_0}) begin + buffer_1_addr <= + (matches_1_0 ? io_enqData_0_addr : 32'h0) + | (matches_1_1 ? io_enqData_1_addr : 32'h0) + | (matches_1_2 ? io_enqData_2_addr : 32'h0) + | (matches_1_3 ? io_enqData_3_addr : 32'h0); + buffer_1_inst <= + (matches_1_0 ? io_enqData_0_inst : 32'h0) + | (matches_1_1 ? io_enqData_1_inst : 32'h0) + | (matches_1_2 ? io_enqData_2_inst : 32'h0) + | (matches_1_3 ? io_enqData_3_inst : 32'h0); + buffer_1_brchFwd <= + matches_1_0 & io_enqData_0_brchFwd | matches_1_1 & io_enqData_1_brchFwd + | matches_1_2 & io_enqData_2_brchFwd | matches_1_3 & io_enqData_3_brchFwd; end - else if (|_minstretThisCycle_T_2) - minstret <= minstret + {61'h0, _minstretThisCycle_T_2}; - if (req_pipe_v & mieEn) - mie <= wdata[0]; - if (req_pipe_v & mtvecEn) - mtvec <= wdata; - if (req_pipe_v & mscratchEn) - mscratch <= wdata; - if (io_bru_in_mepc_valid) - mepc <= io_bru_in_mepc_bits; - else if (req_pipe_v & mepcEn) - mepc <= wdata; - if (req_pipe_v & mstatusEn) - mpp <= wdata[12:11]; - mcycle <= - (req_pipe_v - ? {mcyclehEn ? wdata : mcycle[63:32], mcycleEn ? wdata : mcycle[31:0]} - : mcycle) + 64'h1; + if (|{matches_2_3, matches_2_2, matches_2_1, matches_2_0}) begin + buffer_2_addr <= + (matches_2_0 ? io_enqData_0_addr : 32'h0) + | (matches_2_1 ? io_enqData_1_addr : 32'h0) + | (matches_2_2 ? io_enqData_2_addr : 32'h0) + | (matches_2_3 ? io_enqData_3_addr : 32'h0); + buffer_2_inst <= + (matches_2_0 ? io_enqData_0_inst : 32'h0) + | (matches_2_1 ? io_enqData_1_inst : 32'h0) + | (matches_2_2 ? io_enqData_2_inst : 32'h0) + | (matches_2_3 ? io_enqData_3_inst : 32'h0); + buffer_2_brchFwd <= + matches_2_0 & io_enqData_0_brchFwd | matches_2_1 & io_enqData_1_brchFwd + | matches_2_2 & io_enqData_2_brchFwd | matches_2_3 & io_enqData_3_brchFwd; + end + if (|{matches_3_3, matches_3_2, matches_3_1, matches_3_0}) begin + buffer_3_addr <= + (matches_3_0 ? io_enqData_0_addr : 32'h0) + | (matches_3_1 ? io_enqData_1_addr : 32'h0) + | (matches_3_2 ? io_enqData_2_addr : 32'h0) + | (matches_3_3 ? io_enqData_3_addr : 32'h0); + buffer_3_inst <= + (matches_3_0 ? io_enqData_0_inst : 32'h0) + | (matches_3_1 ? io_enqData_1_inst : 32'h0) + | (matches_3_2 ? io_enqData_2_inst : 32'h0) + | (matches_3_3 ? io_enqData_3_inst : 32'h0); + buffer_3_brchFwd <= + matches_3_0 & io_enqData_0_brchFwd | matches_3_1 & io_enqData_1_brchFwd + | matches_3_2 & io_enqData_2_brchFwd | matches_3_3 & io_enqData_3_brchFwd; + end + if (|{matches_4_3, matches_4_2, matches_4_1, matches_4_0}) begin + buffer_4_addr <= + (matches_4_0 ? io_enqData_0_addr : 32'h0) + | (matches_4_1 ? io_enqData_1_addr : 32'h0) + | (matches_4_2 ? io_enqData_2_addr : 32'h0) + | (matches_4_3 ? io_enqData_3_addr : 32'h0); + buffer_4_inst <= + (matches_4_0 ? io_enqData_0_inst : 32'h0) + | (matches_4_1 ? io_enqData_1_inst : 32'h0) + | (matches_4_2 ? io_enqData_2_inst : 32'h0) + | (matches_4_3 ? io_enqData_3_inst : 32'h0); + buffer_4_brchFwd <= + matches_4_0 & io_enqData_0_brchFwd | matches_4_1 & io_enqData_1_brchFwd + | matches_4_2 & io_enqData_2_brchFwd | matches_4_3 & io_enqData_3_brchFwd; + end + if (|{matches_5_3, matches_5_2, matches_5_1, matches_5_0}) begin + buffer_5_addr <= + (matches_5_0 ? io_enqData_0_addr : 32'h0) + | (matches_5_1 ? io_enqData_1_addr : 32'h0) + | (matches_5_2 ? io_enqData_2_addr : 32'h0) + | (matches_5_3 ? io_enqData_3_addr : 32'h0); + buffer_5_inst <= + (matches_5_0 ? io_enqData_0_inst : 32'h0) + | (matches_5_1 ? io_enqData_1_inst : 32'h0) + | (matches_5_2 ? io_enqData_2_inst : 32'h0) + | (matches_5_3 ? io_enqData_3_inst : 32'h0); + buffer_5_brchFwd <= + matches_5_0 & io_enqData_0_brchFwd | matches_5_1 & io_enqData_1_brchFwd + | matches_5_2 & io_enqData_2_brchFwd | matches_5_3 & io_enqData_3_brchFwd; + end + if (|{matches_6_3, matches_6_2, matches_6_1, matches_6_0}) begin + buffer_6_addr <= + (matches_6_0 ? io_enqData_0_addr : 32'h0) + | (matches_6_1 ? io_enqData_1_addr : 32'h0) + | (matches_6_2 ? io_enqData_2_addr : 32'h0) + | (matches_6_3 ? io_enqData_3_addr : 32'h0); + buffer_6_inst <= + (matches_6_0 ? io_enqData_0_inst : 32'h0) + | (matches_6_1 ? io_enqData_1_inst : 32'h0) + | (matches_6_2 ? io_enqData_2_inst : 32'h0) + | (matches_6_3 ? io_enqData_3_inst : 32'h0); + buffer_6_brchFwd <= + matches_6_0 & io_enqData_0_brchFwd | matches_6_1 & io_enqData_1_brchFwd + | matches_6_2 & io_enqData_2_brchFwd | matches_6_3 & io_enqData_3_brchFwd; + end + if (|{matches_7_3, matches_7_2, matches_7_1, matches_7_0}) begin + buffer_7_addr <= + (matches_7_0 ? io_enqData_0_addr : 32'h0) + | (matches_7_1 ? io_enqData_1_addr : 32'h0) + | (matches_7_2 ? io_enqData_2_addr : 32'h0) + | (matches_7_3 ? io_enqData_3_addr : 32'h0); + buffer_7_inst <= + (matches_7_0 ? io_enqData_0_inst : 32'h0) + | (matches_7_1 ? io_enqData_1_inst : 32'h0) + | (matches_7_2 ? io_enqData_2_inst : 32'h0) + | (matches_7_3 ? io_enqData_3_inst : 32'h0); + buffer_7_brchFwd <= + matches_7_0 & io_enqData_0_brchFwd | matches_7_1 & io_enqData_1_brchFwd + | matches_7_2 & io_enqData_2_brchFwd | matches_7_3 & io_enqData_3_brchFwd; + end + enqPtr <= io_flush ? 3'h0 : enqPtr + io_enqValid; + deqPtr <= io_flush ? 3'h0 : deqPtr + io_deqReady; + nEnqueued <= + io_flush ? 4'h0 : nEnqueued + {1'h0, io_enqValid} - {1'h0, io_deqReady}; end end // always @(posedge, posedge) - always @(posedge clock) begin - if (io_req_valid) begin - req_pipe_b_addr <= io_req_bits_addr; - req_pipe_b_index <= io_req_bits_index; - req_pipe_b_op <= io_req_bits_op; - end - end // always @(posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:21]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin - _RANDOM[i] = `RANDOM; - end - req_pipe_v = _RANDOM[5'h0][0]; - req_pipe_b_addr = _RANDOM[5'h0][5:1]; - req_pipe_b_index = _RANDOM[5'h0][17:6]; - req_pipe_b_op = _RANDOM[5'h0][19:18]; - halted = _RANDOM[5'h0][20]; - fault = _RANDOM[5'h0][21]; - wfi = _RANDOM[5'h0][22]; - mode = _RANDOM[5'h0][24:23]; - mpc = {_RANDOM[5'h0][31:25], _RANDOM[5'h1][24:0]}; - msp = {_RANDOM[5'h1][31:25], _RANDOM[5'h2][24:0]}; - mcause = {_RANDOM[5'h2][31:25], _RANDOM[5'h3][24:0]}; - mtval = {_RANDOM[5'h3][31:25], _RANDOM[5'h4][24:0]}; - mcontext0 = {_RANDOM[5'h4][31:25], _RANDOM[5'h5][24:0]}; - mcontext1 = {_RANDOM[5'h5][31:25], _RANDOM[5'h6][24:0]}; - mcontext2 = {_RANDOM[5'h6][31:25], _RANDOM[5'h7][24:0]}; - mcontext3 = {_RANDOM[5'h7][31:25], _RANDOM[5'h8][24:0]}; - mcontext4 = {_RANDOM[5'h8][31:25], _RANDOM[5'h9][24:0]}; - mcontext5 = {_RANDOM[5'h9][31:25], _RANDOM[5'hA][24:0]}; - mcontext6 = {_RANDOM[5'hA][31:25], _RANDOM[5'hB][24:0]}; - mcontext7 = {_RANDOM[5'hB][31:25], _RANDOM[5'hC][24:0]}; - fflags = _RANDOM[5'hC][29:25]; - frm = {_RANDOM[5'hC][31:30], _RANDOM[5'hD][0]}; - mie = _RANDOM[5'hD][1]; - mtvec = {_RANDOM[5'hD][31:2], _RANDOM[5'hE][1:0]}; - mscratch = {_RANDOM[5'hE][31:2], _RANDOM[5'hF][1:0]}; - mepc = {_RANDOM[5'hF][31:2], _RANDOM[5'h10][1:0]}; - mpp = _RANDOM[5'h10][3:2]; - mcycle = {_RANDOM[5'h11][31:4], _RANDOM[5'h12], _RANDOM[5'h13][3:0]}; - minstret = {_RANDOM[5'h13][31:4], _RANDOM[5'h14], _RANDOM[5'h15][3:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - req_pipe_v = 1'h0; - halted = 1'h0; - fault = 1'h0; - wfi = 1'h0; - mode = 2'h0; - mpc = 32'h0; - msp = 32'h0; - mcause = 32'h0; - mtval = 32'h0; - mcontext0 = 32'h0; - mcontext1 = 32'h0; - mcontext2 = 32'h0; - mcontext3 = 32'h0; - mcontext4 = 32'h0; - mcontext5 = 32'h0; - mcontext6 = 32'h0; - mcontext7 = 32'h0; - fflags = 5'h0; - frm = 3'h0; - mie = 1'h0; - mtvec = 32'h0; - mscratch = 32'h0; - mepc = 32'h0; - mpp = 2'h0; - mcycle = 64'h0; - minstret = 64'h0; + buffer_0_addr = 32'h0; + buffer_0_inst = 32'h0; + buffer_0_brchFwd = 1'h0; + buffer_1_addr = 32'h0; + buffer_1_inst = 32'h0; + buffer_1_brchFwd = 1'h0; + buffer_2_addr = 32'h0; + buffer_2_inst = 32'h0; + buffer_2_brchFwd = 1'h0; + buffer_3_addr = 32'h0; + buffer_3_inst = 32'h0; + buffer_3_brchFwd = 1'h0; + buffer_4_addr = 32'h0; + buffer_4_inst = 32'h0; + buffer_4_brchFwd = 1'h0; + buffer_5_addr = 32'h0; + buffer_5_inst = 32'h0; + buffer_5_brchFwd = 1'h0; + buffer_6_addr = 32'h0; + buffer_6_inst = 32'h0; + buffer_6_brchFwd = 1'h0; + buffer_7_addr = 32'h0; + buffer_7_inst = 32'h0; + buffer_7_brchFwd = 1'h0; + enqPtr = 3'h0; + deqPtr = 3'h0; + nEnqueued = 4'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_csr_out_value_0 = io_csr_in_value_12; - assign io_csr_out_value_1 = mepc; - assign io_csr_out_value_2 = mtval; - assign io_csr_out_value_3 = mcause; - assign io_csr_out_value_4 = mcycle[31:0]; - assign io_csr_out_value_5 = mcycle[63:32]; - assign io_csr_out_value_6 = minstret[31:0]; - assign io_csr_out_value_7 = minstret[63:32]; - assign io_rd_valid = req_pipe_v; - assign io_rd_bits_addr = req_pipe_b_addr; - assign io_rd_bits_data = rdata; - assign io_bru_out_mode = mode; - assign io_bru_out_mepc = mepcEn & req_pipe_v ? wdata : mepc; - assign io_bru_out_mtvec = mtvecEn & req_pipe_v ? wdata : mtvec; - assign io_float_out_frm = frmEn & req_pipe_v ? wdata[2:0] : frm; - assign io_halted = halted; - assign io_fault = fault; - assign io_wfi = wfi; -endmodule - -module Decode( - input io_halted, - output io_inst_ready, - input io_inst_valid, - input [31:0] io_inst_bits_addr, - io_inst_bits_inst, - input io_inst_bits_brchFwd, - input [31:0] io_scoreboard_regd, - io_scoreboard_comb, - output [31:0] io_scoreboard_spec, - input [31:0] io_fscoreboard, - input io_lsuActive, - output io_rs1Read_valid, - output [4:0] io_rs1Read_addr, - output io_rs1Set_valid, - output [31:0] io_rs1Set_value, - output io_rs2Read_valid, - output [4:0] io_rs2Read_addr, - output io_rs2Set_valid, - output [31:0] io_rs2Set_value, - output io_rdMark_valid, - output [4:0] io_rdMark_addr, - output io_rdMark_flt_valid, - output [4:0] io_rdMark_flt_addr, - output io_busRead_bypass, - io_busRead_immen, - output [31:0] io_busRead_immed, - output io_jalFault, - io_jalrFault, - io_bxxFault, - io_undefFault, - output [31:0] io_bruTarget, - input [31:0] io_jalrTarget_data, - output io_alu_valid, - output [4:0] io_alu_bits_addr, - io_alu_bits_op, - output io_bru_valid, - io_bru_bits_fwd, - output [3:0] io_bru_bits_op, - output [31:0] io_bru_bits_pc, - io_bru_bits_target, - output [4:0] io_bru_bits_link, - output io_csr_valid, - output [4:0] io_csr_bits_addr, - output [11:0] io_csr_bits_index, - output [1:0] io_csr_bits_op, - output io_csrFault, - input io_lsu_ready, - output io_lsu_valid, - io_lsu_bits_store, - output [4:0] io_lsu_bits_addr, - io_lsu_bits_op, - output [31:0] io_lsu_bits_pc, - output io_mlu_valid, - output [4:0] io_mlu_bits_addr, - output [2:0] io_mlu_bits_op, - input io_dvu_ready, - output io_dvu_valid, - output [4:0] io_dvu_bits_addr, - output [1:0] io_dvu_bits_op, - input io_float_ready, - output io_float_valid, - output [2:0] io_float_bits_opcode, - output [4:0] io_float_bits_funct5, - io_float_bits_rs3, - io_float_bits_rs2, - io_float_bits_rs1, - output [2:0] io_float_bits_rm, - output [31:0] io_float_bits_inst, - io_float_bits_pc, - output io_float_bits_scalar_rd, - io_float_bits_scalar_rs1, - output [4:0] io_float_bits_rd, - output io_float_bits_uses_rs3, - io_float_bits_uses_rs2, - input io_branchTaken, - io_interlock, - output io_serializeOut_mul, - io_serializeOut_jump, - io_serializeOut_brcond, - io_serializeOut_wfi, - io_serializeOut_fence, - io_serializeOut_csr, - io_serializeOut_undef, - io_slog -); - - wire io_inst_ready_0; - wire io_busRead_bypass_0; - wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; - wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; - wire [31:0] d_immcsr = {27'h0, io_inst_bits_inst[19:15]}; - wire d_lui = io_inst_bits_inst[6:0] == 7'h37; - wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; - wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; - wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_jalr = _GEN == 10'h67; - wire d_beq = _GEN == 10'h63; - wire d_bne = _GEN == 10'hE3; - wire d_blt = _GEN == 10'h263; - wire d_bge = _GEN == 10'h2E3; - wire d_bltu = _GEN == 10'h363; - wire d_bgeu = _GEN == 10'h3E3; - wire [8:0] _GEN_0 = {io_inst_bits_inst[13:12], io_inst_bits_inst[6:0]}; - wire d_csrrw = _GEN_0 == 9'hF3; - wire d_csrrs = _GEN_0 == 9'h173; - wire d_csrrc = _GEN_0 == 9'h1F3; - wire d_lb = _GEN == 10'h3; - wire d_lh = _GEN == 10'h83; - wire d_lw = _GEN == 10'h103; - wire d_lbu = _GEN == 10'h203; - wire d_lhu = _GEN == 10'h283; - wire d_sb = _GEN == 10'h23; - wire d_sh = _GEN == 10'hA3; - wire d_sw = _GEN == 10'h123; - wire d_addi = _GEN == 10'h13; - wire d_slti = _GEN == 10'h113; - wire d_sltiu = _GEN == 10'h193; - wire d_xori = _GEN == 10'h213; - wire d_ori = _GEN == 10'h313; - wire d_andi = _GEN == 10'h393; - wire [16:0] _GEN_1 = - {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_slli = _GEN_1 == 17'h93; - wire d_srli = _GEN_1 == 17'h293; - wire d_srai = _GEN_1 == 17'h8293; - wire d_add = _GEN_1 == 17'h33; - wire d_sub = _GEN_1 == 17'h8033; - wire d_slt = _GEN_1 == 17'h133; - wire d_sltu = _GEN_1 == 17'h1B3; - wire d_xor = _GEN_1 == 17'h233; - wire d_or = _GEN_1 == 17'h333; - wire d_and = _GEN_1 == 17'h3B3; - wire d_sll = _GEN_1 == 17'hB3; - wire d_srl = _GEN_1 == 17'h2B3; - wire d_sra = _GEN_1 == 17'h82B3; - wire d_mul = _GEN_1 == 17'h433; - wire d_mulh = _GEN_1 == 17'h4B3; - wire d_mulhsu = _GEN_1 == 17'h533; - wire d_mulhu = _GEN_1 == 17'h5B3; - wire d_div = _GEN_1 == 17'h633; - wire d_divu = _GEN_1 == 17'h6B3; - wire d_rem = _GEN_1 == 17'h733; - wire d_remu = _GEN_1 == 17'h7B3; - wire d_andn = _GEN_1 == 17'h83B3; - wire d_orn = _GEN_1 == 17'h8333; - wire d_xnor = _GEN_1 == 17'h8233; - wire [21:0] _GEN_2 = - {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_clz = _GEN_2 == 22'h180093; - wire d_ctz = _GEN_2 == 22'h180493; - wire d_cpop = _GEN_2 == 22'h180893; - wire d_max = _GEN_1 == 17'h1733; - wire d_maxu = _GEN_1 == 17'h17B3; - wire d_min = _GEN_1 == 17'h1633; - wire d_minu = _GEN_1 == 17'h16B3; - wire d_sextb = _GEN_2 == 22'h181093; - wire d_sexth = _GEN_2 == 22'h181493; - wire d_rol = _GEN_1 == 17'hC0B3; - wire d_ror = _GEN_1 == 17'hC2B3; - wire d_orcb = _GEN_2 == 22'hA1E93; - wire d_rev8 = _GEN_2 == 22'h1A6293; - wire d_zexth = _GEN_2 == 22'h20233; - wire d_rori = _GEN_1 == 17'hC293; - wire d_slog = - {io_inst_bits_inst[31:20], - io_inst_bits_inst[14], - io_inst_bits_inst[11:0]} == 25'hF00077; - wire d_ebreak = io_inst_bits_inst == 32'h100073; - wire d_ecall = io_inst_bits_inst == 32'h73; - wire d_mpause = io_inst_bits_inst == 32'h8000073; - wire d_mret = io_inst_bits_inst == 32'h30200073; - wire d_wfi = io_inst_bits_inst == 32'h10500073; - wire d_fencei = io_inst_bits_inst == 32'h100F; - wire d_flushat = - {io_inst_bits_inst[31:28], - io_inst_bits_inst[24:20], - io_inst_bits_inst[14:0]} == 24'h200077 & (|(io_inst_bits_inst[19:15])); - wire d_flushall = - {io_inst_bits_inst[31:28], io_inst_bits_inst[24:0]} == 29'h4000077; - wire d_d_float_load_store_rm_valid = - io_inst_bits_inst[14:12] == 3'h1 | io_inst_bits_inst[14:12] == 3'h2; - wire _d_d_float_opcode_T_4 = io_inst_bits_inst[6:2] == 5'h9; - wire _d_d_float_opcode_T_6 = io_inst_bits_inst[6:2] == 5'h14; - wire _d_d_float_opcode_T_8 = io_inst_bits_inst[6:2] == 5'h10; - wire _d_d_float_opcode_T_10 = io_inst_bits_inst[6:2] == 5'h11; - wire _d_d_float_opcode_T_12 = io_inst_bits_inst[6:2] == 5'h12; - wire _d_d_float_opcode_T_14 = io_inst_bits_inst[6:2] == 5'h13; - wire [2:0] d_d_float_opcode_bits = - _d_d_float_opcode_T_14 - ? 3'h5 - : _d_d_float_opcode_T_12 - ? 3'h6 - : _d_d_float_opcode_T_10 - ? 3'h4 - : _d_d_float_opcode_T_8 - ? 3'h3 - : _d_d_float_opcode_T_6 - ? 3'h2 - : {2'h0, _d_d_float_opcode_T_4 & d_d_float_load_store_rm_valid}; - wire _d_d_float_uses_rs2_T_5 = io_inst_bits_inst[31:27] == 5'h1C; - wire _d_d_float_uses_rs2_T_7 = io_inst_bits_inst[31:27] == 5'h18; - wire _d_d_float_uses_rs2_T_2 = d_d_float_opcode_bits == 3'h2; - wire d_d_float_scalar_rd = - (_d_d_float_uses_rs2_T_7 | _d_d_float_uses_rs2_T_5 - | io_inst_bits_inst[31:27] == 5'h14) & _d_d_float_uses_rs2_T_2; - wire _d_d_float_uses_rs2_T_9 = io_inst_bits_inst[31:27] == 5'h1E; - wire _d_d_float_uses_rs2_T_11 = io_inst_bits_inst[31:27] == 5'h1A; - wire d_d_float_scalar_rs1 = _d_d_float_uses_rs2_T_11 | _d_d_float_uses_rs2_T_9; - wire _d_d_float_T_1 = d_d_float_opcode_bits == 3'h1; - wire d_d_float_y = - (_d_d_float_opcode_T_14 | _d_d_float_opcode_T_12 | _d_d_float_opcode_T_10 - | _d_d_float_opcode_T_8 | _d_d_float_opcode_T_6 - | (_d_d_float_opcode_T_4 | io_inst_bits_inst[6:2] == 5'h1) - & d_d_float_load_store_rm_valid) - & (d_d_float_opcode_bits == 3'h0 | _d_d_float_T_1 | io_inst_bits_inst[26:25] == 2'h0); - wire d_undef = - {d_lui, - d_auipc, - d_jal, - d_jalr, - d_beq, - d_bne, - d_blt, - d_bge, - d_bltu, - d_bgeu, - d_csrrw, - d_csrrs, - d_csrrc, - d_lb, - d_lh, - d_lw, - d_lbu, - d_lhu, - d_sb, - d_sh, - d_sw, - {io_inst_bits_inst[31:28], io_inst_bits_inst[19:0]} == 24'hF, - d_addi, - d_slti, - d_sltiu, - d_xori, - d_ori, - d_andi, - d_add, - d_sub, - d_slt, - d_sltu, - d_xor, - d_or, - d_and, - d_xnor, - d_orn, - d_andn, - d_slli, - d_srli, - d_srai, - d_sll, - d_srl, - d_sra, - d_mul, - d_mulh, - d_mulhsu, - d_mulhu, - d_div, - d_divu, - d_rem, - d_remu, - d_clz, - d_ctz, - d_cpop, - d_min, - d_minu, - d_max, - d_maxu, - d_sextb, - d_sexth, - d_zexth, - d_rol, - d_ror, - d_orcb, - d_rev8, - d_rori, - d_ebreak, - d_ecall, - d_wfi, - d_mpause, - d_mret, - d_fencei, - d_flushat, - d_flushall, - d_slog, - d_d_float_y} == 77'h0; - wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[11:7]}; - wire [31:0] _floatEn_T_12 = io_scoreboard_comb >> _GEN_3; - wire _io_rs2Read_valid_T_24 = d_sb | d_sh; - wire _io_rs2Read_valid_T = d_beq | d_bne; - wire [31:0] _floatEn_T_18 = io_scoreboard_comb >> d_immcsr; - wire _rdMark_valid_T_5 = d_lb | d_lh; - wire _io_float_valid_T_5 = d_d_float_opcode_bits == 3'h0; - wire _lsu_T_3 = d_d_float_opcode_bits == 3'h1; - wire [31:0] _GEN_4 = {27'h0, io_inst_bits_inst[24:20]}; - wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> _GEN_4; - wire _io_rs2Set_valid_T_5 = d_addi | d_slti; - wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; - wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> d_immcsr; - wire bruEn = - ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 - & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; - wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; - wire _rdMark_valid_T_15 = d_d_float_y & d_d_float_scalar_rd; - wire _io_rs1Read_valid_T_58 = d_d_float_y & d_d_float_scalar_rs1; - wire [31:0] _floatEn_T_25 = io_fscoreboard >> _GEN_3; - wire [31:0] _floatEn_T_32 = io_fscoreboard >> d_immcsr; - wire [31:0] _floatEn_T_37 = io_fscoreboard >> _GEN_4; - wire [31:0] _floatEn_T_42 = io_fscoreboard >> io_inst_bits_inst[31:27]; - wire _io_serializeOut_fence_T = d_fencei | d_ebreak; - wire _alu_T_1 = d_auipc | d_addi | d_add; - wire _alu_T_2 = d_slti | d_slt; - wire _alu_T_3 = d_sltiu | d_sltu; - wire _alu_T_4 = d_xori | d_xor; - wire _alu_T_5 = d_ori | d_or; - wire _alu_T_6 = d_andi | d_and; - wire _alu_T_7 = d_slli | d_sll; - wire _alu_T_8 = d_srli | d_srl; - wire _alu_T_9 = d_srai | d_sra; - wire alu_valid = - _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 - | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop - | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb - | d_rev8 | d_zexth | d_rori; - wire bru_valid = - d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu | d_ebreak | d_ecall - | d_mpause | d_mret | d_wfi; - wire [3:0] bru_bits = - d_jal - ? 4'h0 - : d_jalr - ? 4'h1 - : d_beq - ? 4'h2 - : d_bne - ? 4'h3 - : d_blt - ? 4'h4 - : d_bge - ? 4'h5 - : d_bltu - ? 4'h6 - : d_bgeu - ? 4'h7 - : d_ebreak - ? 4'h8 - : d_ecall - ? 4'h9 - : d_mpause - ? 4'hA - : d_mret ? 4'hB : d_wfi ? 4'hC : 4'h0; - wire [31:0] _bru_target_T_2 = - io_inst_bits_addr - + {{12{io_inst_bits_inst[31]}}, - io_inst_bits_inst[2] - ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} - : {{8{io_inst_bits_inst[31]}}, - io_inst_bits_inst[7], - io_inst_bits_inst[30:25], - io_inst_bits_inst[11:8]}, - 1'h0}; - wire _bxx_fault_T = bruEn & bru_valid; - wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; - wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); - wire bxx_fault = - _bxx_fault_T - & (|{bru_bits == 4'h7, - bru_bits == 4'h6, - bru_bits == 4'h5, - bru_bits == 4'h4, - bru_bits == 4'h3, - bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); - wire _io_inst_ready_T_25 = jalr_fault | jal_fault; - wire csr_valid = d_csrrw | d_csrrs | d_csrrc; - wire _io_rs1Set_value_T = d_csrrw | d_csrrs; - wire csrEn = ~(_io_rs1Set_value_T | d_csrrc) | csr_valid & io_float_ready; - wire _GEN_5 = - csr_valid - & ~(io_inst_bits_inst[31:20] == 12'h1 | io_inst_bits_inst[31:20] == 12'h2 - | io_inst_bits_inst[31:20] == 12'h3 | io_inst_bits_inst[31:20] == 12'h8 - | io_inst_bits_inst[31:20] == 12'h9 | io_inst_bits_inst[31:20] == 12'hA - | io_inst_bits_inst[31:20] == 12'h300 | io_inst_bits_inst[31:20] == 12'h301 - | io_inst_bits_inst[31:20] == 12'h304 | io_inst_bits_inst[31:20] == 12'h305 - | io_inst_bits_inst[31:20] == 12'h340 | io_inst_bits_inst[31:20] == 12'h341 - | io_inst_bits_inst[31:20] == 12'h342 | io_inst_bits_inst[31:20] == 12'h343 - | io_inst_bits_inst[31:20] == 12'h7A0 | io_inst_bits_inst[31:20] == 12'h7A1 - | io_inst_bits_inst[31:20] == 12'h7A2 | io_inst_bits_inst[31:20] == 12'h7A4 - | io_inst_bits_inst[31:20] == 12'h7B0 | io_inst_bits_inst[31:20] == 12'h7B1 - | io_inst_bits_inst[31:20] == 12'h7B2 | io_inst_bits_inst[31:20] == 12'h7B3 - | io_inst_bits_inst[31:20] == 12'h7C0 | io_inst_bits_inst[31:20] == 12'h7C1 - | io_inst_bits_inst[31:20] == 12'h7C2 | io_inst_bits_inst[31:20] == 12'h7C3 - | io_inst_bits_inst[31:20] == 12'h7C4 | io_inst_bits_inst[31:20] == 12'h7C5 - | io_inst_bits_inst[31:20] == 12'h7C6 | io_inst_bits_inst[31:20] == 12'h7C7 - | io_inst_bits_inst[31:20] == 12'h7E0 | io_inst_bits_inst[31:20] == 12'h7E1 - | io_inst_bits_inst[31:20] == 12'hB00 | io_inst_bits_inst[31:20] == 12'hB02 - | io_inst_bits_inst[31:20] == 12'hB80 | io_inst_bits_inst[31:20] == 12'hB82 - | io_inst_bits_inst[31:20] == 12'hC20 | io_inst_bits_inst[31:20] == 12'hC21 - | io_inst_bits_inst[31:20] == 12'hC22 | io_inst_bits_inst[31:20] == 12'hF11 - | io_inst_bits_inst[31:20] == 12'hF12 | io_inst_bits_inst[31:20] == 12'hF13 - | io_inst_bits_inst[31:20] == 12'hF14 | io_inst_bits_inst[31:20] == 12'hFC0 - | io_inst_bits_inst[31:20] == 12'hFC4 | io_inst_bits_inst[31:20] == 12'hFC8 - | io_inst_bits_inst[31:20] == 12'hFCC | io_inst_bits_inst[31:20] == 12'hFD0 - | io_inst_bits_inst[31:20] == 12'hFD4); - wire io_csr_valid_0 = decodeEn & csr_valid & ~_GEN_5; - wire _lsu_T_7_valid = d_d_float_y & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3; - wire lsu_valid = - d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw | d_wfi | d_fencei | d_flushat - | d_flushall | _lsu_T_7_valid; - wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; - wire dvu_valid = d_div | d_divu | d_rem | d_remu; - wire _io_rs2Read_valid_T_5 = d_add | d_sub; - wire _io_rs2Read_valid_T_18 = d_min | d_minu; - wire _io_rs2Read_valid_T_37 = d_div | d_divu; - wire rdMark_valid = - alu_valid | io_csr_valid_0 | mlu_valid | dvu_valid & io_dvu_ready | lsu_valid - & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) | _rdMark_valid_T_15 | bru_valid - & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); - wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_3; - assign io_busRead_bypass_0 = - io_inst_bits_inst[31:25] == 7'h0 - & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] - ? io_inst_bits_inst[24:20] == 5'h0 - : ~(|(io_inst_bits_inst[11:7]))); - assign io_inst_ready_0 = - (~(_floatEn_T_12[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt - | d_bge | d_bltu | d_bgeu) - & (~(_floatEn_T_18[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_flushat | d_flushall | d_d_float_y - & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3 | d_auipc | d_lui) - & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_flushat | d_flushall | d_d_float_y - & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3 | d_auipc | d_lui - | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli | d_srli - | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth - | d_orcb | d_rev8 | d_d_float_y) & bruEn - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw - | d_flushat | d_flushall | d_d_float_y & _io_float_valid_T_5 | d_d_float_y - & _lsu_T_3) | io_lsu_ready - & ~((io_busRead_bypass_0 ? _floatEn_T_18[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] - & (_io_rs2Read_valid_T_24 | d_sw))) & (~dvu_valid | io_dvu_ready) - & ~((_io_serializeOut_fence_T | d_wfi | d_mpause | d_flushat | d_flushall) - & io_lsuActive) - & (~d_d_float_y | d_d_float_y & _io_float_valid_T_5 | io_float_ready & ~io_lsuActive - & ~(_rdMark_valid_T_15 & _floatEn_T_12[0]) - & ~(_io_rs1Read_valid_T_58 & _floatEn_T_18[0]) - & ~(d_d_float_y & ~d_d_float_scalar_rd & _floatEn_T_25[0]) - & ~(d_d_float_y & ~d_d_float_scalar_rs1 & _floatEn_T_32[0]) - & ~(d_d_float_y & _floatEn_T_37[0]) & ~(d_d_float_y & _floatEn_T_42[0])) & csrEn - & ~io_halted & ~io_interlock & ~(_io_inst_ready_T_25 | _GEN_5 | bxx_fault); - assign io_inst_ready = io_inst_ready_0; - assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; - assign io_rs1Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol - | d_ror | _io_rs1Set_value_T | d_csrrc | _io_rs2Read_valid_T_33 | d_mulhsu - | d_mulhu | _io_rs2Read_valid_T_37 | d_rem | d_remu | d_slog | d_jalr - | _io_rs1Read_valid_T_58); - assign io_rs1Read_addr = - io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; - assign io_rs1Set_valid = - decodeEn & (d_auipc | (_io_rs1Set_value_T | d_csrrc) & io_inst_bits_inst[14]); - assign io_rs1Set_value = _io_rs1Set_value_T | d_csrrc ? d_immcsr : io_inst_bits_addr; - assign io_rs2Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror - | _io_rs2Read_valid_T_24 | d_sw | (_io_rs1Set_value_T | d_csrrc) - & ~(io_inst_bits_inst[14]) | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu - | _io_rs2Read_valid_T_37 | d_rem | d_remu | d_slog); - assign io_rs2Read_addr = io_inst_bits_inst[24:20]; - assign io_rs2Set_valid = - decodeEn - & (d_auipc | (_io_rs1Set_value_T | d_csrrc) & io_inst_bits_inst[14] - | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli | d_srli - | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth - | d_orcb | d_rev8 | d_lui); - assign io_rs2Set_value = - d_auipc | d_lui - ? {io_inst_bits_inst[31:12], 12'h0} - : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; - assign io_rdMark_valid = decodeEn & rdMark_valid; - assign io_rdMark_addr = io_inst_bits_inst[11:7]; - assign io_rdMark_flt_valid = - decodeEn & d_d_float_y & ~d_d_float_scalar_rd & d_d_float_opcode_bits != 3'h1; - assign io_rdMark_flt_addr = io_inst_bits_inst[11:7]; - assign io_busRead_bypass = io_busRead_bypass_0; - assign io_busRead_immen = ~d_flushat; - assign io_busRead_immed = - {_d_d_imm12_T_1, - io_inst_bits_inst[31:25], - io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) - ? io_inst_bits_inst[11:7] - : io_inst_bits_inst[24:20]}; - assign io_jalFault = jal_fault; - assign io_jalrFault = jalr_fault; - assign io_bxxFault = bxx_fault; - assign io_undefFault = io_inst_valid & d_undef; - assign io_bruTarget = _bru_target_T_2; - assign io_alu_valid = decodeEn & alu_valid; - assign io_alu_bits_addr = io_inst_bits_inst[11:7]; - assign io_alu_bits_op = - _alu_T_1 - ? 5'h0 - : d_sub - ? 5'h1 - : _alu_T_2 - ? 5'h2 - : _alu_T_3 - ? 5'h3 - : _alu_T_4 - ? 5'h4 - : _alu_T_5 - ? 5'h5 - : _alu_T_6 - ? 5'h6 - : _alu_T_7 - ? 5'h7 - : _alu_T_8 - ? 5'h8 - : _alu_T_9 - ? 5'h9 - : d_lui - ? 5'hA - : d_andn - ? 5'hB - : d_orn - ? 5'hC - : d_xnor - ? 5'hD - : d_clz - ? 5'hE - : d_ctz - ? 5'hF - : d_cpop - ? 5'h10 - : d_max - ? 5'h11 - : d_maxu - ? 5'h12 - : d_min - ? 5'h13 - : d_minu - ? 5'h14 - : d_sextb - ? 5'h15 - : d_sexth - ? 5'h16 - : d_rol - ? 5'h17 - : d_ror - ? 5'h18 - : d_orcb - ? 5'h19 - : d_rev8 - ? 5'h1A - : d_zexth - ? 5'h1B - : d_rori - ? 5'h18 - : 5'h0; - assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_25 | bxx_fault); - assign io_bru_bits_fwd = io_inst_bits_brchFwd; - assign io_bru_bits_op = bru_bits; - assign io_bru_bits_pc = io_inst_bits_addr; - assign io_bru_bits_target = _bru_target_T_2; - assign io_bru_bits_link = io_inst_bits_inst[11:7]; - assign io_csr_valid = io_csr_valid_0; - assign io_csr_bits_addr = io_inst_bits_inst[11:7]; - assign io_csr_bits_index = io_inst_bits_inst[31:20]; - assign io_csr_bits_op = d_csrrw ? 2'h0 : d_csrrs ? 2'h1 : {d_csrrc, 1'h0}; - assign io_csrFault = csrEn & _GEN_5; - assign io_lsu_valid = decodeEn & lsu_valid; - assign io_lsu_bits_store = io_inst_bits_inst[5]; - assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; - assign io_lsu_bits_op = - d_lb - ? 5'h0 - : d_lh - ? 5'h1 - : d_lw - ? 5'h2 - : d_lbu - ? 5'h3 - : d_lhu - ? 5'h4 - : d_sb - ? 5'h5 - : d_sh - ? 5'h6 - : d_sw - ? 5'h7 - : d_wfi | d_fencei - ? 5'h8 - : d_flushat - ? 5'h9 - : d_flushall - ? 5'hA - : _lsu_T_7_valid ? 5'hC : 5'h0; - assign io_lsu_bits_pc = io_inst_bits_addr; - assign io_mlu_valid = decodeEn & mlu_valid; - assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; - assign io_mlu_bits_op = - d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; - assign io_dvu_valid = decodeEn & dvu_valid; - assign io_dvu_bits_addr = io_inst_bits_inst[11:7]; - assign io_dvu_bits_op = d_div ? 2'h0 : d_divu ? 2'h1 : d_rem ? 2'h2 : {2{d_remu}}; - assign io_float_valid = decodeEn & d_d_float_y & ~(d_d_float_y & _io_float_valid_T_5); - assign io_float_bits_opcode = d_d_float_opcode_bits; - assign io_float_bits_funct5 = io_inst_bits_inst[31:27]; - assign io_float_bits_rs3 = io_inst_bits_inst[31:27]; - assign io_float_bits_rs2 = io_inst_bits_inst[24:20]; - assign io_float_bits_rs1 = io_inst_bits_inst[19:15]; - assign io_float_bits_rm = io_inst_bits_inst[14:12]; - assign io_float_bits_inst = io_inst_bits_inst; - assign io_float_bits_pc = io_inst_bits_addr; - assign io_float_bits_scalar_rd = d_d_float_scalar_rd; - assign io_float_bits_scalar_rs1 = d_d_float_scalar_rs1; - assign io_float_bits_rd = io_inst_bits_inst[11:7]; - assign io_float_bits_uses_rs3 = - |{d_d_float_opcode_bits == 3'h6, - d_d_float_opcode_bits == 3'h5, - d_d_float_opcode_bits == 3'h4, - d_d_float_opcode_bits == 3'h3}; - assign io_float_bits_uses_rs2 = - _d_d_float_T_1 | _d_d_float_uses_rs2_T_2 - & ~(io_inst_bits_inst[31:27] == 5'hB | _d_d_float_uses_rs2_T_11 - | _d_d_float_uses_rs2_T_9 | _d_d_float_uses_rs2_T_7 | _d_d_float_uses_rs2_T_5) - & io_inst_bits_inst[31:27] != 5'h1C; - assign io_serializeOut_mul = mlu_valid; - assign io_serializeOut_jump = d_jal | d_jalr | d_ebreak | d_ecall | d_mpause | d_mret; - assign io_serializeOut_brcond = d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - assign io_serializeOut_wfi = d_wfi; - assign io_serializeOut_fence = - _io_serializeOut_fence_T | d_wfi | d_mpause | d_flushat | d_flushall; - assign io_serializeOut_csr = d_csrrw | d_csrrs | d_csrrc; - assign io_serializeOut_undef = d_undef; - assign io_slog = decodeEn & d_slog; + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 4'h8 - nEnqueued; + assign io_dataOut_0_addr = + deqPtr[0] + ? _shifted_WIRE_1_addr + : deqPtr[1] ? _shifted_T_7_addr : deqPtr[2] ? buffer_4_addr : buffer_0_addr; + assign io_dataOut_0_inst = + deqPtr[0] + ? _shifted_WIRE_1_inst + : deqPtr[1] ? _shifted_T_7_inst : deqPtr[2] ? buffer_4_inst : buffer_0_inst; + assign io_dataOut_0_brchFwd = + deqPtr[0] + ? _shifted_WIRE_1_brchFwd + : deqPtr[1] + ? _shifted_T_7_brchFwd + : deqPtr[2] ? buffer_4_brchFwd : buffer_0_brchFwd; + assign io_dataOut_1_addr = deqPtr[0] ? _shifted_WIRE_2_addr : _shifted_WIRE_1_addr; + assign io_dataOut_1_inst = deqPtr[0] ? _shifted_WIRE_2_inst : _shifted_WIRE_1_inst; + assign io_dataOut_1_brchFwd = + deqPtr[0] ? _shifted_WIRE_2_brchFwd : _shifted_WIRE_1_brchFwd; + assign io_dataOut_2_addr = deqPtr[0] ? _shifted_WIRE_3_addr : _shifted_WIRE_2_addr; + assign io_dataOut_2_inst = deqPtr[0] ? _shifted_WIRE_3_inst : _shifted_WIRE_2_inst; + assign io_dataOut_2_brchFwd = + deqPtr[0] ? _shifted_WIRE_3_brchFwd : _shifted_WIRE_2_brchFwd; + assign io_dataOut_3_addr = + deqPtr[0] + ? (deqPtr[1] ? (deqPtr[2] ? buffer_2_addr : buffer_6_addr) : _shifted_T_13_addr) + : _shifted_WIRE_3_addr; + assign io_dataOut_3_inst = + deqPtr[0] + ? (deqPtr[1] ? (deqPtr[2] ? buffer_2_inst : buffer_6_inst) : _shifted_T_13_inst) + : _shifted_WIRE_3_inst; + assign io_dataOut_3_brchFwd = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] ? buffer_2_brchFwd : buffer_6_brchFwd) + : _shifted_T_13_brchFwd) + : _shifted_WIRE_3_brchFwd; endmodule -module Decode_1( - input io_halted, - output io_inst_ready, - input io_inst_valid, - input [31:0] io_inst_bits_addr, - io_inst_bits_inst, - input io_inst_bits_brchFwd, - input [31:0] io_scoreboard_regd, - io_scoreboard_comb, - output [31:0] io_scoreboard_spec, - output io_rs1Read_valid, - output [4:0] io_rs1Read_addr, - output io_rs1Set_valid, - output [31:0] io_rs1Set_value, - output io_rs2Read_valid, - output [4:0] io_rs2Read_addr, - output io_rs2Set_valid, - output [31:0] io_rs2Set_value, - output io_rdMark_valid, - output [4:0] io_rdMark_addr, - output io_busRead_bypass, - output [31:0] io_busRead_immed, - output io_jalFault, - io_jalrFault, - io_bxxFault, - output [31:0] io_bruTarget, - input [31:0] io_jalrTarget_data, - output io_alu_valid, - output [4:0] io_alu_bits_addr, - io_alu_bits_op, - output io_bru_valid, - io_bru_bits_fwd, - output [3:0] io_bru_bits_op, - output [31:0] io_bru_bits_pc, - io_bru_bits_target, - output [4:0] io_bru_bits_link, - input io_lsu_ready, - output io_lsu_valid, - io_lsu_bits_store, - output [4:0] io_lsu_bits_addr, - io_lsu_bits_op, - output [31:0] io_lsu_bits_pc, - output io_mlu_valid, - output [4:0] io_mlu_bits_addr, - output [2:0] io_mlu_bits_op, - input io_branchTaken, - io_interlock, - io_serializeIn_mul, - io_serializeIn_jump, - io_serializeIn_brcond, - io_serializeIn_wfi, - io_serializeIn_fence, - io_serializeIn_csr, - io_serializeIn_undef, - output io_serializeOut_mul, - io_serializeOut_jump, - io_serializeOut_brcond, - io_serializeOut_wfi, - io_serializeOut_fence, - io_serializeOut_csr, - io_serializeOut_undef +module InstructionBuffer( + input clock, + reset, + output [2:0] io_feedIn_nReady, + input [2:0] io_feedIn_nValid, + input [31:0] io_feedIn_bits_0_addr, + io_feedIn_bits_0_inst, + input io_feedIn_bits_0_brchFwd, + input [31:0] io_feedIn_bits_1_addr, + io_feedIn_bits_1_inst, + input io_feedIn_bits_1_brchFwd, + input [31:0] io_feedIn_bits_2_addr, + io_feedIn_bits_2_inst, + input io_feedIn_bits_2_brchFwd, + input [31:0] io_feedIn_bits_3_addr, + io_feedIn_bits_3_inst, + input io_feedIn_bits_3_brchFwd, + io_out_0_ready, + output io_out_0_valid, + output [31:0] io_out_0_bits_addr, + io_out_0_bits_inst, + output io_out_0_bits_brchFwd, + input io_out_1_ready, + output io_out_1_valid, + output [31:0] io_out_1_bits_addr, + io_out_1_bits_inst, + output io_out_1_bits_brchFwd, + input io_out_2_ready, + output io_out_2_valid, + output [31:0] io_out_2_bits_addr, + io_out_2_bits_inst, + output io_out_2_bits_brchFwd, + input io_out_3_ready, + output io_out_3_valid, + output [31:0] io_out_3_bits_addr, + io_out_3_bits_inst, + output io_out_3_bits_brchFwd, + input io_flush, + output [3:0] io_nEnqueued, + io_nSpace ); - wire io_inst_ready_0; - wire io_busRead_bypass_0; - wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; - wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; - wire d_lui = io_inst_bits_inst[6:0] == 7'h37; - wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; - wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; - wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_jalr = _GEN == 10'h67; - wire d_beq = _GEN == 10'h63; - wire d_bne = _GEN == 10'hE3; - wire d_blt = _GEN == 10'h263; - wire d_bge = _GEN == 10'h2E3; - wire d_bltu = _GEN == 10'h363; - wire d_bgeu = _GEN == 10'h3E3; - wire d_lb = _GEN == 10'h3; - wire d_lh = _GEN == 10'h83; - wire d_lw = _GEN == 10'h103; - wire d_lbu = _GEN == 10'h203; - wire d_lhu = _GEN == 10'h283; - wire d_sb = _GEN == 10'h23; - wire d_sh = _GEN == 10'hA3; - wire d_sw = _GEN == 10'h123; - wire d_addi = _GEN == 10'h13; - wire d_slti = _GEN == 10'h113; - wire d_sltiu = _GEN == 10'h193; - wire d_xori = _GEN == 10'h213; - wire d_ori = _GEN == 10'h313; - wire d_andi = _GEN == 10'h393; - wire [16:0] _GEN_0 = - {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_slli = _GEN_0 == 17'h93; - wire d_srli = _GEN_0 == 17'h293; - wire d_srai = _GEN_0 == 17'h8293; - wire d_add = _GEN_0 == 17'h33; - wire d_sub = _GEN_0 == 17'h8033; - wire d_slt = _GEN_0 == 17'h133; - wire d_sltu = _GEN_0 == 17'h1B3; - wire d_xor = _GEN_0 == 17'h233; - wire d_or = _GEN_0 == 17'h333; - wire d_and = _GEN_0 == 17'h3B3; - wire d_sll = _GEN_0 == 17'hB3; - wire d_srl = _GEN_0 == 17'h2B3; - wire d_sra = _GEN_0 == 17'h82B3; - wire d_mul = _GEN_0 == 17'h433; - wire d_mulh = _GEN_0 == 17'h4B3; - wire d_mulhsu = _GEN_0 == 17'h533; - wire d_mulhu = _GEN_0 == 17'h5B3; - wire d_andn = _GEN_0 == 17'h83B3; - wire d_orn = _GEN_0 == 17'h8333; - wire d_xnor = _GEN_0 == 17'h8233; - wire [21:0] _GEN_1 = - {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_clz = _GEN_1 == 22'h180093; - wire d_ctz = _GEN_1 == 22'h180493; - wire d_cpop = _GEN_1 == 22'h180893; - wire d_max = _GEN_0 == 17'h1733; - wire d_maxu = _GEN_0 == 17'h17B3; - wire d_min = _GEN_0 == 17'h1633; - wire d_minu = _GEN_0 == 17'h16B3; - wire d_sextb = _GEN_1 == 22'h181093; - wire d_sexth = _GEN_1 == 22'h181493; - wire d_rol = _GEN_0 == 17'hC0B3; - wire d_ror = _GEN_0 == 17'hC2B3; - wire d_orcb = _GEN_1 == 22'hA1E93; - wire d_rev8 = _GEN_1 == 22'h1A6293; - wire d_zexth = _GEN_1 == 22'h20233; - wire d_rori = _GEN_0 == 17'hC293; - wire d_undef = - {d_lui, - d_auipc, - d_jal, - d_jalr, - d_beq, - d_bne, - d_blt, - d_bge, - d_bltu, - d_bgeu, - d_lb, - d_lh, - d_lw, - d_lbu, - d_lhu, - d_sb, - d_sh, - d_sw, - d_addi, - d_slti, - d_sltiu, - d_xori, - d_ori, - d_andi, - d_add, - d_sub, - d_slt, - d_sltu, - d_xor, - d_or, - d_and, - d_xnor, - d_orn, - d_andn, - d_slli, - d_srli, - d_srai, - d_sll, - d_srl, - d_sra, - d_mul, - d_mulh, - d_mulhsu, - d_mulhu, - d_clz, - d_ctz, - d_cpop, - d_min, - d_minu, - d_max, - d_maxu, - d_sextb, - d_sexth, - d_zexth, - d_rol, - d_ror, - d_orcb, - d_rev8, - d_rori} == 59'h0; - wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[11:7]}; - wire [31:0] _aluRdEn_T = io_scoreboard_comb >> _GEN_2; - wire _io_rs2Read_valid_T_24 = d_sb | d_sh; - wire _io_rs2Read_valid_T = d_beq | d_bne; - wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[19:15]}; - wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_3; - wire _rdMark_valid_T_5 = d_lb | d_lh; - wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; - wire _io_rs2Set_valid_T_5 = d_addi | d_slti; - wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; - wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_3; - wire bruEn = - ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 - & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; - wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; - wire _alu_T_1 = d_auipc | d_addi | d_add; - wire _alu_T_2 = d_slti | d_slt; - wire _alu_T_3 = d_sltiu | d_sltu; - wire _alu_T_4 = d_xori | d_xor; - wire _alu_T_5 = d_ori | d_or; - wire _alu_T_6 = d_andi | d_and; - wire _alu_T_7 = d_slli | d_sll; - wire _alu_T_8 = d_srli | d_srl; - wire _alu_T_9 = d_srai | d_sra; - wire alu_valid = - _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 - | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop - | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb - | d_rev8 | d_zexth | d_rori; - wire bru_valid = - d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - wire [3:0] bru_bits = - d_jal - ? 4'h0 - : d_jalr - ? 4'h1 - : d_beq - ? 4'h2 - : d_bne - ? 4'h3 - : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; - wire [31:0] _bru_target_T_2 = - io_inst_bits_addr - + {{12{io_inst_bits_inst[31]}}, - io_inst_bits_inst[2] - ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} - : {{8{io_inst_bits_inst[31]}}, - io_inst_bits_inst[7], - io_inst_bits_inst[30:25], - io_inst_bits_inst[11:8]}, - 1'h0}; - wire _bxx_fault_T = bruEn & bru_valid; - wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; - wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); - wire bxx_fault = - _bxx_fault_T - & (|{bru_bits == 4'h7, - bru_bits == 4'h6, - bru_bits == 4'h5, - bru_bits == 4'h4, - bru_bits == 4'h3, - bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); - wire _io_inst_ready_T_26 = jalr_fault | jal_fault; - wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; - wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; - wire _io_rs2Read_valid_T_5 = d_add | d_sub; - wire _io_rs2Read_valid_T_18 = d_min | d_minu; - wire rdMark_valid = - alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) - | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); - wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_2; - assign io_busRead_bypass_0 = - io_inst_bits_inst[31:25] == 7'h0 - & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] - ? io_inst_bits_inst[24:20] == 5'h0 - : ~(|(io_inst_bits_inst[11:7]))); - assign io_inst_ready_0 = - (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt - | d_bge | d_bltu | d_bgeu) - & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) - & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu - | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori - | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) - & bruEn - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | io_lsu_ready - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | ~io_serializeIn_brcond) - & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] - & (_io_rs2Read_valid_T_24 | d_sw))) - & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) - & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump - & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted - & ~io_interlock & ~d_undef & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_inst_ready = io_inst_ready_0; - assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; - assign io_rs1Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol - | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); - assign io_rs1Read_addr = - io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; - assign io_rs1Set_valid = decodeEn & d_auipc; - assign io_rs1Set_value = io_inst_bits_addr; - assign io_rs2Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror - | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); - assign io_rs2Read_addr = io_inst_bits_inst[24:20]; - assign io_rs2Set_valid = - decodeEn - & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | d_lui); - assign io_rs2Set_value = - d_auipc | d_lui - ? {io_inst_bits_inst[31:12], 12'h0} - : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; - assign io_rdMark_valid = decodeEn & rdMark_valid; - assign io_rdMark_addr = io_inst_bits_inst[11:7]; - assign io_busRead_bypass = io_busRead_bypass_0; - assign io_busRead_immed = - {_d_d_imm12_T_1, - io_inst_bits_inst[31:25], - io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) - ? io_inst_bits_inst[11:7] - : io_inst_bits_inst[24:20]}; - assign io_jalFault = jal_fault; - assign io_jalrFault = jalr_fault; - assign io_bxxFault = bxx_fault; - assign io_bruTarget = _bru_target_T_2; - assign io_alu_valid = decodeEn & alu_valid; - assign io_alu_bits_addr = io_inst_bits_inst[11:7]; - assign io_alu_bits_op = - _alu_T_1 - ? 5'h0 - : d_sub - ? 5'h1 - : _alu_T_2 - ? 5'h2 - : _alu_T_3 - ? 5'h3 - : _alu_T_4 - ? 5'h4 - : _alu_T_5 - ? 5'h5 - : _alu_T_6 - ? 5'h6 - : _alu_T_7 - ? 5'h7 - : _alu_T_8 - ? 5'h8 - : _alu_T_9 - ? 5'h9 - : d_lui - ? 5'hA - : d_andn - ? 5'hB - : d_orn - ? 5'hC - : d_xnor - ? 5'hD - : d_clz - ? 5'hE - : d_ctz - ? 5'hF - : d_cpop - ? 5'h10 - : d_max - ? 5'h11 - : d_maxu - ? 5'h12 - : d_min - ? 5'h13 - : d_minu - ? 5'h14 - : d_sextb - ? 5'h15 - : d_sexth - ? 5'h16 - : d_rol - ? 5'h17 - : d_ror - ? 5'h18 - : d_orcb - ? 5'h19 - : d_rev8 - ? 5'h1A - : d_zexth - ? 5'h1B - : d_rori - ? 5'h18 - : 5'h0; - assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_bru_bits_fwd = io_inst_bits_brchFwd; - assign io_bru_bits_op = bru_bits; - assign io_bru_bits_pc = io_inst_bits_addr; - assign io_bru_bits_target = _bru_target_T_2; - assign io_bru_bits_link = io_inst_bits_inst[11:7]; - assign io_lsu_valid = decodeEn & lsu_valid; - assign io_lsu_bits_store = io_inst_bits_inst[5]; - assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; - assign io_lsu_bits_op = - d_lb - ? 5'h0 - : d_lh - ? 5'h1 - : d_lw - ? 5'h2 - : d_lbu - ? 5'h3 - : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; - assign io_lsu_bits_pc = io_inst_bits_addr; - assign io_mlu_valid = decodeEn & mlu_valid; - assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; - assign io_mlu_bits_op = - d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; - assign io_serializeOut_mul = io_serializeIn_mul | mlu_valid; - assign io_serializeOut_jump = io_serializeIn_jump | d_jal | d_jalr; - assign io_serializeOut_brcond = - io_serializeIn_brcond | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - assign io_serializeOut_wfi = io_serializeIn_wfi; - assign io_serializeOut_fence = io_serializeIn_fence; - assign io_serializeOut_csr = io_serializeIn_csr; - assign io_serializeOut_undef = io_serializeIn_undef | d_undef; + wire [3:0] _circularBuffer_io_nEnqueued; + wire [3:0] _circularBuffer_io_nSpace; + wire io_out_0_valid_0 = (|_circularBuffer_io_nEnqueued) & ~io_flush; + wire io_out_1_valid_0 = (|(_circularBuffer_io_nEnqueued[3:1])) & ~io_flush; + wire io_out_2_valid_0 = _circularBuffer_io_nEnqueued > 4'h2 & ~io_flush; + wire io_out_3_valid_0 = (|(_circularBuffer_io_nEnqueued[3:2])) & ~io_flush; + CircularBufferMulti circularBuffer ( + .clock (clock), + .reset (reset), + .io_enqValid (io_feedIn_nValid), + .io_enqData_0_addr (io_feedIn_bits_0_addr), + .io_enqData_0_inst (io_feedIn_bits_0_inst), + .io_enqData_0_brchFwd (io_feedIn_bits_0_brchFwd), + .io_enqData_1_addr (io_feedIn_bits_1_addr), + .io_enqData_1_inst (io_feedIn_bits_1_inst), + .io_enqData_1_brchFwd (io_feedIn_bits_1_brchFwd), + .io_enqData_2_addr (io_feedIn_bits_2_addr), + .io_enqData_2_inst (io_feedIn_bits_2_inst), + .io_enqData_2_brchFwd (io_feedIn_bits_2_brchFwd), + .io_enqData_3_addr (io_feedIn_bits_3_addr), + .io_enqData_3_inst (io_feedIn_bits_3_inst), + .io_enqData_3_brchFwd (io_feedIn_bits_3_brchFwd), + .io_nEnqueued (_circularBuffer_io_nEnqueued), + .io_nSpace (_circularBuffer_io_nSpace), + .io_dataOut_0_addr (io_out_0_bits_addr), + .io_dataOut_0_inst (io_out_0_bits_inst), + .io_dataOut_0_brchFwd (io_out_0_bits_brchFwd), + .io_dataOut_1_addr (io_out_1_bits_addr), + .io_dataOut_1_inst (io_out_1_bits_inst), + .io_dataOut_1_brchFwd (io_out_1_bits_brchFwd), + .io_dataOut_2_addr (io_out_2_bits_addr), + .io_dataOut_2_inst (io_out_2_bits_inst), + .io_dataOut_2_brchFwd (io_out_2_bits_brchFwd), + .io_dataOut_3_addr (io_out_3_bits_addr), + .io_dataOut_3_inst (io_out_3_bits_inst), + .io_dataOut_3_brchFwd (io_out_3_bits_brchFwd), + .io_deqReady + ({1'h0, + {1'h0, io_out_0_ready & io_out_0_valid_0} + + {1'h0, io_out_1_ready & io_out_1_valid_0}} + + {1'h0, + {1'h0, io_out_2_ready & io_out_2_valid_0} + + {1'h0, io_out_3_ready & io_out_3_valid_0}}), + .io_flush (io_flush) + ); + assign io_feedIn_nReady = + _circularBuffer_io_nSpace < 4'h4 ? _circularBuffer_io_nSpace[2:0] : 3'h4; + assign io_out_0_valid = io_out_0_valid_0; + assign io_out_1_valid = io_out_1_valid_0; + assign io_out_2_valid = io_out_2_valid_0; + assign io_out_3_valid = io_out_3_valid_0; + assign io_nEnqueued = _circularBuffer_io_nEnqueued; + assign io_nSpace = _circularBuffer_io_nSpace; endmodule -module Decode_2( - input io_halted, - output io_inst_ready, - input io_inst_valid, - input [31:0] io_inst_bits_addr, - io_inst_bits_inst, - input io_inst_bits_brchFwd, - input [31:0] io_scoreboard_regd, - io_scoreboard_comb, - output [31:0] io_scoreboard_spec, - output io_rs1Read_valid, - output [4:0] io_rs1Read_addr, - output io_rs1Set_valid, - output [31:0] io_rs1Set_value, - output io_rs2Read_valid, - output [4:0] io_rs2Read_addr, - output io_rs2Set_valid, - output [31:0] io_rs2Set_value, - output io_rdMark_valid, - output [4:0] io_rdMark_addr, - output io_busRead_bypass, - output [31:0] io_busRead_immed, - output io_jalFault, - io_jalrFault, - io_bxxFault, - output [31:0] io_bruTarget, - input [31:0] io_jalrTarget_data, - output io_alu_valid, - output [4:0] io_alu_bits_addr, - io_alu_bits_op, - output io_bru_valid, - io_bru_bits_fwd, - output [3:0] io_bru_bits_op, - output [31:0] io_bru_bits_pc, - io_bru_bits_target, - output [4:0] io_bru_bits_link, - input io_lsu_ready, - output io_lsu_valid, - io_lsu_bits_store, - output [4:0] io_lsu_bits_addr, - io_lsu_bits_op, - output [31:0] io_lsu_bits_pc, - output io_mlu_valid, - output [4:0] io_mlu_bits_addr, - output [2:0] io_mlu_bits_op, - input io_branchTaken, - io_interlock, - io_serializeIn_mul, - io_serializeIn_jump, - io_serializeIn_brcond, - io_serializeIn_wfi, - io_serializeIn_fence, - io_serializeIn_csr, - io_serializeIn_undef, - output io_serializeOut_mul, - io_serializeOut_jump, - io_serializeOut_brcond, - io_serializeOut_wfi, - io_serializeOut_fence, - io_serializeOut_csr, - io_serializeOut_undef +module UncachedFetch( + input clock, + reset, + input [31:0] io_csr_value_0, + input io_debug_pc_valid, + input [31:0] io_debug_pc_bits, + output io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + input io_ibus_fault_valid, + io_inst_lanes_0_ready, + output io_inst_lanes_0_valid, + output [31:0] io_inst_lanes_0_bits_addr, + io_inst_lanes_0_bits_inst, + output io_inst_lanes_0_bits_brchFwd, + input io_inst_lanes_1_ready, + output io_inst_lanes_1_valid, + output [31:0] io_inst_lanes_1_bits_addr, + io_inst_lanes_1_bits_inst, + output io_inst_lanes_1_bits_brchFwd, + input io_inst_lanes_2_ready, + output io_inst_lanes_2_valid, + output [31:0] io_inst_lanes_2_bits_addr, + io_inst_lanes_2_bits_inst, + output io_inst_lanes_2_bits_brchFwd, + input io_inst_lanes_3_ready, + output io_inst_lanes_3_valid, + output [31:0] io_inst_lanes_3_bits_addr, + io_inst_lanes_3_bits_inst, + output io_inst_lanes_3_bits_brchFwd, + input io_branch_0_valid, + input [31:0] io_branch_0_value, + input io_branch_1_valid, + input [31:0] io_branch_1_value, + input io_branch_2_valid, + input [31:0] io_branch_2_value, + input io_branch_3_valid, + input [31:0] io_branch_3_value, + input io_iflush_valid, + input [31:0] io_iflush_pcNext, + output [31:0] io_pc, + output io_fault_valid, + output [31:0] io_fault_bits ); - wire io_inst_ready_0; - wire io_busRead_bypass_0; - wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; - wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; - wire d_lui = io_inst_bits_inst[6:0] == 7'h37; - wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; - wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; - wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_jalr = _GEN == 10'h67; - wire d_beq = _GEN == 10'h63; - wire d_bne = _GEN == 10'hE3; - wire d_blt = _GEN == 10'h263; - wire d_bge = _GEN == 10'h2E3; - wire d_bltu = _GEN == 10'h363; - wire d_bgeu = _GEN == 10'h3E3; - wire d_lb = _GEN == 10'h3; - wire d_lh = _GEN == 10'h83; - wire d_lw = _GEN == 10'h103; - wire d_lbu = _GEN == 10'h203; - wire d_lhu = _GEN == 10'h283; - wire d_sb = _GEN == 10'h23; - wire d_sh = _GEN == 10'hA3; - wire d_sw = _GEN == 10'h123; - wire d_addi = _GEN == 10'h13; - wire d_slti = _GEN == 10'h113; - wire d_sltiu = _GEN == 10'h193; - wire d_xori = _GEN == 10'h213; - wire d_ori = _GEN == 10'h313; - wire d_andi = _GEN == 10'h393; - wire [16:0] _GEN_0 = - {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_slli = _GEN_0 == 17'h93; - wire d_srli = _GEN_0 == 17'h293; - wire d_srai = _GEN_0 == 17'h8293; - wire d_add = _GEN_0 == 17'h33; - wire d_sub = _GEN_0 == 17'h8033; - wire d_slt = _GEN_0 == 17'h133; - wire d_sltu = _GEN_0 == 17'h1B3; - wire d_xor = _GEN_0 == 17'h233; - wire d_or = _GEN_0 == 17'h333; - wire d_and = _GEN_0 == 17'h3B3; - wire d_sll = _GEN_0 == 17'hB3; - wire d_srl = _GEN_0 == 17'h2B3; - wire d_sra = _GEN_0 == 17'h82B3; - wire d_mul = _GEN_0 == 17'h433; - wire d_mulh = _GEN_0 == 17'h4B3; - wire d_mulhsu = _GEN_0 == 17'h533; - wire d_mulhu = _GEN_0 == 17'h5B3; - wire d_andn = _GEN_0 == 17'h83B3; - wire d_orn = _GEN_0 == 17'h8333; - wire d_xnor = _GEN_0 == 17'h8233; - wire [21:0] _GEN_1 = - {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_clz = _GEN_1 == 22'h180093; - wire d_ctz = _GEN_1 == 22'h180493; - wire d_cpop = _GEN_1 == 22'h180893; - wire d_max = _GEN_0 == 17'h1733; - wire d_maxu = _GEN_0 == 17'h17B3; - wire d_min = _GEN_0 == 17'h1633; - wire d_minu = _GEN_0 == 17'h16B3; - wire d_sextb = _GEN_1 == 22'h181093; - wire d_sexth = _GEN_1 == 22'h181493; - wire d_rol = _GEN_0 == 17'hC0B3; - wire d_ror = _GEN_0 == 17'hC2B3; - wire d_orcb = _GEN_1 == 22'hA1E93; - wire d_rev8 = _GEN_1 == 22'h1A6293; - wire d_zexth = _GEN_1 == 22'h20233; - wire d_rori = _GEN_0 == 17'hC293; - wire d_undef = - {d_lui, - d_auipc, - d_jal, - d_jalr, - d_beq, - d_bne, - d_blt, - d_bge, - d_bltu, - d_bgeu, - d_lb, - d_lh, - d_lw, - d_lbu, - d_lhu, - d_sb, - d_sh, - d_sw, - d_addi, - d_slti, - d_sltiu, - d_xori, - d_ori, - d_andi, - d_add, - d_sub, - d_slt, - d_sltu, - d_xor, - d_or, - d_and, - d_xnor, - d_orn, - d_andn, - d_slli, - d_srli, - d_srai, - d_sll, - d_srl, - d_sra, - d_mul, - d_mulh, - d_mulhsu, - d_mulhu, - d_clz, - d_ctz, - d_cpop, - d_min, - d_minu, - d_max, - d_maxu, - d_sextb, - d_sexth, - d_zexth, - d_rol, - d_ror, - d_orcb, - d_rev8, - d_rori} == 59'h0; - wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[11:7]}; - wire [31:0] _aluRdEn_T = io_scoreboard_comb >> _GEN_2; - wire _io_rs2Read_valid_T_24 = d_sb | d_sh; - wire _io_rs2Read_valid_T = d_beq | d_bne; - wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[19:15]}; - wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_3; - wire _rdMark_valid_T_5 = d_lb | d_lh; - wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; - wire _io_rs2Set_valid_T_5 = d_addi | d_slti; - wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; - wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_3; - wire bruEn = - ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 - & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; - wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; - wire _alu_T_1 = d_auipc | d_addi | d_add; - wire _alu_T_2 = d_slti | d_slt; - wire _alu_T_3 = d_sltiu | d_sltu; - wire _alu_T_4 = d_xori | d_xor; - wire _alu_T_5 = d_ori | d_or; - wire _alu_T_6 = d_andi | d_and; - wire _alu_T_7 = d_slli | d_sll; - wire _alu_T_8 = d_srli | d_srl; - wire _alu_T_9 = d_srai | d_sra; - wire alu_valid = - _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 - | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop - | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb - | d_rev8 | d_zexth | d_rori; - wire bru_valid = - d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - wire [3:0] bru_bits = - d_jal - ? 4'h0 - : d_jalr - ? 4'h1 - : d_beq - ? 4'h2 - : d_bne - ? 4'h3 - : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; - wire [31:0] _bru_target_T_2 = - io_inst_bits_addr - + {{12{io_inst_bits_inst[31]}}, - io_inst_bits_inst[2] - ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} - : {{8{io_inst_bits_inst[31]}}, - io_inst_bits_inst[7], - io_inst_bits_inst[30:25], - io_inst_bits_inst[11:8]}, - 1'h0}; - wire _bxx_fault_T = bruEn & bru_valid; - wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; - wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); - wire bxx_fault = - _bxx_fault_T - & (|{bru_bits == 4'h7, - bru_bits == 4'h6, - bru_bits == 4'h5, - bru_bits == 4'h4, - bru_bits == 4'h3, - bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); - wire _io_inst_ready_T_26 = jalr_fault | jal_fault; - wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; - wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; - wire _io_rs2Read_valid_T_5 = d_add | d_sub; - wire _io_rs2Read_valid_T_18 = d_min | d_minu; - wire rdMark_valid = - alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) - | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); - wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_2; - assign io_busRead_bypass_0 = - io_inst_bits_inst[31:25] == 7'h0 - & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] - ? io_inst_bits_inst[24:20] == 5'h0 - : ~(|(io_inst_bits_inst[11:7]))); - assign io_inst_ready_0 = - (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt - | d_bge | d_bltu | d_bgeu) - & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) - & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu - | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori - | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) - & bruEn - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | io_lsu_ready - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | ~io_serializeIn_brcond) - & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] - & (_io_rs2Read_valid_T_24 | d_sw))) - & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) - & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump - & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted - & ~io_interlock & ~d_undef & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_inst_ready = io_inst_ready_0; - assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; - assign io_rs1Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol - | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); - assign io_rs1Read_addr = - io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; - assign io_rs1Set_valid = decodeEn & d_auipc; - assign io_rs1Set_value = io_inst_bits_addr; - assign io_rs2Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror - | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); - assign io_rs2Read_addr = io_inst_bits_inst[24:20]; - assign io_rs2Set_valid = - decodeEn - & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | d_lui); - assign io_rs2Set_value = - d_auipc | d_lui - ? {io_inst_bits_inst[31:12], 12'h0} - : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; - assign io_rdMark_valid = decodeEn & rdMark_valid; - assign io_rdMark_addr = io_inst_bits_inst[11:7]; - assign io_busRead_bypass = io_busRead_bypass_0; - assign io_busRead_immed = - {_d_d_imm12_T_1, - io_inst_bits_inst[31:25], - io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) - ? io_inst_bits_inst[11:7] - : io_inst_bits_inst[24:20]}; - assign io_jalFault = jal_fault; - assign io_jalrFault = jalr_fault; - assign io_bxxFault = bxx_fault; - assign io_bruTarget = _bru_target_T_2; - assign io_alu_valid = decodeEn & alu_valid; - assign io_alu_bits_addr = io_inst_bits_inst[11:7]; - assign io_alu_bits_op = - _alu_T_1 - ? 5'h0 - : d_sub - ? 5'h1 - : _alu_T_2 - ? 5'h2 - : _alu_T_3 - ? 5'h3 - : _alu_T_4 - ? 5'h4 - : _alu_T_5 - ? 5'h5 - : _alu_T_6 - ? 5'h6 - : _alu_T_7 - ? 5'h7 - : _alu_T_8 - ? 5'h8 - : _alu_T_9 - ? 5'h9 - : d_lui - ? 5'hA - : d_andn - ? 5'hB - : d_orn - ? 5'hC - : d_xnor - ? 5'hD - : d_clz - ? 5'hE - : d_ctz - ? 5'hF - : d_cpop - ? 5'h10 - : d_max - ? 5'h11 - : d_maxu - ? 5'h12 - : d_min - ? 5'h13 - : d_minu - ? 5'h14 - : d_sextb - ? 5'h15 - : d_sexth - ? 5'h16 - : d_rol - ? 5'h17 - : d_ror - ? 5'h18 - : d_orcb - ? 5'h19 - : d_rev8 - ? 5'h1A - : d_zexth - ? 5'h1B - : d_rori - ? 5'h18 - : 5'h0; - assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_bru_bits_fwd = io_inst_bits_brchFwd; - assign io_bru_bits_op = bru_bits; - assign io_bru_bits_pc = io_inst_bits_addr; - assign io_bru_bits_target = _bru_target_T_2; - assign io_bru_bits_link = io_inst_bits_inst[11:7]; - assign io_lsu_valid = decodeEn & lsu_valid; - assign io_lsu_bits_store = io_inst_bits_inst[5]; - assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; - assign io_lsu_bits_op = - d_lb - ? 5'h0 - : d_lh - ? 5'h1 - : d_lw - ? 5'h2 - : d_lbu - ? 5'h3 - : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; - assign io_lsu_bits_pc = io_inst_bits_addr; - assign io_mlu_valid = decodeEn & mlu_valid; - assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; - assign io_mlu_bits_op = - d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; - assign io_serializeOut_mul = io_serializeIn_mul | mlu_valid; - assign io_serializeOut_jump = io_serializeIn_jump | d_jal | d_jalr; - assign io_serializeOut_brcond = - io_serializeIn_brcond | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - assign io_serializeOut_wfi = io_serializeIn_wfi; - assign io_serializeOut_fence = io_serializeIn_fence; - assign io_serializeOut_csr = io_serializeIn_csr; - assign io_serializeOut_undef = io_serializeIn_undef | d_undef; + wire [2:0] _instructionBuffer_io_feedIn_nReady; + wire _instructionBuffer_io_out_0_valid; + wire [31:0] _instructionBuffer_io_out_0_bits_addr; + wire _fetcher_io_ctrl_ready; + wire _fetcher_io_fetch_valid; + wire [31:0] _fetcher_io_fetch_bits_addr; + wire [31:0] _fetcher_io_fetch_bits_inst_0; + wire [31:0] _fetcher_io_fetch_bits_inst_1; + wire [31:0] _fetcher_io_fetch_bits_inst_2; + wire [31:0] _fetcher_io_fetch_bits_inst_3; + wire _fetcher_io_fetch_bits_fault; + wire _ctrl_io_fetchData_ready; + wire _ctrl_io_fetchAddr_valid; + wire [31:0] _ctrl_io_fetchAddr_bits; + wire _ctrl_io_flushTx; + wire [2:0] _ctrl_io_bufferRequest_nValid; + wire [31:0] _ctrl_io_bufferRequest_bits_0_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_0_inst; + wire _ctrl_io_bufferRequest_bits_0_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_1_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_1_inst; + wire _ctrl_io_bufferRequest_bits_1_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_2_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_2_inst; + wire _ctrl_io_bufferRequest_bits_2_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_3_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_3_inst; + wire _ctrl_io_bufferRequest_bits_3_brchFwd; + wire branch_valid = + io_branch_0_valid | io_branch_1_valid | io_branch_2_valid | io_branch_3_valid; + reg [31:0] pc; + always @(posedge clock or posedge reset) begin + if (reset) + pc <= 32'h0; + else if (_instructionBuffer_io_out_0_valid) + pc <= _instructionBuffer_io_out_0_bits_addr; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + pc = 32'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FetchControl ctrl ( + .clock (clock), + .reset (reset), + .io_fetchFault_valid (io_fault_valid), + .io_fetchFault_bits (io_fault_bits), + .io_csr_value_0 (io_csr_value_0), + .io_iflush_valid (io_iflush_valid | io_debug_pc_valid), + .io_iflush_bits + (io_iflush_valid ? io_iflush_pcNext : io_debug_pc_valid ? io_debug_pc_bits : 32'h0), + .io_branch_valid (branch_valid), + .io_branch_bits + (io_branch_0_valid + ? io_branch_0_value + : io_branch_1_valid + ? io_branch_1_value + : io_branch_2_valid + ? io_branch_2_value + : io_branch_3_valid ? io_branch_3_value : 32'h0), + .io_fetchData_ready (_ctrl_io_fetchData_ready), + .io_fetchData_valid (_fetcher_io_fetch_valid), + .io_fetchData_bits_addr (_fetcher_io_fetch_bits_addr), + .io_fetchData_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), + .io_fetchData_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), + .io_fetchData_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), + .io_fetchData_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), + .io_fetchData_bits_fault (_fetcher_io_fetch_bits_fault), + .io_fetchAddr_ready (_fetcher_io_ctrl_ready), + .io_fetchAddr_valid (_ctrl_io_fetchAddr_valid), + .io_fetchAddr_bits (_ctrl_io_fetchAddr_bits), + .io_flushTx (_ctrl_io_flushTx), + .io_bufferRequest_nReady (_instructionBuffer_io_feedIn_nReady), + .io_bufferRequest_nValid (_ctrl_io_bufferRequest_nValid), + .io_bufferRequest_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), + .io_bufferRequest_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), + .io_bufferRequest_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_bufferRequest_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), + .io_bufferRequest_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), + .io_bufferRequest_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_bufferRequest_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), + .io_bufferRequest_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), + .io_bufferRequest_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_bufferRequest_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), + .io_bufferRequest_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), + .io_bufferRequest_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd) + ); + Fetcher fetcher ( + .clock (clock), + .reset (reset), + .io_ctrl_ready (_fetcher_io_ctrl_ready), + .io_ctrl_valid (_ctrl_io_fetchAddr_valid), + .io_ctrl_bits (_ctrl_io_fetchAddr_bits), + .io_flushTx (_ctrl_io_flushTx), + .io_fetch_ready (_ctrl_io_fetchData_ready), + .io_fetch_valid (_fetcher_io_fetch_valid), + .io_fetch_bits_addr (_fetcher_io_fetch_bits_addr), + .io_fetch_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), + .io_fetch_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), + .io_fetch_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), + .io_fetch_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), + .io_fetch_bits_fault (_fetcher_io_fetch_bits_fault), + .io_ibus_valid (io_ibus_valid), + .io_ibus_ready (io_ibus_ready), + .io_ibus_addr (io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_ibus_fault_valid (io_ibus_fault_valid) + ); + InstructionBuffer instructionBuffer ( + .clock (clock), + .reset (reset), + .io_feedIn_nReady (_instructionBuffer_io_feedIn_nReady), + .io_feedIn_nValid (_ctrl_io_bufferRequest_nValid), + .io_feedIn_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), + .io_feedIn_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), + .io_feedIn_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_feedIn_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), + .io_feedIn_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), + .io_feedIn_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_feedIn_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), + .io_feedIn_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), + .io_feedIn_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_feedIn_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), + .io_feedIn_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), + .io_feedIn_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd), + .io_out_0_ready (io_inst_lanes_0_ready), + .io_out_0_valid (_instructionBuffer_io_out_0_valid), + .io_out_0_bits_addr (_instructionBuffer_io_out_0_bits_addr), + .io_out_0_bits_inst (io_inst_lanes_0_bits_inst), + .io_out_0_bits_brchFwd (io_inst_lanes_0_bits_brchFwd), + .io_out_1_ready (io_inst_lanes_1_ready), + .io_out_1_valid (io_inst_lanes_1_valid), + .io_out_1_bits_addr (io_inst_lanes_1_bits_addr), + .io_out_1_bits_inst (io_inst_lanes_1_bits_inst), + .io_out_1_bits_brchFwd (io_inst_lanes_1_bits_brchFwd), + .io_out_2_ready (io_inst_lanes_2_ready), + .io_out_2_valid (io_inst_lanes_2_valid), + .io_out_2_bits_addr (io_inst_lanes_2_bits_addr), + .io_out_2_bits_inst (io_inst_lanes_2_bits_inst), + .io_out_2_bits_brchFwd (io_inst_lanes_2_bits_brchFwd), + .io_out_3_ready (io_inst_lanes_3_ready), + .io_out_3_valid (io_inst_lanes_3_valid), + .io_out_3_bits_addr (io_inst_lanes_3_bits_addr), + .io_out_3_bits_inst (io_inst_lanes_3_bits_inst), + .io_out_3_bits_brchFwd (io_inst_lanes_3_bits_brchFwd), + .io_flush (io_iflush_valid | branch_valid | io_debug_pc_valid), + .io_nEnqueued (/* unused */), + .io_nSpace (/* unused */) + ); + assign io_inst_lanes_0_valid = _instructionBuffer_io_out_0_valid; + assign io_inst_lanes_0_bits_addr = _instructionBuffer_io_out_0_bits_addr; + assign io_pc = pc; endmodule -module Decode_3( - input io_halted, - output io_inst_ready, - input io_inst_valid, - input [31:0] io_inst_bits_addr, - io_inst_bits_inst, - input io_inst_bits_brchFwd, - input [31:0] io_scoreboard_regd, - io_scoreboard_comb, - output io_rs1Read_valid, - output [4:0] io_rs1Read_addr, - output io_rs1Set_valid, - output [31:0] io_rs1Set_value, - output io_rs2Read_valid, - output [4:0] io_rs2Read_addr, - output io_rs2Set_valid, - output [31:0] io_rs2Set_value, - output io_rdMark_valid, - output [4:0] io_rdMark_addr, - output io_busRead_bypass, - output [31:0] io_busRead_immed, - output io_jalFault, - io_jalrFault, - io_bxxFault, - output [31:0] io_bruTarget, - input [31:0] io_jalrTarget_data, - output io_alu_valid, - output [4:0] io_alu_bits_addr, - io_alu_bits_op, - output io_bru_valid, - io_bru_bits_fwd, - output [3:0] io_bru_bits_op, - output [31:0] io_bru_bits_pc, - io_bru_bits_target, - output [4:0] io_bru_bits_link, - input io_lsu_ready, - output io_lsu_valid, - io_lsu_bits_store, - output [4:0] io_lsu_bits_addr, - io_lsu_bits_op, - output [31:0] io_lsu_bits_pc, - output io_mlu_valid, - output [4:0] io_mlu_bits_addr, - output [2:0] io_mlu_bits_op, - input io_branchTaken, - io_interlock, - io_serializeIn_mul, - io_serializeIn_jump, - io_serializeIn_brcond, - io_serializeIn_wfi, - io_serializeIn_fence, - io_serializeIn_csr, - io_serializeIn_undef +module Csr( + input clock, + reset, + input [31:0] io_csr_in_value_12, + output [31:0] io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + io_csr_out_value_8, + input io_req_valid, + input [4:0] io_req_bits_addr, + input [11:0] io_req_bits_index, + input [4:0] io_req_bits_rs1, + input [1:0] io_req_bits_op, + input [31:0] io_rs1_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + input io_bru_in_mode_valid, + io_bru_in_mcause_valid, + input [31:0] io_bru_in_mcause_bits, + input io_bru_in_mepc_valid, + input [31:0] io_bru_in_mepc_bits, + input io_bru_in_mtval_valid, + input [31:0] io_bru_in_mtval_bits, + input io_bru_in_halt, + io_bru_in_fault, + io_bru_in_wfi, + output [31:0] io_bru_out_mepc, + io_bru_out_mtvec, + output io_bru_out_interrupt, + output [31:0] io_bru_out_interrupt_cause, + input io_float_in_fflags_valid, + input [4:0] io_float_in_fflags_bits, + output [2:0] io_float_out_frm, + input io_float_dirty, + input [3:0] io_counters_nRetired, + output io_halted, + io_fault, + io_wfi, + input io_irq, + io_dm_debug_req, + io_dm_resume_req, + output io_dm_debug_mode, + io_dm_entering_debug_mode, + io_dm_single_step, + io_dm_dcsr_step, + input [31:0] io_dm_current_pc, + io_dm_next_pc, + output io_dm_debug_pc_valid, + output [31:0] io_dm_debug_pc_bits, + input io_timer_irq, + io_software_irq ); - wire io_inst_ready_0; - wire io_busRead_bypass_0; - wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; - wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; - wire d_lui = io_inst_bits_inst[6:0] == 7'h37; - wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; - wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; - wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_jalr = _GEN == 10'h67; - wire d_beq = _GEN == 10'h63; - wire d_bne = _GEN == 10'hE3; - wire d_blt = _GEN == 10'h263; - wire d_bge = _GEN == 10'h2E3; - wire d_bltu = _GEN == 10'h363; - wire d_bgeu = _GEN == 10'h3E3; - wire d_lb = _GEN == 10'h3; - wire d_lh = _GEN == 10'h83; - wire d_lw = _GEN == 10'h103; - wire d_lbu = _GEN == 10'h203; - wire d_lhu = _GEN == 10'h283; - wire d_sb = _GEN == 10'h23; - wire d_sh = _GEN == 10'hA3; - wire d_sw = _GEN == 10'h123; - wire d_addi = _GEN == 10'h13; - wire d_slti = _GEN == 10'h113; - wire d_sltiu = _GEN == 10'h193; - wire d_xori = _GEN == 10'h213; - wire d_ori = _GEN == 10'h313; - wire d_andi = _GEN == 10'h393; - wire [16:0] _GEN_0 = - {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_slli = _GEN_0 == 17'h93; - wire d_srli = _GEN_0 == 17'h293; - wire d_srai = _GEN_0 == 17'h8293; - wire d_add = _GEN_0 == 17'h33; - wire d_sub = _GEN_0 == 17'h8033; - wire d_slt = _GEN_0 == 17'h133; - wire d_sltu = _GEN_0 == 17'h1B3; - wire d_xor = _GEN_0 == 17'h233; - wire d_or = _GEN_0 == 17'h333; - wire d_and = _GEN_0 == 17'h3B3; - wire d_sll = _GEN_0 == 17'hB3; - wire d_srl = _GEN_0 == 17'h2B3; - wire d_sra = _GEN_0 == 17'h82B3; - wire d_mul = _GEN_0 == 17'h433; - wire d_mulh = _GEN_0 == 17'h4B3; - wire d_mulhsu = _GEN_0 == 17'h533; - wire d_mulhu = _GEN_0 == 17'h5B3; - wire d_andn = _GEN_0 == 17'h83B3; - wire d_orn = _GEN_0 == 17'h8333; - wire d_xnor = _GEN_0 == 17'h8233; - wire [21:0] _GEN_1 = - {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; - wire d_clz = _GEN_1 == 22'h180093; - wire d_ctz = _GEN_1 == 22'h180493; - wire d_cpop = _GEN_1 == 22'h180893; - wire d_max = _GEN_0 == 17'h1733; - wire d_maxu = _GEN_0 == 17'h17B3; - wire d_min = _GEN_0 == 17'h1633; - wire d_minu = _GEN_0 == 17'h16B3; - wire d_sextb = _GEN_1 == 22'h181093; - wire d_sexth = _GEN_1 == 22'h181493; - wire d_rol = _GEN_0 == 17'hC0B3; - wire d_ror = _GEN_0 == 17'hC2B3; - wire d_orcb = _GEN_1 == 22'hA1E93; - wire d_rev8 = _GEN_1 == 22'h1A6293; - wire d_zexth = _GEN_1 == 22'h20233; - wire d_rori = _GEN_0 == 17'hC293; - wire [31:0] _aluRdEn_T = io_scoreboard_comb >> io_inst_bits_inst[11:7]; - wire _io_rs2Read_valid_T_24 = d_sb | d_sh; - wire _io_rs2Read_valid_T = d_beq | d_bne; - wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[19:15]}; - wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_2; - wire _rdMark_valid_T_5 = d_lb | d_lh; - wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; - wire _io_rs2Set_valid_T_5 = d_addi | d_slti; - wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; - wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_2; - wire bruEn = - ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 - & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; - wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; - wire _alu_T_1 = d_auipc | d_addi | d_add; - wire _alu_T_2 = d_slti | d_slt; - wire _alu_T_3 = d_sltiu | d_sltu; - wire _alu_T_4 = d_xori | d_xor; - wire _alu_T_5 = d_ori | d_or; - wire _alu_T_6 = d_andi | d_and; - wire _alu_T_7 = d_slli | d_sll; - wire _alu_T_8 = d_srli | d_srl; - wire _alu_T_9 = d_srai | d_sra; - wire alu_valid = - _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 - | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop - | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb - | d_rev8 | d_zexth | d_rori; - wire bru_valid = - d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; - wire [3:0] bru_bits = - d_jal - ? 4'h0 - : d_jalr - ? 4'h1 - : d_beq - ? 4'h2 - : d_bne - ? 4'h3 - : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; - wire [31:0] _bru_target_T_2 = - io_inst_bits_addr - + {{12{io_inst_bits_inst[31]}}, - io_inst_bits_inst[2] - ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} - : {{8{io_inst_bits_inst[31]}}, - io_inst_bits_inst[7], - io_inst_bits_inst[30:25], - io_inst_bits_inst[11:8]}, - 1'h0}; - wire _bxx_fault_T = bruEn & bru_valid; - wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; - wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); - wire bxx_fault = - _bxx_fault_T - & (|{bru_bits == 4'h7, - bru_bits == 4'h6, - bru_bits == 4'h5, - bru_bits == 4'h4, - bru_bits == 4'h3, - bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); - wire _io_inst_ready_T_26 = jalr_fault | jal_fault; - wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; - wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; - wire _io_rs2Read_valid_T_5 = d_add | d_sub; - wire _io_rs2Read_valid_T_18 = d_min | d_minu; - assign io_busRead_bypass_0 = - io_inst_bits_inst[31:25] == 7'h0 - & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] - ? io_inst_bits_inst[24:20] == 5'h0 - : ~(|(io_inst_bits_inst[11:7]))); - assign io_inst_ready_0 = - (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt - | d_bge | d_bltu | d_bgeu) - & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) - & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu - | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu - | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori - | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) - & bruEn - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | io_lsu_ready - & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) - | ~io_serializeIn_brcond) - & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] - & (_io_rs2Read_valid_T_24 | d_sw))) - & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) - & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump - & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted - & ~io_interlock - & (|{d_lui, - d_auipc, - d_jal, - d_jalr, - d_beq, - d_bne, - d_blt, - d_bge, - d_bltu, - d_bgeu, - d_lb, - d_lh, - d_lw, - d_lbu, - d_lhu, - d_sb, - d_sh, - d_sw, - d_addi, - d_slti, - d_sltiu, - d_xori, - d_ori, - d_andi, - d_add, - d_sub, - d_slt, - d_sltu, - d_xor, - d_or, - d_and, - d_xnor, - d_orn, - d_andn, - d_slli, - d_srli, - d_srai, - d_sll, - d_srl, - d_sra, - d_mul, - d_mulh, - d_mulhsu, - d_mulhu, - d_clz, - d_ctz, - d_cpop, - d_min, - d_minu, - d_max, - d_maxu, - d_sextb, - d_sexth, - d_zexth, - d_rol, - d_ror, - d_orcb, - d_rev8, - d_rori}) & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_inst_ready = io_inst_ready_0; - assign io_rs1Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol - | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); - assign io_rs1Read_addr = - io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; - assign io_rs1Set_valid = decodeEn & d_auipc; - assign io_rs1Set_value = io_inst_bits_addr; - assign io_rs2Read_valid = - decodeEn - & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 - | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl - | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror - | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); - assign io_rs2Read_addr = io_inst_bits_inst[24:20]; - assign io_rs2Set_valid = - decodeEn - & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli - | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth - | d_zexth | d_orcb | d_rev8 | d_lui); - assign io_rs2Set_value = - d_auipc | d_lui - ? {io_inst_bits_inst[31:12], 12'h0} - : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; - assign io_rdMark_valid = - decodeEn - & (alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) - | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) - & (|(io_inst_bits_inst[11:7]))); - assign io_rdMark_addr = io_inst_bits_inst[11:7]; - assign io_busRead_bypass = io_busRead_bypass_0; - assign io_busRead_immed = - {_d_d_imm12_T_1, - io_inst_bits_inst[31:25], - io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) - ? io_inst_bits_inst[11:7] - : io_inst_bits_inst[24:20]}; - assign io_jalFault = jal_fault; - assign io_jalrFault = jalr_fault; - assign io_bxxFault = bxx_fault; - assign io_bruTarget = _bru_target_T_2; - assign io_alu_valid = decodeEn & alu_valid; - assign io_alu_bits_addr = io_inst_bits_inst[11:7]; - assign io_alu_bits_op = - _alu_T_1 - ? 5'h0 - : d_sub - ? 5'h1 - : _alu_T_2 - ? 5'h2 - : _alu_T_3 - ? 5'h3 - : _alu_T_4 - ? 5'h4 - : _alu_T_5 - ? 5'h5 - : _alu_T_6 - ? 5'h6 - : _alu_T_7 - ? 5'h7 - : _alu_T_8 - ? 5'h8 - : _alu_T_9 - ? 5'h9 - : d_lui - ? 5'hA - : d_andn - ? 5'hB - : d_orn - ? 5'hC - : d_xnor - ? 5'hD - : d_clz - ? 5'hE - : d_ctz - ? 5'hF - : d_cpop - ? 5'h10 - : d_max - ? 5'h11 - : d_maxu - ? 5'h12 - : d_min - ? 5'h13 - : d_minu - ? 5'h14 - : d_sextb - ? 5'h15 - : d_sexth - ? 5'h16 - : d_rol - ? 5'h17 - : d_ror - ? 5'h18 - : d_orcb - ? 5'h19 - : d_rev8 - ? 5'h1A - : d_zexth - ? 5'h1B - : d_rori - ? 5'h18 - : 5'h0; - assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); - assign io_bru_bits_fwd = io_inst_bits_brchFwd; - assign io_bru_bits_op = bru_bits; - assign io_bru_bits_pc = io_inst_bits_addr; - assign io_bru_bits_target = _bru_target_T_2; - assign io_bru_bits_link = io_inst_bits_inst[11:7]; - assign io_lsu_valid = decodeEn & lsu_valid; - assign io_lsu_bits_store = io_inst_bits_inst[5]; - assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; - assign io_lsu_bits_op = - d_lb - ? 5'h0 - : d_lh - ? 5'h1 - : d_lw - ? 5'h2 - : d_lbu - ? 5'h3 - : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; - assign io_lsu_bits_pc = io_inst_bits_addr; - assign io_mlu_valid = decodeEn & mlu_valid; - assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; - assign io_mlu_bits_op = - d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; + wire [3:0] _minstretThisCycle_delayed_T; + reg req_valid; + reg [4:0] req_bits_addr; + reg [11:0] req_bits_index; + reg [4:0] req_bits_rs1; + reg [1:0] req_bits_op; + reg halted; + reg fault; + reg wfi; + reg [1:0] mode; + reg [31:0] mpc; + reg [31:0] msp; + reg [31:0] mcause; + reg [31:0] mtval; + reg [31:0] mcontext0; + reg [31:0] mcontext1; + reg [31:0] mcontext2; + reg [31:0] mcontext3; + reg [31:0] mcontext4; + reg [31:0] mcontext5; + reg [31:0] mcontext6; + reg [31:0] mcontext7; + reg [3:0] dcsr_debugver; + reg [2:0] dcsr_extcause; + reg dcsr_cetrig; + reg dcsr_pelp; + reg dcsr_ebreakvs; + reg dcsr_ebreakvu; + reg dcsr_ebreakm; + reg dcsr_ebreaks; + reg dcsr_ebreaku; + reg dcsr_stepie; + reg dcsr_stopcount; + reg dcsr_stoptime; + reg [2:0] dcsr_cause; + reg dcsr_v; + reg dcsr_mprven; + reg dcsr_nmip; + reg dcsr_step; + reg [1:0] dcsr_prv; + reg [31:0] dpc; + reg [31:0] dscratch0; + reg [31:0] dscratch1; + reg [31:0] tdata1_data; + reg [31:0] tdata2; + reg [4:0] fflags; + reg [2:0] frm; + reg mstatus_mie; + reg mstatus_mpie; + reg [31:0] mie; + reg [31:0] mtvec; + reg [31:0] mscratch; + reg [31:0] mepc; + reg [63:0] mcycle; + reg [63:0] minstret; + wire [63:0] _minstret_T = minstret + {60'h0, _minstretThisCycle_delayed_T}; + reg [1:0] fs; + wire fflagsEn = req_bits_index == 12'h1; + wire frmEn = req_bits_index == 12'h2; + wire fcsrEn = req_bits_index == 12'h3; + wire mstatusEn = req_bits_index == 12'h300; + wire mieEn = req_bits_index == 12'h304; + wire mtvecEn = req_bits_index == 12'h305; + wire mscratchEn = req_bits_index == 12'h340; + wire mepcEn = req_bits_index == 12'h341; + wire mcauseEn = req_bits_index == 12'h342; + wire mtvalEn = req_bits_index == 12'h343; + wire tdata1En = req_bits_index == 12'h7A1; + wire tdata2En = req_bits_index == 12'h7A2; + wire dcsrEn = req_bits_index == 12'h7B0; + wire dpcEn = req_bits_index == 12'h7B1; + wire dscratch0En = req_bits_index == 12'h7B2; + wire dscratch1En = req_bits_index == 12'h7B3; + wire mcontext0En = req_bits_index == 12'h7C0; + wire mcontext1En = req_bits_index == 12'h7C1; + wire mcontext2En = req_bits_index == 12'h7C2; + wire mcontext3En = req_bits_index == 12'h7C3; + wire mcontext4En = req_bits_index == 12'h7C4; + wire mcontext5En = req_bits_index == 12'h7C5; + wire mcontext6En = req_bits_index == 12'h7C6; + wire mcontext7En = req_bits_index == 12'h7C7; + wire mpcEn = req_bits_index == 12'h7E0; + wire mspEn = req_bits_index == 12'h7E1; + wire mcycleEn = req_bits_index == 12'hB00; + wire minstretEn = req_bits_index == 12'hB02; + wire mcyclehEn = req_bits_index == 12'hB80; + wire minstrethEn = req_bits_index == 12'hB82; + wire mtip_pending = io_timer_irq & mie[7]; + wire meip_pending = io_irq & mie[11]; + wire msip_pending = io_software_irq & mie[3]; + wire _interrupt_pending_T = mtip_pending | meip_pending; + wire [31:0] rdata = + (fflagsEn ? {27'h0, fflags} : 32'h0) | (frmEn ? {29'h0, frm} : 32'h0) + | (fcsrEn ? {24'h0, frm, fflags} : 32'h0) + | (mstatusEn ? {&fs, 16'h0, fs, 5'h18, mstatus_mpie, 3'h0, mstatus_mie, 3'h0} : 32'h0) + | (req_bits_index == 12'h301 ? 32'h40801120 : 32'h0) | (mieEn ? mie : 32'h0) + | (req_bits_index == 12'h344 + ? {20'h0, io_irq, 3'h0, io_timer_irq, 3'h0, io_software_irq, 3'h0} + : 32'h0) | (mtvecEn ? mtvec : 32'h0) | (mscratchEn ? mscratch : 32'h0) + | (mepcEn ? mepc : 32'h0) | (mcauseEn ? mcause : 32'h0) | (mtvalEn ? mtval : 32'h0) + | (mcontext0En ? mcontext0 : 32'h0) | (mcontext1En ? mcontext1 : 32'h0) + | (mcontext2En ? mcontext2 : 32'h0) | (mcontext3En ? mcontext3 : 32'h0) + | (mcontext4En ? mcontext4 : 32'h0) | (mcontext5En ? mcontext5 : 32'h0) + | (mcontext6En ? mcontext6 : 32'h0) | (mcontext7En ? mcontext7 : 32'h0) + | (mpcEn ? mpc : 32'h0) | (mspEn ? msp : 32'h0) | (mcycleEn ? mcycle[31:0] : 32'h0) + | (minstretEn ? _minstret_T[31:0] : 32'h0) + | (req_bits_index == 12'hF11 ? 32'h426 : 32'h0) + | (req_bits_index == 12'hFC4 ? 32'hB0A08695 : 32'h0) + | (req_bits_index == 12'hFC8 ? 32'hC110D9F4 : 32'h0) + | (req_bits_index == 12'hFCC ? 32'h907B6CDE : 32'h0) + | (req_bits_index == 12'hFD0 ? 32'h6925576B : 32'h0) + | (req_bits_index == 12'hFD4 ? 32'hB50B85A9 : 32'h0) + | (mcyclehEn ? mcycle[63:32] : 32'h0) | (minstrethEn ? _minstret_T[63:32] : 32'h0) + | (tdata1En ? tdata1_data : 32'h0) | (tdata2En ? tdata2 : 32'h0) + | (req_bits_index == 12'h7A4 ? 32'h1000040 : 32'h0) + | (dcsrEn + ? {dcsr_debugver, + 1'h0, + dcsr_extcause, + 4'h0, + dcsr_cetrig, + dcsr_pelp, + dcsr_ebreakvs, + dcsr_ebreakvu, + dcsr_ebreakm, + 1'h0, + dcsr_ebreaks, + dcsr_ebreaku, + dcsr_stepie, + dcsr_stopcount, + dcsr_stoptime, + dcsr_cause, + dcsr_v, + dcsr_mprven, + dcsr_nmip, + dcsr_step, + dcsr_prv} + : 32'h0) | (dpcEn ? dpc : 32'h0) | (dscratch0En ? dscratch0 : 32'h0) + | (dscratch1En ? dscratch1 : 32'h0); + wire [31:0] _trace_data_T_19 = ~io_rs1_data; + wire [31:0] wdata = + req_bits_op == 2'h2 + ? rdata & _trace_data_T_19 + : req_bits_op == 2'h1 ? rdata | io_rs1_data : (|req_bits_op) ? 32'h0 : io_rs1_data; + wire [31:0] mtvec_w = + {req_bits_op == 2'h2 + ? mtvec[31:2] & _trace_data_T_19[31:2] + : req_bits_op == 2'h1 + ? mtvec[31:2] | io_rs1_data[31:2] + : (|req_bits_op) ? 30'h0 : io_rs1_data[31:2], + 2'h0}; + wire [2:0] _GEN = _trace_data_T_19[2:0] & frm; + wire [7:0] _GEN_0 = _trace_data_T_19[7:0] & {frm, fflags}; + reg minstret_written_delayed; + assign _minstretThisCycle_delayed_T = + minstret_written_delayed ? 4'h0 : io_counters_nRetired; + wire trigger_enabled = tdata1_data[31:28] == 4'h6 & tdata1_data[6]; + wire trigger_match = trigger_enabled & io_dm_current_pc == tdata2; + wire entering_debug_mode = mode != 2'h2 & (io_dm_debug_req | trigger_match); + wire in_debug = mode == 2'h2; + wire _io_dm_debug_pc_T = req_valid & dpcEn; + wire io_dm_debug_pc_valid_0 = _io_dm_debug_pc_T & in_debug; + wire is_csr_write = + req_valid & ~((|{req_bits_op == 2'h2, req_bits_op == 2'h1}) & req_bits_rs1 == 5'h0); + wire mstatus_write_fs = is_csr_write & mstatusEn; + wire [7:0] fcsr_w = + req_bits_op == 2'h2 + ? _GEN_0 + : req_bits_op == 2'h1 + ? {frm, fflags} | io_rs1_data[7:0] + : (|req_bits_op) ? 8'h0 : io_rs1_data[7:0]; + wire minstret_written = is_csr_write & (minstretEn | minstrethEn); + wire [2:0] newCause = + io_dm_debug_req & ~dcsr_step ? 3'h3 : trigger_match ? 3'h2 : dcsr_step ? 3'h4 : 3'h7; + wire _dcsr_T = req_valid & dcsrEn; + always @(posedge clock or posedge reset) begin + if (reset) begin + req_valid <= 1'h0; + req_bits_addr <= 5'h0; + req_bits_index <= 12'h0; + req_bits_rs1 <= 5'h0; + req_bits_op <= 2'h0; + halted <= 1'h0; + fault <= 1'h0; + wfi <= 1'h0; + mode <= 2'h0; + mpc <= 32'h0; + msp <= 32'h0; + mcause <= 32'h0; + mtval <= 32'h0; + mcontext0 <= 32'h0; + mcontext1 <= 32'h0; + mcontext2 <= 32'h0; + mcontext3 <= 32'h0; + mcontext4 <= 32'h0; + mcontext5 <= 32'h0; + mcontext6 <= 32'h0; + mcontext7 <= 32'h0; + dcsr_debugver <= 4'h0; + dcsr_extcause <= 3'h0; + dcsr_cetrig <= 1'h0; + dcsr_pelp <= 1'h0; + dcsr_ebreakvs <= 1'h0; + dcsr_ebreakvu <= 1'h0; + dcsr_ebreakm <= 1'h0; + dcsr_ebreaks <= 1'h0; + dcsr_ebreaku <= 1'h0; + dcsr_stepie <= 1'h0; + dcsr_stopcount <= 1'h0; + dcsr_stoptime <= 1'h0; + dcsr_cause <= 3'h0; + dcsr_v <= 1'h0; + dcsr_mprven <= 1'h0; + dcsr_nmip <= 1'h0; + dcsr_step <= 1'h0; + dcsr_prv <= 2'h0; + dpc <= 32'h0; + dscratch0 <= 32'h0; + dscratch1 <= 32'h0; + tdata1_data <= 32'h60000000; + tdata2 <= 32'h0; + fflags <= 5'h0; + frm <= 3'h0; + mstatus_mie <= 1'h0; + mstatus_mpie <= 1'h0; + mie <= 32'h0; + mtvec <= 32'h0; + mscratch <= 32'h0; + mepc <= 32'h0; + mcycle <= 64'h0; + minstret <= 64'h0; + fs <= 2'h1; + minstret_written_delayed <= 1'h0; + end + else begin + req_valid <= io_req_valid; + if (io_req_valid) begin + req_bits_addr <= io_req_bits_addr; + req_bits_index <= io_req_bits_index; + req_bits_rs1 <= io_req_bits_rs1; + req_bits_op <= io_req_bits_op; + end + halted <= io_bru_in_halt | halted; + fault <= io_bru_in_fault | fault; + if (wfi) + wfi <= ~(_interrupt_pending_T | msip_pending | io_dm_debug_req); + else + wfi <= io_bru_in_wfi; + if (entering_debug_mode) begin + mode <= 2'h2; + dcsr_extcause <= 3'h0; + dcsr_cause <= newCause; + dcsr_prv <= 2'h3; + end + else begin + if (in_debug & io_dm_resume_req | io_bru_in_mode_valid) + mode <= 2'h0; + if (_dcsr_T) begin + dcsr_extcause <= wdata[21:19]; + dcsr_cause <= wdata[8:6]; + dcsr_prv <= wdata[1:0]; + end + end + if (req_valid & mpcEn) + mpc <= wdata; + if (req_valid & mspEn) + msp <= wdata; + if (io_bru_in_mcause_valid) + mcause <= io_bru_in_mcause_bits; + else if (req_valid & mcauseEn) + mcause <= wdata; + if (io_bru_in_mtval_valid) + mtval <= io_bru_in_mtval_bits; + else if (req_valid & mtvalEn) + mtval <= wdata; + if (req_valid & mcontext0En) + mcontext0 <= wdata; + if (req_valid & mcontext1En) + mcontext1 <= wdata; + if (req_valid & mcontext2En) + mcontext2 <= wdata; + if (req_valid & mcontext3En) + mcontext3 <= wdata; + if (req_valid & mcontext4En) + mcontext4 <= wdata; + if (req_valid & mcontext5En) + mcontext5 <= wdata; + if (req_valid & mcontext6En) + mcontext6 <= wdata; + if (req_valid & mcontext7En) + mcontext7 <= wdata; + if (entering_debug_mode | ~_dcsr_T) begin + end + else begin + dcsr_debugver <= wdata[25:22]; + dcsr_cetrig <= wdata[18]; + dcsr_pelp <= wdata[17]; + dcsr_ebreakvs <= wdata[16]; + dcsr_ebreakvu <= wdata[15]; + dcsr_ebreakm <= wdata[14]; + dcsr_ebreaks <= wdata[13]; + dcsr_ebreaku <= wdata[12]; + dcsr_stepie <= wdata[11]; + dcsr_stopcount <= wdata[10]; + dcsr_stoptime <= wdata[9]; + dcsr_v <= wdata[5]; + dcsr_mprven <= wdata[4]; + dcsr_nmip <= wdata[3]; + dcsr_step <= wdata[2]; + end + if (_io_dm_debug_pc_T) + dpc <= wdata; + else if (entering_debug_mode) + dpc <= newCause == 3'h4 ? io_dm_next_pc : io_dm_current_pc; + if (req_valid & dscratch0En) + dscratch0 <= wdata; + if (req_valid & dscratch1En) + dscratch1 <= wdata; + if (req_valid & tdata1En) + tdata1_data <= + {4'h6, wdata[27], 14'h0, wdata[12], 5'h0, wdata[6], 3'h0, wdata[2], 2'h0}; + if (req_valid & tdata2En) + tdata2 <= wdata; + fflags <= + {5{io_float_in_fflags_valid}} + & (io_float_in_fflags_valid ? io_float_in_fflags_bits : 5'h0) + | (req_valid ? (fcsrEn ? fcsr_w[4:0] : fflagsEn ? wdata[4:0] : fflags) : fflags); + if (req_valid) begin + if (fcsrEn) + frm <= fcsr_w[7:5]; + else if (frmEn) + frm <= + req_bits_op == 2'h2 + ? _GEN + : req_bits_op == 2'h1 + ? frm | io_rs1_data[2:0] + : (|req_bits_op) ? 3'h0 : io_rs1_data[2:0]; + end + mstatus_mie <= + io_bru_in_mode_valid + ? mstatus_mpie + : ~io_bru_in_mcause_valid & (mstatus_write_fs ? wdata[3] : mstatus_mie); + mstatus_mpie <= + io_bru_in_mode_valid + | (io_bru_in_mcause_valid + ? mstatus_mie + : mstatus_write_fs ? wdata[7] : mstatus_mpie); + if (req_valid & mieEn) + mie <= {20'h0, wdata[11:3] & 9'h111, 3'h0}; + if (req_valid & mtvecEn) + mtvec <= mtvec_w; + if (req_valid & mscratchEn) + mscratch <= wdata; + if (io_bru_in_mepc_valid) + mepc <= {io_bru_in_mepc_bits[31:2], 2'h0}; + else if (req_valid & mepcEn) + mepc <= + {req_bits_op == 2'h2 + ? mepc[31:2] & _trace_data_T_19[31:2] + : req_bits_op == 2'h1 + ? mepc[31:2] | io_rs1_data[31:2] + : (|req_bits_op) ? 30'h0 : io_rs1_data[31:2], + 2'h0}; + mcycle <= + is_csr_write & (mcycleEn | mcyclehEn) + ? {mcyclehEn ? wdata : mcycle[63:32], mcycleEn ? wdata : mcycle[31:0]} + : mcycle + 64'h1; + minstret <= + minstret_written + ? {minstrethEn ? wdata : minstret[63:32], minstretEn ? wdata : minstret[31:0]} + : _minstret_T; + fs <= + (mstatus_write_fs ? (wdata[14:13] == 2'h0 ? 2'h3 : wdata[14:13]) : fs) + | {2{is_csr_write & (fflagsEn | frmEn | fcsrEn) | io_float_in_fflags_valid + | io_float_dirty}}; + minstret_written_delayed <= minstret_written; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + req_valid = 1'h0; + req_bits_addr = 5'h0; + req_bits_index = 12'h0; + req_bits_rs1 = 5'h0; + req_bits_op = 2'h0; + halted = 1'h0; + fault = 1'h0; + wfi = 1'h0; + mode = 2'h0; + mpc = 32'h0; + msp = 32'h0; + mcause = 32'h0; + mtval = 32'h0; + mcontext0 = 32'h0; + mcontext1 = 32'h0; + mcontext2 = 32'h0; + mcontext3 = 32'h0; + mcontext4 = 32'h0; + mcontext5 = 32'h0; + mcontext6 = 32'h0; + mcontext7 = 32'h0; + dcsr_debugver = 4'h0; + dcsr_extcause = 3'h0; + dcsr_cetrig = 1'h0; + dcsr_pelp = 1'h0; + dcsr_ebreakvs = 1'h0; + dcsr_ebreakvu = 1'h0; + dcsr_ebreakm = 1'h0; + dcsr_ebreaks = 1'h0; + dcsr_ebreaku = 1'h0; + dcsr_stepie = 1'h0; + dcsr_stopcount = 1'h0; + dcsr_stoptime = 1'h0; + dcsr_cause = 3'h0; + dcsr_v = 1'h0; + dcsr_mprven = 1'h0; + dcsr_nmip = 1'h0; + dcsr_step = 1'h0; + dcsr_prv = 2'h0; + dpc = 32'h0; + dscratch0 = 32'h0; + dscratch1 = 32'h0; + tdata1_data = 32'h60000000; + tdata2 = 32'h0; + fflags = 5'h0; + frm = 3'h0; + mstatus_mie = 1'h0; + mstatus_mpie = 1'h0; + mie = 32'h0; + mtvec = 32'h0; + mscratch = 32'h0; + mepc = 32'h0; + mcycle = 64'h0; + minstret = 64'h0; + fs = 2'h1; + minstret_written_delayed = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_csr_out_value_0 = io_csr_in_value_12; + assign io_csr_out_value_1 = mepc; + assign io_csr_out_value_2 = mtval; + assign io_csr_out_value_3 = mcause; + assign io_csr_out_value_4 = mcycle[31:0]; + assign io_csr_out_value_5 = mcycle[63:32]; + assign io_csr_out_value_6 = minstret[31:0]; + assign io_csr_out_value_7 = minstret[63:32]; + assign io_csr_out_value_8 = mcontext0; + assign io_rd_valid = req_valid; + assign io_rd_bits_addr = req_bits_addr; + assign io_rd_bits_data = rdata; + assign io_bru_out_mepc = + mepcEn & req_valid + ? {req_bits_op == 2'h2 + ? mepc[31:2] & _trace_data_T_19[31:2] + : req_bits_op == 2'h1 + ? mepc[31:2] | io_rs1_data[31:2] + : (|req_bits_op) ? 30'h0 : io_rs1_data[31:2], + 2'h0} + : mepc; + assign io_bru_out_mtvec = mtvecEn & req_valid ? mtvec_w : mtvec; + assign io_bru_out_interrupt = + (_interrupt_pending_T | msip_pending) & mstatus_mie & mode != 2'h2; + assign io_bru_out_interrupt_cause = + meip_pending + ? 32'h8000000B + : msip_pending ? 32'h80000003 : mtip_pending ? 32'h80000007 : 32'h0; + assign io_float_out_frm = + frmEn & req_valid + ? (req_bits_op == 2'h2 + ? _GEN + : req_bits_op == 2'h1 + ? frm | io_rs1_data[2:0] + : (|req_bits_op) ? 3'h0 : io_rs1_data[2:0]) + : fcsrEn & req_valid + ? (req_bits_op == 2'h2 + ? _GEN_0[7:5] + : req_bits_op == 2'h1 + ? frm | io_rs1_data[7:5] + : (|req_bits_op) ? 3'h0 : io_rs1_data[7:5]) + : frm; + assign io_halted = halted; + assign io_fault = fault; + assign io_wfi = wfi; + assign io_dm_debug_mode = in_debug; + assign io_dm_entering_debug_mode = entering_debug_mode; + assign io_dm_single_step = trigger_enabled; + assign io_dm_dcsr_step = dcsr_step; + assign io_dm_debug_pc_valid = io_dm_debug_pc_valid_0; + assign io_dm_debug_pc_bits = io_dm_debug_pc_valid_0 ? wdata : 32'h0; endmodule -module DispatchV1( +module DispatchV2( input io_halted, io_lsuActive, input [31:0] io_scoreboard_regd, @@ -5619,29 +5394,24 @@ module DispatchV1( output [4:0] io_rdMark_2_addr, output io_rdMark_3_valid, output [4:0] io_rdMark_3_addr, - output io_busRead_0_bypass, - io_busRead_0_immen, output [31:0] io_busRead_0_immed, - output io_busRead_1_bypass, - output [31:0] io_busRead_1_immed, - output io_busRead_2_bypass, - output [31:0] io_busRead_2_immed, - output io_busRead_3_bypass, - output [31:0] io_busRead_3_immed, + io_busRead_1_immed, + io_busRead_2_immed, + io_busRead_3_immed, output io_rdMark_flt_valid, output [4:0] io_rdMark_flt_addr, output io_alu_0_valid, output [4:0] io_alu_0_bits_addr, - io_alu_0_bits_op, + output [5:0] io_alu_0_bits_op, output io_alu_1_valid, output [4:0] io_alu_1_bits_addr, - io_alu_1_bits_op, + output [5:0] io_alu_1_bits_op, output io_alu_2_valid, output [4:0] io_alu_2_bits_addr, - io_alu_2_bits_op, + output [5:0] io_alu_2_bits_op, output io_alu_3_valid, output [4:0] io_alu_3_bits_addr, - io_alu_3_bits_op, + output [5:0] io_alu_3_bits_op, output io_bru_0_valid, io_bru_0_bits_fwd, output [3:0] io_bru_0_bits_op, @@ -5669,6 +5439,7 @@ module DispatchV1( output io_csr_valid, output [4:0] io_csr_bits_addr, output [11:0] io_csr_bits_index, + output [4:0] io_csr_bits_rs1, output [1:0] io_csr_bits_op, input io_lsu_0_ready, output io_lsu_0_valid, @@ -5694,27 +5465,33 @@ module DispatchV1( output [4:0] io_lsu_3_bits_addr, io_lsu_3_bits_op, output [31:0] io_lsu_3_bits_pc, + input [2:0] io_lsuQueueCapacity, output io_mlu_0_valid, output [4:0] io_mlu_0_bits_addr, output [2:0] io_mlu_0_bits_op, + input io_mlu_1_ready, output io_mlu_1_valid, output [4:0] io_mlu_1_bits_addr, output [2:0] io_mlu_1_bits_op, + input io_mlu_2_ready, output io_mlu_2_valid, output [4:0] io_mlu_2_bits_addr, output [2:0] io_mlu_2_bits_op, + input io_mlu_3_ready, output io_mlu_3_valid, output [4:0] io_mlu_3_bits_addr, output [2:0] io_mlu_3_bits_op, input io_dvu_0_ready, output io_dvu_0_valid, output [4:0] io_dvu_0_bits_addr, - output [1:0] io_dvu_0_bits_op, + output [2:0] io_dvu_0_bits_op, input io_float_ready, output io_float_valid, output [2:0] io_float_bits_opcode, output [4:0] io_float_bits_funct5, - io_float_bits_rs3, + output [2:0] io_float_bits_src_fmt, + io_float_bits_dst_fmt, + output [4:0] io_float_bits_rs3, io_float_bits_rs2, io_float_bits_rs1, output [2:0] io_float_bits_rm, @@ -5722,3475 +5499,11171 @@ module DispatchV1( io_float_bits_pc, output io_float_bits_scalar_rd, io_float_bits_scalar_rs1, + io_float_bits_float_rs1, output [4:0] io_float_bits_rd, output io_float_bits_uses_rs3, io_float_bits_uses_rs2, + input [2:0] io_csrFrm, output [4:0] io_fbusPortAddr, - output io_slog + input [4:0] io_retirement_buffer_nSpace, + input io_retirement_buffer_empty, + io_retirement_buffer_trap_pending, + io_single_step, + output io_branch_0, + io_branch_1, + io_branch_2, + io_branch_3, + io_jump_0, + io_jump_1, + io_jump_2, + io_jump_3 ); - wire _decode_3_io_inst_ready; - wire _decode_3_io_jalFault; - wire _decode_3_io_jalrFault; - wire _decode_3_io_bxxFault; - wire _decode_2_io_inst_ready; - wire [31:0] _decode_2_io_scoreboard_spec; - wire _decode_2_io_jalFault; - wire _decode_2_io_jalrFault; - wire _decode_2_io_bxxFault; - wire _decode_2_io_serializeOut_mul; - wire _decode_2_io_serializeOut_jump; - wire _decode_2_io_serializeOut_brcond; - wire _decode_2_io_serializeOut_wfi; - wire _decode_2_io_serializeOut_fence; - wire _decode_2_io_serializeOut_csr; - wire _decode_2_io_serializeOut_undef; - wire _decode_1_io_inst_ready; - wire [31:0] _decode_1_io_scoreboard_spec; - wire _decode_1_io_jalFault; - wire _decode_1_io_jalrFault; - wire _decode_1_io_bxxFault; - wire _decode_1_io_serializeOut_mul; - wire _decode_1_io_serializeOut_jump; - wire _decode_1_io_serializeOut_brcond; - wire _decode_1_io_serializeOut_wfi; - wire _decode_1_io_serializeOut_fence; - wire _decode_1_io_serializeOut_csr; - wire _decode_1_io_serializeOut_undef; - wire _decode_0_io_inst_ready; - wire [31:0] _decode_0_io_scoreboard_spec; - wire _decode_0_io_jalFault; - wire _decode_0_io_jalrFault; - wire _decode_0_io_bxxFault; - wire _decode_0_io_undefFault; - wire _decode_0_io_csrFault; - wire _decode_0_io_serializeOut_mul; - wire _decode_0_io_serializeOut_jump; - wire _decode_0_io_serializeOut_brcond; - wire _decode_0_io_serializeOut_wfi; - wire _decode_0_io_serializeOut_fence; - wire _decode_0_io_serializeOut_csr; - wire _decode_0_io_serializeOut_undef; - wire mask_2 = _decode_0_io_inst_ready & _decode_1_io_inst_ready; - wire mask_3 = mask_2 & _decode_2_io_inst_ready; - wire decode_1_io_inst_valid = io_inst_1_valid & _decode_0_io_inst_ready; - wire decode_2_io_inst_valid = io_inst_2_valid & mask_2; - wire decode_3_io_inst_valid = io_inst_3_valid & mask_3; - wire [31:0] scoreboard_spec_2 = - _decode_0_io_scoreboard_spec | _decode_1_io_scoreboard_spec; - wire [31:0] scoreboard_spec_3 = scoreboard_spec_2 | _decode_2_io_scoreboard_spec; - Decode decode_0 ( - .io_halted (io_halted), - .io_inst_ready (_decode_0_io_inst_ready), - .io_inst_valid (io_inst_0_valid), - .io_inst_bits_addr (io_inst_0_bits_addr), - .io_inst_bits_inst (io_inst_0_bits_inst), - .io_inst_bits_brchFwd (io_inst_0_bits_brchFwd), - .io_scoreboard_regd (io_scoreboard_regd), - .io_scoreboard_comb (io_scoreboard_comb), - .io_scoreboard_spec (_decode_0_io_scoreboard_spec), - .io_fscoreboard (io_fscoreboard), - .io_lsuActive (io_lsuActive), - .io_rs1Read_valid (io_rs1Read_0_valid), - .io_rs1Read_addr (io_rs1Read_0_addr), - .io_rs1Set_valid (io_rs1Set_0_valid), - .io_rs1Set_value (io_rs1Set_0_value), - .io_rs2Read_valid (io_rs2Read_0_valid), - .io_rs2Read_addr (io_rs2Read_0_addr), - .io_rs2Set_valid (io_rs2Set_0_valid), - .io_rs2Set_value (io_rs2Set_0_value), - .io_rdMark_valid (io_rdMark_0_valid), - .io_rdMark_addr (io_rdMark_0_addr), - .io_rdMark_flt_valid (io_rdMark_flt_valid), - .io_rdMark_flt_addr (io_rdMark_flt_addr), - .io_busRead_bypass (io_busRead_0_bypass), - .io_busRead_immen (io_busRead_0_immen), - .io_busRead_immed (io_busRead_0_immed), - .io_jalFault (_decode_0_io_jalFault), - .io_jalrFault (_decode_0_io_jalrFault), - .io_bxxFault (_decode_0_io_bxxFault), - .io_undefFault (_decode_0_io_undefFault), - .io_bruTarget (io_bruTarget_0), - .io_jalrTarget_data (io_jalrTarget_0_data), - .io_alu_valid (io_alu_0_valid), - .io_alu_bits_addr (io_alu_0_bits_addr), - .io_alu_bits_op (io_alu_0_bits_op), - .io_bru_valid (io_bru_0_valid), - .io_bru_bits_fwd (io_bru_0_bits_fwd), - .io_bru_bits_op (io_bru_0_bits_op), - .io_bru_bits_pc (io_bru_0_bits_pc), - .io_bru_bits_target (io_bru_0_bits_target), - .io_bru_bits_link (io_bru_0_bits_link), - .io_csr_valid (io_csr_valid), - .io_csr_bits_addr (io_csr_bits_addr), - .io_csr_bits_index (io_csr_bits_index), - .io_csr_bits_op (io_csr_bits_op), - .io_csrFault (_decode_0_io_csrFault), - .io_lsu_ready (io_lsu_0_ready), - .io_lsu_valid (io_lsu_0_valid), - .io_lsu_bits_store (io_lsu_0_bits_store), - .io_lsu_bits_addr (io_lsu_0_bits_addr), - .io_lsu_bits_op (io_lsu_0_bits_op), - .io_lsu_bits_pc (io_lsu_0_bits_pc), - .io_mlu_valid (io_mlu_0_valid), - .io_mlu_bits_addr (io_mlu_0_bits_addr), - .io_mlu_bits_op (io_mlu_0_bits_op), - .io_dvu_ready (io_dvu_0_ready), - .io_dvu_valid (io_dvu_0_valid), - .io_dvu_bits_addr (io_dvu_0_bits_addr), - .io_dvu_bits_op (io_dvu_0_bits_op), - .io_float_ready (io_float_ready), - .io_float_valid (io_float_valid), - .io_float_bits_opcode (io_float_bits_opcode), - .io_float_bits_funct5 (io_float_bits_funct5), - .io_float_bits_rs3 (io_float_bits_rs3), - .io_float_bits_rs2 (io_float_bits_rs2), - .io_float_bits_rs1 (io_float_bits_rs1), - .io_float_bits_rm (io_float_bits_rm), - .io_float_bits_inst (io_float_bits_inst), - .io_float_bits_pc (io_float_bits_pc), - .io_float_bits_scalar_rd (io_float_bits_scalar_rd), - .io_float_bits_scalar_rs1 (io_float_bits_scalar_rs1), - .io_float_bits_rd (io_float_bits_rd), - .io_float_bits_uses_rs3 (io_float_bits_uses_rs3), - .io_float_bits_uses_rs2 (io_float_bits_uses_rs2), - .io_branchTaken (io_branchTaken), - .io_interlock (io_interlock), - .io_serializeOut_mul (_decode_0_io_serializeOut_mul), - .io_serializeOut_jump (_decode_0_io_serializeOut_jump), - .io_serializeOut_brcond (_decode_0_io_serializeOut_brcond), - .io_serializeOut_wfi (_decode_0_io_serializeOut_wfi), - .io_serializeOut_fence (_decode_0_io_serializeOut_fence), - .io_serializeOut_csr (_decode_0_io_serializeOut_csr), - .io_serializeOut_undef (_decode_0_io_serializeOut_undef), - .io_slog (io_slog) - ); - Decode_1 decode_1 ( - .io_halted (io_halted), - .io_inst_ready (_decode_1_io_inst_ready), - .io_inst_valid (decode_1_io_inst_valid), - .io_inst_bits_addr (io_inst_1_bits_addr), - .io_inst_bits_inst (io_inst_1_bits_inst), - .io_inst_bits_brchFwd (io_inst_1_bits_brchFwd), - .io_scoreboard_regd (io_scoreboard_regd | _decode_0_io_scoreboard_spec), - .io_scoreboard_comb (io_scoreboard_comb | _decode_0_io_scoreboard_spec), - .io_scoreboard_spec (_decode_1_io_scoreboard_spec), - .io_rs1Read_valid (io_rs1Read_1_valid), - .io_rs1Read_addr (io_rs1Read_1_addr), - .io_rs1Set_valid (io_rs1Set_1_valid), - .io_rs1Set_value (io_rs1Set_1_value), - .io_rs2Read_valid (io_rs2Read_1_valid), - .io_rs2Read_addr (io_rs2Read_1_addr), - .io_rs2Set_valid (io_rs2Set_1_valid), - .io_rs2Set_value (io_rs2Set_1_value), - .io_rdMark_valid (io_rdMark_1_valid), - .io_rdMark_addr (io_rdMark_1_addr), - .io_busRead_bypass (io_busRead_1_bypass), - .io_busRead_immed (io_busRead_1_immed), - .io_jalFault (_decode_1_io_jalFault), - .io_jalrFault (_decode_1_io_jalrFault), - .io_bxxFault (_decode_1_io_bxxFault), - .io_bruTarget (io_bruTarget_1), - .io_jalrTarget_data (io_jalrTarget_1_data), - .io_alu_valid (io_alu_1_valid), - .io_alu_bits_addr (io_alu_1_bits_addr), - .io_alu_bits_op (io_alu_1_bits_op), - .io_bru_valid (io_bru_1_valid), - .io_bru_bits_fwd (io_bru_1_bits_fwd), - .io_bru_bits_op (io_bru_1_bits_op), - .io_bru_bits_pc (io_bru_1_bits_pc), - .io_bru_bits_target (io_bru_1_bits_target), - .io_bru_bits_link (io_bru_1_bits_link), - .io_lsu_ready (io_lsu_1_ready), - .io_lsu_valid (io_lsu_1_valid), - .io_lsu_bits_store (io_lsu_1_bits_store), - .io_lsu_bits_addr (io_lsu_1_bits_addr), - .io_lsu_bits_op (io_lsu_1_bits_op), - .io_lsu_bits_pc (io_lsu_1_bits_pc), - .io_mlu_valid (io_mlu_1_valid), - .io_mlu_bits_addr (io_mlu_1_bits_addr), - .io_mlu_bits_op (io_mlu_1_bits_op), - .io_branchTaken (io_branchTaken), - .io_interlock (io_interlock), - .io_serializeIn_mul (_decode_0_io_serializeOut_mul), - .io_serializeIn_jump (_decode_0_io_serializeOut_jump), - .io_serializeIn_brcond (_decode_0_io_serializeOut_brcond), - .io_serializeIn_wfi (_decode_0_io_serializeOut_wfi), - .io_serializeIn_fence (_decode_0_io_serializeOut_fence), - .io_serializeIn_csr (_decode_0_io_serializeOut_csr), - .io_serializeIn_undef (_decode_0_io_serializeOut_undef), - .io_serializeOut_mul (_decode_1_io_serializeOut_mul), - .io_serializeOut_jump (_decode_1_io_serializeOut_jump), - .io_serializeOut_brcond (_decode_1_io_serializeOut_brcond), - .io_serializeOut_wfi (_decode_1_io_serializeOut_wfi), - .io_serializeOut_fence (_decode_1_io_serializeOut_fence), - .io_serializeOut_csr (_decode_1_io_serializeOut_csr), - .io_serializeOut_undef (_decode_1_io_serializeOut_undef) - ); - Decode_2 decode_2 ( - .io_halted (io_halted), - .io_inst_ready (_decode_2_io_inst_ready), - .io_inst_valid (decode_2_io_inst_valid), - .io_inst_bits_addr (io_inst_2_bits_addr), - .io_inst_bits_inst (io_inst_2_bits_inst), - .io_inst_bits_brchFwd (io_inst_2_bits_brchFwd), - .io_scoreboard_regd (io_scoreboard_regd | scoreboard_spec_2), - .io_scoreboard_comb (io_scoreboard_comb | scoreboard_spec_2), - .io_scoreboard_spec (_decode_2_io_scoreboard_spec), - .io_rs1Read_valid (io_rs1Read_2_valid), - .io_rs1Read_addr (io_rs1Read_2_addr), - .io_rs1Set_valid (io_rs1Set_2_valid), - .io_rs1Set_value (io_rs1Set_2_value), - .io_rs2Read_valid (io_rs2Read_2_valid), - .io_rs2Read_addr (io_rs2Read_2_addr), - .io_rs2Set_valid (io_rs2Set_2_valid), - .io_rs2Set_value (io_rs2Set_2_value), - .io_rdMark_valid (io_rdMark_2_valid), - .io_rdMark_addr (io_rdMark_2_addr), - .io_busRead_bypass (io_busRead_2_bypass), - .io_busRead_immed (io_busRead_2_immed), - .io_jalFault (_decode_2_io_jalFault), - .io_jalrFault (_decode_2_io_jalrFault), - .io_bxxFault (_decode_2_io_bxxFault), - .io_bruTarget (io_bruTarget_2), - .io_jalrTarget_data (io_jalrTarget_2_data), - .io_alu_valid (io_alu_2_valid), - .io_alu_bits_addr (io_alu_2_bits_addr), - .io_alu_bits_op (io_alu_2_bits_op), - .io_bru_valid (io_bru_2_valid), - .io_bru_bits_fwd (io_bru_2_bits_fwd), - .io_bru_bits_op (io_bru_2_bits_op), - .io_bru_bits_pc (io_bru_2_bits_pc), - .io_bru_bits_target (io_bru_2_bits_target), - .io_bru_bits_link (io_bru_2_bits_link), - .io_lsu_ready (io_lsu_2_ready), - .io_lsu_valid (io_lsu_2_valid), - .io_lsu_bits_store (io_lsu_2_bits_store), - .io_lsu_bits_addr (io_lsu_2_bits_addr), - .io_lsu_bits_op (io_lsu_2_bits_op), - .io_lsu_bits_pc (io_lsu_2_bits_pc), - .io_mlu_valid (io_mlu_2_valid), - .io_mlu_bits_addr (io_mlu_2_bits_addr), - .io_mlu_bits_op (io_mlu_2_bits_op), - .io_branchTaken (io_branchTaken), - .io_interlock (io_interlock), - .io_serializeIn_mul (_decode_1_io_serializeOut_mul), - .io_serializeIn_jump (_decode_1_io_serializeOut_jump), - .io_serializeIn_brcond (_decode_1_io_serializeOut_brcond), - .io_serializeIn_wfi (_decode_1_io_serializeOut_wfi), - .io_serializeIn_fence (_decode_1_io_serializeOut_fence), - .io_serializeIn_csr (_decode_1_io_serializeOut_csr), - .io_serializeIn_undef (_decode_1_io_serializeOut_undef), - .io_serializeOut_mul (_decode_2_io_serializeOut_mul), - .io_serializeOut_jump (_decode_2_io_serializeOut_jump), - .io_serializeOut_brcond (_decode_2_io_serializeOut_brcond), - .io_serializeOut_wfi (_decode_2_io_serializeOut_wfi), - .io_serializeOut_fence (_decode_2_io_serializeOut_fence), - .io_serializeOut_csr (_decode_2_io_serializeOut_csr), - .io_serializeOut_undef (_decode_2_io_serializeOut_undef) - ); - Decode_3 decode_3 ( - .io_halted (io_halted), - .io_inst_ready (_decode_3_io_inst_ready), - .io_inst_valid (decode_3_io_inst_valid), - .io_inst_bits_addr (io_inst_3_bits_addr), - .io_inst_bits_inst (io_inst_3_bits_inst), - .io_inst_bits_brchFwd (io_inst_3_bits_brchFwd), - .io_scoreboard_regd (io_scoreboard_regd | scoreboard_spec_3), - .io_scoreboard_comb (io_scoreboard_comb | scoreboard_spec_3), - .io_rs1Read_valid (io_rs1Read_3_valid), - .io_rs1Read_addr (io_rs1Read_3_addr), - .io_rs1Set_valid (io_rs1Set_3_valid), - .io_rs1Set_value (io_rs1Set_3_value), - .io_rs2Read_valid (io_rs2Read_3_valid), - .io_rs2Read_addr (io_rs2Read_3_addr), - .io_rs2Set_valid (io_rs2Set_3_valid), - .io_rs2Set_value (io_rs2Set_3_value), - .io_rdMark_valid (io_rdMark_3_valid), - .io_rdMark_addr (io_rdMark_3_addr), - .io_busRead_bypass (io_busRead_3_bypass), - .io_busRead_immed (io_busRead_3_immed), - .io_jalFault (_decode_3_io_jalFault), - .io_jalrFault (_decode_3_io_jalrFault), - .io_bxxFault (_decode_3_io_bxxFault), - .io_bruTarget (io_bruTarget_3), - .io_jalrTarget_data (io_jalrTarget_3_data), - .io_alu_valid (io_alu_3_valid), - .io_alu_bits_addr (io_alu_3_bits_addr), - .io_alu_bits_op (io_alu_3_bits_op), - .io_bru_valid (io_bru_3_valid), - .io_bru_bits_fwd (io_bru_3_bits_fwd), - .io_bru_bits_op (io_bru_3_bits_op), - .io_bru_bits_pc (io_bru_3_bits_pc), - .io_bru_bits_target (io_bru_3_bits_target), - .io_bru_bits_link (io_bru_3_bits_link), - .io_lsu_ready (io_lsu_3_ready), - .io_lsu_valid (io_lsu_3_valid), - .io_lsu_bits_store (io_lsu_3_bits_store), - .io_lsu_bits_addr (io_lsu_3_bits_addr), - .io_lsu_bits_op (io_lsu_3_bits_op), - .io_lsu_bits_pc (io_lsu_3_bits_pc), - .io_mlu_valid (io_mlu_3_valid), - .io_mlu_bits_addr (io_mlu_3_bits_addr), - .io_mlu_bits_op (io_mlu_3_bits_op), - .io_branchTaken (io_branchTaken), - .io_interlock (io_interlock), - .io_serializeIn_mul (_decode_2_io_serializeOut_mul), - .io_serializeIn_jump (_decode_2_io_serializeOut_jump), - .io_serializeIn_brcond (_decode_2_io_serializeOut_brcond), - .io_serializeIn_wfi (_decode_2_io_serializeOut_wfi), - .io_serializeIn_fence (_decode_2_io_serializeOut_fence), - .io_serializeIn_csr (_decode_2_io_serializeOut_csr), - .io_serializeIn_undef (_decode_2_io_serializeOut_undef) - ); - assign io_csrFault_0 = _decode_0_io_csrFault & ~io_branchTaken & io_inst_0_valid; - assign io_jalFault_0 = _decode_0_io_jalFault & ~io_branchTaken & io_inst_0_valid; - assign io_jalFault_1 = _decode_1_io_jalFault & ~io_branchTaken & decode_1_io_inst_valid; - assign io_jalFault_2 = _decode_2_io_jalFault & ~io_branchTaken & decode_2_io_inst_valid; - assign io_jalFault_3 = _decode_3_io_jalFault & ~io_branchTaken & decode_3_io_inst_valid; - assign io_jalrFault_0 = _decode_0_io_jalrFault & ~io_branchTaken & io_inst_0_valid; - assign io_jalrFault_1 = - _decode_1_io_jalrFault & ~io_branchTaken & decode_1_io_inst_valid; - assign io_jalrFault_2 = - _decode_2_io_jalrFault & ~io_branchTaken & decode_2_io_inst_valid; - assign io_jalrFault_3 = - _decode_3_io_jalrFault & ~io_branchTaken & decode_3_io_inst_valid; - assign io_bxxFault_0 = _decode_0_io_bxxFault & ~io_branchTaken & io_inst_0_valid; - assign io_bxxFault_1 = _decode_1_io_bxxFault & ~io_branchTaken & decode_1_io_inst_valid; - assign io_bxxFault_2 = _decode_2_io_bxxFault & ~io_branchTaken & decode_2_io_inst_valid; - assign io_bxxFault_3 = _decode_3_io_bxxFault & ~io_branchTaken & decode_3_io_inst_valid; - assign io_undefFault_0 = _decode_0_io_undefFault & ~io_branchTaken & io_inst_0_valid; - assign io_inst_0_ready = _decode_0_io_inst_ready; - assign io_inst_1_ready = _decode_1_io_inst_ready & _decode_0_io_inst_ready; - assign io_inst_2_ready = _decode_2_io_inst_ready & mask_2; - assign io_inst_3_ready = _decode_3_io_inst_ready & mask_3; + wire [19:0] _decodedInsts_d_imm12_T_1 = {20{io_inst_0_bits_inst[31]}}; + wire decodedInsts_0_fencetso = io_inst_0_bits_inst == 32'h8330000F; + wire decodedInsts_0_fencei = io_inst_0_bits_inst == 32'h100F; + wire decodedInsts_0_wfi = io_inst_0_bits_inst == 32'h10500073; + wire decodedInsts_0_mret = io_inst_0_bits_inst == 32'h30200073; + wire decodedInsts_0_mpause = io_inst_0_bits_inst == 32'h8000073; + wire decodedInsts_0_ecall = io_inst_0_bits_inst == 32'h73; + wire decodedInsts_0_ebreak = io_inst_0_bits_inst == 32'h100073; + wire [16:0] _GEN = + {io_inst_0_bits_inst[31:25], io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_rori = _GEN == 17'hC293; + wire [21:0] _GEN_0 = + {io_inst_0_bits_inst[31:20], io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_zexth = _GEN_0 == 22'h20233; + wire decodedInsts_0_rev8 = _GEN_0 == 22'h1A6293; + wire decodedInsts_0_orcb = _GEN_0 == 22'hA1E93; + wire decodedInsts_0_ror = _GEN == 17'hC2B3; + wire decodedInsts_0_rol = _GEN == 17'hC0B3; + wire decodedInsts_0_sexth = _GEN_0 == 22'h181493; + wire decodedInsts_0_sextb = _GEN_0 == 22'h181093; + wire decodedInsts_0_minu = _GEN == 17'h16B3; + wire decodedInsts_0_min = _GEN == 17'h1633; + wire decodedInsts_0_maxu = _GEN == 17'h17B3; + wire decodedInsts_0_max = _GEN == 17'h1733; + wire decodedInsts_0_cpop = _GEN_0 == 22'h180893; + wire decodedInsts_0_ctz = _GEN_0 == 22'h180493; + wire decodedInsts_0_clz = _GEN_0 == 22'h180093; + wire decodedInsts_0_xnor = _GEN == 17'h8233; + wire decodedInsts_0_orn = _GEN == 17'h8333; + wire decodedInsts_0_andn = _GEN == 17'h83B3; + wire decodedInsts_0_remu = _GEN == 17'h7B3; + wire decodedInsts_0_rem = _GEN == 17'h733; + wire decodedInsts_0_divu = _GEN == 17'h6B3; + wire decodedInsts_0_div = _GEN == 17'h633; + wire decodedInsts_0_mulhu = _GEN == 17'h5B3; + wire decodedInsts_0_mulhsu = _GEN == 17'h533; + wire decodedInsts_0_mulh = _GEN == 17'h4B3; + wire decodedInsts_0_mul = _GEN == 17'h433; + wire decodedInsts_0_sra = _GEN == 17'h82B3; + wire decodedInsts_0_srl = _GEN == 17'h2B3; + wire decodedInsts_0_sll = _GEN == 17'hB3; + wire decodedInsts_0_and = _GEN == 17'h3B3; + wire decodedInsts_0_or = _GEN == 17'h333; + wire decodedInsts_0_xor = _GEN == 17'h233; + wire decodedInsts_0_sltu = _GEN == 17'h1B3; + wire decodedInsts_0_slt = _GEN == 17'h133; + wire decodedInsts_0_sub = _GEN == 17'h8033; + wire decodedInsts_0_add = _GEN == 17'h33; + wire decodedInsts_0_srai = _GEN == 17'h8293; + wire decodedInsts_0_srli = _GEN == 17'h293; + wire decodedInsts_0_slli = _GEN == 17'h93; + wire [9:0] _GEN_1 = {io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_andi = _GEN_1 == 10'h393; + wire decodedInsts_0_ori = _GEN_1 == 10'h313; + wire decodedInsts_0_xori = _GEN_1 == 10'h213; + wire decodedInsts_0_sltiu = _GEN_1 == 10'h193; + wire decodedInsts_0_slti = _GEN_1 == 10'h113; + wire decodedInsts_0_addi = _GEN_1 == 10'h13; + wire decodedInsts_0_fence = + {io_inst_0_bits_inst[31:28], io_inst_0_bits_inst[19:0]} == 24'hF; + wire decodedInsts_0_sw = _GEN_1 == 10'h123; + wire decodedInsts_0_sh = _GEN_1 == 10'hA3; + wire decodedInsts_0_sb = _GEN_1 == 10'h23; + wire decodedInsts_0_lhu = _GEN_1 == 10'h283; + wire decodedInsts_0_lbu = _GEN_1 == 10'h203; + wire decodedInsts_0_lw = _GEN_1 == 10'h103; + wire decodedInsts_0_lh = _GEN_1 == 10'h83; + wire decodedInsts_0_lb = _GEN_1 == 10'h3; + wire [8:0] _GEN_2 = {io_inst_0_bits_inst[13:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_csrrc = _GEN_2 == 9'h1F3; + wire decodedInsts_0_csrrs = _GEN_2 == 9'h173; + wire decodedInsts_0_csrrw = _GEN_2 == 9'hF3; + wire decodedInsts_0_bgeu = _GEN_1 == 10'h3E3; + wire decodedInsts_0_bltu = _GEN_1 == 10'h363; + wire decodedInsts_0_bge = _GEN_1 == 10'h2E3; + wire decodedInsts_0_blt = _GEN_1 == 10'h263; + wire decodedInsts_0_bne = _GEN_1 == 10'hE3; + wire decodedInsts_0_beq = _GEN_1 == 10'h63; + wire decodedInsts_0_jalr = _GEN_1 == 10'h67; + wire decodedInsts_0_jal = io_inst_0_bits_inst[6:0] == 7'h6F; + wire decodedInsts_0_auipc = io_inst_0_bits_inst[6:0] == 7'h17; + wire decodedInsts_0_lui = io_inst_0_bits_inst[6:0] == 7'h37; + wire decodedInsts_float_load_store_rm_valid = + io_inst_0_bits_inst[14:12] == 3'h1 | io_inst_0_bits_inst[14:12] == 3'h2; + wire _decodedInsts_float_opcode_T_4 = io_inst_0_bits_inst[6:2] == 5'h9; + wire _decodedInsts_float_opcode_T_6 = io_inst_0_bits_inst[6:2] == 5'h14; + wire _decodedInsts_float_opcode_T_8 = io_inst_0_bits_inst[6:2] == 5'h10; + wire _decodedInsts_float_opcode_T_10 = io_inst_0_bits_inst[6:2] == 5'h11; + wire _decodedInsts_float_opcode_T_12 = io_inst_0_bits_inst[6:2] == 5'h12; + wire _decodedInsts_float_opcode_T_14 = io_inst_0_bits_inst[6:2] == 5'h13; + wire [2:0] io_float_bits_opcode_0 = + _decodedInsts_float_opcode_T_14 + ? 3'h5 + : _decodedInsts_float_opcode_T_12 + ? 3'h6 + : _decodedInsts_float_opcode_T_10 + ? 3'h4 + : _decodedInsts_float_opcode_T_8 + ? 3'h3 + : _decodedInsts_float_opcode_T_6 + ? 3'h2 + : {2'h0, + _decodedInsts_float_opcode_T_4 + & decodedInsts_float_load_store_rm_valid}; + wire _decodedInsts_float_uses_rs2_T_20 = io_inst_0_bits_inst[31:27] == 5'h8; + wire decodedInsts_float_fcvt_s_bf16 = + _decodedInsts_float_uses_rs2_T_20 & io_inst_0_bits_inst[24:20] == 5'h6 + & ~(|(io_inst_0_bits_inst[26:25])); + wire _decodedInsts_float_fmv_h_T_5 = io_inst_0_bits_inst[26:25] == 2'h2; + wire decodedInsts_float_fcvt_bf16_s = + _decodedInsts_float_uses_rs2_T_20 & io_inst_0_bits_inst[24:20] == 5'h8 + & _decodedInsts_float_fmv_h_T_5; + wire _decodedInsts_float_uses_rs2_T_14 = io_inst_0_bits_inst[31:27] == 5'h1E; + wire _decodedInsts_float_uses_rs2_T_10 = io_inst_0_bits_inst[31:27] == 5'h1C; + wire _decodedInsts_float_uses_rs2_T_12 = io_inst_0_bits_inst[31:27] == 5'h18; + wire _decodedInsts_float_uses_rs2_T_7 = io_float_bits_opcode_0 == 3'h2; + wire decodedInsts_float_scalar_rd = + (_decodedInsts_float_uses_rs2_T_12 | _decodedInsts_float_uses_rs2_T_10 + | io_inst_0_bits_inst[31:27] == 5'h14) & _decodedInsts_float_uses_rs2_T_7; + wire _decodedInsts_float_uses_rs2_T_16 = io_inst_0_bits_inst[31:27] == 5'h1A; + wire decodedInsts_float_scalar_rs1 = + _decodedInsts_float_uses_rs2_T_16 | _decodedInsts_float_uses_rs2_T_14; + wire _decodedInsts_float_uses_rs2_WIRE_1 = io_float_bits_opcode_0 == 3'h3; + wire _decodedInsts_float_uses_rs2_WIRE_2 = io_float_bits_opcode_0 == 3'h4; + wire _decodedInsts_float_uses_rs2_WIRE_3 = io_float_bits_opcode_0 == 3'h5; + wire _decodedInsts_float_uses_rs2_WIRE_4 = io_float_bits_opcode_0 == 3'h6; + wire [3:0] _decodedInsts_float_uses_rs3_T_4 = + {_decodedInsts_float_uses_rs2_WIRE_4, + _decodedInsts_float_uses_rs2_WIRE_3, + _decodedInsts_float_uses_rs2_WIRE_2, + _decodedInsts_float_uses_rs2_WIRE_1}; + wire _decodedInsts_float_float_rs1_WIRE_0 = io_float_bits_opcode_0 == 3'h1; + wire decodedInsts_float_uses_rs2 = + (|{_decodedInsts_float_uses_rs2_WIRE_4, + _decodedInsts_float_uses_rs2_WIRE_3, + _decodedInsts_float_uses_rs2_WIRE_2, + _decodedInsts_float_uses_rs2_WIRE_1, + _decodedInsts_float_float_rs1_WIRE_0}) | _decodedInsts_float_uses_rs2_T_7 + & ~(_decodedInsts_float_uses_rs2_T_20 | io_inst_0_bits_inst[31:27] == 5'hB + | _decodedInsts_float_uses_rs2_T_16 | _decodedInsts_float_uses_rs2_T_14 + | _decodedInsts_float_uses_rs2_T_12 | _decodedInsts_float_uses_rs2_T_10) + & io_inst_0_bits_inst[31:27] != 5'h1C; + wire decodedInsts_float_float_rs1 = + {~(|io_float_bits_opcode_0), _decodedInsts_float_float_rs1_WIRE_0} == 2'h0 + & ~decodedInsts_float_scalar_rs1; + wire decodedInsts_floatValid = + (_decodedInsts_float_opcode_T_14 | _decodedInsts_float_opcode_T_12 + | _decodedInsts_float_opcode_T_10 | _decodedInsts_float_opcode_T_8 + | _decodedInsts_float_opcode_T_6 + | (_decodedInsts_float_opcode_T_4 | io_inst_0_bits_inst[6:2] == 5'h1) + & decodedInsts_float_load_store_rm_valid) + & (~(|io_float_bits_opcode_0) | _decodedInsts_float_float_rs1_WIRE_0 + | ~(|(io_inst_0_bits_inst[26:25])) | decodedInsts_float_fcvt_s_bf16 + | decodedInsts_float_fcvt_bf16_s + | (_decodedInsts_float_uses_rs2_T_14 | _decodedInsts_float_uses_rs2_T_10) + & io_inst_0_bits_inst[24:20] == 5'h0 & _decodedInsts_float_fmv_h_T_5 + & io_inst_0_bits_inst[14:12] == 3'h0) + & (~((|{io_float_bits_opcode_0 == 3'h5, + io_float_bits_opcode_0 == 3'h6, + io_float_bits_opcode_0 == 3'h4, + io_float_bits_opcode_0 == 3'h3}) | io_float_bits_opcode_0 == 3'h2 + & (io_inst_0_bits_inst[31:27] == 5'h0 | io_inst_0_bits_inst[31:27] == 5'h1 + | io_inst_0_bits_inst[31:27] == 5'h2 | io_inst_0_bits_inst[31:27] == 5'h3 + | io_inst_0_bits_inst[31:27] == 5'h4 | io_inst_0_bits_inst[31:27] == 5'h1A)) + | io_inst_0_bits_inst[14:12] < 3'h5 | (&(io_inst_0_bits_inst[14:12])) + & io_csrFrm < 3'h5); + wire [19:0] _decodedInsts_d_imm12_T_5 = {20{io_inst_1_bits_inst[31]}}; + wire [16:0] _GEN_3 = + {io_inst_1_bits_inst[31:25], io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_rori = _GEN_3 == 17'hC293; + wire [21:0] _GEN_4 = + {io_inst_1_bits_inst[31:20], io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_zexth = _GEN_4 == 22'h20233; + wire decodedInsts_1_rev8 = _GEN_4 == 22'h1A6293; + wire decodedInsts_1_orcb = _GEN_4 == 22'hA1E93; + wire decodedInsts_1_ror = _GEN_3 == 17'hC2B3; + wire decodedInsts_1_rol = _GEN_3 == 17'hC0B3; + wire decodedInsts_1_sexth = _GEN_4 == 22'h181493; + wire decodedInsts_1_sextb = _GEN_4 == 22'h181093; + wire decodedInsts_1_minu = _GEN_3 == 17'h16B3; + wire decodedInsts_1_min = _GEN_3 == 17'h1633; + wire decodedInsts_1_maxu = _GEN_3 == 17'h17B3; + wire decodedInsts_1_max = _GEN_3 == 17'h1733; + wire decodedInsts_1_cpop = _GEN_4 == 22'h180893; + wire decodedInsts_1_ctz = _GEN_4 == 22'h180493; + wire decodedInsts_1_clz = _GEN_4 == 22'h180093; + wire decodedInsts_1_xnor = _GEN_3 == 17'h8233; + wire decodedInsts_1_orn = _GEN_3 == 17'h8333; + wire decodedInsts_1_andn = _GEN_3 == 17'h83B3; + wire decodedInsts_1_mulhu = _GEN_3 == 17'h5B3; + wire decodedInsts_1_mulhsu = _GEN_3 == 17'h533; + wire decodedInsts_1_mulh = _GEN_3 == 17'h4B3; + wire decodedInsts_1_mul = _GEN_3 == 17'h433; + wire decodedInsts_1_sra = _GEN_3 == 17'h82B3; + wire decodedInsts_1_srl = _GEN_3 == 17'h2B3; + wire decodedInsts_1_sll = _GEN_3 == 17'hB3; + wire decodedInsts_1_and = _GEN_3 == 17'h3B3; + wire decodedInsts_1_or = _GEN_3 == 17'h333; + wire decodedInsts_1_xor = _GEN_3 == 17'h233; + wire decodedInsts_1_sltu = _GEN_3 == 17'h1B3; + wire decodedInsts_1_slt = _GEN_3 == 17'h133; + wire decodedInsts_1_sub = _GEN_3 == 17'h8033; + wire decodedInsts_1_add = _GEN_3 == 17'h33; + wire decodedInsts_1_srai = _GEN_3 == 17'h8293; + wire decodedInsts_1_srli = _GEN_3 == 17'h293; + wire decodedInsts_1_slli = _GEN_3 == 17'h93; + wire [9:0] _GEN_5 = {io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_andi = _GEN_5 == 10'h393; + wire decodedInsts_1_ori = _GEN_5 == 10'h313; + wire decodedInsts_1_xori = _GEN_5 == 10'h213; + wire decodedInsts_1_sltiu = _GEN_5 == 10'h193; + wire decodedInsts_1_slti = _GEN_5 == 10'h113; + wire decodedInsts_1_addi = _GEN_5 == 10'h13; + wire decodedInsts_1_sw = _GEN_5 == 10'h123; + wire decodedInsts_1_sh = _GEN_5 == 10'hA3; + wire decodedInsts_1_sb = _GEN_5 == 10'h23; + wire decodedInsts_1_lhu = _GEN_5 == 10'h283; + wire decodedInsts_1_lbu = _GEN_5 == 10'h203; + wire decodedInsts_1_lw = _GEN_5 == 10'h103; + wire decodedInsts_1_lh = _GEN_5 == 10'h83; + wire decodedInsts_1_lb = _GEN_5 == 10'h3; + wire decodedInsts_1_bgeu = _GEN_5 == 10'h3E3; + wire decodedInsts_1_bltu = _GEN_5 == 10'h363; + wire decodedInsts_1_bge = _GEN_5 == 10'h2E3; + wire decodedInsts_1_blt = _GEN_5 == 10'h263; + wire decodedInsts_1_bne = _GEN_5 == 10'hE3; + wire decodedInsts_1_beq = _GEN_5 == 10'h63; + wire decodedInsts_1_jalr = _GEN_5 == 10'h67; + wire decodedInsts_1_jal = io_inst_1_bits_inst[6:0] == 7'h6F; + wire decodedInsts_1_auipc = io_inst_1_bits_inst[6:0] == 7'h17; + wire decodedInsts_1_lui = io_inst_1_bits_inst[6:0] == 7'h37; + wire [19:0] _decodedInsts_d_imm12_T_9 = {20{io_inst_2_bits_inst[31]}}; + wire [16:0] _GEN_6 = + {io_inst_2_bits_inst[31:25], io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_rori = _GEN_6 == 17'hC293; + wire [21:0] _GEN_7 = + {io_inst_2_bits_inst[31:20], io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_zexth = _GEN_7 == 22'h20233; + wire decodedInsts_2_rev8 = _GEN_7 == 22'h1A6293; + wire decodedInsts_2_orcb = _GEN_7 == 22'hA1E93; + wire decodedInsts_2_ror = _GEN_6 == 17'hC2B3; + wire decodedInsts_2_rol = _GEN_6 == 17'hC0B3; + wire decodedInsts_2_sexth = _GEN_7 == 22'h181493; + wire decodedInsts_2_sextb = _GEN_7 == 22'h181093; + wire decodedInsts_2_minu = _GEN_6 == 17'h16B3; + wire decodedInsts_2_min = _GEN_6 == 17'h1633; + wire decodedInsts_2_maxu = _GEN_6 == 17'h17B3; + wire decodedInsts_2_max = _GEN_6 == 17'h1733; + wire decodedInsts_2_cpop = _GEN_7 == 22'h180893; + wire decodedInsts_2_ctz = _GEN_7 == 22'h180493; + wire decodedInsts_2_clz = _GEN_7 == 22'h180093; + wire decodedInsts_2_xnor = _GEN_6 == 17'h8233; + wire decodedInsts_2_orn = _GEN_6 == 17'h8333; + wire decodedInsts_2_andn = _GEN_6 == 17'h83B3; + wire decodedInsts_2_mulhu = _GEN_6 == 17'h5B3; + wire decodedInsts_2_mulhsu = _GEN_6 == 17'h533; + wire decodedInsts_2_mulh = _GEN_6 == 17'h4B3; + wire decodedInsts_2_mul = _GEN_6 == 17'h433; + wire decodedInsts_2_sra = _GEN_6 == 17'h82B3; + wire decodedInsts_2_srl = _GEN_6 == 17'h2B3; + wire decodedInsts_2_sll = _GEN_6 == 17'hB3; + wire decodedInsts_2_and = _GEN_6 == 17'h3B3; + wire decodedInsts_2_or = _GEN_6 == 17'h333; + wire decodedInsts_2_xor = _GEN_6 == 17'h233; + wire decodedInsts_2_sltu = _GEN_6 == 17'h1B3; + wire decodedInsts_2_slt = _GEN_6 == 17'h133; + wire decodedInsts_2_sub = _GEN_6 == 17'h8033; + wire decodedInsts_2_add = _GEN_6 == 17'h33; + wire decodedInsts_2_srai = _GEN_6 == 17'h8293; + wire decodedInsts_2_srli = _GEN_6 == 17'h293; + wire decodedInsts_2_slli = _GEN_6 == 17'h93; + wire [9:0] _GEN_8 = {io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_andi = _GEN_8 == 10'h393; + wire decodedInsts_2_ori = _GEN_8 == 10'h313; + wire decodedInsts_2_xori = _GEN_8 == 10'h213; + wire decodedInsts_2_sltiu = _GEN_8 == 10'h193; + wire decodedInsts_2_slti = _GEN_8 == 10'h113; + wire decodedInsts_2_addi = _GEN_8 == 10'h13; + wire decodedInsts_2_sw = _GEN_8 == 10'h123; + wire decodedInsts_2_sh = _GEN_8 == 10'hA3; + wire decodedInsts_2_sb = _GEN_8 == 10'h23; + wire decodedInsts_2_lhu = _GEN_8 == 10'h283; + wire decodedInsts_2_lbu = _GEN_8 == 10'h203; + wire decodedInsts_2_lw = _GEN_8 == 10'h103; + wire decodedInsts_2_lh = _GEN_8 == 10'h83; + wire decodedInsts_2_lb = _GEN_8 == 10'h3; + wire decodedInsts_2_bgeu = _GEN_8 == 10'h3E3; + wire decodedInsts_2_bltu = _GEN_8 == 10'h363; + wire decodedInsts_2_bge = _GEN_8 == 10'h2E3; + wire decodedInsts_2_blt = _GEN_8 == 10'h263; + wire decodedInsts_2_bne = _GEN_8 == 10'hE3; + wire decodedInsts_2_beq = _GEN_8 == 10'h63; + wire decodedInsts_2_jalr = _GEN_8 == 10'h67; + wire decodedInsts_2_jal = io_inst_2_bits_inst[6:0] == 7'h6F; + wire decodedInsts_2_auipc = io_inst_2_bits_inst[6:0] == 7'h17; + wire decodedInsts_2_lui = io_inst_2_bits_inst[6:0] == 7'h37; + wire [19:0] _decodedInsts_d_imm12_T_13 = {20{io_inst_3_bits_inst[31]}}; + wire [16:0] _GEN_9 = + {io_inst_3_bits_inst[31:25], io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_rori = _GEN_9 == 17'hC293; + wire [21:0] _GEN_10 = + {io_inst_3_bits_inst[31:20], io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_zexth = _GEN_10 == 22'h20233; + wire decodedInsts_3_rev8 = _GEN_10 == 22'h1A6293; + wire decodedInsts_3_orcb = _GEN_10 == 22'hA1E93; + wire decodedInsts_3_ror = _GEN_9 == 17'hC2B3; + wire decodedInsts_3_rol = _GEN_9 == 17'hC0B3; + wire decodedInsts_3_sexth = _GEN_10 == 22'h181493; + wire decodedInsts_3_sextb = _GEN_10 == 22'h181093; + wire decodedInsts_3_minu = _GEN_9 == 17'h16B3; + wire decodedInsts_3_min = _GEN_9 == 17'h1633; + wire decodedInsts_3_maxu = _GEN_9 == 17'h17B3; + wire decodedInsts_3_max = _GEN_9 == 17'h1733; + wire decodedInsts_3_cpop = _GEN_10 == 22'h180893; + wire decodedInsts_3_ctz = _GEN_10 == 22'h180493; + wire decodedInsts_3_clz = _GEN_10 == 22'h180093; + wire decodedInsts_3_xnor = _GEN_9 == 17'h8233; + wire decodedInsts_3_orn = _GEN_9 == 17'h8333; + wire decodedInsts_3_andn = _GEN_9 == 17'h83B3; + wire decodedInsts_3_mulhu = _GEN_9 == 17'h5B3; + wire decodedInsts_3_mulhsu = _GEN_9 == 17'h533; + wire decodedInsts_3_mulh = _GEN_9 == 17'h4B3; + wire decodedInsts_3_mul = _GEN_9 == 17'h433; + wire decodedInsts_3_sra = _GEN_9 == 17'h82B3; + wire decodedInsts_3_srl = _GEN_9 == 17'h2B3; + wire decodedInsts_3_sll = _GEN_9 == 17'hB3; + wire decodedInsts_3_and = _GEN_9 == 17'h3B3; + wire decodedInsts_3_or = _GEN_9 == 17'h333; + wire decodedInsts_3_xor = _GEN_9 == 17'h233; + wire decodedInsts_3_sltu = _GEN_9 == 17'h1B3; + wire decodedInsts_3_slt = _GEN_9 == 17'h133; + wire decodedInsts_3_sub = _GEN_9 == 17'h8033; + wire decodedInsts_3_add = _GEN_9 == 17'h33; + wire decodedInsts_3_srai = _GEN_9 == 17'h8293; + wire decodedInsts_3_srli = _GEN_9 == 17'h293; + wire decodedInsts_3_slli = _GEN_9 == 17'h93; + wire [9:0] _GEN_11 = {io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_andi = _GEN_11 == 10'h393; + wire decodedInsts_3_ori = _GEN_11 == 10'h313; + wire decodedInsts_3_xori = _GEN_11 == 10'h213; + wire decodedInsts_3_sltiu = _GEN_11 == 10'h193; + wire decodedInsts_3_slti = _GEN_11 == 10'h113; + wire decodedInsts_3_addi = _GEN_11 == 10'h13; + wire decodedInsts_3_sw = _GEN_11 == 10'h123; + wire decodedInsts_3_sh = _GEN_11 == 10'hA3; + wire decodedInsts_3_sb = _GEN_11 == 10'h23; + wire decodedInsts_3_lhu = _GEN_11 == 10'h283; + wire decodedInsts_3_lbu = _GEN_11 == 10'h203; + wire decodedInsts_3_lw = _GEN_11 == 10'h103; + wire decodedInsts_3_lh = _GEN_11 == 10'h83; + wire decodedInsts_3_lb = _GEN_11 == 10'h3; + wire decodedInsts_3_bgeu = _GEN_11 == 10'h3E3; + wire decodedInsts_3_bltu = _GEN_11 == 10'h363; + wire decodedInsts_3_bge = _GEN_11 == 10'h2E3; + wire decodedInsts_3_blt = _GEN_11 == 10'h263; + wire decodedInsts_3_bne = _GEN_11 == 10'hE3; + wire decodedInsts_3_beq = _GEN_11 == 10'h63; + wire decodedInsts_3_jalr = _GEN_11 == 10'h67; + wire decodedInsts_3_jal = io_inst_3_bits_inst[6:0] == 7'h6F; + wire decodedInsts_3_auipc = io_inst_3_bits_inst[6:0] == 7'h17; + wire decodedInsts_3_lui = io_inst_3_bits_inst[6:0] == 7'h37; + wire _bru_defaultSel_T = decodedInsts_0_jal | decodedInsts_0_jalr; + wire _slot0Interlock_T_44 = decodedInsts_0_fencei | decodedInsts_0_ebreak; + wire isJump_0 = + _bru_defaultSel_T | decodedInsts_0_ecall | decodedInsts_0_mpause | decodedInsts_0_mret + | _slot0Interlock_T_44 | decodedInsts_0_wfi; + wire isJump_1 = decodedInsts_1_jal | decodedInsts_1_jalr; + wire isJump_2 = decodedInsts_2_jal | decodedInsts_2_jalr; + wire jumped_2 = isJump_0 | isJump_1; + wire _io_rs2Read_0_valid_T_1 = decodedInsts_0_beq | decodedInsts_0_bne; + wire isBranch_0 = + _io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu; + wire _io_rs2Read_1_valid_T_1 = decodedInsts_1_beq | decodedInsts_1_bne; + wire isBranch_1 = + _io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu; + wire _io_rs2Read_2_valid_T_1 = decodedInsts_2_beq | decodedInsts_2_bne; + wire isBranch_2 = + _io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu; + wire _io_rs2Read_3_valid_T_1 = decodedInsts_3_beq | decodedInsts_3_bne; + wire branched_2 = isBranch_0 | isBranch_1; + wire _io_rs2Read_0_valid_T_32 = decodedInsts_0_sb | decodedInsts_0_sh; + wire _writesFloatRd_T = decodedInsts_floatValid & decodedInsts_float_scalar_rd; + wire _io_rs2Read_1_valid_T_32 = decodedInsts_1_sb | decodedInsts_1_sh; + wire _io_rs2Read_2_valid_T_32 = decodedInsts_2_sb | decodedInsts_2_sh; + wire _io_rs2Read_3_valid_T_32 = decodedInsts_3_sb | decodedInsts_3_sh; + wire [31:0] _GEN_12 = {27'h0, io_inst_0_bits_inst[11:7]}; + wire [31:0] rdScoreboard_0 = + ~(_io_rs2Read_0_valid_T_32 | decodedInsts_0_sw) + & ~(_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu) | _writesFloatRd_T + ? 32'h1 << _GEN_12 + : 32'h0; + wire [31:0] rdScoreboard_1 = + _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw | _io_rs2Read_1_valid_T_1 + | decodedInsts_1_blt | decodedInsts_1_bge | decodedInsts_1_bltu | decodedInsts_1_bgeu + ? 32'h0 + : 32'h1 << io_inst_1_bits_inst[11:7]; + wire [31:0] rdScoreboard_2 = + _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw | _io_rs2Read_2_valid_T_1 + | decodedInsts_2_blt | decodedInsts_2_bge | decodedInsts_2_bltu | decodedInsts_2_bgeu + ? 32'h0 + : 32'h1 << io_inst_2_bits_inst[11:7]; + wire [31:0] scoreboardScan_2 = rdScoreboard_0 | rdScoreboard_1; + wire [31:0] scoreboardScan_3 = scoreboardScan_2 | rdScoreboard_2; + wire [31:0] comb_1 = rdScoreboard_0 | io_scoreboard_comb; + wire [31:0] comb_2 = scoreboardScan_2 | io_scoreboard_comb; + wire [31:0] comb_3 = scoreboardScan_3 | io_scoreboard_comb; + wire _rdMark_valid_T_5 = decodedInsts_0_lb | decodedInsts_0_lh; + wire _io_float_valid_T_3 = io_float_bits_opcode_0 == 3'h1; + wire _rdMark_valid_T_30 = decodedInsts_1_lb | decodedInsts_1_lh; + wire _rdMark_valid_T_53 = decodedInsts_2_lb | decodedInsts_2_lh; + wire _rdMark_valid_T_76 = decodedInsts_3_lb | decodedInsts_3_lh; + wire _io_rs2Read_0_valid_T_6 = decodedInsts_0_add | decodedInsts_0_sub; + wire _io_rs2Read_0_valid_T_24 = decodedInsts_0_min | decodedInsts_0_minu; + wire _io_rs2Set_0_valid_T_1 = decodedInsts_0_csrrw | decodedInsts_0_csrrs; + wire _io_rs2Read_0_valid_T_42 = decodedInsts_0_mul | decodedInsts_0_mulh; + wire _io_rs2Read_0_valid_T_47 = decodedInsts_0_div | decodedInsts_0_divu; + wire _io_rs2Read_1_valid_T_6 = decodedInsts_1_add | decodedInsts_1_sub; + wire _io_rs2Read_1_valid_T_24 = decodedInsts_1_min | decodedInsts_1_minu; + wire _io_rs2Read_1_valid_T_42 = decodedInsts_1_mul | decodedInsts_1_mulh; + wire _io_rs2Read_2_valid_T_6 = decodedInsts_2_add | decodedInsts_2_sub; + wire _io_rs2Read_2_valid_T_24 = decodedInsts_2_min | decodedInsts_2_minu; + wire _io_rs2Read_2_valid_T_42 = decodedInsts_2_mul | decodedInsts_2_mulh; + wire _io_rs2Read_3_valid_T_6 = decodedInsts_3_add | decodedInsts_3_sub; + wire _io_rs2Read_3_valid_T_24 = decodedInsts_3_min | decodedInsts_3_minu; + wire _io_rs2Read_3_valid_T_42 = decodedInsts_3_mul | decodedInsts_3_mulh; + wire [31:0] _GEN_13 = {27'h0, io_inst_0_bits_inst[19:15]}; + wire [31:0] _GEN_14 = {27'h0, io_inst_0_bits_inst[24:20]}; + wire [31:0] _GEN_15 = {27'h0, io_inst_1_bits_inst[19:15]}; + wire [31:0] _GEN_16 = {27'h0, io_inst_1_bits_inst[24:20]}; + wire [31:0] _GEN_17 = {27'h0, io_inst_2_bits_inst[19:15]}; + wire [31:0] _GEN_18 = {27'h0, io_inst_2_bits_inst[24:20]}; + wire [31:0] _GEN_19 = {27'h0, io_inst_3_bits_inst[19:15]}; + wire [31:0] _GEN_20 = {27'h0, io_inst_3_bits_inst[24:20]}; + wire _io_rs2Set_0_valid_T_6 = decodedInsts_0_addi | decodedInsts_0_slti; + wire _io_rs2Set_0_valid_T_21 = decodedInsts_0_clz | decodedInsts_0_ctz; + wire _io_rs1Read_0_valid_T_75 = + decodedInsts_floatValid & decodedInsts_float_scalar_rs1; + wire _io_rs2Set_1_valid_T_6 = decodedInsts_1_addi | decodedInsts_1_slti; + wire _io_rs2Set_1_valid_T_21 = decodedInsts_1_clz | decodedInsts_1_ctz; + wire _io_rs2Set_2_valid_T_6 = decodedInsts_2_addi | decodedInsts_2_slti; + wire _io_rs2Set_2_valid_T_21 = decodedInsts_2_clz | decodedInsts_2_ctz; + wire _io_rs2Set_3_valid_T_6 = decodedInsts_3_addi | decodedInsts_3_slti; + wire _io_rs2Set_3_valid_T_21 = decodedInsts_3_clz | decodedInsts_3_ctz; + wire isLsu_0 = + _rdMark_valid_T_5 | decodedInsts_0_lw | decodedInsts_0_lbu | decodedInsts_0_lhu + | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw | decodedInsts_floatValid + & ~(|io_float_bits_opcode_0) | decodedInsts_floatValid & _io_float_valid_T_3; + wire [3:0] _isLsuCount_T_1 = + {3'h0, isLsu_0} + + {3'h0, + _rdMark_valid_T_30 | decodedInsts_1_lw | decodedInsts_1_lbu | decodedInsts_1_lhu + | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw}; + wire [3:0] _GEN_21 = {1'h0, io_lsuQueueCapacity}; + wire coreIdle = + io_scoreboard_regd == 32'h0 & io_fscoreboard == 32'h0 & ~io_lsuActive; + wire tryDispatch = + ~io_halted & ~io_interlock & io_inst_0_valid + & {((decodedInsts_0_jalr | _rdMark_valid_T_5 | decodedInsts_0_lw | decodedInsts_0_lbu + | decodedInsts_0_lhu | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw + | decodedInsts_floatValid & ~(|io_float_bits_opcode_0) | decodedInsts_floatValid + & _io_float_valid_T_3 + ? 32'h1 << _GEN_13 + : 32'h0) + | ((_rdMark_valid_T_5 | decodedInsts_0_lw | decodedInsts_0_lbu + | decodedInsts_0_lhu | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw + | decodedInsts_floatValid & ~(|io_float_bits_opcode_0) + | decodedInsts_floatValid & _io_float_valid_T_3) + & (_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu | _io_rs2Read_0_valid_T_6 + | decodedInsts_0_slt | decodedInsts_0_sltu | decodedInsts_0_xor + | decodedInsts_0_or | decodedInsts_0_and | decodedInsts_0_xnor + | decodedInsts_0_orn | decodedInsts_0_andn | decodedInsts_0_sll + | decodedInsts_0_srl | decodedInsts_0_sra | _io_rs2Read_0_valid_T_24 + | decodedInsts_0_max | decodedInsts_0_maxu | decodedInsts_0_rol + | decodedInsts_0_ror | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw + | (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) + & ~(io_inst_0_bits_inst[14]) | _io_rs2Read_0_valid_T_42 + | decodedInsts_0_mulhsu | decodedInsts_0_mulhu | _io_rs2Read_0_valid_T_47 + | decodedInsts_0_rem | decodedInsts_0_remu) + ? 32'h1 << _GEN_14 + : 32'h0)) & io_scoreboard_regd, + ((_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu | _io_rs2Read_0_valid_T_6 + | decodedInsts_0_slt | decodedInsts_0_sltu | decodedInsts_0_xor + | decodedInsts_0_or | decodedInsts_0_and | decodedInsts_0_xnor + | decodedInsts_0_orn | decodedInsts_0_andn | decodedInsts_0_sll + | decodedInsts_0_srl | decodedInsts_0_sra | _io_rs2Set_0_valid_T_6 + | decodedInsts_0_sltiu | decodedInsts_0_xori | decodedInsts_0_ori + | decodedInsts_0_andi | decodedInsts_0_slli | decodedInsts_0_srli + | decodedInsts_0_srai | decodedInsts_0_rori | _io_rs2Set_0_valid_T_21 + | decodedInsts_0_cpop | decodedInsts_0_sextb | decodedInsts_0_sexth + | decodedInsts_0_zexth | decodedInsts_0_orcb | decodedInsts_0_rev8 + | _io_rs2Read_0_valid_T_24 | decodedInsts_0_max | decodedInsts_0_maxu + | decodedInsts_0_rol | decodedInsts_0_ror | _io_rs2Set_0_valid_T_1 + | decodedInsts_0_csrrc | _io_rs2Read_0_valid_T_42 | decodedInsts_0_mulhsu + | decodedInsts_0_mulhu | _io_rs2Read_0_valid_T_47 | decodedInsts_0_rem + | decodedInsts_0_remu | decodedInsts_0_jalr | _io_rs1Read_0_valid_T_75 + ? 32'h1 << _GEN_13 + : 32'h0) + | (_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu | _io_rs2Read_0_valid_T_6 + | decodedInsts_0_slt | decodedInsts_0_sltu | decodedInsts_0_xor + | decodedInsts_0_or | decodedInsts_0_and | decodedInsts_0_xnor + | decodedInsts_0_orn | decodedInsts_0_andn | decodedInsts_0_sll + | decodedInsts_0_srl | decodedInsts_0_sra | _io_rs2Read_0_valid_T_24 + | decodedInsts_0_max | decodedInsts_0_maxu | decodedInsts_0_rol + | decodedInsts_0_ror | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw + | (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) & ~(io_inst_0_bits_inst[14]) + | _io_rs2Read_0_valid_T_42 | decodedInsts_0_mulhsu | decodedInsts_0_mulhu + | _io_rs2Read_0_valid_T_47 | decodedInsts_0_rem | decodedInsts_0_remu + ? 32'h1 << _GEN_14 + : 32'h0)) & io_scoreboard_comb} == 64'h0 + & (rdScoreboard_0 & io_scoreboard_comb) == 32'h0 + & (((decodedInsts_floatValid & decodedInsts_float_float_rs1 + ? 32'h1 << _GEN_13 + : 32'h0) + | (decodedInsts_floatValid & decodedInsts_float_uses_rs2 + ? 32'h1 << _GEN_14 + : 32'h0) + | (decodedInsts_floatValid & (|_decodedInsts_float_uses_rs3_T_4) + ? 32'h1 << io_inst_0_bits_inst[31:27] + : 32'h0)) & io_fscoreboard) == 32'h0 + & ((decodedInsts_floatValid & ~_writesFloatRd_T ? 32'h1 << _GEN_12 : 32'h0) + & io_fscoreboard) == 32'h0 + & ~((_slot0Interlock_T_44 | decodedInsts_0_wfi | decodedInsts_0_mpause) + & io_lsuActive) & (|io_lsuQueueCapacity) & (|io_retirement_buffer_nSpace) + & ~io_retirement_buffer_trap_pending + & (~(_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) | io_retirement_buffer_empty) + & (~io_single_step | coreIdle) & (io_inst_0_bits_inst != 32'h8000073 | coreIdle); + wire _alu_T_215 = decodedInsts_0_slti | decodedInsts_0_slt; + wire _alu_T_216 = decodedInsts_0_sltiu | decodedInsts_0_sltu; + wire _alu_T_217 = decodedInsts_0_xori | decodedInsts_0_xor; + wire _alu_T_218 = decodedInsts_0_ori | decodedInsts_0_or; + wire _alu_T_219 = decodedInsts_0_andi | decodedInsts_0_and; + wire _alu_T_220 = decodedInsts_0_slli | decodedInsts_0_sll; + wire _alu_T_221 = decodedInsts_0_srli | decodedInsts_0_srl; + wire _alu_T_222 = decodedInsts_0_srai | decodedInsts_0_sra; + wire io_alu_0_valid_0 = + tryDispatch + & (decodedInsts_0_auipc | decodedInsts_0_addi | decodedInsts_0_add + | decodedInsts_0_sub | _alu_T_215 | _alu_T_216 | _alu_T_217 | _alu_T_218 + | _alu_T_219 | _alu_T_220 | _alu_T_221 | _alu_T_222 | decodedInsts_0_lui + | decodedInsts_0_andn | decodedInsts_0_orn | decodedInsts_0_xnor + | decodedInsts_0_clz | decodedInsts_0_ctz | decodedInsts_0_cpop + | decodedInsts_0_max | decodedInsts_0_maxu | decodedInsts_0_min + | decodedInsts_0_minu | decodedInsts_0_sextb | decodedInsts_0_sexth + | decodedInsts_0_rol | decodedInsts_0_ror | decodedInsts_0_orcb + | decodedInsts_0_rev8 | decodedInsts_0_zexth | decodedInsts_0_rori); + wire [3:0] bru_bits = + {3'h0, decodedInsts_0_jalr} | {2'h0, decodedInsts_0_beq, 1'h0} + | (decodedInsts_0_bne ? 4'h3 : 4'h0) | {1'h0, decodedInsts_0_blt, 2'h0} + | (decodedInsts_0_bge ? 4'h5 : 4'h0) | (decodedInsts_0_bltu ? 4'h6 : 4'h0) + | (decodedInsts_0_bgeu ? 4'h7 : 4'h0) | {decodedInsts_0_ebreak, 3'h0} + | (decodedInsts_0_ecall ? 4'h9 : 4'h0) | (decodedInsts_0_mpause ? 4'hA : 4'h0) + | (decodedInsts_0_mret ? 4'hB : 4'h0) | (decodedInsts_0_wfi ? 4'hC : 4'h0); + wire [31:0] _bru_target_T_2 = + io_inst_0_bits_addr + + {{12{io_inst_0_bits_inst[31]}}, + io_inst_0_bits_inst[2] + ? {io_inst_0_bits_inst[19:12], + io_inst_0_bits_inst[20], + io_inst_0_bits_inst[30:21]} + : {{8{io_inst_0_bits_inst[31]}}, + io_inst_0_bits_inst[7], + io_inst_0_bits_inst[30:25], + io_inst_0_bits_inst[11:8]}, + 1'h0}; + wire _io_bru_0_valid_T = + tryDispatch + & (decodedInsts_0_jal | decodedInsts_0_jalr | decodedInsts_0_beq | decodedInsts_0_bne + | decodedInsts_0_blt | decodedInsts_0_bge | decodedInsts_0_bltu + | decodedInsts_0_bgeu | decodedInsts_0_ebreak | decodedInsts_0_ecall + | decodedInsts_0_mpause | decodedInsts_0_mret | decodedInsts_0_wfi); + wire jalFault = + _io_bru_0_valid_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])) & ~io_branchTaken; + wire jalrFault = + _io_bru_0_valid_T & bru_bits == 4'h1 & io_jalrTarget_0_data[1] & ~io_branchTaken; + wire bxxFault = + _io_bru_0_valid_T + & (|{bru_bits == 4'h7, + bru_bits == 4'h6, + bru_bits == 4'h5, + bru_bits == 4'h4, + bru_bits == 4'h3, + bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])) & ~io_branchTaken; + wire io_bru_0_valid_0 = _io_bru_0_valid_T & ~(jalFault | jalrFault | bxxFault); + wire io_mlu_0_valid_0 = + tryDispatch + & (decodedInsts_0_mul | decodedInsts_0_mulh | decodedInsts_0_mulhsu + | decodedInsts_0_mulhu); + wire io_dvu_0_valid_0 = + tryDispatch + & (decodedInsts_0_div | decodedInsts_0_divu | decodedInsts_0_rem + | decodedInsts_0_remu); + wire _lsu_T_93 = + decodedInsts_floatValid & ~(|io_float_bits_opcode_0) | decodedInsts_floatValid + & _io_float_valid_T_3; + wire io_lsu_0_valid_0 = + tryDispatch + & (decodedInsts_0_lb | decodedInsts_0_lh | decodedInsts_0_lw | decodedInsts_0_lbu + | decodedInsts_0_lhu | decodedInsts_0_sb | decodedInsts_0_sh | decodedInsts_0_sw + | decodedInsts_0_wfi | decodedInsts_0_fencei | _lsu_T_93); + wire [1:0] csr_bits = {1'h0, decodedInsts_0_csrrs} | {decodedInsts_0_csrrc, 1'h0}; + wire csr_valid = + decodedInsts_0_csrrw | decodedInsts_0_csrrs | decodedInsts_0_csrrc; + wire csr_op_valid = + (io_inst_0_bits_inst[31:20] == 12'h0 | io_inst_0_bits_inst[31:20] == 12'h1 + | io_inst_0_bits_inst[31:20] == 12'h2 | io_inst_0_bits_inst[31:20] == 12'h3 + | io_inst_0_bits_inst[31:20] == 12'h8 | io_inst_0_bits_inst[31:20] == 12'h9 + | io_inst_0_bits_inst[31:20] == 12'hA | io_inst_0_bits_inst[31:20] == 12'h300 + | io_inst_0_bits_inst[31:20] == 12'h301 | io_inst_0_bits_inst[31:20] == 12'h304 + | io_inst_0_bits_inst[31:20] == 12'h305 | io_inst_0_bits_inst[31:20] == 12'h310 + | io_inst_0_bits_inst[31:20] == 12'h340 | io_inst_0_bits_inst[31:20] == 12'h341 + | io_inst_0_bits_inst[31:20] == 12'h342 | io_inst_0_bits_inst[31:20] == 12'h343 + | io_inst_0_bits_inst[31:20] == 12'h344 | io_inst_0_bits_inst[31:20] == 12'h7A0 + | io_inst_0_bits_inst[31:20] == 12'h7A1 | io_inst_0_bits_inst[31:20] == 12'h7A2 + | io_inst_0_bits_inst[31:20] == 12'h7A4 | io_inst_0_bits_inst[31:20] == 12'h7B0 + | io_inst_0_bits_inst[31:20] == 12'h7B1 | io_inst_0_bits_inst[31:20] == 12'h7B2 + | io_inst_0_bits_inst[31:20] == 12'h7B3 | io_inst_0_bits_inst[31:20] == 12'h7C0 + | io_inst_0_bits_inst[31:20] == 12'h7C1 | io_inst_0_bits_inst[31:20] == 12'h7C2 + | io_inst_0_bits_inst[31:20] == 12'h7C3 | io_inst_0_bits_inst[31:20] == 12'h7C4 + | io_inst_0_bits_inst[31:20] == 12'h7C5 | io_inst_0_bits_inst[31:20] == 12'h7C6 + | io_inst_0_bits_inst[31:20] == 12'h7C7 | io_inst_0_bits_inst[31:20] == 12'h7E0 + | io_inst_0_bits_inst[31:20] == 12'h7E1 | io_inst_0_bits_inst[31:20] == 12'hB00 + | io_inst_0_bits_inst[31:20] == 12'hB02 | io_inst_0_bits_inst[31:20] == 12'hB80 + | io_inst_0_bits_inst[31:20] == 12'hB82 | io_inst_0_bits_inst[31:20] == 12'hC20 + | io_inst_0_bits_inst[31:20] == 12'hC21 | io_inst_0_bits_inst[31:20] == 12'hC22 + | io_inst_0_bits_inst[31:20] == 12'hC23 | io_inst_0_bits_inst[31:20] == 12'hF11 + | io_inst_0_bits_inst[31:20] == 12'hF12 | io_inst_0_bits_inst[31:20] == 12'hF13 + | io_inst_0_bits_inst[31:20] == 12'hF14 | io_inst_0_bits_inst[31:20] == 12'hFC0 + | io_inst_0_bits_inst[31:20] == 12'hFC4 | io_inst_0_bits_inst[31:20] == 12'hFC8 + | io_inst_0_bits_inst[31:20] == 12'hFCC | io_inst_0_bits_inst[31:20] == 12'hFD0 + | io_inst_0_bits_inst[31:20] == 12'hFD4) + & ~(~((|{csr_bits == 2'h2, csr_bits == 2'h1}) & io_inst_0_bits_inst[19:15] == 5'h0) + & (&(io_inst_0_bits_inst[31:30]))); + wire io_csr_valid_0 = tryDispatch & csr_valid & csr_op_valid & io_float_ready; + wire io_float_valid_0 = + tryDispatch & decodedInsts_floatValid + & ~(decodedInsts_floatValid & ~(|io_float_bits_opcode_0) | decodedInsts_floatValid + & _io_float_valid_T_3); + wire dispatched_3 = io_dvu_0_ready & io_dvu_0_valid_0; + wire dispatched_4 = io_lsu_0_ready & io_lsu_0_valid_0; + wire dispatched_7 = io_float_ready & io_float_valid_0; + wire lastReady_1 = + io_alu_0_valid_0 | io_bru_0_valid_0 | io_mlu_0_valid_0 | dispatched_3 | dispatched_4 + | io_csr_valid_0 | tryDispatch & (decodedInsts_0_fence | decodedInsts_0_fencetso) + | dispatched_7; + wire tryDispatch_1 = + lastReady_1 & ~io_halted & ~io_interlock & io_inst_1_valid & ~isJump_0 + & {((decodedInsts_1_jalr | _rdMark_valid_T_30 | decodedInsts_1_lw | decodedInsts_1_lbu + | decodedInsts_1_lhu | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw + ? 32'h1 << _GEN_15 + : 32'h0) + | ((_rdMark_valid_T_30 | decodedInsts_1_lw | decodedInsts_1_lbu + | decodedInsts_1_lhu | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw) + & (_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu | _io_rs2Read_1_valid_T_6 + | decodedInsts_1_slt | decodedInsts_1_sltu | decodedInsts_1_xor + | decodedInsts_1_or | decodedInsts_1_and | decodedInsts_1_xnor + | decodedInsts_1_orn | decodedInsts_1_andn | decodedInsts_1_sll + | decodedInsts_1_srl | decodedInsts_1_sra | _io_rs2Read_1_valid_T_24 + | decodedInsts_1_max | decodedInsts_1_maxu | decodedInsts_1_rol + | decodedInsts_1_ror | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw + | _io_rs2Read_1_valid_T_42 | decodedInsts_1_mulhsu | decodedInsts_1_mulhu) + ? 32'h1 << _GEN_16 + : 32'h0)) & (rdScoreboard_0 | io_scoreboard_regd), + ((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu | _io_rs2Read_1_valid_T_6 + | decodedInsts_1_slt | decodedInsts_1_sltu | decodedInsts_1_xor + | decodedInsts_1_or | decodedInsts_1_and | decodedInsts_1_xnor + | decodedInsts_1_orn | decodedInsts_1_andn | decodedInsts_1_sll + | decodedInsts_1_srl | decodedInsts_1_sra | _io_rs2Set_1_valid_T_6 + | decodedInsts_1_sltiu | decodedInsts_1_xori | decodedInsts_1_ori + | decodedInsts_1_andi | decodedInsts_1_slli | decodedInsts_1_srli + | decodedInsts_1_srai | decodedInsts_1_rori | _io_rs2Set_1_valid_T_21 + | decodedInsts_1_cpop | decodedInsts_1_sextb | decodedInsts_1_sexth + | decodedInsts_1_zexth | decodedInsts_1_orcb | decodedInsts_1_rev8 + | _io_rs2Read_1_valid_T_24 | decodedInsts_1_max | decodedInsts_1_maxu + | decodedInsts_1_rol | decodedInsts_1_ror | _io_rs2Read_1_valid_T_42 + | decodedInsts_1_mulhsu | decodedInsts_1_mulhu | decodedInsts_1_jalr + ? 32'h1 << _GEN_15 + : 32'h0) + | (_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu | _io_rs2Read_1_valid_T_6 + | decodedInsts_1_slt | decodedInsts_1_sltu | decodedInsts_1_xor + | decodedInsts_1_or | decodedInsts_1_and | decodedInsts_1_xnor + | decodedInsts_1_orn | decodedInsts_1_andn | decodedInsts_1_sll + | decodedInsts_1_srl | decodedInsts_1_sra | _io_rs2Read_1_valid_T_24 + | decodedInsts_1_max | decodedInsts_1_maxu | decodedInsts_1_rol + | decodedInsts_1_ror | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw + | _io_rs2Read_1_valid_T_42 | decodedInsts_1_mulhsu | decodedInsts_1_mulhu + ? 32'h1 << _GEN_16 + : 32'h0)) & comb_1} == 64'h0 & (rdScoreboard_1 & comb_1) == 32'h0 + & ~isBranch_0 + & ~(_slot0Interlock_T_44 | decodedInsts_0_wfi | decodedInsts_0_mpause + | _io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc | decodedInsts_floatValid) + & {3'h0, isLsu_0} < _GEN_21 + & (|{decodedInsts_1_lui, + decodedInsts_1_auipc, + decodedInsts_1_jal, + decodedInsts_1_jalr, + decodedInsts_1_beq, + decodedInsts_1_bne, + decodedInsts_1_blt, + decodedInsts_1_bge, + decodedInsts_1_bltu, + decodedInsts_1_bgeu, + decodedInsts_1_lb, + decodedInsts_1_lh, + decodedInsts_1_lw, + decodedInsts_1_lbu, + decodedInsts_1_lhu, + decodedInsts_1_sb, + decodedInsts_1_sh, + decodedInsts_1_sw, + decodedInsts_1_addi, + decodedInsts_1_slti, + decodedInsts_1_sltiu, + decodedInsts_1_xori, + decodedInsts_1_ori, + decodedInsts_1_andi, + decodedInsts_1_slli, + decodedInsts_1_srli, + decodedInsts_1_srai, + decodedInsts_1_add, + decodedInsts_1_sub, + decodedInsts_1_slt, + decodedInsts_1_sltu, + decodedInsts_1_xor, + decodedInsts_1_or, + decodedInsts_1_and, + decodedInsts_1_sll, + decodedInsts_1_srl, + decodedInsts_1_sra, + decodedInsts_1_mul, + decodedInsts_1_mulh, + decodedInsts_1_mulhsu, + decodedInsts_1_mulhu, + decodedInsts_1_andn, + decodedInsts_1_orn, + decodedInsts_1_xnor, + decodedInsts_1_clz, + decodedInsts_1_ctz, + decodedInsts_1_cpop, + decodedInsts_1_max, + decodedInsts_1_maxu, + decodedInsts_1_min, + decodedInsts_1_minu, + decodedInsts_1_sextb, + decodedInsts_1_sexth, + decodedInsts_1_rol, + decodedInsts_1_ror, + decodedInsts_1_orcb, + decodedInsts_1_rev8, + decodedInsts_1_zexth, + decodedInsts_1_rori}) & (|(io_retirement_buffer_nSpace[4:1])) + & ~io_retirement_buffer_trap_pending & ~io_single_step; + wire _alu_T_508 = decodedInsts_1_slti | decodedInsts_1_slt; + wire _alu_T_509 = decodedInsts_1_sltiu | decodedInsts_1_sltu; + wire _alu_T_510 = decodedInsts_1_xori | decodedInsts_1_xor; + wire _alu_T_511 = decodedInsts_1_ori | decodedInsts_1_or; + wire _alu_T_512 = decodedInsts_1_andi | decodedInsts_1_and; + wire _alu_T_513 = decodedInsts_1_slli | decodedInsts_1_sll; + wire _alu_T_514 = decodedInsts_1_srli | decodedInsts_1_srl; + wire _alu_T_515 = decodedInsts_1_srai | decodedInsts_1_sra; + wire io_alu_1_valid_0 = + tryDispatch_1 + & (decodedInsts_1_auipc | decodedInsts_1_addi | decodedInsts_1_add + | decodedInsts_1_sub | _alu_T_508 | _alu_T_509 | _alu_T_510 | _alu_T_511 + | _alu_T_512 | _alu_T_513 | _alu_T_514 | _alu_T_515 | decodedInsts_1_lui + | decodedInsts_1_andn | decodedInsts_1_orn | decodedInsts_1_xnor + | decodedInsts_1_clz | decodedInsts_1_ctz | decodedInsts_1_cpop + | decodedInsts_1_max | decodedInsts_1_maxu | decodedInsts_1_min + | decodedInsts_1_minu | decodedInsts_1_sextb | decodedInsts_1_sexth + | decodedInsts_1_rol | decodedInsts_1_ror | decodedInsts_1_orcb + | decodedInsts_1_rev8 | decodedInsts_1_zexth | decodedInsts_1_rori); + wire [3:0] bru_1_bits = + {3'h0, decodedInsts_1_jalr} | {2'h0, decodedInsts_1_beq, 1'h0} + | (decodedInsts_1_bne ? 4'h3 : 4'h0) | {1'h0, decodedInsts_1_blt, 2'h0} + | (decodedInsts_1_bge ? 4'h5 : 4'h0) | (decodedInsts_1_bltu ? 4'h6 : 4'h0) + | (decodedInsts_1_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_5 = + io_inst_1_bits_addr + + {{12{io_inst_1_bits_inst[31]}}, + io_inst_1_bits_inst[2] + ? {io_inst_1_bits_inst[19:12], + io_inst_1_bits_inst[20], + io_inst_1_bits_inst[30:21]} + : {{8{io_inst_1_bits_inst[31]}}, + io_inst_1_bits_inst[7], + io_inst_1_bits_inst[30:25], + io_inst_1_bits_inst[11:8]}, + 1'h0}; + wire _io_bru_1_valid_T = + tryDispatch_1 + & (decodedInsts_1_jal | decodedInsts_1_jalr | decodedInsts_1_beq | decodedInsts_1_bne + | decodedInsts_1_blt | decodedInsts_1_bge | decodedInsts_1_bltu + | decodedInsts_1_bgeu); + wire jalFault_1 = + _io_bru_1_valid_T & bru_1_bits[2:0] == 3'h0 & (|(_bru_target_T_5[1:0])) + & ~io_branchTaken; + wire jalrFault_1 = + _io_bru_1_valid_T & bru_1_bits[2:0] == 3'h1 & io_jalrTarget_1_data[1] + & ~io_branchTaken; + wire bxxFault_1 = + _io_bru_1_valid_T + & (|{&(bru_1_bits[2:0]), + bru_1_bits[2:0] == 3'h6, + bru_1_bits[2:0] == 3'h5, + bru_1_bits[2:0] == 3'h4, + bru_1_bits[2:0] == 3'h3, + bru_1_bits[2:0] == 3'h2}) & (|(_bru_target_T_5[1:0])) & ~io_branchTaken; + wire io_bru_1_valid_0 = + _io_bru_1_valid_T & ~(jalFault_1 | jalrFault_1 | bxxFault_1); + wire io_mlu_1_valid_0 = + tryDispatch_1 + & (decodedInsts_1_mul | decodedInsts_1_mulh | decodedInsts_1_mulhsu + | decodedInsts_1_mulhu); + wire io_lsu_1_valid_0 = + tryDispatch_1 + & (decodedInsts_1_lb | decodedInsts_1_lh | decodedInsts_1_lw | decodedInsts_1_lbu + | decodedInsts_1_lhu | decodedInsts_1_sb | decodedInsts_1_sh | decodedInsts_1_sw); + wire dispatched_2_1 = io_mlu_1_ready & io_mlu_1_valid_0; + wire dispatched_4_1 = io_lsu_1_ready & io_lsu_1_valid_0; + wire lastReady_2 = + io_alu_1_valid_0 | io_bru_1_valid_0 | dispatched_2_1 | dispatched_4_1; + wire tryDispatch_2 = + lastReady_2 & ~io_halted & ~io_interlock & io_inst_2_valid & ~jumped_2 + & {((decodedInsts_2_jalr | _rdMark_valid_T_53 | decodedInsts_2_lw | decodedInsts_2_lbu + | decodedInsts_2_lhu | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw + ? 32'h1 << _GEN_17 + : 32'h0) + | ((_rdMark_valid_T_53 | decodedInsts_2_lw | decodedInsts_2_lbu + | decodedInsts_2_lhu | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw) + & (_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu | _io_rs2Read_2_valid_T_6 + | decodedInsts_2_slt | decodedInsts_2_sltu | decodedInsts_2_xor + | decodedInsts_2_or | decodedInsts_2_and | decodedInsts_2_xnor + | decodedInsts_2_orn | decodedInsts_2_andn | decodedInsts_2_sll + | decodedInsts_2_srl | decodedInsts_2_sra | _io_rs2Read_2_valid_T_24 + | decodedInsts_2_max | decodedInsts_2_maxu | decodedInsts_2_rol + | decodedInsts_2_ror | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw + | _io_rs2Read_2_valid_T_42 | decodedInsts_2_mulhsu | decodedInsts_2_mulhu) + ? 32'h1 << _GEN_18 + : 32'h0)) & (scoreboardScan_2 | io_scoreboard_regd), + ((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu | _io_rs2Read_2_valid_T_6 + | decodedInsts_2_slt | decodedInsts_2_sltu | decodedInsts_2_xor + | decodedInsts_2_or | decodedInsts_2_and | decodedInsts_2_xnor + | decodedInsts_2_orn | decodedInsts_2_andn | decodedInsts_2_sll + | decodedInsts_2_srl | decodedInsts_2_sra | _io_rs2Set_2_valid_T_6 + | decodedInsts_2_sltiu | decodedInsts_2_xori | decodedInsts_2_ori + | decodedInsts_2_andi | decodedInsts_2_slli | decodedInsts_2_srli + | decodedInsts_2_srai | decodedInsts_2_rori | _io_rs2Set_2_valid_T_21 + | decodedInsts_2_cpop | decodedInsts_2_sextb | decodedInsts_2_sexth + | decodedInsts_2_zexth | decodedInsts_2_orcb | decodedInsts_2_rev8 + | _io_rs2Read_2_valid_T_24 | decodedInsts_2_max | decodedInsts_2_maxu + | decodedInsts_2_rol | decodedInsts_2_ror | _io_rs2Read_2_valid_T_42 + | decodedInsts_2_mulhsu | decodedInsts_2_mulhu | decodedInsts_2_jalr + ? 32'h1 << _GEN_17 + : 32'h0) + | (_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu | _io_rs2Read_2_valid_T_6 + | decodedInsts_2_slt | decodedInsts_2_sltu | decodedInsts_2_xor + | decodedInsts_2_or | decodedInsts_2_and | decodedInsts_2_xnor + | decodedInsts_2_orn | decodedInsts_2_andn | decodedInsts_2_sll + | decodedInsts_2_srl | decodedInsts_2_sra | _io_rs2Read_2_valid_T_24 + | decodedInsts_2_max | decodedInsts_2_maxu | decodedInsts_2_rol + | decodedInsts_2_ror | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw + | _io_rs2Read_2_valid_T_42 | decodedInsts_2_mulhsu | decodedInsts_2_mulhu + ? 32'h1 << _GEN_18 + : 32'h0)) & comb_2} == 64'h0 & (rdScoreboard_2 & comb_2) == 32'h0 + & ~branched_2 + & ~(_slot0Interlock_T_44 | decodedInsts_0_wfi | decodedInsts_0_mpause + | _io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc | decodedInsts_floatValid) + & _isLsuCount_T_1 < _GEN_21 + & (|{decodedInsts_2_lui, + decodedInsts_2_auipc, + decodedInsts_2_jal, + decodedInsts_2_jalr, + decodedInsts_2_beq, + decodedInsts_2_bne, + decodedInsts_2_blt, + decodedInsts_2_bge, + decodedInsts_2_bltu, + decodedInsts_2_bgeu, + decodedInsts_2_lb, + decodedInsts_2_lh, + decodedInsts_2_lw, + decodedInsts_2_lbu, + decodedInsts_2_lhu, + decodedInsts_2_sb, + decodedInsts_2_sh, + decodedInsts_2_sw, + decodedInsts_2_addi, + decodedInsts_2_slti, + decodedInsts_2_sltiu, + decodedInsts_2_xori, + decodedInsts_2_ori, + decodedInsts_2_andi, + decodedInsts_2_slli, + decodedInsts_2_srli, + decodedInsts_2_srai, + decodedInsts_2_add, + decodedInsts_2_sub, + decodedInsts_2_slt, + decodedInsts_2_sltu, + decodedInsts_2_xor, + decodedInsts_2_or, + decodedInsts_2_and, + decodedInsts_2_sll, + decodedInsts_2_srl, + decodedInsts_2_sra, + decodedInsts_2_mul, + decodedInsts_2_mulh, + decodedInsts_2_mulhsu, + decodedInsts_2_mulhu, + decodedInsts_2_andn, + decodedInsts_2_orn, + decodedInsts_2_xnor, + decodedInsts_2_clz, + decodedInsts_2_ctz, + decodedInsts_2_cpop, + decodedInsts_2_max, + decodedInsts_2_maxu, + decodedInsts_2_min, + decodedInsts_2_minu, + decodedInsts_2_sextb, + decodedInsts_2_sexth, + decodedInsts_2_rol, + decodedInsts_2_ror, + decodedInsts_2_orcb, + decodedInsts_2_rev8, + decodedInsts_2_zexth, + decodedInsts_2_rori}) & io_retirement_buffer_nSpace > 5'h2 + & ~io_retirement_buffer_trap_pending & ~io_single_step; + wire _alu_T_801 = decodedInsts_2_slti | decodedInsts_2_slt; + wire _alu_T_802 = decodedInsts_2_sltiu | decodedInsts_2_sltu; + wire _alu_T_803 = decodedInsts_2_xori | decodedInsts_2_xor; + wire _alu_T_804 = decodedInsts_2_ori | decodedInsts_2_or; + wire _alu_T_805 = decodedInsts_2_andi | decodedInsts_2_and; + wire _alu_T_806 = decodedInsts_2_slli | decodedInsts_2_sll; + wire _alu_T_807 = decodedInsts_2_srli | decodedInsts_2_srl; + wire _alu_T_808 = decodedInsts_2_srai | decodedInsts_2_sra; + wire io_alu_2_valid_0 = + tryDispatch_2 + & (decodedInsts_2_auipc | decodedInsts_2_addi | decodedInsts_2_add + | decodedInsts_2_sub | _alu_T_801 | _alu_T_802 | _alu_T_803 | _alu_T_804 + | _alu_T_805 | _alu_T_806 | _alu_T_807 | _alu_T_808 | decodedInsts_2_lui + | decodedInsts_2_andn | decodedInsts_2_orn | decodedInsts_2_xnor + | decodedInsts_2_clz | decodedInsts_2_ctz | decodedInsts_2_cpop + | decodedInsts_2_max | decodedInsts_2_maxu | decodedInsts_2_min + | decodedInsts_2_minu | decodedInsts_2_sextb | decodedInsts_2_sexth + | decodedInsts_2_rol | decodedInsts_2_ror | decodedInsts_2_orcb + | decodedInsts_2_rev8 | decodedInsts_2_zexth | decodedInsts_2_rori); + wire [3:0] bru_2_bits = + {3'h0, decodedInsts_2_jalr} | {2'h0, decodedInsts_2_beq, 1'h0} + | (decodedInsts_2_bne ? 4'h3 : 4'h0) | {1'h0, decodedInsts_2_blt, 2'h0} + | (decodedInsts_2_bge ? 4'h5 : 4'h0) | (decodedInsts_2_bltu ? 4'h6 : 4'h0) + | (decodedInsts_2_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_8 = + io_inst_2_bits_addr + + {{12{io_inst_2_bits_inst[31]}}, + io_inst_2_bits_inst[2] + ? {io_inst_2_bits_inst[19:12], + io_inst_2_bits_inst[20], + io_inst_2_bits_inst[30:21]} + : {{8{io_inst_2_bits_inst[31]}}, + io_inst_2_bits_inst[7], + io_inst_2_bits_inst[30:25], + io_inst_2_bits_inst[11:8]}, + 1'h0}; + wire _io_bru_2_valid_T = + tryDispatch_2 + & (decodedInsts_2_jal | decodedInsts_2_jalr | decodedInsts_2_beq | decodedInsts_2_bne + | decodedInsts_2_blt | decodedInsts_2_bge | decodedInsts_2_bltu + | decodedInsts_2_bgeu); + wire jalFault_2 = + _io_bru_2_valid_T & bru_2_bits[2:0] == 3'h0 & (|(_bru_target_T_8[1:0])) + & ~io_branchTaken; + wire jalrFault_2 = + _io_bru_2_valid_T & bru_2_bits[2:0] == 3'h1 & io_jalrTarget_2_data[1] + & ~io_branchTaken; + wire bxxFault_2 = + _io_bru_2_valid_T + & (|{&(bru_2_bits[2:0]), + bru_2_bits[2:0] == 3'h6, + bru_2_bits[2:0] == 3'h5, + bru_2_bits[2:0] == 3'h4, + bru_2_bits[2:0] == 3'h3, + bru_2_bits[2:0] == 3'h2}) & (|(_bru_target_T_8[1:0])) & ~io_branchTaken; + wire io_bru_2_valid_0 = + _io_bru_2_valid_T & ~(jalFault_2 | jalrFault_2 | bxxFault_2); + wire io_mlu_2_valid_0 = + tryDispatch_2 + & (decodedInsts_2_mul | decodedInsts_2_mulh | decodedInsts_2_mulhsu + | decodedInsts_2_mulhu); + wire io_lsu_2_valid_0 = + tryDispatch_2 + & (decodedInsts_2_lb | decodedInsts_2_lh | decodedInsts_2_lw | decodedInsts_2_lbu + | decodedInsts_2_lhu | decodedInsts_2_sb | decodedInsts_2_sh | decodedInsts_2_sw); + wire dispatched_2_2 = io_mlu_2_ready & io_mlu_2_valid_0; + wire dispatched_4_2 = io_lsu_2_ready & io_lsu_2_valid_0; + wire lastReady_3 = + io_alu_2_valid_0 | io_bru_2_valid_0 | dispatched_2_2 | dispatched_4_2; + wire tryDispatch_3 = + lastReady_3 & ~io_halted & ~io_interlock & io_inst_3_valid & ~(jumped_2 | isJump_2) + & {((decodedInsts_3_jalr | _rdMark_valid_T_76 | decodedInsts_3_lw | decodedInsts_3_lbu + | decodedInsts_3_lhu | _io_rs2Read_3_valid_T_32 | decodedInsts_3_sw + ? 32'h1 << _GEN_19 + : 32'h0) + | ((_rdMark_valid_T_76 | decodedInsts_3_lw | decodedInsts_3_lbu + | decodedInsts_3_lhu | _io_rs2Read_3_valid_T_32 | decodedInsts_3_sw) + & (_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu | _io_rs2Read_3_valid_T_6 + | decodedInsts_3_slt | decodedInsts_3_sltu | decodedInsts_3_xor + | decodedInsts_3_or | decodedInsts_3_and | decodedInsts_3_xnor + | decodedInsts_3_orn | decodedInsts_3_andn | decodedInsts_3_sll + | decodedInsts_3_srl | decodedInsts_3_sra | _io_rs2Read_3_valid_T_24 + | decodedInsts_3_max | decodedInsts_3_maxu | decodedInsts_3_rol + | decodedInsts_3_ror | _io_rs2Read_3_valid_T_32 | decodedInsts_3_sw + | _io_rs2Read_3_valid_T_42 | decodedInsts_3_mulhsu | decodedInsts_3_mulhu) + ? 32'h1 << _GEN_20 + : 32'h0)) & (scoreboardScan_3 | io_scoreboard_regd), + ((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu | _io_rs2Read_3_valid_T_6 + | decodedInsts_3_slt | decodedInsts_3_sltu | decodedInsts_3_xor + | decodedInsts_3_or | decodedInsts_3_and | decodedInsts_3_xnor + | decodedInsts_3_orn | decodedInsts_3_andn | decodedInsts_3_sll + | decodedInsts_3_srl | decodedInsts_3_sra | _io_rs2Set_3_valid_T_6 + | decodedInsts_3_sltiu | decodedInsts_3_xori | decodedInsts_3_ori + | decodedInsts_3_andi | decodedInsts_3_slli | decodedInsts_3_srli + | decodedInsts_3_srai | decodedInsts_3_rori | _io_rs2Set_3_valid_T_21 + | decodedInsts_3_cpop | decodedInsts_3_sextb | decodedInsts_3_sexth + | decodedInsts_3_zexth | decodedInsts_3_orcb | decodedInsts_3_rev8 + | _io_rs2Read_3_valid_T_24 | decodedInsts_3_max | decodedInsts_3_maxu + | decodedInsts_3_rol | decodedInsts_3_ror | _io_rs2Read_3_valid_T_42 + | decodedInsts_3_mulhsu | decodedInsts_3_mulhu | decodedInsts_3_jalr + ? 32'h1 << _GEN_19 + : 32'h0) + | (_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu | _io_rs2Read_3_valid_T_6 + | decodedInsts_3_slt | decodedInsts_3_sltu | decodedInsts_3_xor + | decodedInsts_3_or | decodedInsts_3_and | decodedInsts_3_xnor + | decodedInsts_3_orn | decodedInsts_3_andn | decodedInsts_3_sll + | decodedInsts_3_srl | decodedInsts_3_sra | _io_rs2Read_3_valid_T_24 + | decodedInsts_3_max | decodedInsts_3_maxu | decodedInsts_3_rol + | decodedInsts_3_ror | _io_rs2Read_3_valid_T_32 | decodedInsts_3_sw + | _io_rs2Read_3_valid_T_42 | decodedInsts_3_mulhsu | decodedInsts_3_mulhu + ? 32'h1 << _GEN_20 + : 32'h0)) & comb_3} == 64'h0 + & ((_io_rs2Read_3_valid_T_32 | decodedInsts_3_sw | _io_rs2Read_3_valid_T_1 + | decodedInsts_3_blt | decodedInsts_3_bge | decodedInsts_3_bltu + | decodedInsts_3_bgeu + ? 32'h0 + : 32'h1 << io_inst_3_bits_inst[11:7]) & comb_3) == 32'h0 + & ~(branched_2 | isBranch_2) + & ~(_slot0Interlock_T_44 | decodedInsts_0_wfi | decodedInsts_0_mpause + | _io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc | decodedInsts_floatValid) + & _isLsuCount_T_1 + + {3'h0, + _rdMark_valid_T_53 | decodedInsts_2_lw | decodedInsts_2_lbu | decodedInsts_2_lhu + | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw} < _GEN_21 + & (|{decodedInsts_3_lui, + decodedInsts_3_auipc, + decodedInsts_3_jal, + decodedInsts_3_jalr, + decodedInsts_3_beq, + decodedInsts_3_bne, + decodedInsts_3_blt, + decodedInsts_3_bge, + decodedInsts_3_bltu, + decodedInsts_3_bgeu, + decodedInsts_3_lb, + decodedInsts_3_lh, + decodedInsts_3_lw, + decodedInsts_3_lbu, + decodedInsts_3_lhu, + decodedInsts_3_sb, + decodedInsts_3_sh, + decodedInsts_3_sw, + decodedInsts_3_addi, + decodedInsts_3_slti, + decodedInsts_3_sltiu, + decodedInsts_3_xori, + decodedInsts_3_ori, + decodedInsts_3_andi, + decodedInsts_3_slli, + decodedInsts_3_srli, + decodedInsts_3_srai, + decodedInsts_3_add, + decodedInsts_3_sub, + decodedInsts_3_slt, + decodedInsts_3_sltu, + decodedInsts_3_xor, + decodedInsts_3_or, + decodedInsts_3_and, + decodedInsts_3_sll, + decodedInsts_3_srl, + decodedInsts_3_sra, + decodedInsts_3_mul, + decodedInsts_3_mulh, + decodedInsts_3_mulhsu, + decodedInsts_3_mulhu, + decodedInsts_3_andn, + decodedInsts_3_orn, + decodedInsts_3_xnor, + decodedInsts_3_clz, + decodedInsts_3_ctz, + decodedInsts_3_cpop, + decodedInsts_3_max, + decodedInsts_3_maxu, + decodedInsts_3_min, + decodedInsts_3_minu, + decodedInsts_3_sextb, + decodedInsts_3_sexth, + decodedInsts_3_rol, + decodedInsts_3_ror, + decodedInsts_3_orcb, + decodedInsts_3_rev8, + decodedInsts_3_zexth, + decodedInsts_3_rori}) & (|(io_retirement_buffer_nSpace[4:2])) + & ~io_retirement_buffer_trap_pending & ~io_single_step; + wire _alu_T_1094 = decodedInsts_3_slti | decodedInsts_3_slt; + wire _alu_T_1095 = decodedInsts_3_sltiu | decodedInsts_3_sltu; + wire _alu_T_1096 = decodedInsts_3_xori | decodedInsts_3_xor; + wire _alu_T_1097 = decodedInsts_3_ori | decodedInsts_3_or; + wire _alu_T_1098 = decodedInsts_3_andi | decodedInsts_3_and; + wire _alu_T_1099 = decodedInsts_3_slli | decodedInsts_3_sll; + wire _alu_T_1100 = decodedInsts_3_srli | decodedInsts_3_srl; + wire _alu_T_1101 = decodedInsts_3_srai | decodedInsts_3_sra; + wire io_alu_3_valid_0 = + tryDispatch_3 + & (decodedInsts_3_auipc | decodedInsts_3_addi | decodedInsts_3_add + | decodedInsts_3_sub | _alu_T_1094 | _alu_T_1095 | _alu_T_1096 | _alu_T_1097 + | _alu_T_1098 | _alu_T_1099 | _alu_T_1100 | _alu_T_1101 | decodedInsts_3_lui + | decodedInsts_3_andn | decodedInsts_3_orn | decodedInsts_3_xnor + | decodedInsts_3_clz | decodedInsts_3_ctz | decodedInsts_3_cpop + | decodedInsts_3_max | decodedInsts_3_maxu | decodedInsts_3_min + | decodedInsts_3_minu | decodedInsts_3_sextb | decodedInsts_3_sexth + | decodedInsts_3_rol | decodedInsts_3_ror | decodedInsts_3_orcb + | decodedInsts_3_rev8 | decodedInsts_3_zexth | decodedInsts_3_rori); + wire [3:0] bru_3_bits = + {3'h0, decodedInsts_3_jalr} | {2'h0, decodedInsts_3_beq, 1'h0} + | (decodedInsts_3_bne ? 4'h3 : 4'h0) | {1'h0, decodedInsts_3_blt, 2'h0} + | (decodedInsts_3_bge ? 4'h5 : 4'h0) | (decodedInsts_3_bltu ? 4'h6 : 4'h0) + | (decodedInsts_3_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_11 = + io_inst_3_bits_addr + + {{12{io_inst_3_bits_inst[31]}}, + io_inst_3_bits_inst[2] + ? {io_inst_3_bits_inst[19:12], + io_inst_3_bits_inst[20], + io_inst_3_bits_inst[30:21]} + : {{8{io_inst_3_bits_inst[31]}}, + io_inst_3_bits_inst[7], + io_inst_3_bits_inst[30:25], + io_inst_3_bits_inst[11:8]}, + 1'h0}; + wire _io_bru_3_valid_T = + tryDispatch_3 + & (decodedInsts_3_jal | decodedInsts_3_jalr | decodedInsts_3_beq | decodedInsts_3_bne + | decodedInsts_3_blt | decodedInsts_3_bge | decodedInsts_3_bltu + | decodedInsts_3_bgeu); + wire jalFault_3 = + _io_bru_3_valid_T & bru_3_bits[2:0] == 3'h0 & (|(_bru_target_T_11[1:0])) + & ~io_branchTaken; + wire jalrFault_3 = + _io_bru_3_valid_T & bru_3_bits[2:0] == 3'h1 & io_jalrTarget_3_data[1] + & ~io_branchTaken; + wire bxxFault_3 = + _io_bru_3_valid_T + & (|{&(bru_3_bits[2:0]), + bru_3_bits[2:0] == 3'h6, + bru_3_bits[2:0] == 3'h5, + bru_3_bits[2:0] == 3'h4, + bru_3_bits[2:0] == 3'h3, + bru_3_bits[2:0] == 3'h2}) & (|(_bru_target_T_11[1:0])) & ~io_branchTaken; + wire io_bru_3_valid_0 = + _io_bru_3_valid_T & ~(jalFault_3 | jalrFault_3 | bxxFault_3); + wire io_mlu_3_valid_0 = + tryDispatch_3 + & (decodedInsts_3_mul | decodedInsts_3_mulh | decodedInsts_3_mulhsu + | decodedInsts_3_mulhu); + wire io_lsu_3_valid_0 = + tryDispatch_3 + & (decodedInsts_3_lb | decodedInsts_3_lh | decodedInsts_3_lw | decodedInsts_3_lbu + | decodedInsts_3_lhu | decodedInsts_3_sb | decodedInsts_3_sh | decodedInsts_3_sw); + wire dispatched_2_3 = io_mlu_3_ready & io_mlu_3_valid_0; + wire dispatched_4_3 = io_lsu_3_ready & io_lsu_3_valid_0; + wire lastReady_4 = + io_alu_3_valid_0 | io_bru_3_valid_0 | dispatched_2_3 | dispatched_4_3; + wire _io_frs1Read_0_valid_T = lastReady_1 & io_inst_0_valid; + wire _io_frs1Read_1_valid_T = lastReady_2 & io_inst_1_valid; + wire _io_frs1Read_2_valid_T = lastReady_3 & io_inst_2_valid; + wire _io_frs1Read_3_valid_T = lastReady_4 & io_inst_3_valid; + assign io_csrFault_0 = csr_valid & ~csr_op_valid & tryDispatch; + assign io_jalFault_0 = jalFault; + assign io_jalFault_1 = jalFault_1; + assign io_jalFault_2 = jalFault_2; + assign io_jalFault_3 = jalFault_3; + assign io_jalrFault_0 = jalrFault; + assign io_jalrFault_1 = jalrFault_1; + assign io_jalrFault_2 = jalrFault_2; + assign io_jalrFault_3 = jalrFault_3; + assign io_bxxFault_0 = bxxFault; + assign io_bxxFault_1 = bxxFault_1; + assign io_bxxFault_2 = bxxFault_2; + assign io_bxxFault_3 = bxxFault_3; + assign io_undefFault_0 = + tryDispatch + & {decodedInsts_0_lui, + decodedInsts_0_auipc, + decodedInsts_0_jal, + decodedInsts_0_jalr, + decodedInsts_0_beq, + decodedInsts_0_bne, + decodedInsts_0_blt, + decodedInsts_0_bge, + decodedInsts_0_bltu, + decodedInsts_0_bgeu, + decodedInsts_0_csrrw, + decodedInsts_0_csrrs, + decodedInsts_0_csrrc, + decodedInsts_0_lb, + decodedInsts_0_lh, + decodedInsts_0_lw, + decodedInsts_0_lbu, + decodedInsts_0_lhu, + decodedInsts_0_sb, + decodedInsts_0_sh, + decodedInsts_0_sw, + decodedInsts_0_fence, + decodedInsts_0_addi, + decodedInsts_0_slti, + decodedInsts_0_sltiu, + decodedInsts_0_xori, + decodedInsts_0_ori, + decodedInsts_0_andi, + decodedInsts_0_slli, + decodedInsts_0_srli, + decodedInsts_0_srai, + decodedInsts_0_add, + decodedInsts_0_sub, + decodedInsts_0_slt, + decodedInsts_0_sltu, + decodedInsts_0_xor, + decodedInsts_0_or, + decodedInsts_0_and, + decodedInsts_0_sll, + decodedInsts_0_srl, + decodedInsts_0_sra, + decodedInsts_0_mul, + decodedInsts_0_mulh, + decodedInsts_0_mulhsu, + decodedInsts_0_mulhu, + decodedInsts_0_div, + decodedInsts_0_divu, + decodedInsts_0_rem, + decodedInsts_0_remu, + decodedInsts_0_andn, + decodedInsts_0_orn, + decodedInsts_0_xnor, + decodedInsts_0_clz, + decodedInsts_0_ctz, + decodedInsts_0_cpop, + decodedInsts_0_max, + decodedInsts_0_maxu, + decodedInsts_0_min, + decodedInsts_0_minu, + decodedInsts_0_sextb, + decodedInsts_0_sexth, + decodedInsts_0_rol, + decodedInsts_0_ror, + decodedInsts_0_orcb, + decodedInsts_0_rev8, + decodedInsts_0_zexth, + decodedInsts_0_rori, + decodedInsts_0_ebreak, + decodedInsts_0_ecall, + decodedInsts_0_mpause, + decodedInsts_0_mret, + decodedInsts_0_wfi, + decodedInsts_0_fencei, + decodedInsts_0_fencetso, + decodedInsts_floatValid} == 75'h0; + assign io_bruTarget_0 = _bru_target_T_2; + assign io_bruTarget_1 = _bru_target_T_5; + assign io_bruTarget_2 = _bru_target_T_8; + assign io_bruTarget_3 = _bru_target_T_11; + assign io_inst_0_ready = lastReady_1; + assign io_inst_1_ready = lastReady_2; + assign io_inst_2_ready = lastReady_3; + assign io_inst_3_ready = lastReady_4; + assign io_rs1Read_0_valid = + _io_frs1Read_0_valid_T + & (_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu | _io_rs2Read_0_valid_T_6 + | decodedInsts_0_slt | decodedInsts_0_sltu | decodedInsts_0_xor | decodedInsts_0_or + | decodedInsts_0_and | decodedInsts_0_xnor | decodedInsts_0_orn + | decodedInsts_0_andn | decodedInsts_0_sll | decodedInsts_0_srl + | decodedInsts_0_sra | _io_rs2Set_0_valid_T_6 | decodedInsts_0_sltiu + | decodedInsts_0_xori | decodedInsts_0_ori | decodedInsts_0_andi + | decodedInsts_0_slli | decodedInsts_0_srli | decodedInsts_0_srai + | decodedInsts_0_rori | _io_rs2Set_0_valid_T_21 | decodedInsts_0_cpop + | decodedInsts_0_sextb | decodedInsts_0_sexth | decodedInsts_0_zexth + | decodedInsts_0_orcb | decodedInsts_0_rev8 | _io_rs2Read_0_valid_T_24 + | decodedInsts_0_max | decodedInsts_0_maxu | decodedInsts_0_rol + | decodedInsts_0_ror | _io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc + | _io_rs2Read_0_valid_T_42 | decodedInsts_0_mulhsu | decodedInsts_0_mulhu + | _io_rs2Read_0_valid_T_47 | decodedInsts_0_rem | decodedInsts_0_remu + | decodedInsts_0_jalr | _io_rs1Read_0_valid_T_75); + assign io_rs1Read_0_addr = + io_inst_0_bits_inst[0] ? io_inst_0_bits_inst[19:15] : {4'h0, io_inst_0_bits_inst[27]}; + assign io_rs1Read_1_valid = + _io_frs1Read_1_valid_T + & (_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu | _io_rs2Read_1_valid_T_6 + | decodedInsts_1_slt | decodedInsts_1_sltu | decodedInsts_1_xor | decodedInsts_1_or + | decodedInsts_1_and | decodedInsts_1_xnor | decodedInsts_1_orn + | decodedInsts_1_andn | decodedInsts_1_sll | decodedInsts_1_srl + | decodedInsts_1_sra | _io_rs2Set_1_valid_T_6 | decodedInsts_1_sltiu + | decodedInsts_1_xori | decodedInsts_1_ori | decodedInsts_1_andi + | decodedInsts_1_slli | decodedInsts_1_srli | decodedInsts_1_srai + | decodedInsts_1_rori | _io_rs2Set_1_valid_T_21 | decodedInsts_1_cpop + | decodedInsts_1_sextb | decodedInsts_1_sexth | decodedInsts_1_zexth + | decodedInsts_1_orcb | decodedInsts_1_rev8 | _io_rs2Read_1_valid_T_24 + | decodedInsts_1_max | decodedInsts_1_maxu | decodedInsts_1_rol + | decodedInsts_1_ror | _io_rs2Read_1_valid_T_42 | decodedInsts_1_mulhsu + | decodedInsts_1_mulhu | decodedInsts_1_jalr); + assign io_rs1Read_1_addr = + io_inst_1_bits_inst[0] ? io_inst_1_bits_inst[19:15] : {4'h0, io_inst_1_bits_inst[28]}; + assign io_rs1Read_2_valid = + _io_frs1Read_2_valid_T + & (_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu | _io_rs2Read_2_valid_T_6 + | decodedInsts_2_slt | decodedInsts_2_sltu | decodedInsts_2_xor | decodedInsts_2_or + | decodedInsts_2_and | decodedInsts_2_xnor | decodedInsts_2_orn + | decodedInsts_2_andn | decodedInsts_2_sll | decodedInsts_2_srl + | decodedInsts_2_sra | _io_rs2Set_2_valid_T_6 | decodedInsts_2_sltiu + | decodedInsts_2_xori | decodedInsts_2_ori | decodedInsts_2_andi + | decodedInsts_2_slli | decodedInsts_2_srli | decodedInsts_2_srai + | decodedInsts_2_rori | _io_rs2Set_2_valid_T_21 | decodedInsts_2_cpop + | decodedInsts_2_sextb | decodedInsts_2_sexth | decodedInsts_2_zexth + | decodedInsts_2_orcb | decodedInsts_2_rev8 | _io_rs2Read_2_valid_T_24 + | decodedInsts_2_max | decodedInsts_2_maxu | decodedInsts_2_rol + | decodedInsts_2_ror | _io_rs2Read_2_valid_T_42 | decodedInsts_2_mulhsu + | decodedInsts_2_mulhu | decodedInsts_2_jalr); + assign io_rs1Read_2_addr = + io_inst_2_bits_inst[0] ? io_inst_2_bits_inst[19:15] : {4'h0, io_inst_2_bits_inst[29]}; + assign io_rs1Read_3_valid = + _io_frs1Read_3_valid_T + & (_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu | _io_rs2Read_3_valid_T_6 + | decodedInsts_3_slt | decodedInsts_3_sltu | decodedInsts_3_xor | decodedInsts_3_or + | decodedInsts_3_and | decodedInsts_3_xnor | decodedInsts_3_orn + | decodedInsts_3_andn | decodedInsts_3_sll | decodedInsts_3_srl + | decodedInsts_3_sra | _io_rs2Set_3_valid_T_6 | decodedInsts_3_sltiu + | decodedInsts_3_xori | decodedInsts_3_ori | decodedInsts_3_andi + | decodedInsts_3_slli | decodedInsts_3_srli | decodedInsts_3_srai + | decodedInsts_3_rori | _io_rs2Set_3_valid_T_21 | decodedInsts_3_cpop + | decodedInsts_3_sextb | decodedInsts_3_sexth | decodedInsts_3_zexth + | decodedInsts_3_orcb | decodedInsts_3_rev8 | _io_rs2Read_3_valid_T_24 + | decodedInsts_3_max | decodedInsts_3_maxu | decodedInsts_3_rol + | decodedInsts_3_ror | _io_rs2Read_3_valid_T_42 | decodedInsts_3_mulhsu + | decodedInsts_3_mulhu | decodedInsts_3_jalr); + assign io_rs1Read_3_addr = + io_inst_3_bits_inst[0] ? io_inst_3_bits_inst[19:15] : {4'h0, io_inst_3_bits_inst[30]}; + assign io_rs1Set_0_valid = + _io_frs1Read_0_valid_T + & (decodedInsts_0_auipc | (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) + & io_inst_0_bits_inst[14]); + assign io_rs1Set_0_value = + _io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc + ? {27'h0, io_inst_0_bits_inst[19:15]} + : io_inst_0_bits_addr; + assign io_rs1Set_1_valid = _io_frs1Read_1_valid_T & decodedInsts_1_auipc; + assign io_rs1Set_1_value = io_inst_1_bits_addr; + assign io_rs1Set_2_valid = _io_frs1Read_2_valid_T & decodedInsts_2_auipc; + assign io_rs1Set_2_value = io_inst_2_bits_addr; + assign io_rs1Set_3_valid = _io_frs1Read_3_valid_T & decodedInsts_3_auipc; + assign io_rs1Set_3_value = io_inst_3_bits_addr; + assign io_rs2Read_0_valid = + _io_frs1Read_0_valid_T + & (_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt | decodedInsts_0_bge + | decodedInsts_0_bltu | decodedInsts_0_bgeu | _io_rs2Read_0_valid_T_6 + | decodedInsts_0_slt | decodedInsts_0_sltu | decodedInsts_0_xor | decodedInsts_0_or + | decodedInsts_0_and | decodedInsts_0_xnor | decodedInsts_0_orn + | decodedInsts_0_andn | decodedInsts_0_sll | decodedInsts_0_srl + | decodedInsts_0_sra | _io_rs2Read_0_valid_T_24 | decodedInsts_0_max + | decodedInsts_0_maxu | decodedInsts_0_rol | decodedInsts_0_ror + | _io_rs2Read_0_valid_T_32 | decodedInsts_0_sw + | (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) & ~(io_inst_0_bits_inst[14]) + | _io_rs2Read_0_valid_T_42 | decodedInsts_0_mulhsu | decodedInsts_0_mulhu + | _io_rs2Read_0_valid_T_47 | decodedInsts_0_rem | decodedInsts_0_remu); + assign io_rs2Read_0_addr = io_inst_0_bits_inst[24:20]; + assign io_rs2Read_1_valid = + _io_frs1Read_1_valid_T + & (_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt | decodedInsts_1_bge + | decodedInsts_1_bltu | decodedInsts_1_bgeu | _io_rs2Read_1_valid_T_6 + | decodedInsts_1_slt | decodedInsts_1_sltu | decodedInsts_1_xor | decodedInsts_1_or + | decodedInsts_1_and | decodedInsts_1_xnor | decodedInsts_1_orn + | decodedInsts_1_andn | decodedInsts_1_sll | decodedInsts_1_srl + | decodedInsts_1_sra | _io_rs2Read_1_valid_T_24 | decodedInsts_1_max + | decodedInsts_1_maxu | decodedInsts_1_rol | decodedInsts_1_ror + | _io_rs2Read_1_valid_T_32 | decodedInsts_1_sw | _io_rs2Read_1_valid_T_42 + | decodedInsts_1_mulhsu | decodedInsts_1_mulhu); + assign io_rs2Read_1_addr = io_inst_1_bits_inst[24:20]; + assign io_rs2Read_2_valid = + _io_frs1Read_2_valid_T + & (_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt | decodedInsts_2_bge + | decodedInsts_2_bltu | decodedInsts_2_bgeu | _io_rs2Read_2_valid_T_6 + | decodedInsts_2_slt | decodedInsts_2_sltu | decodedInsts_2_xor | decodedInsts_2_or + | decodedInsts_2_and | decodedInsts_2_xnor | decodedInsts_2_orn + | decodedInsts_2_andn | decodedInsts_2_sll | decodedInsts_2_srl + | decodedInsts_2_sra | _io_rs2Read_2_valid_T_24 | decodedInsts_2_max + | decodedInsts_2_maxu | decodedInsts_2_rol | decodedInsts_2_ror + | _io_rs2Read_2_valid_T_32 | decodedInsts_2_sw | _io_rs2Read_2_valid_T_42 + | decodedInsts_2_mulhsu | decodedInsts_2_mulhu); + assign io_rs2Read_2_addr = io_inst_2_bits_inst[24:20]; + assign io_rs2Read_3_valid = + _io_frs1Read_3_valid_T + & (_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu | _io_rs2Read_3_valid_T_6 + | decodedInsts_3_slt | decodedInsts_3_sltu | decodedInsts_3_xor | decodedInsts_3_or + | decodedInsts_3_and | decodedInsts_3_xnor | decodedInsts_3_orn + | decodedInsts_3_andn | decodedInsts_3_sll | decodedInsts_3_srl + | decodedInsts_3_sra | _io_rs2Read_3_valid_T_24 | decodedInsts_3_max + | decodedInsts_3_maxu | decodedInsts_3_rol | decodedInsts_3_ror + | _io_rs2Read_3_valid_T_32 | decodedInsts_3_sw | _io_rs2Read_3_valid_T_42 + | decodedInsts_3_mulhsu | decodedInsts_3_mulhu); + assign io_rs2Read_3_addr = io_inst_3_bits_inst[24:20]; + assign io_rs2Set_0_valid = + _io_frs1Read_0_valid_T + & (decodedInsts_0_auipc | (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) + & io_inst_0_bits_inst[14] | _io_rs2Set_0_valid_T_6 | decodedInsts_0_sltiu + | decodedInsts_0_xori | decodedInsts_0_ori | decodedInsts_0_andi + | decodedInsts_0_slli | decodedInsts_0_srli | decodedInsts_0_srai + | decodedInsts_0_rori | _io_rs2Set_0_valid_T_21 | decodedInsts_0_cpop + | decodedInsts_0_sextb | decodedInsts_0_sexth | decodedInsts_0_zexth + | decodedInsts_0_orcb | decodedInsts_0_rev8 | decodedInsts_0_lui); + assign io_rs2Set_0_value = + decodedInsts_0_auipc | decodedInsts_0_lui + ? {io_inst_0_bits_inst[31:12], 12'h0} + : {_decodedInsts_d_imm12_T_1, io_inst_0_bits_inst[31:20]}; + assign io_rs2Set_1_valid = + _io_frs1Read_1_valid_T + & (decodedInsts_1_auipc | _io_rs2Set_1_valid_T_6 | decodedInsts_1_sltiu + | decodedInsts_1_xori | decodedInsts_1_ori | decodedInsts_1_andi + | decodedInsts_1_slli | decodedInsts_1_srli | decodedInsts_1_srai + | decodedInsts_1_rori | _io_rs2Set_1_valid_T_21 | decodedInsts_1_cpop + | decodedInsts_1_sextb | decodedInsts_1_sexth | decodedInsts_1_zexth + | decodedInsts_1_orcb | decodedInsts_1_rev8 | decodedInsts_1_lui); + assign io_rs2Set_1_value = + decodedInsts_1_auipc | decodedInsts_1_lui + ? {io_inst_1_bits_inst[31:12], 12'h0} + : {_decodedInsts_d_imm12_T_5, io_inst_1_bits_inst[31:20]}; + assign io_rs2Set_2_valid = + _io_frs1Read_2_valid_T + & (decodedInsts_2_auipc | _io_rs2Set_2_valid_T_6 | decodedInsts_2_sltiu + | decodedInsts_2_xori | decodedInsts_2_ori | decodedInsts_2_andi + | decodedInsts_2_slli | decodedInsts_2_srli | decodedInsts_2_srai + | decodedInsts_2_rori | _io_rs2Set_2_valid_T_21 | decodedInsts_2_cpop + | decodedInsts_2_sextb | decodedInsts_2_sexth | decodedInsts_2_zexth + | decodedInsts_2_orcb | decodedInsts_2_rev8 | decodedInsts_2_lui); + assign io_rs2Set_2_value = + decodedInsts_2_auipc | decodedInsts_2_lui + ? {io_inst_2_bits_inst[31:12], 12'h0} + : {_decodedInsts_d_imm12_T_9, io_inst_2_bits_inst[31:20]}; + assign io_rs2Set_3_valid = + _io_frs1Read_3_valid_T + & (decodedInsts_3_auipc | _io_rs2Set_3_valid_T_6 | decodedInsts_3_sltiu + | decodedInsts_3_xori | decodedInsts_3_ori | decodedInsts_3_andi + | decodedInsts_3_slli | decodedInsts_3_srli | decodedInsts_3_srai + | decodedInsts_3_rori | _io_rs2Set_3_valid_T_21 | decodedInsts_3_cpop + | decodedInsts_3_sextb | decodedInsts_3_sexth | decodedInsts_3_zexth + | decodedInsts_3_orcb | decodedInsts_3_rev8 | decodedInsts_3_lui); + assign io_rs2Set_3_value = + decodedInsts_3_auipc | decodedInsts_3_lui + ? {io_inst_3_bits_inst[31:12], 12'h0} + : {_decodedInsts_d_imm12_T_13, io_inst_3_bits_inst[31:20]}; + assign io_rdMark_0_valid = + io_alu_0_valid_0 | io_mlu_0_valid_0 | dispatched_3 | dispatched_4 + & (_rdMark_valid_T_5 | decodedInsts_0_lw | decodedInsts_0_lbu | decodedInsts_0_lhu) + | io_csr_valid_0 | dispatched_7 & decodedInsts_float_scalar_rd | io_bru_0_valid_0 + & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_0_bits_inst[11:7])); + assign io_rdMark_0_addr = io_inst_0_bits_inst[11:7]; + assign io_rdMark_1_valid = + io_alu_1_valid_0 | dispatched_2_1 | dispatched_4_1 + & (_rdMark_valid_T_30 | decodedInsts_1_lw | decodedInsts_1_lbu | decodedInsts_1_lhu) + | io_bru_1_valid_0 & (|{bru_1_bits[2:0] == 3'h1, bru_1_bits[2:0] == 3'h0}) + & (|(io_inst_1_bits_inst[11:7])); + assign io_rdMark_1_addr = io_inst_1_bits_inst[11:7]; + assign io_rdMark_2_valid = + io_alu_2_valid_0 | dispatched_2_2 | dispatched_4_2 + & (_rdMark_valid_T_53 | decodedInsts_2_lw | decodedInsts_2_lbu | decodedInsts_2_lhu) + | io_bru_2_valid_0 & (|{bru_2_bits[2:0] == 3'h1, bru_2_bits[2:0] == 3'h0}) + & (|(io_inst_2_bits_inst[11:7])); + assign io_rdMark_2_addr = io_inst_2_bits_inst[11:7]; + assign io_rdMark_3_valid = + io_alu_3_valid_0 | dispatched_2_3 | dispatched_4_3 + & (_rdMark_valid_T_76 | decodedInsts_3_lw | decodedInsts_3_lbu | decodedInsts_3_lhu) + | io_bru_3_valid_0 & (|{bru_3_bits[2:0] == 3'h1, bru_3_bits[2:0] == 3'h0}) + & (|(io_inst_3_bits_inst[11:7])); + assign io_rdMark_3_addr = io_inst_3_bits_inst[11:7]; + assign io_busRead_0_immed = + {_decodedInsts_d_imm12_T_1, + io_inst_0_bits_inst[31:25], + io_inst_0_bits_inst[6:3] == 4'h4 & (&(io_inst_0_bits_inst[1:0])) + ? io_inst_0_bits_inst[11:7] + : io_inst_0_bits_inst[24:20]}; + assign io_busRead_1_immed = + {_decodedInsts_d_imm12_T_5, + io_inst_1_bits_inst[31:25], + io_inst_1_bits_inst[6:3] == 4'h4 & (&(io_inst_1_bits_inst[1:0])) + ? io_inst_1_bits_inst[11:7] + : io_inst_1_bits_inst[24:20]}; + assign io_busRead_2_immed = + {_decodedInsts_d_imm12_T_9, + io_inst_2_bits_inst[31:25], + io_inst_2_bits_inst[6:3] == 4'h4 & (&(io_inst_2_bits_inst[1:0])) + ? io_inst_2_bits_inst[11:7] + : io_inst_2_bits_inst[24:20]}; + assign io_busRead_3_immed = + {_decodedInsts_d_imm12_T_13, + io_inst_3_bits_inst[31:25], + io_inst_3_bits_inst[6:3] == 4'h4 & (&(io_inst_3_bits_inst[1:0])) + ? io_inst_3_bits_inst[11:7] + : io_inst_3_bits_inst[24:20]}; + assign io_rdMark_flt_valid = + dispatched_7 & ~decodedInsts_float_scalar_rd | dispatched_4 & decodedInsts_floatValid + & ~(|io_float_bits_opcode_0); + assign io_rdMark_flt_addr = io_inst_0_bits_inst[11:7]; + assign io_alu_0_valid = io_alu_0_valid_0; + assign io_alu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_alu_0_bits_op = + {5'h0, decodedInsts_0_sub} | {4'h0, _alu_T_215, 1'h0} | (_alu_T_216 ? 6'h3 : 6'h0) + | {3'h0, _alu_T_217, 2'h0} | (_alu_T_218 ? 6'h5 : 6'h0) | (_alu_T_219 ? 6'h6 : 6'h0) + | (_alu_T_220 ? 6'h7 : 6'h0) | {2'h0, _alu_T_221, 3'h0} | (_alu_T_222 ? 6'h9 : 6'h0) + | (decodedInsts_0_lui ? 6'hA : 6'h0) | {1'h0, decodedInsts_0_andn, 4'h0} + | (decodedInsts_0_orn ? 6'h11 : 6'h0) | (decodedInsts_0_xnor ? 6'h12 : 6'h0) + | (decodedInsts_0_clz ? 6'h13 : 6'h0) | (decodedInsts_0_ctz ? 6'h14 : 6'h0) + | (decodedInsts_0_cpop ? 6'h15 : 6'h0) | (decodedInsts_0_max ? 6'h16 : 6'h0) + | (decodedInsts_0_maxu ? 6'h17 : 6'h0) | (decodedInsts_0_min ? 6'h18 : 6'h0) + | (decodedInsts_0_minu ? 6'h19 : 6'h0) | (decodedInsts_0_sextb ? 6'h1A : 6'h0) + | (decodedInsts_0_sexth ? 6'h1B : 6'h0) | (decodedInsts_0_rol ? 6'h1C : 6'h0) + | (decodedInsts_0_ror ? 6'h1D : 6'h0) | (decodedInsts_0_orcb ? 6'h1E : 6'h0) + | (decodedInsts_0_rev8 ? 6'h1F : 6'h0) | {decodedInsts_0_zexth, 5'h0} + | (decodedInsts_0_rori ? 6'h1D : 6'h0); + assign io_alu_1_valid = io_alu_1_valid_0; + assign io_alu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_alu_1_bits_op = + {5'h0, decodedInsts_1_sub} | {4'h0, _alu_T_508, 1'h0} | (_alu_T_509 ? 6'h3 : 6'h0) + | {3'h0, _alu_T_510, 2'h0} | (_alu_T_511 ? 6'h5 : 6'h0) | (_alu_T_512 ? 6'h6 : 6'h0) + | (_alu_T_513 ? 6'h7 : 6'h0) | {2'h0, _alu_T_514, 3'h0} | (_alu_T_515 ? 6'h9 : 6'h0) + | (decodedInsts_1_lui ? 6'hA : 6'h0) | {1'h0, decodedInsts_1_andn, 4'h0} + | (decodedInsts_1_orn ? 6'h11 : 6'h0) | (decodedInsts_1_xnor ? 6'h12 : 6'h0) + | (decodedInsts_1_clz ? 6'h13 : 6'h0) | (decodedInsts_1_ctz ? 6'h14 : 6'h0) + | (decodedInsts_1_cpop ? 6'h15 : 6'h0) | (decodedInsts_1_max ? 6'h16 : 6'h0) + | (decodedInsts_1_maxu ? 6'h17 : 6'h0) | (decodedInsts_1_min ? 6'h18 : 6'h0) + | (decodedInsts_1_minu ? 6'h19 : 6'h0) | (decodedInsts_1_sextb ? 6'h1A : 6'h0) + | (decodedInsts_1_sexth ? 6'h1B : 6'h0) | (decodedInsts_1_rol ? 6'h1C : 6'h0) + | (decodedInsts_1_ror ? 6'h1D : 6'h0) | (decodedInsts_1_orcb ? 6'h1E : 6'h0) + | (decodedInsts_1_rev8 ? 6'h1F : 6'h0) | {decodedInsts_1_zexth, 5'h0} + | (decodedInsts_1_rori ? 6'h1D : 6'h0); + assign io_alu_2_valid = io_alu_2_valid_0; + assign io_alu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_alu_2_bits_op = + {5'h0, decodedInsts_2_sub} | {4'h0, _alu_T_801, 1'h0} | (_alu_T_802 ? 6'h3 : 6'h0) + | {3'h0, _alu_T_803, 2'h0} | (_alu_T_804 ? 6'h5 : 6'h0) | (_alu_T_805 ? 6'h6 : 6'h0) + | (_alu_T_806 ? 6'h7 : 6'h0) | {2'h0, _alu_T_807, 3'h0} | (_alu_T_808 ? 6'h9 : 6'h0) + | (decodedInsts_2_lui ? 6'hA : 6'h0) | {1'h0, decodedInsts_2_andn, 4'h0} + | (decodedInsts_2_orn ? 6'h11 : 6'h0) | (decodedInsts_2_xnor ? 6'h12 : 6'h0) + | (decodedInsts_2_clz ? 6'h13 : 6'h0) | (decodedInsts_2_ctz ? 6'h14 : 6'h0) + | (decodedInsts_2_cpop ? 6'h15 : 6'h0) | (decodedInsts_2_max ? 6'h16 : 6'h0) + | (decodedInsts_2_maxu ? 6'h17 : 6'h0) | (decodedInsts_2_min ? 6'h18 : 6'h0) + | (decodedInsts_2_minu ? 6'h19 : 6'h0) | (decodedInsts_2_sextb ? 6'h1A : 6'h0) + | (decodedInsts_2_sexth ? 6'h1B : 6'h0) | (decodedInsts_2_rol ? 6'h1C : 6'h0) + | (decodedInsts_2_ror ? 6'h1D : 6'h0) | (decodedInsts_2_orcb ? 6'h1E : 6'h0) + | (decodedInsts_2_rev8 ? 6'h1F : 6'h0) | {decodedInsts_2_zexth, 5'h0} + | (decodedInsts_2_rori ? 6'h1D : 6'h0); + assign io_alu_3_valid = io_alu_3_valid_0; + assign io_alu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_alu_3_bits_op = + {5'h0, decodedInsts_3_sub} | {4'h0, _alu_T_1094, 1'h0} | (_alu_T_1095 ? 6'h3 : 6'h0) + | {3'h0, _alu_T_1096, 2'h0} | (_alu_T_1097 ? 6'h5 : 6'h0) + | (_alu_T_1098 ? 6'h6 : 6'h0) | (_alu_T_1099 ? 6'h7 : 6'h0) + | {2'h0, _alu_T_1100, 3'h0} | (_alu_T_1101 ? 6'h9 : 6'h0) + | (decodedInsts_3_lui ? 6'hA : 6'h0) | {1'h0, decodedInsts_3_andn, 4'h0} + | (decodedInsts_3_orn ? 6'h11 : 6'h0) | (decodedInsts_3_xnor ? 6'h12 : 6'h0) + | (decodedInsts_3_clz ? 6'h13 : 6'h0) | (decodedInsts_3_ctz ? 6'h14 : 6'h0) + | (decodedInsts_3_cpop ? 6'h15 : 6'h0) | (decodedInsts_3_max ? 6'h16 : 6'h0) + | (decodedInsts_3_maxu ? 6'h17 : 6'h0) | (decodedInsts_3_min ? 6'h18 : 6'h0) + | (decodedInsts_3_minu ? 6'h19 : 6'h0) | (decodedInsts_3_sextb ? 6'h1A : 6'h0) + | (decodedInsts_3_sexth ? 6'h1B : 6'h0) | (decodedInsts_3_rol ? 6'h1C : 6'h0) + | (decodedInsts_3_ror ? 6'h1D : 6'h0) | (decodedInsts_3_orcb ? 6'h1E : 6'h0) + | (decodedInsts_3_rev8 ? 6'h1F : 6'h0) | {decodedInsts_3_zexth, 5'h0} + | (decodedInsts_3_rori ? 6'h1D : 6'h0); + assign io_bru_0_valid = io_bru_0_valid_0; + assign io_bru_0_bits_fwd = io_inst_0_bits_brchFwd; + assign io_bru_0_bits_op = bru_bits; + assign io_bru_0_bits_pc = io_inst_0_bits_addr; + assign io_bru_0_bits_target = _bru_target_T_2; + assign io_bru_0_bits_link = io_inst_0_bits_inst[11:7]; + assign io_bru_1_valid = io_bru_1_valid_0; + assign io_bru_1_bits_fwd = io_inst_1_bits_brchFwd; + assign io_bru_1_bits_op = bru_1_bits; + assign io_bru_1_bits_pc = io_inst_1_bits_addr; + assign io_bru_1_bits_target = _bru_target_T_5; + assign io_bru_1_bits_link = io_inst_1_bits_inst[11:7]; + assign io_bru_2_valid = io_bru_2_valid_0; + assign io_bru_2_bits_fwd = io_inst_2_bits_brchFwd; + assign io_bru_2_bits_op = bru_2_bits; + assign io_bru_2_bits_pc = io_inst_2_bits_addr; + assign io_bru_2_bits_target = _bru_target_T_8; + assign io_bru_2_bits_link = io_inst_2_bits_inst[11:7]; + assign io_bru_3_valid = io_bru_3_valid_0; + assign io_bru_3_bits_fwd = io_inst_3_bits_brchFwd; + assign io_bru_3_bits_op = bru_3_bits; + assign io_bru_3_bits_pc = io_inst_3_bits_addr; + assign io_bru_3_bits_target = _bru_target_T_11; + assign io_bru_3_bits_link = io_inst_3_bits_inst[11:7]; + assign io_csr_valid = io_csr_valid_0; + assign io_csr_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_csr_bits_index = io_inst_0_bits_inst[31:20]; + assign io_csr_bits_rs1 = io_inst_0_bits_inst[19:15]; + assign io_csr_bits_op = csr_bits; + assign io_lsu_0_valid = io_lsu_0_valid_0; + assign io_lsu_0_bits_store = io_inst_0_bits_inst[5]; + assign io_lsu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_lsu_0_bits_op = + {4'h0, decodedInsts_0_lh} | {3'h0, decodedInsts_0_lw, 1'h0} + | (decodedInsts_0_lbu ? 5'h3 : 5'h0) | {2'h0, decodedInsts_0_lhu, 2'h0} + | (decodedInsts_0_sb ? 5'h5 : 5'h0) | (decodedInsts_0_sh ? 5'h6 : 5'h0) + | (decodedInsts_0_sw ? 5'h7 : 5'h0) | (decodedInsts_0_wfi ? 5'hB : 5'h0) + | (decodedInsts_0_fencei ? 5'hB : 5'h0) + | (_lsu_T_93 ? {4'h6, io_inst_0_bits_inst[14:12] == 3'h1} : 5'h0); + assign io_lsu_0_bits_pc = io_inst_0_bits_addr; + assign io_lsu_1_valid = io_lsu_1_valid_0; + assign io_lsu_1_bits_store = io_inst_1_bits_inst[5]; + assign io_lsu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_lsu_1_bits_op = + {4'h0, decodedInsts_1_lh} | {3'h0, decodedInsts_1_lw, 1'h0} + | (decodedInsts_1_lbu ? 5'h3 : 5'h0) | {2'h0, decodedInsts_1_lhu, 2'h0} + | (decodedInsts_1_sb ? 5'h5 : 5'h0) | (decodedInsts_1_sh ? 5'h6 : 5'h0) + | (decodedInsts_1_sw ? 5'h7 : 5'h0); + assign io_lsu_1_bits_pc = io_inst_1_bits_addr; + assign io_lsu_2_valid = io_lsu_2_valid_0; + assign io_lsu_2_bits_store = io_inst_2_bits_inst[5]; + assign io_lsu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_lsu_2_bits_op = + {4'h0, decodedInsts_2_lh} | {3'h0, decodedInsts_2_lw, 1'h0} + | (decodedInsts_2_lbu ? 5'h3 : 5'h0) | {2'h0, decodedInsts_2_lhu, 2'h0} + | (decodedInsts_2_sb ? 5'h5 : 5'h0) | (decodedInsts_2_sh ? 5'h6 : 5'h0) + | (decodedInsts_2_sw ? 5'h7 : 5'h0); + assign io_lsu_2_bits_pc = io_inst_2_bits_addr; + assign io_lsu_3_valid = io_lsu_3_valid_0; + assign io_lsu_3_bits_store = io_inst_3_bits_inst[5]; + assign io_lsu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_lsu_3_bits_op = + {4'h0, decodedInsts_3_lh} | {3'h0, decodedInsts_3_lw, 1'h0} + | (decodedInsts_3_lbu ? 5'h3 : 5'h0) | {2'h0, decodedInsts_3_lhu, 2'h0} + | (decodedInsts_3_sb ? 5'h5 : 5'h0) | (decodedInsts_3_sh ? 5'h6 : 5'h0) + | (decodedInsts_3_sw ? 5'h7 : 5'h0); + assign io_lsu_3_bits_pc = io_inst_3_bits_addr; + assign io_mlu_0_valid = io_mlu_0_valid_0; + assign io_mlu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_mlu_0_bits_op = + {2'h0, decodedInsts_0_mulh} | {1'h0, decodedInsts_0_mulhsu, 1'h0} + | (decodedInsts_0_mulhu ? 3'h3 : 3'h0); + assign io_mlu_1_valid = io_mlu_1_valid_0; + assign io_mlu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_mlu_1_bits_op = + {2'h0, decodedInsts_1_mulh} | {1'h0, decodedInsts_1_mulhsu, 1'h0} + | (decodedInsts_1_mulhu ? 3'h3 : 3'h0); + assign io_mlu_2_valid = io_mlu_2_valid_0; + assign io_mlu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_mlu_2_bits_op = + {2'h0, decodedInsts_2_mulh} | {1'h0, decodedInsts_2_mulhsu, 1'h0} + | (decodedInsts_2_mulhu ? 3'h3 : 3'h0); + assign io_mlu_3_valid = io_mlu_3_valid_0; + assign io_mlu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_mlu_3_bits_op = + {2'h0, decodedInsts_3_mulh} | {1'h0, decodedInsts_3_mulhsu, 1'h0} + | (decodedInsts_3_mulhu ? 3'h3 : 3'h0); + assign io_dvu_0_valid = io_dvu_0_valid_0; + assign io_dvu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_dvu_0_bits_op = + {2'h0, decodedInsts_0_divu} | {1'h0, decodedInsts_0_rem, 1'h0} + | (decodedInsts_0_remu ? 3'h3 : 3'h0); + assign io_float_valid = io_float_valid_0; + assign io_float_bits_opcode = io_float_bits_opcode_0; + assign io_float_bits_funct5 = io_inst_0_bits_inst[31:27]; + assign io_float_bits_src_fmt = + decodedInsts_float_fcvt_bf16_s ? 3'h0 : {decodedInsts_float_fcvt_s_bf16, 2'h0}; + assign io_float_bits_dst_fmt = {decodedInsts_float_fcvt_bf16_s, 2'h0}; + assign io_float_bits_rs3 = io_inst_0_bits_inst[31:27]; + assign io_float_bits_rs2 = io_inst_0_bits_inst[24:20]; + assign io_float_bits_rs1 = io_inst_0_bits_inst[19:15]; + assign io_float_bits_rm = io_inst_0_bits_inst[14:12]; + assign io_float_bits_inst = io_inst_0_bits_inst; + assign io_float_bits_pc = io_inst_0_bits_addr; + assign io_float_bits_scalar_rd = decodedInsts_float_scalar_rd; + assign io_float_bits_scalar_rs1 = decodedInsts_float_scalar_rs1; + assign io_float_bits_float_rs1 = decodedInsts_float_float_rs1; + assign io_float_bits_rd = io_inst_0_bits_inst[11:7]; + assign io_float_bits_uses_rs3 = |_decodedInsts_float_uses_rs3_T_4; + assign io_float_bits_uses_rs2 = decodedInsts_float_uses_rs2; assign io_fbusPortAddr = io_inst_0_bits_inst[24:20]; + assign io_branch_0 = isBranch_0; + assign io_branch_1 = isBranch_1; + assign io_branch_2 = isBranch_2; + assign io_branch_3 = + _io_rs2Read_3_valid_T_1 | decodedInsts_3_blt | decodedInsts_3_bge + | decodedInsts_3_bltu | decodedInsts_3_bgeu; + assign io_jump_0 = + (_bru_defaultSel_T | decodedInsts_0_ebreak | decodedInsts_0_ecall + | decodedInsts_0_mpause | decodedInsts_0_mret) & io_inst_0_bits_inst != 32'h73 + & io_inst_0_bits_inst != 32'h30200073; + assign io_jump_1 = isJump_1; + assign io_jump_2 = isJump_2; + assign io_jump_3 = decodedInsts_3_jal | decodedInsts_3_jalr; +endmodule + +module CircularBufferMulti_1( + input clock, + reset, + input [2:0] io_enqValid, + input io_enqData_0_store, + input [4:0] io_enqData_0_rd, + io_enqData_0_op, + input [31:0] io_enqData_0_pc, + io_enqData_0_addr, + io_enqData_0_data, + input [2:0] io_enqData_0_unreachableCell, + input io_enqData_0_initAsConstStride, + io_enqData_1_store, + input [4:0] io_enqData_1_rd, + io_enqData_1_op, + input [31:0] io_enqData_1_pc, + io_enqData_1_addr, + io_enqData_1_data, + input [2:0] io_enqData_1_unreachableCell, + input io_enqData_1_initAsConstStride, + io_enqData_2_store, + input [4:0] io_enqData_2_rd, + io_enqData_2_op, + input [31:0] io_enqData_2_pc, + io_enqData_2_addr, + io_enqData_2_data, + input [2:0] io_enqData_2_unreachableCell, + input io_enqData_2_initAsConstStride, + io_enqData_3_store, + input [4:0] io_enqData_3_rd, + io_enqData_3_op, + input [31:0] io_enqData_3_pc, + io_enqData_3_addr, + io_enqData_3_data, + input [2:0] io_enqData_3_unreachableCell, + input io_enqData_3_initAsConstStride, + output [2:0] io_nEnqueued, + io_nSpace, + output io_dataOut_0_store, + output [4:0] io_dataOut_0_rd, + io_dataOut_0_op, + output [31:0] io_dataOut_0_pc, + io_dataOut_0_addr, + io_dataOut_0_data, + output [2:0] io_dataOut_0_unreachableCell, + output io_dataOut_0_initAsConstStride, + io_dataOut_1_store, + output [4:0] io_dataOut_1_rd, + io_dataOut_1_op, + output [31:0] io_dataOut_1_pc, + io_dataOut_1_addr, + io_dataOut_1_data, + output [2:0] io_dataOut_1_unreachableCell, + output io_dataOut_1_initAsConstStride, + io_dataOut_2_store, + output [4:0] io_dataOut_2_rd, + io_dataOut_2_op, + output [31:0] io_dataOut_2_pc, + io_dataOut_2_addr, + io_dataOut_2_data, + output [2:0] io_dataOut_2_unreachableCell, + output io_dataOut_2_initAsConstStride, + io_dataOut_3_store, + output [4:0] io_dataOut_3_rd, + io_dataOut_3_op, + output [31:0] io_dataOut_3_pc, + io_dataOut_3_addr, + io_dataOut_3_data, + output [2:0] io_dataOut_3_unreachableCell, + output io_dataOut_3_initAsConstStride, + input [2:0] io_deqReady, + input io_flush +); + + reg buffer_0_store; + reg [4:0] buffer_0_rd; + reg [4:0] buffer_0_op; + reg [31:0] buffer_0_pc; + reg [31:0] buffer_0_addr; + reg [31:0] buffer_0_data; + reg [2:0] buffer_0_unreachableCell; + reg buffer_0_initAsConstStride; + reg buffer_1_store; + reg [4:0] buffer_1_rd; + reg [4:0] buffer_1_op; + reg [31:0] buffer_1_pc; + reg [31:0] buffer_1_addr; + reg [31:0] buffer_1_data; + reg [2:0] buffer_1_unreachableCell; + reg buffer_1_initAsConstStride; + reg buffer_2_store; + reg [4:0] buffer_2_rd; + reg [4:0] buffer_2_op; + reg [31:0] buffer_2_pc; + reg [31:0] buffer_2_addr; + reg [31:0] buffer_2_data; + reg [2:0] buffer_2_unreachableCell; + reg buffer_2_initAsConstStride; + reg buffer_3_store; + reg [4:0] buffer_3_rd; + reg [4:0] buffer_3_op; + reg [31:0] buffer_3_pc; + reg [31:0] buffer_3_addr; + reg [31:0] buffer_3_data; + reg [2:0] buffer_3_unreachableCell; + reg buffer_3_initAsConstStride; + reg [1:0] enqPtr; + reg [1:0] deqPtr; + reg [2:0] nEnqueued; + wire _shifted_T_4_store = deqPtr[1] ? buffer_3_store : buffer_1_store; + wire [4:0] _shifted_T_4_rd = deqPtr[1] ? buffer_3_rd : buffer_1_rd; + wire [4:0] _shifted_T_4_op = deqPtr[1] ? buffer_3_op : buffer_1_op; + wire [31:0] _shifted_T_4_pc = deqPtr[1] ? buffer_3_pc : buffer_1_pc; + wire [31:0] _shifted_T_4_addr = deqPtr[1] ? buffer_3_addr : buffer_1_addr; + wire [31:0] _shifted_T_4_data = deqPtr[1] ? buffer_3_data : buffer_1_data; + wire [2:0] _shifted_T_4_unreachableCell = + deqPtr[1] ? buffer_3_unreachableCell : buffer_1_unreachableCell; + wire _shifted_T_4_initAsConstStride = + deqPtr[1] ? buffer_3_initAsConstStride : buffer_1_initAsConstStride; + wire _shifted_T_7_store = deqPtr[1] ? buffer_0_store : buffer_2_store; + wire [4:0] _shifted_T_7_rd = deqPtr[1] ? buffer_0_rd : buffer_2_rd; + wire [4:0] _shifted_T_7_op = deqPtr[1] ? buffer_0_op : buffer_2_op; + wire [31:0] _shifted_T_7_pc = deqPtr[1] ? buffer_0_pc : buffer_2_pc; + wire [31:0] _shifted_T_7_addr = deqPtr[1] ? buffer_0_addr : buffer_2_addr; + wire [31:0] _shifted_T_7_data = deqPtr[1] ? buffer_0_data : buffer_2_data; + wire [2:0] _shifted_T_7_unreachableCell = + deqPtr[1] ? buffer_0_unreachableCell : buffer_2_unreachableCell; + wire _shifted_T_7_initAsConstStride = + deqPtr[1] ? buffer_0_initAsConstStride : buffer_2_initAsConstStride; + wire _shifted_T_10_store = deqPtr[1] ? buffer_1_store : buffer_3_store; + wire [4:0] _shifted_T_10_rd = deqPtr[1] ? buffer_1_rd : buffer_3_rd; + wire [4:0] _shifted_T_10_op = deqPtr[1] ? buffer_1_op : buffer_3_op; + wire [31:0] _shifted_T_10_pc = deqPtr[1] ? buffer_1_pc : buffer_3_pc; + wire [31:0] _shifted_T_10_addr = deqPtr[1] ? buffer_1_addr : buffer_3_addr; + wire [31:0] _shifted_T_10_data = deqPtr[1] ? buffer_1_data : buffer_3_data; + wire [2:0] _shifted_T_10_unreachableCell = + deqPtr[1] ? buffer_1_unreachableCell : buffer_3_unreachableCell; + wire _shifted_T_10_initAsConstStride = + deqPtr[1] ? buffer_1_initAsConstStride : buffer_3_initAsConstStride; + wire matches_isTargetSlot = enqPtr == 2'h0; + wire matches_0 = (|io_enqValid) & matches_isTargetSlot; + wire matches_1 = (|(io_enqValid[2:1])) & (&enqPtr); + wire matches_isTargetSlot_2 = enqPtr == 2'h2; + wire _matches_T_28 = io_enqValid > 3'h2; + wire matches_2 = _matches_T_28 & matches_isTargetSlot_2; + wire matches_isTargetSlot_3 = enqPtr == 2'h1; + wire matches_3 = io_enqValid[2] & matches_isTargetSlot_3; + wire matches_1_0 = (|io_enqValid) & matches_isTargetSlot_3; + wire matches_1_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot; + wire matches_1_2 = _matches_T_28 & (&enqPtr); + wire matches_1_3 = io_enqValid[2] & matches_isTargetSlot_2; + wire matches_2_0 = (|io_enqValid) & matches_isTargetSlot_2; + wire matches_2_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_3; + wire matches_2_2 = _matches_T_28 & matches_isTargetSlot; + wire matches_2_3 = io_enqValid[2] & (&enqPtr); + wire matches_3_0 = (|io_enqValid) & (&enqPtr); + wire matches_3_1 = (|(io_enqValid[2:1])) & matches_isTargetSlot_2; + wire matches_3_2 = _matches_T_28 & matches_isTargetSlot_3; + wire matches_3_3 = io_enqValid[2] & matches_isTargetSlot; + always @(posedge clock or posedge reset) begin + if (reset) begin + buffer_0_store <= 1'h0; + buffer_0_rd <= 5'h0; + buffer_0_op <= 5'h0; + buffer_0_pc <= 32'h0; + buffer_0_addr <= 32'h0; + buffer_0_data <= 32'h0; + buffer_0_unreachableCell <= 3'h0; + buffer_0_initAsConstStride <= 1'h0; + buffer_1_store <= 1'h0; + buffer_1_rd <= 5'h0; + buffer_1_op <= 5'h0; + buffer_1_pc <= 32'h0; + buffer_1_addr <= 32'h0; + buffer_1_data <= 32'h0; + buffer_1_unreachableCell <= 3'h0; + buffer_1_initAsConstStride <= 1'h0; + buffer_2_store <= 1'h0; + buffer_2_rd <= 5'h0; + buffer_2_op <= 5'h0; + buffer_2_pc <= 32'h0; + buffer_2_addr <= 32'h0; + buffer_2_data <= 32'h0; + buffer_2_unreachableCell <= 3'h0; + buffer_2_initAsConstStride <= 1'h0; + buffer_3_store <= 1'h0; + buffer_3_rd <= 5'h0; + buffer_3_op <= 5'h0; + buffer_3_pc <= 32'h0; + buffer_3_addr <= 32'h0; + buffer_3_data <= 32'h0; + buffer_3_unreachableCell <= 3'h0; + buffer_3_initAsConstStride <= 1'h0; + enqPtr <= 2'h0; + deqPtr <= 2'h0; + nEnqueued <= 3'h0; + end + else begin + if (|{matches_3, matches_2, matches_1, matches_0}) begin + buffer_0_store <= + matches_0 & io_enqData_0_store | matches_1 & io_enqData_1_store | matches_2 + & io_enqData_2_store | matches_3 & io_enqData_3_store; + buffer_0_rd <= + (matches_0 ? io_enqData_0_rd : 5'h0) | (matches_1 ? io_enqData_1_rd : 5'h0) + | (matches_2 ? io_enqData_2_rd : 5'h0) | (matches_3 ? io_enqData_3_rd : 5'h0); + buffer_0_op <= + (matches_0 ? io_enqData_0_op : 5'h0) | (matches_1 ? io_enqData_1_op : 5'h0) + | (matches_2 ? io_enqData_2_op : 5'h0) | (matches_3 ? io_enqData_3_op : 5'h0); + buffer_0_pc <= + (matches_0 ? io_enqData_0_pc : 32'h0) | (matches_1 ? io_enqData_1_pc : 32'h0) + | (matches_2 ? io_enqData_2_pc : 32'h0) | (matches_3 ? io_enqData_3_pc : 32'h0); + buffer_0_addr <= + (matches_0 ? io_enqData_0_addr : 32'h0) + | (matches_1 ? io_enqData_1_addr : 32'h0) + | (matches_2 ? io_enqData_2_addr : 32'h0) + | (matches_3 ? io_enqData_3_addr : 32'h0); + buffer_0_data <= + (matches_0 ? io_enqData_0_data : 32'h0) + | (matches_1 ? io_enqData_1_data : 32'h0) + | (matches_2 ? io_enqData_2_data : 32'h0) + | (matches_3 ? io_enqData_3_data : 32'h0); + buffer_0_unreachableCell <= + (matches_0 ? io_enqData_0_unreachableCell : 3'h0) + | (matches_1 ? io_enqData_1_unreachableCell : 3'h0) + | (matches_2 ? io_enqData_2_unreachableCell : 3'h0) + | (matches_3 ? io_enqData_3_unreachableCell : 3'h0); + buffer_0_initAsConstStride <= + matches_0 & io_enqData_0_initAsConstStride | matches_1 + & io_enqData_1_initAsConstStride | matches_2 & io_enqData_2_initAsConstStride + | matches_3 & io_enqData_3_initAsConstStride; + end + if (|{matches_1_3, matches_1_2, matches_1_1, matches_1_0}) begin + buffer_1_store <= + matches_1_0 & io_enqData_0_store | matches_1_1 & io_enqData_1_store + | matches_1_2 & io_enqData_2_store | matches_1_3 & io_enqData_3_store; + buffer_1_rd <= + (matches_1_0 ? io_enqData_0_rd : 5'h0) | (matches_1_1 ? io_enqData_1_rd : 5'h0) + | (matches_1_2 ? io_enqData_2_rd : 5'h0) + | (matches_1_3 ? io_enqData_3_rd : 5'h0); + buffer_1_op <= + (matches_1_0 ? io_enqData_0_op : 5'h0) | (matches_1_1 ? io_enqData_1_op : 5'h0) + | (matches_1_2 ? io_enqData_2_op : 5'h0) + | (matches_1_3 ? io_enqData_3_op : 5'h0); + buffer_1_pc <= + (matches_1_0 ? io_enqData_0_pc : 32'h0) + | (matches_1_1 ? io_enqData_1_pc : 32'h0) + | (matches_1_2 ? io_enqData_2_pc : 32'h0) + | (matches_1_3 ? io_enqData_3_pc : 32'h0); + buffer_1_addr <= + (matches_1_0 ? io_enqData_0_addr : 32'h0) + | (matches_1_1 ? io_enqData_1_addr : 32'h0) + | (matches_1_2 ? io_enqData_2_addr : 32'h0) + | (matches_1_3 ? io_enqData_3_addr : 32'h0); + buffer_1_data <= + (matches_1_0 ? io_enqData_0_data : 32'h0) + | (matches_1_1 ? io_enqData_1_data : 32'h0) + | (matches_1_2 ? io_enqData_2_data : 32'h0) + | (matches_1_3 ? io_enqData_3_data : 32'h0); + buffer_1_unreachableCell <= + (matches_1_0 ? io_enqData_0_unreachableCell : 3'h0) + | (matches_1_1 ? io_enqData_1_unreachableCell : 3'h0) + | (matches_1_2 ? io_enqData_2_unreachableCell : 3'h0) + | (matches_1_3 ? io_enqData_3_unreachableCell : 3'h0); + buffer_1_initAsConstStride <= + matches_1_0 & io_enqData_0_initAsConstStride | matches_1_1 + & io_enqData_1_initAsConstStride | matches_1_2 & io_enqData_2_initAsConstStride + | matches_1_3 & io_enqData_3_initAsConstStride; + end + if (|{matches_2_3, matches_2_2, matches_2_1, matches_2_0}) begin + buffer_2_store <= + matches_2_0 & io_enqData_0_store | matches_2_1 & io_enqData_1_store + | matches_2_2 & io_enqData_2_store | matches_2_3 & io_enqData_3_store; + buffer_2_rd <= + (matches_2_0 ? io_enqData_0_rd : 5'h0) | (matches_2_1 ? io_enqData_1_rd : 5'h0) + | (matches_2_2 ? io_enqData_2_rd : 5'h0) + | (matches_2_3 ? io_enqData_3_rd : 5'h0); + buffer_2_op <= + (matches_2_0 ? io_enqData_0_op : 5'h0) | (matches_2_1 ? io_enqData_1_op : 5'h0) + | (matches_2_2 ? io_enqData_2_op : 5'h0) + | (matches_2_3 ? io_enqData_3_op : 5'h0); + buffer_2_pc <= + (matches_2_0 ? io_enqData_0_pc : 32'h0) + | (matches_2_1 ? io_enqData_1_pc : 32'h0) + | (matches_2_2 ? io_enqData_2_pc : 32'h0) + | (matches_2_3 ? io_enqData_3_pc : 32'h0); + buffer_2_addr <= + (matches_2_0 ? io_enqData_0_addr : 32'h0) + | (matches_2_1 ? io_enqData_1_addr : 32'h0) + | (matches_2_2 ? io_enqData_2_addr : 32'h0) + | (matches_2_3 ? io_enqData_3_addr : 32'h0); + buffer_2_data <= + (matches_2_0 ? io_enqData_0_data : 32'h0) + | (matches_2_1 ? io_enqData_1_data : 32'h0) + | (matches_2_2 ? io_enqData_2_data : 32'h0) + | (matches_2_3 ? io_enqData_3_data : 32'h0); + buffer_2_unreachableCell <= + (matches_2_0 ? io_enqData_0_unreachableCell : 3'h0) + | (matches_2_1 ? io_enqData_1_unreachableCell : 3'h0) + | (matches_2_2 ? io_enqData_2_unreachableCell : 3'h0) + | (matches_2_3 ? io_enqData_3_unreachableCell : 3'h0); + buffer_2_initAsConstStride <= + matches_2_0 & io_enqData_0_initAsConstStride | matches_2_1 + & io_enqData_1_initAsConstStride | matches_2_2 & io_enqData_2_initAsConstStride + | matches_2_3 & io_enqData_3_initAsConstStride; + end + if (|{matches_3_3, matches_3_2, matches_3_1, matches_3_0}) begin + buffer_3_store <= + matches_3_0 & io_enqData_0_store | matches_3_1 & io_enqData_1_store + | matches_3_2 & io_enqData_2_store | matches_3_3 & io_enqData_3_store; + buffer_3_rd <= + (matches_3_0 ? io_enqData_0_rd : 5'h0) | (matches_3_1 ? io_enqData_1_rd : 5'h0) + | (matches_3_2 ? io_enqData_2_rd : 5'h0) + | (matches_3_3 ? io_enqData_3_rd : 5'h0); + buffer_3_op <= + (matches_3_0 ? io_enqData_0_op : 5'h0) | (matches_3_1 ? io_enqData_1_op : 5'h0) + | (matches_3_2 ? io_enqData_2_op : 5'h0) + | (matches_3_3 ? io_enqData_3_op : 5'h0); + buffer_3_pc <= + (matches_3_0 ? io_enqData_0_pc : 32'h0) + | (matches_3_1 ? io_enqData_1_pc : 32'h0) + | (matches_3_2 ? io_enqData_2_pc : 32'h0) + | (matches_3_3 ? io_enqData_3_pc : 32'h0); + buffer_3_addr <= + (matches_3_0 ? io_enqData_0_addr : 32'h0) + | (matches_3_1 ? io_enqData_1_addr : 32'h0) + | (matches_3_2 ? io_enqData_2_addr : 32'h0) + | (matches_3_3 ? io_enqData_3_addr : 32'h0); + buffer_3_data <= + (matches_3_0 ? io_enqData_0_data : 32'h0) + | (matches_3_1 ? io_enqData_1_data : 32'h0) + | (matches_3_2 ? io_enqData_2_data : 32'h0) + | (matches_3_3 ? io_enqData_3_data : 32'h0); + buffer_3_unreachableCell <= + (matches_3_0 ? io_enqData_0_unreachableCell : 3'h0) + | (matches_3_1 ? io_enqData_1_unreachableCell : 3'h0) + | (matches_3_2 ? io_enqData_2_unreachableCell : 3'h0) + | (matches_3_3 ? io_enqData_3_unreachableCell : 3'h0); + buffer_3_initAsConstStride <= + matches_3_0 & io_enqData_0_initAsConstStride | matches_3_1 + & io_enqData_1_initAsConstStride | matches_3_2 & io_enqData_2_initAsConstStride + | matches_3_3 & io_enqData_3_initAsConstStride; + end + enqPtr <= io_flush ? 2'h0 : enqPtr + io_enqValid[1:0]; + deqPtr <= io_flush ? 2'h0 : deqPtr + io_deqReady[1:0]; + nEnqueued <= io_flush ? 3'h0 : nEnqueued + io_enqValid - io_deqReady; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + buffer_0_store = 1'h0; + buffer_0_rd = 5'h0; + buffer_0_op = 5'h0; + buffer_0_pc = 32'h0; + buffer_0_addr = 32'h0; + buffer_0_data = 32'h0; + buffer_0_unreachableCell = 3'h0; + buffer_0_initAsConstStride = 1'h0; + buffer_1_store = 1'h0; + buffer_1_rd = 5'h0; + buffer_1_op = 5'h0; + buffer_1_pc = 32'h0; + buffer_1_addr = 32'h0; + buffer_1_data = 32'h0; + buffer_1_unreachableCell = 3'h0; + buffer_1_initAsConstStride = 1'h0; + buffer_2_store = 1'h0; + buffer_2_rd = 5'h0; + buffer_2_op = 5'h0; + buffer_2_pc = 32'h0; + buffer_2_addr = 32'h0; + buffer_2_data = 32'h0; + buffer_2_unreachableCell = 3'h0; + buffer_2_initAsConstStride = 1'h0; + buffer_3_store = 1'h0; + buffer_3_rd = 5'h0; + buffer_3_op = 5'h0; + buffer_3_pc = 32'h0; + buffer_3_addr = 32'h0; + buffer_3_data = 32'h0; + buffer_3_unreachableCell = 3'h0; + buffer_3_initAsConstStride = 1'h0; + enqPtr = 2'h0; + deqPtr = 2'h0; + nEnqueued = 3'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 3'h4 - nEnqueued; + assign io_dataOut_0_store = + deqPtr[0] ? _shifted_T_4_store : deqPtr[1] ? buffer_2_store : buffer_0_store; + assign io_dataOut_0_rd = + deqPtr[0] ? _shifted_T_4_rd : deqPtr[1] ? buffer_2_rd : buffer_0_rd; + assign io_dataOut_0_op = + deqPtr[0] ? _shifted_T_4_op : deqPtr[1] ? buffer_2_op : buffer_0_op; + assign io_dataOut_0_pc = + deqPtr[0] ? _shifted_T_4_pc : deqPtr[1] ? buffer_2_pc : buffer_0_pc; + assign io_dataOut_0_addr = + deqPtr[0] ? _shifted_T_4_addr : deqPtr[1] ? buffer_2_addr : buffer_0_addr; + assign io_dataOut_0_data = + deqPtr[0] ? _shifted_T_4_data : deqPtr[1] ? buffer_2_data : buffer_0_data; + assign io_dataOut_0_unreachableCell = + deqPtr[0] + ? _shifted_T_4_unreachableCell + : deqPtr[1] ? buffer_2_unreachableCell : buffer_0_unreachableCell; + assign io_dataOut_0_initAsConstStride = + deqPtr[0] + ? _shifted_T_4_initAsConstStride + : deqPtr[1] ? buffer_2_initAsConstStride : buffer_0_initAsConstStride; + assign io_dataOut_1_store = deqPtr[0] ? _shifted_T_7_store : _shifted_T_4_store; + assign io_dataOut_1_rd = deqPtr[0] ? _shifted_T_7_rd : _shifted_T_4_rd; + assign io_dataOut_1_op = deqPtr[0] ? _shifted_T_7_op : _shifted_T_4_op; + assign io_dataOut_1_pc = deqPtr[0] ? _shifted_T_7_pc : _shifted_T_4_pc; + assign io_dataOut_1_addr = deqPtr[0] ? _shifted_T_7_addr : _shifted_T_4_addr; + assign io_dataOut_1_data = deqPtr[0] ? _shifted_T_7_data : _shifted_T_4_data; + assign io_dataOut_1_unreachableCell = + deqPtr[0] ? _shifted_T_7_unreachableCell : _shifted_T_4_unreachableCell; + assign io_dataOut_1_initAsConstStride = + deqPtr[0] ? _shifted_T_7_initAsConstStride : _shifted_T_4_initAsConstStride; + assign io_dataOut_2_store = deqPtr[0] ? _shifted_T_10_store : _shifted_T_7_store; + assign io_dataOut_2_rd = deqPtr[0] ? _shifted_T_10_rd : _shifted_T_7_rd; + assign io_dataOut_2_op = deqPtr[0] ? _shifted_T_10_op : _shifted_T_7_op; + assign io_dataOut_2_pc = deqPtr[0] ? _shifted_T_10_pc : _shifted_T_7_pc; + assign io_dataOut_2_addr = deqPtr[0] ? _shifted_T_10_addr : _shifted_T_7_addr; + assign io_dataOut_2_data = deqPtr[0] ? _shifted_T_10_data : _shifted_T_7_data; + assign io_dataOut_2_unreachableCell = + deqPtr[0] ? _shifted_T_10_unreachableCell : _shifted_T_7_unreachableCell; + assign io_dataOut_2_initAsConstStride = + deqPtr[0] ? _shifted_T_10_initAsConstStride : _shifted_T_7_initAsConstStride; + assign io_dataOut_3_store = + deqPtr[0] ? (deqPtr[1] ? buffer_2_store : buffer_0_store) : _shifted_T_10_store; + assign io_dataOut_3_rd = + deqPtr[0] ? (deqPtr[1] ? buffer_2_rd : buffer_0_rd) : _shifted_T_10_rd; + assign io_dataOut_3_op = + deqPtr[0] ? (deqPtr[1] ? buffer_2_op : buffer_0_op) : _shifted_T_10_op; + assign io_dataOut_3_pc = + deqPtr[0] ? (deqPtr[1] ? buffer_2_pc : buffer_0_pc) : _shifted_T_10_pc; + assign io_dataOut_3_addr = + deqPtr[0] ? (deqPtr[1] ? buffer_2_addr : buffer_0_addr) : _shifted_T_10_addr; + assign io_dataOut_3_data = + deqPtr[0] ? (deqPtr[1] ? buffer_2_data : buffer_0_data) : _shifted_T_10_data; + assign io_dataOut_3_unreachableCell = + deqPtr[0] + ? (deqPtr[1] ? buffer_2_unreachableCell : buffer_0_unreachableCell) + : _shifted_T_10_unreachableCell; + assign io_dataOut_3_initAsConstStride = + deqPtr[0] + ? (deqPtr[1] ? buffer_2_initAsConstStride : buffer_0_initAsConstStride) + : _shifted_T_10_initAsConstStride; endmodule -module Alu( - input clock, - reset, - io_req_valid, - input [4:0] io_req_bits_addr, - io_req_bits_op, - input io_rs1_valid, - input [31:0] io_rs1_data, - input io_rs2_valid, - input [31:0] io_rs2_data, - output io_rd_valid, - output [4:0] io_rd_bits_addr, - output [31:0] io_rd_bits_data +module IndexAllocatorShifting_1( + input clock, + reset, + io_alloc_ready, + output io_alloc_valid, + output [1:0] io_alloc_bits, + input io_free_valid, + input [1:0] io_free_bits ); - reg valid; - reg [4:0] addr; - reg [4:0] op; - wire r2IsGreater = $signed(io_rs1_data) < $signed(io_rs2_data); - wire r2IsGreaterU = io_rs1_data < io_rs2_data; - wire [31:0] _io_rd_bits_data_T_19 = io_rs1_data ^ io_rs2_data; - wire [62:0] _io_rd_bits_data_T_7 = {31'h0, io_rs1_data} << io_rs2_data[4:0]; - wire [31:0] _GEN = {27'h0, io_rs2_data[4:0]}; - wire [31:0] _io_rd_bits_data_T_29 = - {16'h0, io_rs1_data[31:16]} | {io_rs1_data[15:0], 16'h0}; - wire [31:0] _io_rd_bits_data_T_39 = - {8'h0, _io_rd_bits_data_T_29[31:8] & 24'hFF00FF} - | {_io_rd_bits_data_T_29[23:0] & 24'hFF00FF, 8'h0}; - wire [31:0] _io_rd_bits_data_T_49 = - {4'h0, _io_rd_bits_data_T_39[31:4] & 28'hF0F0F0F} - | {_io_rd_bits_data_T_39[27:0] & 28'hF0F0F0F, 4'h0}; - wire [31:0] _io_rd_bits_data_T_59 = - {2'h0, _io_rd_bits_data_T_49[31:2] & 30'h33333333} - | {_io_rd_bits_data_T_49[29:0] & 30'h33333333, 2'h0}; - wire [31:0] _io_rd_bits_data_T_69 = - {1'h0, _io_rd_bits_data_T_59[31:1] & 31'h55555555} - | {_io_rd_bits_data_T_59[30:0] & 31'h55555555, 1'h0}; - wire [31:0] _io_rd_bits_data_T_312 = - io_rs2_data[0] ? {io_rs1_data[30:0], io_rs1_data[31]} : io_rs1_data; - wire [31:0] _io_rd_bits_data_T_316 = - io_rs2_data[1] - ? {_io_rd_bits_data_T_312[29:0], _io_rd_bits_data_T_312[31:30]} - : _io_rd_bits_data_T_312; - wire [31:0] _io_rd_bits_data_T_320 = - io_rs2_data[2] - ? {_io_rd_bits_data_T_316[27:0], _io_rd_bits_data_T_316[31:28]} - : _io_rd_bits_data_T_316; - wire [31:0] _io_rd_bits_data_T_324 = - io_rs2_data[3] - ? {_io_rd_bits_data_T_320[23:0], _io_rd_bits_data_T_320[31:24]} - : _io_rd_bits_data_T_320; - wire [31:0] _io_rd_bits_data_T_337 = - io_rs2_data[0] ? {io_rs1_data[0], io_rs1_data[31:1]} : io_rs1_data; - wire [31:0] _io_rd_bits_data_T_341 = - io_rs2_data[1] - ? {_io_rd_bits_data_T_337[1:0], _io_rd_bits_data_T_337[31:2]} - : _io_rd_bits_data_T_337; - wire [31:0] _io_rd_bits_data_T_345 = - io_rs2_data[2] - ? {_io_rd_bits_data_T_341[3:0], _io_rd_bits_data_T_341[31:4]} - : _io_rd_bits_data_T_341; - wire [31:0] _io_rd_bits_data_T_349 = - io_rs2_data[3] - ? {_io_rd_bits_data_T_345[7:0], _io_rd_bits_data_T_345[31:8]} - : _io_rd_bits_data_T_345; - wire [31:0][31:0] _GEN_0 = - {{32'h0}, - {32'h0}, - {32'h0}, - {32'h0}, - {{16'h0, io_rs1_data[15:0]}}, - {{io_rs1_data[7:0], io_rs1_data[15:8], io_rs1_data[23:16], io_rs1_data[31:24]}}, - {{io_rs1_data[31:24] == 8'h0 ? 8'h0 : 8'hFF, - io_rs1_data[23:16] == 8'h0 ? 8'h0 : 8'hFF, - io_rs1_data[15:8] == 8'h0 ? 8'h0 : 8'hFF, - io_rs1_data[7:0] == 8'h0 ? 8'h0 : 8'hFF}}, - {io_rs2_data[4] - ? {_io_rd_bits_data_T_349[15:0], _io_rd_bits_data_T_349[31:16]} - : _io_rd_bits_data_T_349}, - {io_rs2_data[4] - ? {_io_rd_bits_data_T_324[15:0], _io_rd_bits_data_T_324[31:16]} - : _io_rd_bits_data_T_324}, - {{{16{io_rs1_data[15]}}, io_rs1_data[15:0]}}, - {{{24{io_rs1_data[7]}}, io_rs1_data[7:0]}}, - {r2IsGreaterU ? io_rs1_data : io_rs2_data}, - {r2IsGreater ? io_rs1_data : io_rs2_data}, - {r2IsGreaterU ? io_rs2_data : io_rs1_data}, - {r2IsGreater ? io_rs2_data : io_rs1_data}, - {{26'h0, - {1'h0, - {1'h0, - {1'h0, - {1'h0, {1'h0, io_rs1_data[0]} + {1'h0, io_rs1_data[1]}} - + {1'h0, {1'h0, io_rs1_data[2]} + {1'h0, io_rs1_data[3]}}} - + {1'h0, - {1'h0, {1'h0, io_rs1_data[4]} + {1'h0, io_rs1_data[5]}} - + {1'h0, {1'h0, io_rs1_data[6]} + {1'h0, io_rs1_data[7]}}}} - + {1'h0, - {1'h0, - {1'h0, {1'h0, io_rs1_data[8]} + {1'h0, io_rs1_data[9]}} - + {1'h0, {1'h0, io_rs1_data[10]} + {1'h0, io_rs1_data[11]}}} - + {1'h0, - {1'h0, {1'h0, io_rs1_data[12]} + {1'h0, io_rs1_data[13]}} - + {1'h0, {1'h0, io_rs1_data[14]} + {1'h0, io_rs1_data[15]}}}}} - + {1'h0, - {1'h0, - {1'h0, - {1'h0, {1'h0, io_rs1_data[16]} + {1'h0, io_rs1_data[17]}} - + {1'h0, {1'h0, io_rs1_data[18]} + {1'h0, io_rs1_data[19]}}} - + {1'h0, - {1'h0, {1'h0, io_rs1_data[20]} + {1'h0, io_rs1_data[21]}} - + {1'h0, {1'h0, io_rs1_data[22]} + {1'h0, io_rs1_data[23]}}}} - + {1'h0, - {1'h0, - {1'h0, {1'h0, io_rs1_data[24]} + {1'h0, io_rs1_data[25]}} - + {1'h0, {1'h0, io_rs1_data[26]} + {1'h0, io_rs1_data[27]}}} - + {1'h0, - {1'h0, {1'h0, io_rs1_data[28]} + {1'h0, io_rs1_data[29]}} - + {1'h0, {1'h0, io_rs1_data[30]} + {1'h0, io_rs1_data[31]}}}}}}}, - {{26'h0, - io_rs1_data[0] - ? 6'h0 - : io_rs1_data[1] - ? 6'h1 - : io_rs1_data[2] - ? 6'h2 - : io_rs1_data[3] - ? 6'h3 - : io_rs1_data[4] - ? 6'h4 - : io_rs1_data[5] - ? 6'h5 - : io_rs1_data[6] - ? 6'h6 - : io_rs1_data[7] - ? 6'h7 - : io_rs1_data[8] - ? 6'h8 - : io_rs1_data[9] - ? 6'h9 - : io_rs1_data[10] - ? 6'hA - : io_rs1_data[11] - ? 6'hB - : io_rs1_data[12] - ? 6'hC - : io_rs1_data[13] - ? 6'hD - : io_rs1_data[14] - ? 6'hE - : io_rs1_data[15] - ? 6'hF - : io_rs1_data[16] - ? 6'h10 - : io_rs1_data[17] - ? 6'h11 - : io_rs1_data[18] - ? 6'h12 - : io_rs1_data[19] - ? 6'h13 - : io_rs1_data[20] - ? 6'h14 - : io_rs1_data[21] - ? 6'h15 - : io_rs1_data[22] - ? 6'h16 - : io_rs1_data[23] - ? 6'h17 - : io_rs1_data[24] - ? 6'h18 - : io_rs1_data[25] - ? 6'h19 - : io_rs1_data[26] - ? 6'h1A - : io_rs1_data[27] - ? 6'h1B - : io_rs1_data[28] - ? 6'h1C - : io_rs1_data[29] - ? 6'h1D - : io_rs1_data[30] - ? 6'h1E - : io_rs1_data[31] - ? 6'h1F - : 6'h20}}, - {{26'h0, - _io_rd_bits_data_T_69[0] - ? 6'h0 - : _io_rd_bits_data_T_69[1] - ? 6'h1 - : _io_rd_bits_data_T_69[2] - ? 6'h2 - : _io_rd_bits_data_T_69[3] - ? 6'h3 - : _io_rd_bits_data_T_69[4] - ? 6'h4 - : _io_rd_bits_data_T_69[5] - ? 6'h5 - : _io_rd_bits_data_T_69[6] - ? 6'h6 - : _io_rd_bits_data_T_69[7] - ? 6'h7 - : _io_rd_bits_data_T_69[8] - ? 6'h8 - : _io_rd_bits_data_T_69[9] - ? 6'h9 - : _io_rd_bits_data_T_69[10] - ? 6'hA - : _io_rd_bits_data_T_69[11] - ? 6'hB - : _io_rd_bits_data_T_69[12] - ? 6'hC - : _io_rd_bits_data_T_69[13] - ? 6'hD - : _io_rd_bits_data_T_69[14] - ? 6'hE - : _io_rd_bits_data_T_69[15] - ? 6'hF - : _io_rd_bits_data_T_69[16] - ? 6'h10 - : _io_rd_bits_data_T_69[17] - ? 6'h11 - : _io_rd_bits_data_T_69[18] - ? 6'h12 - : _io_rd_bits_data_T_69[19] - ? 6'h13 - : _io_rd_bits_data_T_69[20] - ? 6'h14 - : _io_rd_bits_data_T_69[21] - ? 6'h15 - : _io_rd_bits_data_T_69[22] - ? 6'h16 - : _io_rd_bits_data_T_69[23] - ? 6'h17 - : _io_rd_bits_data_T_69[24] - ? 6'h18 - : _io_rd_bits_data_T_69[25] - ? 6'h19 - : _io_rd_bits_data_T_69[26] - ? 6'h1A - : _io_rd_bits_data_T_69[27] - ? 6'h1B - : _io_rd_bits_data_T_69[28] - ? 6'h1C - : _io_rd_bits_data_T_69[29] - ? 6'h1D - : _io_rd_bits_data_T_69[30] - ? 6'h1E - : _io_rd_bits_data_T_69[31] - ? 6'h1F - : 6'h20}}, - {~_io_rd_bits_data_T_19}, - {io_rs1_data | ~io_rs2_data}, - {io_rs1_data & ~io_rs2_data}, - {io_rs2_data}, - {$signed($signed(io_rs1_data) >>> _GEN)}, - {io_rs1_data >> _GEN}, - {_io_rd_bits_data_T_7[31:0]}, - {io_rs1_data & io_rs2_data}, - {io_rs1_data | io_rs2_data}, - {_io_rd_bits_data_T_19}, - {{31'h0, r2IsGreaterU}}, - {{31'h0, r2IsGreater}}, - {io_rs1_data - io_rs2_data}, - {io_rs1_data + io_rs2_data}}; + reg [1:0] state_regs_0; + reg [1:0] state_regs_1; + reg [1:0] state_regs_2; + reg [1:0] state_regs_3; + reg [2:0] state_nAvail; + reg state_isNonEmpty; + wire io_alloc_valid_0 = state_isNonEmpty | io_free_valid; + wire _state_T_28 = io_alloc_ready & io_alloc_valid_0; + wire _state_T_29 = ~(state_nAvail[2]) & io_free_valid; + wire _state_T_3 = _state_T_28 & ~_state_T_29; + wire _state_T_24 = ~_state_T_28 & _state_T_29; + wire _state_T_31 = _state_T_28 & _state_T_29 & state_isNonEmpty; + wire _state_defaultSel_T_2 = + _state_T_3 | _state_T_24 | _state_T_31 | state_nAvail[2] & io_free_valid; + wire _GEN = _state_T_3 & state_isNonEmpty & state_nAvail < 3'h5; + wire _GEN_0 = _state_T_31 & ~(state_nAvail[2]); + wire _GEN_1 = _state_T_24 & ~(state_nAvail[2]); always @(posedge clock or posedge reset) begin if (reset) begin - valid <= 1'h0; - addr <= 5'h0; - op <= 5'h0; + state_regs_0 <= 2'h0; + state_regs_1 <= 2'h1; + state_regs_2 <= 2'h2; + state_regs_3 <= 2'h3; + state_nAvail <= 3'h4; + state_isNonEmpty <= 1'h1; end else begin - valid <= io_req_valid; - if (io_req_valid) begin - addr <= io_req_bits_addr; - op <= io_req_bits_op; - end + state_regs_0 <= + (_GEN ? ((|(state_nAvail[2:1])) ? state_regs_1 : state_regs_0) : 2'h0) + | (_GEN_1 ? (state_nAvail[1:0] == 2'h0 ? io_free_bits : state_regs_0) : 2'h0) + | (_GEN_0 ? io_free_bits : 2'h0) | (_state_defaultSel_T_2 ? 2'h0 : state_regs_0); + state_regs_1 <= + (_GEN ? (state_nAvail > 3'h2 ? state_regs_2 : state_regs_1) : 2'h0) + | (_GEN_1 ? (state_nAvail[1:0] == 2'h1 ? io_free_bits : state_regs_1) : 2'h0) + | (_GEN_0 ? state_regs_1 : 2'h0) | (_state_defaultSel_T_2 ? 2'h0 : state_regs_1); + state_regs_2 <= + (_GEN ? (state_nAvail[2] ? state_regs_3 : state_regs_2) : 2'h0) + | (_GEN_1 ? (state_nAvail[1:0] == 2'h2 ? io_free_bits : state_regs_2) : 2'h0) + | (_GEN_0 ? state_regs_2 : 2'h0) | (_state_defaultSel_T_2 ? 2'h0 : state_regs_2); + state_regs_3 <= + (_GEN ? state_regs_3 : 2'h0) + | (_GEN_1 ? ((&(state_nAvail[1:0])) ? io_free_bits : state_regs_3) : 2'h0) + | (_GEN_0 ? state_regs_3 : 2'h0) | (_state_defaultSel_T_2 ? 2'h0 : state_regs_3); + state_nAvail <= + (_GEN ? state_nAvail - 3'h1 : 3'h0) | (_GEN_1 ? state_nAvail + 3'h1 : 3'h0) + | (_GEN_0 ? state_nAvail : 3'h0) | (_state_defaultSel_T_2 ? 3'h0 : state_nAvail); + state_isNonEmpty <= + _GEN & (|(state_nAvail[2:1])) | _state_T_24 & ~(state_nAvail[2]) | _GEN_0 + & state_isNonEmpty | ~_state_defaultSel_T_2 & state_isNonEmpty; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - valid = _RANDOM[/*Zero width*/ 1'b0][0]; - addr = _RANDOM[/*Zero width*/ 1'b0][5:1]; - op = _RANDOM[/*Zero width*/ 1'b0][10:6]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - valid = 1'h0; - addr = 5'h0; - op = 5'h0; + state_regs_0 = 2'h0; + state_regs_1 = 2'h1; + state_regs_2 = 2'h2; + state_regs_3 = 2'h3; + state_nAvail = 3'h4; + state_isNonEmpty = 1'h1; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_rd_valid = valid; - assign io_rd_bits_addr = addr; - assign io_rd_bits_data = _GEN_0[op]; + assign io_alloc_valid = io_alloc_valid_0; + assign io_alloc_bits = state_isNonEmpty ? state_regs_0 : io_free_bits; endmodule -module Bru( - input clock, - reset, - io_req_valid, - io_req_bits_fwd, - input [3:0] io_req_bits_op, - input [31:0] io_req_bits_pc, - io_req_bits_target, - input [4:0] io_req_bits_link, - output io_csr_in_mode_valid, - output [1:0] io_csr_in_mode_bits, - output io_csr_in_mcause_valid, - output [31:0] io_csr_in_mcause_bits, - output io_csr_in_mepc_valid, - output [31:0] io_csr_in_mepc_bits, - output io_csr_in_mtval_valid, - output [31:0] io_csr_in_mtval_bits, - output io_csr_in_halt, - io_csr_in_fault, - io_csr_in_wfi, - input [1:0] io_csr_out_mode, - input [31:0] io_csr_out_mepc, - io_csr_out_mtvec, - input io_rs1_valid, - input [31:0] io_rs1_data, - input io_rs2_valid, - input [31:0] io_rs2_data, - output io_rd_valid, - output [4:0] io_rd_bits_addr, - output [31:0] io_rd_bits_data, - output io_taken_valid, - output [31:0] io_taken_value, - input [31:0] io_target_data, - output io_interlock, - input io_fault_manager_valid, - input [31:0] io_fault_manager_bits_mepc, - io_fault_manager_bits_mtval, - io_fault_manager_bits_mcause +module Queue1_UInt2( + input clock, + reset, + io_enq_valid, + input [1:0] io_enq_bits, + input io_deq_ready, + output io_deq_valid, + output [1:0] io_deq_bits ); - wire io_csr_in_fault_0; - reg stateReg_valid; - reg stateReg_bits_fwd; - reg [3:0] stateReg_bits_op; - reg [31:0] stateReg_bits_target; - reg stateReg_bits_linkValid; - reg [4:0] stateReg_bits_linkAddr; - reg [31:0] stateReg_bits_linkData; - reg [31:0] stateReg_bits_pcEx; - wire _io_csr_in_fault_T = io_csr_out_mode == 2'h0; - wire _io_csr_in_mcause_bits_T_4 = io_csr_out_mode == 2'h1; - wire _ignore_T_2 = stateReg_bits_op == 4'h8; - wire _ignore_T_3 = stateReg_bits_op == 4'h9; - wire _ignore_T_4 = stateReg_bits_op == 4'hA; - wire _ignore_T_5 = stateReg_bits_op == 4'hB; - wire _ignore_T_7 = stateReg_bits_op == 4'hD; - wire usageFault = - stateReg_valid - & (_io_csr_in_mcause_bits_T_4 ? (|{_ignore_T_5, _ignore_T_4}) : _ignore_T_2); - assign io_csr_in_fault_0 = usageFault & _io_csr_in_fault_T; - wire _ignore_T_6 = stateReg_bits_op == 4'hC; - wire [31:0] nextState_linkData = io_req_bits_pc + 32'h4; - wire _nextState_target_T = io_req_bits_op == 4'h1; - wire [31:0] mtvec = {io_csr_out_mtvec[31:2], 2'h0}; - wire _pipeline0Target_call_T = io_req_bits_op == 4'hB; - wire stateRegValid = io_req_valid | io_fault_manager_valid; + wire io_enq_ready; + reg maybe_full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = io_deq_ready | ~maybe_full; + reg [1:0] ram; + always @(posedge clock or posedge reset) begin + if (reset) + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= io_enq_bits; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + maybe_full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_deq_valid = maybe_full; + assign io_deq_bits = ram; +endmodule + +module LsuSuperSlot( + input clock, + reset, + output io_uop_ready, + input io_uop_valid, + io_uop_bits_store, + input [4:0] io_uop_bits_rd, + io_uop_bits_op, + input [31:0] io_uop_bits_pc, + io_uop_bits_addr, + io_uop_bits_data, + input [2:0] io_uop_bits_unreachableCell, + input io_busReq_ready, + output io_busReq_valid, + output [1:0] io_busReq_bits_txid, + output [27:0] io_busReq_bits_req_rowAddr, + output [3:0] io_busReq_bits_req_offset, + output [4:0] io_busReq_bits_req_size, + output io_busReq_bits_req_write, + output [127:0] io_busReq_bits_req_wdata, + output [15:0] io_busReq_bits_req_wmask, + input io_busResp_valid, + input [1:0] io_busResp_bits_txid, + input [127:0] io_busResp_bits_rdata, + input io_busResp_bits_fault, + output io_intWriteback_valid, + output [4:0] io_intWriteback_bits_addr, + output [31:0] io_intWriteback_bits_data, + output io_floatWriteback_valid, + output [4:0] io_floatWriteback_bits_addr, + output [31:0] io_floatWriteback_bits_data, + io_pc, + output io_active, + io_storeComplete, + io_fault_valid, + io_fault_bits_write, + output [31:0] io_fault_bits_addr, + io_fault_bits_epc +); + + wire stateFromAction_isDone; + wire _faultQueue_io_deq_valid; + wire [1:0] _faultQueue_io_deq_bits; + wire _txidAllocator_io_alloc_valid; + wire [1:0] _txidAllocator_io_alloc_bits; + reg [31:0] state_pc; + reg state_write; + reg state_faulted; + reg [4:0] state_rd; + reg state_skipWriteback; + reg [2:0] state_scalarWritebackMode; + reg [4:0] state_tx1Size; + reg [4:0] state_tx2Size; + reg state_float_writeback; + reg [2:0] state_cells_0_state; + reg [7:0] state_cells_0_data; + reg [27:0] state_cells_0_rowAddr; + reg [15:0] state_cells_0_mask; + reg [2:0] state_cells_1_state; + reg [7:0] state_cells_1_data; + reg [27:0] state_cells_1_rowAddr; + reg [15:0] state_cells_1_mask; + reg [2:0] state_cells_2_state; + reg [7:0] state_cells_2_data; + reg [27:0] state_cells_2_rowAddr; + reg [15:0] state_cells_2_mask; + reg [2:0] state_cells_3_state; + reg [7:0] state_cells_3_data; + reg [27:0] state_cells_3_rowAddr; + reg [15:0] state_cells_3_mask; + reg [1:0] state_leadIndex; + reg [27:0] state_rowAddr; + reg state_isDone; + wire newFault = io_busResp_valid & io_busResp_bits_fault; + wire [2:0] _leadWindow_shifted_T_4_state = + state_leadIndex[1] ? state_cells_3_state : state_cells_1_state; + wire [7:0] _leadWindow_shifted_T_4_data = + state_leadIndex[1] ? state_cells_3_data : state_cells_1_data; + wire [15:0] _leadWindow_shifted_T_4_mask = + state_leadIndex[1] ? state_cells_3_mask : state_cells_1_mask; + wire [2:0] leadWindow_0_state = + state_leadIndex[0] + ? _leadWindow_shifted_T_4_state + : state_leadIndex[1] ? state_cells_2_state : state_cells_0_state; + wire [7:0] leadWindow_0_data = + state_leadIndex[0] + ? _leadWindow_shifted_T_4_data + : state_leadIndex[1] ? state_cells_2_data : state_cells_0_data; + wire [7:0] leadWindow_1_data = + state_leadIndex[0] + ? (state_leadIndex[1] ? 8'h0 : state_cells_2_data) + : _leadWindow_shifted_T_4_data; + wire [7:0] _GEN = state_leadIndex[0] ? state_cells_3_data : state_cells_2_data; + wire isFirstTx = state_cells_0_state == 3'h2; + wire cellCanStart_0 = isFirstTx & state_cells_0_rowAddr == state_rowAddr; + wire _stateFromAction_cellsNext_noBadWb_WIRE_3_0 = + state_cells_1_state == 3'h2; + wire cellCanStart_1 = + _stateFromAction_cellsNext_noBadWb_WIRE_3_0 & state_cells_1_rowAddr == state_rowAddr; + wire _stateFromAction_cellsNext_noBadWb_WIRE_5_0 = + state_cells_2_state == 3'h2; + wire cellCanStart_2 = + _stateFromAction_cellsNext_noBadWb_WIRE_5_0 & state_cells_2_rowAddr == state_rowAddr; + wire _stateFromAction_cellsNext_noBadWb_WIRE_7_0 = + state_cells_3_state == 3'h2; + wire cellCanStart_3 = + _stateFromAction_cellsNext_noBadWb_WIRE_7_0 & state_cells_3_rowAddr == state_rowAddr; + wire _cellCanStartWindow_shifted_T_4 = + state_leadIndex[1] ? cellCanStart_3 : cellCanStart_1; + wire _cellCanStartWindow_shifted_T_7 = + ~(state_leadIndex[1]) & cellCanStart_2; + wire reqValidNormal = leadWindow_0_state == 3'h2; + wire [15:0] bundle_0 = + (state_leadIndex[0] + ? _cellCanStartWindow_shifted_T_4 + : state_leadIndex[1] ? cellCanStart_2 : cellCanStart_0) + ? (state_leadIndex[0] + ? _leadWindow_shifted_T_4_mask + : state_leadIndex[1] ? state_cells_2_mask : state_cells_0_mask) + : 16'h0; + wire [15:0] bundle_1 = + (state_leadIndex[0] + ? _cellCanStartWindow_shifted_T_7 + : _cellCanStartWindow_shifted_T_4) + ? (state_leadIndex[0] + ? (state_leadIndex[1] ? 16'h0 : state_cells_2_mask) + : _leadWindow_shifted_T_4_mask) + : 16'h0; + wire [15:0] bundle_2 = + ~(state_leadIndex[0] + ? ~(state_leadIndex[1]) & cellCanStart_3 + : _cellCanStartWindow_shifted_T_7) | state_leadIndex[1] + ? 16'h0 + : state_leadIndex[0] ? state_cells_3_mask : state_cells_2_mask; + wire [15:0] bundle_3 = + ~(~(|state_leadIndex) & cellCanStart_3) | (|state_leadIndex) + ? 16'h0 + : state_cells_3_mask; + wire [3:0] wData_selOH = + bundle_0[0] ? 4'h1 : bundle_1[0] ? 4'h2 : bundle_2[0] ? 4'h4 : {bundle_3[0], 3'h0}; + wire [3:0] wData_selOH_1 = + bundle_0[1] ? 4'h1 : bundle_1[1] ? 4'h2 : bundle_2[1] ? 4'h4 : {bundle_3[1], 3'h0}; + wire [3:0] wData_selOH_2 = + bundle_0[2] ? 4'h1 : bundle_1[2] ? 4'h2 : bundle_2[2] ? 4'h4 : {bundle_3[2], 3'h0}; + wire [3:0] wData_selOH_3 = + bundle_0[3] ? 4'h1 : bundle_1[3] ? 4'h2 : bundle_2[3] ? 4'h4 : {bundle_3[3], 3'h0}; + wire [3:0] wData_selOH_4 = + bundle_0[4] ? 4'h1 : bundle_1[4] ? 4'h2 : bundle_2[4] ? 4'h4 : {bundle_3[4], 3'h0}; + wire [3:0] wData_selOH_5 = + bundle_0[5] ? 4'h1 : bundle_1[5] ? 4'h2 : bundle_2[5] ? 4'h4 : {bundle_3[5], 3'h0}; + wire [3:0] wData_selOH_6 = + bundle_0[6] ? 4'h1 : bundle_1[6] ? 4'h2 : bundle_2[6] ? 4'h4 : {bundle_3[6], 3'h0}; + wire [3:0] wData_selOH_7 = + bundle_0[7] ? 4'h1 : bundle_1[7] ? 4'h2 : bundle_2[7] ? 4'h4 : {bundle_3[7], 3'h0}; + wire [3:0] wData_selOH_8 = + bundle_0[8] ? 4'h1 : bundle_1[8] ? 4'h2 : bundle_2[8] ? 4'h4 : {bundle_3[8], 3'h0}; + wire [3:0] wData_selOH_9 = + bundle_0[9] ? 4'h1 : bundle_1[9] ? 4'h2 : bundle_2[9] ? 4'h4 : {bundle_3[9], 3'h0}; + wire [3:0] wData_selOH_10 = + bundle_0[10] + ? 4'h1 + : bundle_1[10] ? 4'h2 : bundle_2[10] ? 4'h4 : {bundle_3[10], 3'h0}; + wire [3:0] wData_selOH_11 = + bundle_0[11] + ? 4'h1 + : bundle_1[11] ? 4'h2 : bundle_2[11] ? 4'h4 : {bundle_3[11], 3'h0}; + wire [3:0] wData_selOH_12 = + bundle_0[12] + ? 4'h1 + : bundle_1[12] ? 4'h2 : bundle_2[12] ? 4'h4 : {bundle_3[12], 3'h0}; + wire [3:0] wData_selOH_13 = + bundle_0[13] + ? 4'h1 + : bundle_1[13] ? 4'h2 : bundle_2[13] ? 4'h4 : {bundle_3[13], 3'h0}; + wire [3:0] wData_selOH_14 = + bundle_0[14] + ? 4'h1 + : bundle_1[14] ? 4'h2 : bundle_2[14] ? 4'h4 : {bundle_3[14], 3'h0}; + wire [3:0] wData_selOH_15 = + bundle_0[15] + ? 4'h1 + : bundle_1[15] ? 4'h2 : bundle_2[15] ? 4'h4 : {bundle_3[15], 3'h0}; + wire [127:0] wDataNormal = + {(wData_selOH_15[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_15[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_15[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_15[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_14[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_14[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_14[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_14[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_13[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_13[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_13[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_13[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_12[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_12[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_12[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_12[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_11[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_11[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_11[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_11[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_10[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_10[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_10[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_10[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_9[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_9[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_9[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_9[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_8[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_8[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_8[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_8[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_7[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_7[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_7[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_7[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_6[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_6[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_6[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_6[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_5[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_5[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_5[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_5[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_4[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_4[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_4[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_4[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_3[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_3[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_3[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_3[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_2[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_2[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_2[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_2[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH_1[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH_1[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH_1[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH_1[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data), + (wData_selOH[0] ? leadWindow_0_data : 8'h0) + | (wData_selOH[1] ? leadWindow_1_data : 8'h0) + | (~(wData_selOH[2]) | state_leadIndex[1] ? 8'h0 : _GEN) + | (~(wData_selOH[3]) | (|state_leadIndex) ? 8'h0 : state_cells_3_data)}; + wire [15:0] wMaskNormal = bundle_0 | bundle_1 | bundle_2 | bundle_3; + wire [3:0] startedNormal = + {cellCanStart_3 & (|{~state_write, state_cells_3_mask & wMaskNormal}), + cellCanStart_2 & (|{~state_write, state_cells_2_mask & wMaskNormal}), + cellCanStart_1 & (|{~state_write, state_cells_1_mask & wMaskNormal}), + cellCanStart_0 & (|{~state_write, state_cells_0_mask & wMaskNormal})}; + wire [4:0] txSize = isFirstTx ? state_tx1Size : state_tx2Size; + wire [6:0] _txOffset_T_1 = state_cells_0_mask[15:9] | state_cells_0_mask[7:1]; + wire [2:0] _txOffset_T_3 = _txOffset_T_1[6:4] | _txOffset_T_1[2:0]; + wire [3:0] txOffset = + isFirstTx + ? ~(state_tx1Size[3:0] - 4'h1) + & {|(state_cells_0_mask[15:8]), + |(_txOffset_T_1[6:3]), + |(_txOffset_T_3[2:1]), + _txOffset_T_3[2] | _txOffset_T_3[0]} + : 4'h0; + reg txPending_valid; + reg [1:0] txPending_bits_txid; + reg [27:0] txPending_bits_req_rowAddr; + reg [3:0] txPending_bits_req_offset; + reg [4:0] txPending_bits_req_size; + reg txPending_bits_req_write; + reg [127:0] txPending_bits_req_wdata; + reg [15:0] txPending_bits_req_wmask; + wire txOutgoing_valid = + txPending_valid ? txPending_valid : reqValidNormal & _txidAllocator_io_alloc_valid; + wire [1:0] txOutgoing_bits_txid = + txPending_valid ? txPending_bits_txid : _txidAllocator_io_alloc_bits; + wire [27:0] txOutgoing_bits_req_rowAddr = + txPending_valid ? txPending_bits_req_rowAddr : state_rowAddr; + wire [3:0] txOutgoing_bits_req_offset = + txPending_valid ? txPending_bits_req_offset : txOffset; + wire txOutgoing_bits_req_write = + txPending_valid ? txPending_bits_req_write : state_write; + wire isBlocked = state_faulted | newFault; + wire txFire = txOutgoing_valid & (io_busReq_ready | isBlocked); + reg [31:0] bookkeeping_0_addr; + reg [3:0] bookkeeping_0_mask; + reg [31:0] bookkeeping_1_addr; + reg [3:0] bookkeeping_1_mask; + reg [31:0] bookkeeping_2_addr; + reg [3:0] bookkeeping_2_mask; + reg [31:0] bookkeeping_3_addr; + reg [3:0] bookkeeping_3_mask; + wire respValid = io_busResp_valid | _faultQueue_io_deq_valid; + wire [1:0] respTxid = + io_busResp_valid ? io_busResp_bits_txid : _faultQueue_io_deq_bits; + wire [3:0][31:0] _GEN_0 = + {{bookkeeping_3_addr}, + {bookkeeping_2_addr}, + {bookkeeping_1_addr}, + {bookkeeping_0_addr}}; + wire [3:0][3:0] _GEN_1 = + {{bookkeeping_3_mask}, + {bookkeeping_2_mask}, + {bookkeeping_1_mask}, + {bookkeeping_0_mask}}; + wire scalar8Valid = state_cells_0_state == 3'h4; + wire scalar16Valid = + state_cells_0_state == 3'h4 & state_cells_1_state == 3'h4; + wire scalarReq_valid = + state_scalarWritebackMode == 3'h6 + ? scalar16Valid + : state_scalarWritebackMode == 3'h5 + ? state_cells_0_state == 3'h4 & state_cells_1_state == 3'h4 + & state_cells_2_state == 3'h4 & state_cells_3_state == 3'h4 + : state_scalarWritebackMode == 3'h4 | state_scalarWritebackMode == 3'h3 + ? scalar16Valid + : (state_scalarWritebackMode == 3'h2 | state_scalarWritebackMode == 3'h1) + & scalar8Valid; + wire [7:0][31:0] _GEN_2 = + {{32'h0}, + {{16'hFFFF, state_cells_1_data, state_cells_0_data}}, + {{state_cells_3_data, state_cells_2_data, state_cells_1_data, state_cells_0_data}}, + {{{16{state_cells_1_data[7]}}, state_cells_1_data, state_cells_0_data}}, + {{16'h0, state_cells_1_data, state_cells_0_data}}, + {{{24{state_cells_0_data[7]}}, state_cells_0_data}}, + {{24'h0, state_cells_0_data}}, + {32'h0}}; + wire [31:0] scalarReq_bits = _GEN_2[state_scalarWritebackMode]; + wire _stateFromAction_cellsNext_noBadWb_WIRE_2_0 = + state_cells_1_state == 3'h4; + wire _stateFromAction_cellsNext_noBadWb_WIRE_4_0 = + state_cells_2_state == 3'h4; + wire _stateFromAction_cellsNext_noBadWb_WIRE_6_0 = + state_cells_3_state == 3'h4; + wire req_y_valid = ~state_float_writeback & scalarReq_valid; + wire io_floatWriteback_valid_0 = state_float_writeback & scalarReq_valid; + wire [3:0] effectiveStarts = txFire & reqValidNormal ? startedNormal : 4'h0; + wire initCellsData_0_valid = stateFromAction_isDone & io_uop_valid; + wire _stateFromAction_cellsNext_noBadWb_WIRE_1_1 = + state_cells_0_state == 3'h3; + wire stateFromAction_cellsNext_x7_valid = + respValid + & (state_write + ? _GEN_1[respTxid][0] + : state_cells_0_rowAddr == _GEN_0[respTxid][31:4] + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_1_1, isFirstTx})); + wire _stateFromAction_cellsNext_noBadWb_WIRE_3_1 = + state_cells_1_state == 3'h3; + wire stateFromAction_cellsNext_x7_1_valid = + respValid + & (state_write + ? _GEN_1[respTxid][1] + : state_cells_1_rowAddr == _GEN_0[respTxid][31:4] + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_3_1, + _stateFromAction_cellsNext_noBadWb_WIRE_3_0})); + wire _stateFromAction_cellsNext_noBadWb_WIRE_5_1 = + state_cells_2_state == 3'h3; + wire stateFromAction_cellsNext_x7_2_valid = + respValid + & (state_write + ? _GEN_1[respTxid][2] + : state_cells_2_rowAddr == _GEN_0[respTxid][31:4] + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_5_1, + _stateFromAction_cellsNext_noBadWb_WIRE_5_0})); + wire _stateFromAction_cellsNext_noBadWb_WIRE_7_1 = + state_cells_3_state == 3'h3; + wire stateFromAction_cellsNext_x7_3_valid = + respValid + & (state_write + ? _GEN_1[respTxid][3] + : state_cells_3_rowAddr == _GEN_0[respTxid][31:4] + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_7_1, + _stateFromAction_cellsNext_noBadWb_WIRE_7_0})); + wire [3:0] stateFromAction_cellWriteback = + state_skipWriteback + ? {stateFromAction_cellsNext_x7_3_valid, + stateFromAction_cellsNext_x7_2_valid, + stateFromAction_cellsNext_x7_1_valid, + stateFromAction_cellsNext_x7_valid} + : (req_y_valid | io_floatWriteback_valid_0) & (|state_scalarWritebackMode) + ? {(|state_scalarWritebackMode) & _stateFromAction_cellsNext_noBadWb_WIRE_6_0, + (|state_scalarWritebackMode) & _stateFromAction_cellsNext_noBadWb_WIRE_4_0, + (|state_scalarWritebackMode) & _stateFromAction_cellsNext_noBadWb_WIRE_2_0, + (|state_scalarWritebackMode) & scalar8Valid} + : 4'h0; + wire stateFromAction_cellsNext_doStart = + effectiveStarts[0] & ~stateFromAction_cellsNext_x7_valid; + wire stateFromAction_cellsNext_doResp = + stateFromAction_cellsNext_x7_valid & ~(stateFromAction_cellWriteback[0]); + wire _stateFromAction_cellsNext_noBadWb_WIRE_1 = + state_cells_0_state == 3'h0; + wire stateFromAction_cellsNext_precondition = + {1'h0, + {1'h0, stateFromAction_cellsNext_doStart} + {1'h0, stateFromAction_cellsNext_doResp} + + {1'h0, stateFromAction_cellWriteback[0]}} < 3'h2 + & (~stateFromAction_cellsNext_doStart | isFirstTx) + & (|{~stateFromAction_cellsNext_doResp, + _stateFromAction_cellsNext_noBadWb_WIRE_1_1, + isFirstTx}) + & ((|{~(stateFromAction_cellWriteback[0]), + _stateFromAction_cellsNext_noBadWb_WIRE_1, + scalar8Valid}) | state_write + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_1_1, isFirstTx})) + & (state_write | ~stateFromAction_cellsNext_x7_valid + | ~(stateFromAction_cellWriteback[0])) + & (~initCellsData_0_valid | _stateFromAction_cellsNext_noBadWb_WIRE_1 + | stateFromAction_cellWriteback[0]); + wire [2:0] stateFromAction_cells_0_state = + stateFromAction_cellsNext_precondition + ? (stateFromAction_cellsNext_doStart ? 3'h3 : 3'h0) + | {stateFromAction_cellsNext_doResp, 2'h0} + | (stateFromAction_cellsNext_doStart | stateFromAction_cellsNext_doResp + | stateFromAction_cellWriteback[0] + ? 3'h0 + : state_cells_0_state) + : 3'h0; + wire stateFromAction_cellsNext_doStart_1 = + effectiveStarts[1] & ~stateFromAction_cellsNext_x7_1_valid; + wire stateFromAction_cellsNext_doResp_1 = + stateFromAction_cellsNext_x7_1_valid & ~(stateFromAction_cellWriteback[1]); + wire _stateFromAction_cellsNext_noBadWb_WIRE_2_1 = + state_cells_1_state == 3'h0; + wire stateFromAction_cellsNext_precondition_1 = + {1'h0, + {1'h0, stateFromAction_cellsNext_doStart_1} + + {1'h0, stateFromAction_cellsNext_doResp_1} + + {1'h0, stateFromAction_cellWriteback[1]}} < 3'h2 + & (~stateFromAction_cellsNext_doStart_1 | _stateFromAction_cellsNext_noBadWb_WIRE_3_0) + & (|{~stateFromAction_cellsNext_doResp_1, + _stateFromAction_cellsNext_noBadWb_WIRE_3_1, + _stateFromAction_cellsNext_noBadWb_WIRE_3_0}) + & ((|{~(stateFromAction_cellWriteback[1]), + _stateFromAction_cellsNext_noBadWb_WIRE_2_1, + _stateFromAction_cellsNext_noBadWb_WIRE_2_0}) | state_write + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_3_1, + _stateFromAction_cellsNext_noBadWb_WIRE_3_0})) + & (state_write | ~stateFromAction_cellsNext_x7_1_valid + | ~(stateFromAction_cellWriteback[1])) + & (~initCellsData_0_valid | _stateFromAction_cellsNext_noBadWb_WIRE_2_1 + | stateFromAction_cellWriteback[1]); + wire [2:0] stateFromAction_cells_1_state = + stateFromAction_cellsNext_precondition_1 + ? (stateFromAction_cellsNext_doStart_1 ? 3'h3 : 3'h0) + | {stateFromAction_cellsNext_doResp_1, 2'h0} + | (stateFromAction_cellsNext_doStart_1 | stateFromAction_cellsNext_doResp_1 + | stateFromAction_cellWriteback[1] + ? 3'h0 + : state_cells_1_state) + : 3'h0; + wire stateFromAction_cellsNext_doStart_2 = + effectiveStarts[2] & ~stateFromAction_cellsNext_x7_2_valid; + wire stateFromAction_cellsNext_doResp_2 = + stateFromAction_cellsNext_x7_2_valid & ~(stateFromAction_cellWriteback[2]); + wire _stateFromAction_cellsNext_noBadWb_WIRE_4_1 = + state_cells_2_state == 3'h0; + wire stateFromAction_cellsNext_precondition_2 = + {1'h0, + {1'h0, stateFromAction_cellsNext_doStart_2} + + {1'h0, stateFromAction_cellsNext_doResp_2} + + {1'h0, stateFromAction_cellWriteback[2]}} < 3'h2 + & (~stateFromAction_cellsNext_doStart_2 | _stateFromAction_cellsNext_noBadWb_WIRE_5_0) + & (|{~stateFromAction_cellsNext_doResp_2, + _stateFromAction_cellsNext_noBadWb_WIRE_5_1, + _stateFromAction_cellsNext_noBadWb_WIRE_5_0}) + & ((|{~(stateFromAction_cellWriteback[2]), + _stateFromAction_cellsNext_noBadWb_WIRE_4_1, + _stateFromAction_cellsNext_noBadWb_WIRE_4_0}) | state_write + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_5_1, + _stateFromAction_cellsNext_noBadWb_WIRE_5_0})) + & (state_write | ~stateFromAction_cellsNext_x7_2_valid + | ~(stateFromAction_cellWriteback[2])) + & (~initCellsData_0_valid | _stateFromAction_cellsNext_noBadWb_WIRE_4_1 + | stateFromAction_cellWriteback[2]); + wire [2:0] stateFromAction_cells_2_state = + stateFromAction_cellsNext_precondition_2 + ? (stateFromAction_cellsNext_doStart_2 ? 3'h3 : 3'h0) + | {stateFromAction_cellsNext_doResp_2, 2'h0} + | (stateFromAction_cellsNext_doStart_2 | stateFromAction_cellsNext_doResp_2 + | stateFromAction_cellWriteback[2] + ? 3'h0 + : state_cells_2_state) + : 3'h0; + wire stateFromAction_cellsNext_doStart_3 = + effectiveStarts[3] & ~stateFromAction_cellsNext_x7_3_valid; + wire stateFromAction_cellsNext_doResp_3 = + stateFromAction_cellsNext_x7_3_valid & ~(stateFromAction_cellWriteback[3]); + wire _stateFromAction_cellsNext_noBadWb_WIRE_6_1 = + state_cells_3_state == 3'h0; + wire stateFromAction_cellsNext_precondition_3 = + {1'h0, + {1'h0, stateFromAction_cellsNext_doStart_3} + + {1'h0, stateFromAction_cellsNext_doResp_3} + + {1'h0, stateFromAction_cellWriteback[3]}} < 3'h2 + & (~stateFromAction_cellsNext_doStart_3 | _stateFromAction_cellsNext_noBadWb_WIRE_7_0) + & (|{~stateFromAction_cellsNext_doResp_3, + _stateFromAction_cellsNext_noBadWb_WIRE_7_1, + _stateFromAction_cellsNext_noBadWb_WIRE_7_0}) + & ((|{~(stateFromAction_cellWriteback[3]), + _stateFromAction_cellsNext_noBadWb_WIRE_6_1, + _stateFromAction_cellsNext_noBadWb_WIRE_6_0}) | state_write + & (|{_stateFromAction_cellsNext_noBadWb_WIRE_7_1, + _stateFromAction_cellsNext_noBadWb_WIRE_7_0})) + & (state_write | ~stateFromAction_cellsNext_x7_3_valid + | ~(stateFromAction_cellWriteback[3])) + & (~initCellsData_0_valid | _stateFromAction_cellsNext_noBadWb_WIRE_6_1 + | stateFromAction_cellWriteback[3]); + wire [2:0] stateFromAction_cells_3_state = + stateFromAction_cellsNext_precondition_3 + ? (stateFromAction_cellsNext_doStart_3 ? 3'h3 : 3'h0) + | {stateFromAction_cellsNext_doResp_3, 2'h0} + | (stateFromAction_cellsNext_doStart_3 | stateFromAction_cellsNext_doResp_3 + | stateFromAction_cellWriteback[3] + ? 3'h0 + : state_cells_3_state) + : 3'h0; + assign stateFromAction_isDone = + (_stateFromAction_cellsNext_noBadWb_WIRE_1 | stateFromAction_cellWriteback[0]) + & (_stateFromAction_cellsNext_noBadWb_WIRE_2_1 | stateFromAction_cellWriteback[1]) + & (_stateFromAction_cellsNext_noBadWb_WIRE_4_1 | stateFromAction_cellWriteback[2]) + & (_stateFromAction_cellsNext_noBadWb_WIRE_6_1 | stateFromAction_cellWriteback[3]); + wire [4:0] _GEN_3 = {1'h0, io_uop_bits_addr[3:0]}; + wire [4:0] _stateFromUop_bytesInRow1_T_1 = 5'h10 - _GEN_3; + wire [4:0] _stateFromUop_bytesInRow2_T = 5'h2 - _stateFromUop_bytesInRow1_T_1; + wire [2:0] _stateFromUop_tx1SizeSameRow_T = ~(io_uop_bits_addr[2:0]); + wire [4:0] _stateFromUop_bytesInRow2_T_1 = 5'h4 - _stateFromUop_bytesInRow1_T_1; + wire _stateFromUop_is1Byte_WIRE_1 = io_uop_bits_op == 5'h3; + wire _stateFromUop_is1Byte_WIRE_2 = io_uop_bits_op == 5'h5; + wire _stateFromUop_is2Byte_WIRE_0 = io_uop_bits_op == 5'h1; + wire _stateFromUop_is2Byte_WIRE_1 = io_uop_bits_op == 5'h4; + wire _stateFromUop_is2Byte_WIRE_2 = io_uop_bits_op == 5'h6; + wire _stateFromUop_is4Byte_WIRE_0 = io_uop_bits_op == 5'h2; + wire _stateFromUop_is4Byte_WIRE_1 = io_uop_bits_op == 5'h7; + wire [4:0] _GEN_4 = + {4'h0, + |{_stateFromUop_is1Byte_WIRE_2, _stateFromUop_is1Byte_WIRE_1, ~(|io_uop_bits_op)}}; + wire [4:0] stateFromUop_byteSum_1 = _GEN_3 + 5'h1; + wire [4:0] stateFromUop_byteSum_2 = _GEN_3 + 5'h2; + wire [4:0] stateFromUop_byteSum_3 = _GEN_3 + 5'h3; + wire [27:0] _leadWindow_shifted_T_4_rowAddr = + state_leadIndex[1] ? state_cells_3_rowAddr : state_cells_1_rowAddr; + wire [27:0] leadWindow_0_rowAddr = + state_leadIndex[0] + ? _leadWindow_shifted_T_4_rowAddr + : state_leadIndex[1] ? state_cells_2_rowAddr : state_cells_0_rowAddr; + wire [2:0] leadWindow_1_state = + state_leadIndex[0] + ? (state_leadIndex[1] ? 3'h0 : state_cells_2_state) + : _leadWindow_shifted_T_4_state; + wire [27:0] leadWindow_1_rowAddr = + state_leadIndex[0] + ? (state_leadIndex[1] ? 28'h0 : state_cells_2_rowAddr) + : _leadWindow_shifted_T_4_rowAddr; + wire [2:0] leadWindow_2_state = + state_leadIndex[1] + ? 3'h0 + : state_leadIndex[0] ? state_cells_3_state : state_cells_2_state; + wire [27:0] _GEN_5 = + state_leadIndex[0] ? state_cells_3_rowAddr : state_cells_2_rowAddr; + wire [2:0] leadWindow_3_state = (|state_leadIndex) ? 3'h0 : state_cells_3_state; + wire _stopConds_T_24 = leadWindow_0_state != 3'h2; + wire [3:0] moveLeadOHNormal = + leadWindow_0_state == 3'h1 | reqValidNormal + & (leadWindow_0_rowAddr != state_rowAddr | _stopConds_T_24) + ? 4'h1 + : leadWindow_1_state == 3'h1 | leadWindow_1_state == 3'h2 + & (leadWindow_1_rowAddr != state_rowAddr | _stopConds_T_24) + ? 4'h2 + : leadWindow_2_state == 3'h1 | leadWindow_2_state == 3'h2 + & ((state_leadIndex[1] ? 28'h0 : _GEN_5) != state_rowAddr | _stopConds_T_24) + ? 4'h4 + : {leadWindow_3_state == 3'h1 | leadWindow_3_state == 3'h2 + & (((|state_leadIndex) + ? 28'h0 + : state_cells_3_rowAddr) != state_rowAddr | _stopConds_T_24), + 3'h0}; + wire _stateFromUop_is4Byte_WIRE_2 = io_uop_bits_op == 5'hC; + wire _stateFromUop_is2Byte_WIRE_3 = io_uop_bits_op == 5'hD; + wire [1:0] _stateFromUop_isFloat_T_2 = + {_stateFromUop_is2Byte_WIRE_3, _stateFromUop_is4Byte_WIRE_2}; + wire stateFromUop_cellIsActive_2 = io_uop_bits_unreachableCell > 3'h2; + wire [2:0] _GEN_6 = + {~(|_stateFromUop_isFloat_T_2), + _stateFromUop_is2Byte_WIRE_3, + _stateFromUop_is4Byte_WIRE_2}; + wire stateFromUop_isScalarStore = (|_GEN_6) & io_uop_bits_store; + wire canMoveLead = ~state_isDone & (leadWindow_0_state != 3'h2 | txFire); + wire stateFromAction_cellsNext_takeResp = + ~state_write & stateFromAction_cellsNext_doResp; + wire [15:0] stateFromAction_cellsNext_effMask = + stateFromAction_cellsNext_takeResp ? state_cells_0_mask : 16'h0; + wire stateFromAction_cellsNext_takeResp_1 = + ~state_write & stateFromAction_cellsNext_doResp_1; + wire [15:0] stateFromAction_cellsNext_effMask_1 = + stateFromAction_cellsNext_takeResp_1 ? state_cells_1_mask : 16'h0; + wire stateFromAction_cellsNext_takeResp_2 = + ~state_write & stateFromAction_cellsNext_doResp_2; + wire [15:0] stateFromAction_cellsNext_effMask_2 = + stateFromAction_cellsNext_takeResp_2 ? state_cells_2_mask : 16'h0; + wire stateFromAction_cellsNext_takeResp_3 = + ~state_write & stateFromAction_cellsNext_doResp_3; + wire [15:0] stateFromAction_cellsNext_effMask_3 = + stateFromAction_cellsNext_takeResp_3 ? state_cells_3_mask : 16'h0; + wire [27:0] _stateFromUop_rowTable_T_3 = io_uop_bits_addr[31:4] + 28'h1; + wire [3:0] _stateFromUop_is2Byte_T_4 = + {_stateFromUop_is2Byte_WIRE_3, + _stateFromUop_is2Byte_WIRE_2, + _stateFromUop_is2Byte_WIRE_1, + _stateFromUop_is2Byte_WIRE_0}; + wire [2:0] _stateFromUop_is4Byte_T_3 = + {_stateFromUop_is4Byte_WIRE_2, + _stateFromUop_is4Byte_WIRE_1, + _stateFromUop_is4Byte_WIRE_0}; + wire [9:0] _GEN_7 = + {_stateFromUop_is1Byte_WIRE_2, + _stateFromUop_is1Byte_WIRE_1, + ~(|io_uop_bits_op), + _stateFromUop_is2Byte_WIRE_3, + _stateFromUop_is2Byte_WIRE_2, + _stateFromUop_is2Byte_WIRE_1, + _stateFromUop_is2Byte_WIRE_0, + _stateFromUop_is4Byte_WIRE_2, + _stateFromUop_is4Byte_WIRE_1, + _stateFromUop_is4Byte_WIRE_0}; always @(posedge clock or posedge reset) begin if (reset) begin - stateReg_valid <= 1'h0; - stateReg_bits_fwd <= 1'h0; - stateReg_bits_op <= 4'h0; - stateReg_bits_target <= 32'h0; - stateReg_bits_linkValid <= 1'h0; - stateReg_bits_linkAddr <= 5'h0; - stateReg_bits_linkData <= 32'h0; - stateReg_bits_pcEx <= 32'h0; + state_pc <= 32'h0; + state_write <= 1'h0; + state_faulted <= 1'h0; + state_rd <= 5'h0; + state_skipWriteback <= 1'h0; + state_scalarWritebackMode <= 3'h0; + state_tx1Size <= 5'h0; + state_tx2Size <= 5'h0; + state_float_writeback <= 1'h0; + state_cells_0_state <= 3'h0; + state_cells_0_data <= 8'h0; + state_cells_0_rowAddr <= 28'h0; + state_cells_0_mask <= 16'h0; + state_cells_1_state <= 3'h0; + state_cells_1_data <= 8'h0; + state_cells_1_rowAddr <= 28'h0; + state_cells_1_mask <= 16'h0; + state_cells_2_state <= 3'h0; + state_cells_2_data <= 8'h0; + state_cells_2_rowAddr <= 28'h0; + state_cells_2_mask <= 16'h0; + state_cells_3_state <= 3'h0; + state_cells_3_data <= 8'h0; + state_cells_3_rowAddr <= 28'h0; + state_cells_3_mask <= 16'h0; + state_leadIndex <= 2'h0; + state_rowAddr <= 28'h0; + state_isDone <= 1'h1; + txPending_valid <= 1'h0; + txPending_bits_txid <= 2'h0; + txPending_bits_req_rowAddr <= 28'h0; + txPending_bits_req_offset <= 4'h0; + txPending_bits_req_size <= 5'h0; + txPending_bits_req_write <= 1'h0; + txPending_bits_req_wdata <= 128'h0; + txPending_bits_req_wmask <= 16'h0; end else begin - stateReg_valid <= stateRegValid; - if (stateRegValid) begin - stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; - stateReg_bits_op <= io_fault_manager_valid ? 4'hD : io_req_bits_op; - stateReg_bits_target <= - io_fault_manager_valid - ? mtvec - : io_req_bits_fwd - ? nextState_linkData - : _nextState_target_T - ? io_target_data & 32'hFFFFFFFE - : io_req_bits_op == 4'h9 - ? mtvec - : (|{_pipeline0Target_call_T & _io_csr_in_fault_T, - _pipeline0Target_call_T & _io_csr_in_mcause_bits_T_4, - io_req_bits_op == 4'hA, - io_req_bits_op == 4'h8}) - ? io_csr_out_mepc - : io_req_bits_op == 4'hC - ? nextState_linkData - : io_req_bits_target; - stateReg_bits_linkValid <= - io_req_valid & (|io_req_bits_link) - & (|{_nextState_target_T, io_req_bits_op == 4'h0}); - stateReg_bits_linkAddr <= io_req_bits_link; - stateReg_bits_linkData <= nextState_linkData; - stateReg_bits_pcEx <= io_req_bits_pc; + if (initCellsData_0_valid) begin + state_pc <= io_uop_bits_pc; + state_write <= io_uop_bits_store; + state_rd <= io_uop_bits_rd; + state_skipWriteback <= io_uop_bits_store & (|_GEN_6); + state_scalarWritebackMode <= + io_uop_bits_op == 5'hD + ? (io_uop_bits_store ? 3'h0 : 3'h6) + : io_uop_bits_op == 5'hC + ? (io_uop_bits_store ? 3'h0 : 3'h5) + : io_uop_bits_op == 5'h2 + ? 3'h5 + : io_uop_bits_op == 5'h4 + ? 3'h3 + : io_uop_bits_op == 5'h1 + ? 3'h4 + : {1'h0, + io_uop_bits_op == 5'h3 + ? 2'h1 + : {~(|io_uop_bits_op), 1'h0}}; + state_tx1Size <= + _GEN_4 + | ((|_stateFromUop_is2Byte_T_4) + ? ((&(io_uop_bits_addr[3:0])) + ? (_stateFromUop_bytesInRow1_T_1 == 5'h3 + ? 5'h4 + : _stateFromUop_bytesInRow1_T_1) + : 5'h2 + << (_stateFromUop_tx1SizeSameRow_T[0] + ? 2'h0 + : _stateFromUop_tx1SizeSameRow_T[1] + ? 2'h1 + : {1'h1, ~(_stateFromUop_tx1SizeSameRow_T[2])})) + : 5'h0) + | ((|_stateFromUop_is4Byte_T_3) + ? (io_uop_bits_addr[3:0] > 4'hC + ? (_stateFromUop_bytesInRow1_T_1 == 5'h3 + ? 5'h4 + : _stateFromUop_bytesInRow1_T_1) + : io_uop_bits_addr[1:0] == 2'h0 ? 5'h4 : 5'h8 << io_uop_bits_addr[2]) + : 5'h0) | {_GEN_7 == 10'h0, 4'h0}; + state_tx2Size <= + _GEN_4 + | ((|_stateFromUop_is2Byte_T_4) + ? (_stateFromUop_bytesInRow2_T == 5'h3 + ? 5'h4 + : _stateFromUop_bytesInRow2_T) + : 5'h0) + | ((|_stateFromUop_is4Byte_T_3) + ? (_stateFromUop_bytesInRow2_T_1 == 5'h3 + ? 5'h4 + : _stateFromUop_bytesInRow2_T_1) + : 5'h0) | {_GEN_7 == 10'h0, 4'h0}; + state_float_writeback <= (|_stateFromUop_isFloat_T_2) & ~io_uop_bits_store; + if (|io_uop_bits_unreachableCell) begin + state_cells_0_rowAddr <= io_uop_bits_addr[31:4]; + state_cells_0_mask <= 16'h1 << io_uop_bits_addr[3:0]; + end + if (|(io_uop_bits_unreachableCell[2:1])) begin + state_cells_1_rowAddr <= + stateFromUop_byteSum_1[4] + ? _stateFromUop_rowTable_T_3 + : io_uop_bits_addr[31:4]; + state_cells_1_mask <= 16'h1 << stateFromUop_byteSum_1[3:0]; + end + if (stateFromUop_cellIsActive_2) begin + state_cells_2_rowAddr <= + stateFromUop_byteSum_2[4] + ? _stateFromUop_rowTable_T_3 + : io_uop_bits_addr[31:4]; + state_cells_2_mask <= 16'h1 << stateFromUop_byteSum_2[3:0]; + end + if (io_uop_bits_unreachableCell[2]) begin + state_cells_3_rowAddr <= + stateFromUop_byteSum_3[4] + ? _stateFromUop_rowTable_T_3 + : io_uop_bits_addr[31:4]; + state_cells_3_mask <= 16'h1 << stateFromUop_byteSum_3[3:0]; + end + state_leadIndex <= 2'h0; + end + else begin + if (~stateFromAction_cellsNext_precondition) begin + state_cells_0_rowAddr <= 28'h0; + state_cells_0_mask <= 16'h0; + end + if (~stateFromAction_cellsNext_precondition_1) begin + state_cells_1_rowAddr <= 28'h0; + state_cells_1_mask <= 16'h0; + end + if (~stateFromAction_cellsNext_precondition_2) begin + state_cells_2_rowAddr <= 28'h0; + state_cells_2_mask <= 16'h0; + end + if (~stateFromAction_cellsNext_precondition_3) begin + state_cells_3_rowAddr <= 28'h0; + state_cells_3_mask <= 16'h0; + end + if (canMoveLead) + state_leadIndex <= + state_leadIndex + + {|(moveLeadOHNormal[3:2]), moveLeadOHNormal[3] | moveLeadOHNormal[1]}; + end + state_faulted <= ~initCellsData_0_valid & isBlocked; + state_cells_0_state <= + initCellsData_0_valid + ? {1'h0, |io_uop_bits_unreachableCell, 1'h0} + : stateFromAction_cells_0_state; + state_cells_0_data <= + stateFromAction_cellsNext_precondition + ? (stateFromAction_cellsNext_effMask[0] ? io_busResp_bits_rdata[7:0] : 8'h0) + | (stateFromAction_cellsNext_effMask[1] ? io_busResp_bits_rdata[15:8] : 8'h0) + | (stateFromAction_cellsNext_effMask[2] ? io_busResp_bits_rdata[23:16] : 8'h0) + | (stateFromAction_cellsNext_effMask[3] ? io_busResp_bits_rdata[31:24] : 8'h0) + | (stateFromAction_cellsNext_effMask[4] ? io_busResp_bits_rdata[39:32] : 8'h0) + | (stateFromAction_cellsNext_effMask[5] ? io_busResp_bits_rdata[47:40] : 8'h0) + | (stateFromAction_cellsNext_effMask[6] ? io_busResp_bits_rdata[55:48] : 8'h0) + | (stateFromAction_cellsNext_effMask[7] ? io_busResp_bits_rdata[63:56] : 8'h0) + | (stateFromAction_cellsNext_effMask[8] ? io_busResp_bits_rdata[71:64] : 8'h0) + | (stateFromAction_cellsNext_effMask[9] ? io_busResp_bits_rdata[79:72] : 8'h0) + | (stateFromAction_cellsNext_effMask[10] + ? io_busResp_bits_rdata[87:80] + : 8'h0) + | (stateFromAction_cellsNext_effMask[11] + ? io_busResp_bits_rdata[95:88] + : 8'h0) + | (stateFromAction_cellsNext_effMask[12] + ? io_busResp_bits_rdata[103:96] + : 8'h0) + | (stateFromAction_cellsNext_effMask[13] + ? io_busResp_bits_rdata[111:104] + : 8'h0) + | (stateFromAction_cellsNext_effMask[14] + ? io_busResp_bits_rdata[119:112] + : 8'h0) + | (stateFromAction_cellsNext_effMask[15] + ? io_busResp_bits_rdata[127:120] + : 8'h0) + | (stateFromAction_cellsNext_takeResp + ? 8'h0 + : initCellsData_0_valid & (|io_uop_bits_unreachableCell) + & stateFromUop_isScalarStore + ? io_uop_bits_data[7:0] + : state_cells_0_data) + : 8'h0; + state_cells_1_state <= + initCellsData_0_valid + ? {1'h0, |(io_uop_bits_unreachableCell[2:1]), 1'h0} + : stateFromAction_cells_1_state; + state_cells_1_data <= + stateFromAction_cellsNext_precondition_1 + ? (stateFromAction_cellsNext_effMask_1[0] ? io_busResp_bits_rdata[7:0] : 8'h0) + | (stateFromAction_cellsNext_effMask_1[1] + ? io_busResp_bits_rdata[15:8] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[2] + ? io_busResp_bits_rdata[23:16] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[3] + ? io_busResp_bits_rdata[31:24] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[4] + ? io_busResp_bits_rdata[39:32] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[5] + ? io_busResp_bits_rdata[47:40] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[6] + ? io_busResp_bits_rdata[55:48] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[7] + ? io_busResp_bits_rdata[63:56] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[8] + ? io_busResp_bits_rdata[71:64] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[9] + ? io_busResp_bits_rdata[79:72] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[10] + ? io_busResp_bits_rdata[87:80] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[11] + ? io_busResp_bits_rdata[95:88] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[12] + ? io_busResp_bits_rdata[103:96] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[13] + ? io_busResp_bits_rdata[111:104] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[14] + ? io_busResp_bits_rdata[119:112] + : 8'h0) + | (stateFromAction_cellsNext_effMask_1[15] + ? io_busResp_bits_rdata[127:120] + : 8'h0) + | (stateFromAction_cellsNext_takeResp_1 + ? 8'h0 + : initCellsData_0_valid & (|(io_uop_bits_unreachableCell[2:1])) + & stateFromUop_isScalarStore + ? io_uop_bits_data[15:8] + : state_cells_1_data) + : 8'h0; + state_cells_2_state <= + initCellsData_0_valid + ? {1'h0, io_uop_bits_unreachableCell > 3'h2, 1'h0} + : stateFromAction_cells_2_state; + state_cells_2_data <= + stateFromAction_cellsNext_precondition_2 + ? (stateFromAction_cellsNext_effMask_2[0] ? io_busResp_bits_rdata[7:0] : 8'h0) + | (stateFromAction_cellsNext_effMask_2[1] + ? io_busResp_bits_rdata[15:8] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[2] + ? io_busResp_bits_rdata[23:16] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[3] + ? io_busResp_bits_rdata[31:24] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[4] + ? io_busResp_bits_rdata[39:32] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[5] + ? io_busResp_bits_rdata[47:40] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[6] + ? io_busResp_bits_rdata[55:48] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[7] + ? io_busResp_bits_rdata[63:56] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[8] + ? io_busResp_bits_rdata[71:64] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[9] + ? io_busResp_bits_rdata[79:72] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[10] + ? io_busResp_bits_rdata[87:80] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[11] + ? io_busResp_bits_rdata[95:88] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[12] + ? io_busResp_bits_rdata[103:96] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[13] + ? io_busResp_bits_rdata[111:104] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[14] + ? io_busResp_bits_rdata[119:112] + : 8'h0) + | (stateFromAction_cellsNext_effMask_2[15] + ? io_busResp_bits_rdata[127:120] + : 8'h0) + | (stateFromAction_cellsNext_takeResp_2 + ? 8'h0 + : initCellsData_0_valid & stateFromUop_cellIsActive_2 + & stateFromUop_isScalarStore + ? io_uop_bits_data[23:16] + : state_cells_2_data) + : 8'h0; + state_cells_3_state <= + initCellsData_0_valid + ? {1'h0, io_uop_bits_unreachableCell[2], 1'h0} + : stateFromAction_cells_3_state; + state_cells_3_data <= + stateFromAction_cellsNext_precondition_3 + ? (stateFromAction_cellsNext_effMask_3[0] ? io_busResp_bits_rdata[7:0] : 8'h0) + | (stateFromAction_cellsNext_effMask_3[1] + ? io_busResp_bits_rdata[15:8] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[2] + ? io_busResp_bits_rdata[23:16] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[3] + ? io_busResp_bits_rdata[31:24] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[4] + ? io_busResp_bits_rdata[39:32] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[5] + ? io_busResp_bits_rdata[47:40] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[6] + ? io_busResp_bits_rdata[55:48] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[7] + ? io_busResp_bits_rdata[63:56] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[8] + ? io_busResp_bits_rdata[71:64] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[9] + ? io_busResp_bits_rdata[79:72] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[10] + ? io_busResp_bits_rdata[87:80] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[11] + ? io_busResp_bits_rdata[95:88] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[12] + ? io_busResp_bits_rdata[103:96] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[13] + ? io_busResp_bits_rdata[111:104] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[14] + ? io_busResp_bits_rdata[119:112] + : 8'h0) + | (stateFromAction_cellsNext_effMask_3[15] + ? io_busResp_bits_rdata[127:120] + : 8'h0) + | (stateFromAction_cellsNext_takeResp_3 + ? 8'h0 + : initCellsData_0_valid & io_uop_bits_unreachableCell[2] + & stateFromUop_isScalarStore + ? io_uop_bits_data[31:24] + : state_cells_3_data) + : 8'h0; + state_rowAddr <= + initCellsData_0_valid + ? io_uop_bits_addr[31:4] + : canMoveLead + ? (moveLeadOHNormal[0] ? leadWindow_0_rowAddr : 28'h0) + | (moveLeadOHNormal[1] ? leadWindow_1_rowAddr : 28'h0) + | (~(moveLeadOHNormal[2]) | state_leadIndex[1] ? 28'h0 : _GEN_5) + | (~(moveLeadOHNormal[3]) | (|state_leadIndex) + ? 28'h0 + : state_cells_3_rowAddr) + : leadWindow_0_rowAddr; + state_isDone <= ~initCellsData_0_valid & stateFromAction_isDone; + txPending_valid <= ~txFire & txOutgoing_valid; + if (txFire) begin + txPending_bits_txid <= 2'h0; + txPending_bits_req_rowAddr <= 28'h0; + txPending_bits_req_offset <= 4'h0; + txPending_bits_req_size <= 5'h0; + txPending_bits_req_wdata <= 128'h0; + txPending_bits_req_wmask <= 16'h0; + end + else if (txPending_valid) begin + end + else begin + txPending_bits_txid <= _txidAllocator_io_alloc_bits; + txPending_bits_req_rowAddr <= state_rowAddr; + txPending_bits_req_offset <= txOffset; + txPending_bits_req_size <= txSize; + txPending_bits_req_wdata <= wDataNormal; + txPending_bits_req_wmask <= wMaskNormal; end + txPending_bits_req_write <= ~txFire & txOutgoing_bits_req_write; + end + end // always @(posedge, posedge) + wire [3:0] starts = reqValidNormal ? startedNormal : 4'h0; + wire [31:0] entry_y = {txOutgoing_bits_req_rowAddr, txOutgoing_bits_req_offset}; + always @(posedge clock) begin + if (txFire & txOutgoing_bits_txid == 2'h0) begin + bookkeeping_0_addr <= entry_y; + bookkeeping_0_mask <= starts; + end + if (txFire & txOutgoing_bits_txid == 2'h1) begin + bookkeeping_1_addr <= entry_y; + bookkeeping_1_mask <= starts; + end + if (txFire & txOutgoing_bits_txid == 2'h2) begin + bookkeeping_2_addr <= entry_y; + bookkeeping_2_mask <= starts; + end + if (txFire & (&txOutgoing_bits_txid)) begin + bookkeeping_3_addr <= entry_y; + bookkeeping_3_mask <= starts; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + state_pc = 32'h0; + state_write = 1'h0; + state_faulted = 1'h0; + state_rd = 5'h0; + state_skipWriteback = 1'h0; + state_scalarWritebackMode = 3'h0; + state_tx1Size = 5'h0; + state_tx2Size = 5'h0; + state_float_writeback = 1'h0; + state_cells_0_state = 3'h0; + state_cells_0_data = 8'h0; + state_cells_0_rowAddr = 28'h0; + state_cells_0_mask = 16'h0; + state_cells_1_state = 3'h0; + state_cells_1_data = 8'h0; + state_cells_1_rowAddr = 28'h0; + state_cells_1_mask = 16'h0; + state_cells_2_state = 3'h0; + state_cells_2_data = 8'h0; + state_cells_2_rowAddr = 28'h0; + state_cells_2_mask = 16'h0; + state_cells_3_state = 3'h0; + state_cells_3_data = 8'h0; + state_cells_3_rowAddr = 28'h0; + state_cells_3_mask = 16'h0; + state_leadIndex = 2'h0; + state_rowAddr = 28'h0; + state_isDone = 1'h1; + txPending_valid = 1'h0; + txPending_bits_txid = 2'h0; + txPending_bits_req_rowAddr = 28'h0; + txPending_bits_req_offset = 4'h0; + txPending_bits_req_size = 5'h0; + txPending_bits_req_write = 1'h0; + txPending_bits_req_wdata = 128'h0; + txPending_bits_req_wmask = 16'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + IndexAllocatorShifting_1 txidAllocator ( + .clock (clock), + .reset (reset), + .io_alloc_ready (txFire), + .io_alloc_valid (_txidAllocator_io_alloc_valid), + .io_alloc_bits (_txidAllocator_io_alloc_bits), + .io_free_valid (respValid), + .io_free_bits (respTxid) + ); + Queue1_UInt2 faultQueue ( + .clock (clock), + .reset (reset), + .io_enq_valid (txOutgoing_valid & isBlocked), + .io_enq_bits (txOutgoing_bits_txid), + .io_deq_ready (~io_busResp_valid), + .io_deq_valid (_faultQueue_io_deq_valid), + .io_deq_bits (_faultQueue_io_deq_bits) + ); + assign io_uop_ready = stateFromAction_isDone; + assign io_busReq_valid = ~isBlocked & txOutgoing_valid; + assign io_busReq_bits_txid = isBlocked ? 2'h0 : txOutgoing_bits_txid; + assign io_busReq_bits_req_rowAddr = isBlocked ? 28'h0 : txOutgoing_bits_req_rowAddr; + assign io_busReq_bits_req_offset = isBlocked ? 4'h0 : txOutgoing_bits_req_offset; + assign io_busReq_bits_req_size = + isBlocked ? 5'h0 : txPending_valid ? txPending_bits_req_size : txSize; + assign io_busReq_bits_req_write = ~isBlocked & txOutgoing_bits_req_write; + assign io_busReq_bits_req_wdata = + isBlocked ? 128'h0 : txPending_valid ? txPending_bits_req_wdata : wDataNormal; + assign io_busReq_bits_req_wmask = + isBlocked ? 16'h0 : txPending_valid ? txPending_bits_req_wmask : wMaskNormal; + assign io_intWriteback_valid = req_y_valid; + assign io_intWriteback_bits_addr = state_rd; + assign io_intWriteback_bits_data = state_float_writeback ? 32'h0 : scalarReq_bits; + assign io_floatWriteback_valid = io_floatWriteback_valid_0; + assign io_floatWriteback_bits_addr = state_rd; + assign io_floatWriteback_bits_data = state_float_writeback ? scalarReq_bits : 32'h0; + assign io_pc = state_pc; + assign io_active = + ~(_stateFromAction_cellsNext_noBadWb_WIRE_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_2_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_4_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_6_1); + assign io_storeComplete = + state_write + & ~(_stateFromAction_cellsNext_noBadWb_WIRE_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_2_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_4_1 + & _stateFromAction_cellsNext_noBadWb_WIRE_6_1) + & stateFromAction_cells_0_state == 3'h0 & stateFromAction_cells_1_state == 3'h0 + & stateFromAction_cells_2_state == 3'h0 & stateFromAction_cells_3_state == 3'h0; + assign io_fault_valid = newFault & ~state_faulted; + assign io_fault_bits_write = state_write; + assign io_fault_bits_addr = _GEN_0[respTxid]; + assign io_fault_bits_epc = state_pc; +endmodule + +module LsuV3( + input clock, + reset, + output io_req_0_ready, + input io_req_0_valid, + io_req_0_bits_store, + input [4:0] io_req_0_bits_addr, + io_req_0_bits_op, + input [31:0] io_req_0_bits_pc, + output io_req_1_ready, + input io_req_1_valid, + io_req_1_bits_store, + input [4:0] io_req_1_bits_addr, + io_req_1_bits_op, + input [31:0] io_req_1_bits_pc, + output io_req_2_ready, + input io_req_2_valid, + io_req_2_bits_store, + input [4:0] io_req_2_bits_addr, + io_req_2_bits_op, + input [31:0] io_req_2_bits_pc, + output io_req_3_ready, + input io_req_3_valid, + io_req_3_bits_store, + input [4:0] io_req_3_bits_addr, + io_req_3_bits_op, + input [31:0] io_req_3_bits_pc, + io_busPort_addr_0, + io_busPort_addr_1, + io_busPort_addr_2, + io_busPort_addr_3, + io_busPort_data_0, + io_busPort_data_1, + io_busPort_data_2, + io_busPort_data_3, + io_busPort_flt_data_0, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_rd_flt_valid, + output [4:0] io_rd_flt_bits_addr, + output [31:0] io_rd_flt_bits_data, + output io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + output io_dbus_valid, + io_dbus_write, + output [31:0] io_dbus_addr, + output [127:0] io_dbus_wdata, + output [15:0] io_dbus_wmask, + input [127:0] io_dbus_rdata, + output io_flush_valid, + output [31:0] io_flush_pcNext, + input io_flush_ready, + output io_fault_valid, + io_fault_bits_write, + output [31:0] io_fault_bits_addr, + io_fault_bits_epc, + output io_ebus_dbus_valid, + input io_ebus_dbus_ready, + output io_ebus_dbus_write, + output [31:0] io_ebus_dbus_addr, + output [4:0] io_ebus_dbus_size, + output [127:0] io_ebus_dbus_wdata, + output [15:0] io_ebus_dbus_wmask, + input [127:0] io_ebus_dbus_rdata, + input io_ebus_fault_valid, + output [2:0] io_queueCapacity, + output io_active, + io_storeComplete_valid, + output [31:0] io_storeComplete_bits, + input io_pipelineFlush +); + + wire slot_io_uop_valid; + wire _slot_io_uop_ready; + wire _slot_io_busReq_valid; + wire [1:0] _slot_io_busReq_bits_txid; + wire [27:0] _slot_io_busReq_bits_req_rowAddr; + wire [3:0] _slot_io_busReq_bits_req_offset; + wire _slot_io_busReq_bits_req_write; + wire [127:0] _slot_io_busReq_bits_req_wdata; + wire [15:0] _slot_io_busReq_bits_req_wmask; + wire _slot_io_active; + wire _slot_io_fault_valid; + wire _alignedOps_aligner_out_0_valid; + wire [110:0] _alignedOps_aligner_out_0_bits; + wire _alignedOps_aligner_out_1_valid; + wire [110:0] _alignedOps_aligner_out_1_bits; + wire _alignedOps_aligner_out_2_valid; + wire [110:0] _alignedOps_aligner_out_2_bits; + wire _alignedOps_aligner_out_3_valid; + wire [110:0] _alignedOps_aligner_out_3_bits; + wire [2:0] _rs_io_nEnqueued; + wire [2:0] _rs_io_nSpace; + wire _rs_io_dataOut_0_store; + wire [4:0] _rs_io_dataOut_0_rd; + wire [4:0] _rs_io_dataOut_0_op; + wire [31:0] _rs_io_dataOut_0_pc; + wire [31:0] _rs_io_dataOut_0_addr; + wire [31:0] _rs_io_dataOut_0_data; + wire [2:0] _rs_io_dataOut_0_unreachableCell; + reg flushCmd_valid; + reg [31:0] flushCmd_bits_pcNext; + wire [2:0] _validSums_T_1 = {2'h0, io_req_0_valid} + {2'h0, io_req_1_valid}; + wire io_req_0_ready_0 = (|_rs_io_nSpace) & ~flushCmd_valid; + wire io_req_1_ready_0 = + {2'h0, io_req_0_valid} < _rs_io_nSpace & ~flushCmd_valid; + wire io_req_2_ready_0 = _validSums_T_1 < _rs_io_nSpace & ~flushCmd_valid; + wire io_req_3_ready_0 = + _validSums_T_1 + {2'h0, io_req_2_valid} < _rs_io_nSpace & ~flushCmd_valid; + wire _ops_uop_isScalar2B_WIRE_3 = io_req_0_bits_op == 5'hD; + wire [2:0] _ops_uop_isScalar1B_T_3 = + {io_req_0_bits_op == 5'h5, io_req_0_bits_op == 5'h3, io_req_0_bits_op == 5'h0}; + wire [3:0] _ops_uop_isScalar2B_T_4 = + {_ops_uop_isScalar2B_WIRE_3, + io_req_0_bits_op == 5'h6, + io_req_0_bits_op == 5'h4, + io_req_0_bits_op == 5'h1}; + wire _flushCmd_T_2 = io_req_0_ready_0 & io_req_0_valid; + wire _ops_uop_isScalar2B_WIRE_1_3 = io_req_1_bits_op == 5'hD; + wire [2:0] _ops_uop_isScalar1B_T_7 = + {io_req_1_bits_op == 5'h5, io_req_1_bits_op == 5'h3, io_req_1_bits_op == 5'h0}; + wire [3:0] _ops_uop_isScalar2B_T_9 = + {_ops_uop_isScalar2B_WIRE_1_3, + io_req_1_bits_op == 5'h6, + io_req_1_bits_op == 5'h4, + io_req_1_bits_op == 5'h1}; + wire _ops_uop_isScalar2B_WIRE_2_3 = io_req_2_bits_op == 5'hD; + wire [2:0] _ops_uop_isScalar1B_T_11 = + {io_req_2_bits_op == 5'h5, io_req_2_bits_op == 5'h3, io_req_2_bits_op == 5'h0}; + wire [3:0] _ops_uop_isScalar2B_T_14 = + {_ops_uop_isScalar2B_WIRE_2_3, + io_req_2_bits_op == 5'h6, + io_req_2_bits_op == 5'h4, + io_req_2_bits_op == 5'h1}; + wire _ops_uop_isScalar2B_WIRE_3_3 = io_req_3_bits_op == 5'hD; + wire [2:0] _ops_uop_isScalar1B_T_15 = + {io_req_3_bits_op == 5'h5, io_req_3_bits_op == 5'h3, io_req_3_bits_op == 5'h0}; + wire [3:0] _ops_uop_isScalar2B_T_19 = + {_ops_uop_isScalar2B_WIRE_3_3, + io_req_3_bits_op == 5'h6, + io_req_3_bits_op == 5'h4, + io_req_3_bits_op == 5'h1}; + wire [31:0] addr = {_slot_io_busReq_bits_req_rowAddr, 4'h0}; + wire itcm = addr < 32'h2000; + wire dtcm = (|(_slot_io_busReq_bits_req_rowAddr[27:12])) & addr < 32'h18000; + wire _rawFaultValid_T = _slot_io_busReq_valid & _slot_io_busReq_bits_req_write; + wire ibusFault_y = _rawFaultValid_T & itcm; + reg isFaulted; + reg isFlushing; + wire fireNewFault = + _slot_io_fault_valid & ~isFaulted & ~isFlushing & ~io_pipelineFlush; + wire rs_io_flush = io_pipelineFlush | fireNewFault; + assign slot_io_uop_valid = + (|_rs_io_nEnqueued) & ~rs_io_flush & ~isFaulted & ~isFlushing & ~io_pipelineFlush; + wire io_ibus_valid_0 = + itcm & _slot_io_busReq_valid & ~_slot_io_busReq_bits_req_write; + reg ibusResp; + wire io_dbus_valid_0 = dtcm & _slot_io_busReq_valid; + reg dbusResp; + wire _slot_io_busReq_ready_defaultSel_T = itcm | dtcm; + wire io_ebus_dbus_valid_0 = + ~_slot_io_busReq_ready_defaultSel_T & _slot_io_busReq_valid; + reg ebusResp; + reg [1:0] respTxid; + reg slot_io_busResp_bits_fault_REG; + wire _isFlushing_T_1 = isFlushing | io_pipelineFlush; + wire clearFaultState = ~_slot_io_active & _isFlushing_T_1; + wire _flushCmd_T_4 = _flushCmd_T_2 & io_req_0_bits_op == 5'hB; + wire _GEN = rs_io_flush | flushCmd_valid & io_flush_ready; + always @(posedge clock or posedge reset) begin + if (reset) begin + flushCmd_valid <= 1'h0; + flushCmd_bits_pcNext <= 32'h0; + isFaulted <= 1'h0; + isFlushing <= 1'h0; + ibusResp <= 1'h0; + dbusResp <= 1'h0; + ebusResp <= 1'h0; + respTxid <= 2'h0; + slot_io_busResp_bits_fault_REG <= 1'h0; + end + else begin + flushCmd_valid <= ~_GEN & (_flushCmd_T_4 | flushCmd_valid); + if (_GEN) + flushCmd_bits_pcNext <= 32'h0; + else if (_flushCmd_T_4) + flushCmd_bits_pcNext <= io_req_0_bits_pc + 32'h4; + isFaulted <= ~clearFaultState & (isFaulted | fireNewFault); + isFlushing <= ~clearFaultState & _isFlushing_T_1; + ibusResp <= io_ibus_valid_0 & io_ibus_ready | ibusFault_y; + dbusResp <= io_dbus_valid_0; + ebusResp <= io_ebus_dbus_valid_0 & io_ebus_dbus_ready; + respTxid <= _slot_io_busReq_bits_txid; + slot_io_busResp_bits_fault_REG <= _rawFaultValid_T & itcm | io_ebus_fault_valid; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; - end - stateReg_valid = _RANDOM[2'h0][0]; - stateReg_bits_fwd = _RANDOM[2'h0][1]; - stateReg_bits_op = _RANDOM[2'h0][5:2]; - stateReg_bits_target = {_RANDOM[2'h0][31:6], _RANDOM[2'h1][5:0]}; - stateReg_bits_linkValid = _RANDOM[2'h1][6]; - stateReg_bits_linkAddr = _RANDOM[2'h1][11:7]; - stateReg_bits_linkData = {_RANDOM[2'h1][31:12], _RANDOM[2'h2][11:0]}; - stateReg_bits_pcEx = {_RANDOM[2'h2][31:12], _RANDOM[2'h3][11:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - stateReg_valid = 1'h0; - stateReg_bits_fwd = 1'h0; - stateReg_bits_op = 4'h0; - stateReg_bits_target = 32'h0; - stateReg_bits_linkValid = 1'h0; - stateReg_bits_linkAddr = 5'h0; - stateReg_bits_linkData = 32'h0; - stateReg_bits_pcEx = 32'h0; + flushCmd_valid = 1'h0; + flushCmd_bits_pcNext = 32'h0; + isFaulted = 1'h0; + isFlushing = 1'h0; + ibusResp = 1'h0; + dbusResp = 1'h0; + ebusResp = 1'h0; + respTxid = 2'h0; + slot_io_busResp_bits_fault_REG = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_csr_in_mode_valid = - stateReg_valid - & (_io_csr_in_mcause_bits_T_4 - ? (|{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2}) - : _ignore_T_5); - assign io_csr_in_mode_bits = {1'h0, ~(_ignore_T_5 & _io_csr_in_fault_T)}; - assign io_csr_in_mcause_valid = - stateReg_valid & (usageFault | _ignore_T_3 | _io_csr_in_mcause_bits_T_4 & _ignore_T_2) - | io_fault_manager_valid; - assign io_csr_in_mcause_bits = - io_fault_manager_valid - ? io_fault_manager_bits_mcause - : {27'h0, - _ignore_T_3 & _io_csr_in_fault_T - ? 5'hB - : _ignore_T_3 & _io_csr_in_mcause_bits_T_4 - ? 5'h8 - : _ignore_T_2 ? 5'h3 : usageFault ? 5'h19 : 5'h0}; - assign io_csr_in_mepc_valid = stateReg_valid & _ignore_T_3 | io_fault_manager_valid; - assign io_csr_in_mepc_bits = - io_fault_manager_valid ? io_fault_manager_bits_mepc : stateReg_bits_pcEx; - assign io_csr_in_mtval_valid = usageFault | io_fault_manager_valid; - assign io_csr_in_mtval_bits = - io_fault_manager_valid ? io_fault_manager_bits_mtval : stateReg_bits_pcEx; - assign io_csr_in_halt = - stateReg_valid & _ignore_T_4 & _io_csr_in_fault_T | io_csr_in_fault_0; - assign io_csr_in_fault = io_csr_in_fault_0; - assign io_csr_in_wfi = stateReg_valid & _ignore_T_6; - assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; - assign io_rd_bits_addr = stateReg_bits_linkAddr; - assign io_rd_bits_data = stateReg_bits_linkData; - assign io_taken_valid = - stateReg_valid - & (stateReg_bits_op == 4'hD - | (stateReg_bits_op == 4'h7 - ? io_rs1_data >= io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h6 - ? io_rs1_data < io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h5 - ? $signed(io_rs1_data) >= $signed(io_rs2_data) != stateReg_bits_fwd - : stateReg_bits_op == 4'h4 - ? $signed(io_rs1_data) < $signed(io_rs2_data) != stateReg_bits_fwd - : stateReg_bits_op == 4'h3 - ? io_rs1_data != io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h2 - ? io_rs1_data == io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op) - ? ~stateReg_bits_fwd - : stateReg_bits_op == 4'hC - | (stateReg_bits_op == 4'hB - ? _io_csr_in_fault_T - : stateReg_bits_op == 4'hA - ? _io_csr_in_mcause_bits_T_4 - : stateReg_bits_op == 4'h9 - | stateReg_bits_op == 4'h8 - & _io_csr_in_mcause_bits_T_4))); - assign io_taken_value = stateReg_bits_target; - assign io_interlock = - stateReg_valid & (|{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2}); + CircularBufferMulti_1 rs ( + .clock (clock), + .reset (reset), + .io_enqValid + ({1'h0, + {1'h0, _alignedOps_aligner_out_0_valid} + {1'h0, _alignedOps_aligner_out_1_valid}} + + {1'h0, + {1'h0, _alignedOps_aligner_out_2_valid} + + {1'h0, _alignedOps_aligner_out_3_valid}}), + .io_enqData_0_store (_alignedOps_aligner_out_0_bits[110]), + .io_enqData_0_rd (_alignedOps_aligner_out_0_bits[109:105]), + .io_enqData_0_op (_alignedOps_aligner_out_0_bits[104:100]), + .io_enqData_0_pc (_alignedOps_aligner_out_0_bits[99:68]), + .io_enqData_0_addr (_alignedOps_aligner_out_0_bits[67:36]), + .io_enqData_0_data (_alignedOps_aligner_out_0_bits[35:4]), + .io_enqData_0_unreachableCell (_alignedOps_aligner_out_0_bits[3:1]), + .io_enqData_0_initAsConstStride (_alignedOps_aligner_out_0_bits[0]), + .io_enqData_1_store (_alignedOps_aligner_out_1_bits[110]), + .io_enqData_1_rd (_alignedOps_aligner_out_1_bits[109:105]), + .io_enqData_1_op (_alignedOps_aligner_out_1_bits[104:100]), + .io_enqData_1_pc (_alignedOps_aligner_out_1_bits[99:68]), + .io_enqData_1_addr (_alignedOps_aligner_out_1_bits[67:36]), + .io_enqData_1_data (_alignedOps_aligner_out_1_bits[35:4]), + .io_enqData_1_unreachableCell (_alignedOps_aligner_out_1_bits[3:1]), + .io_enqData_1_initAsConstStride (_alignedOps_aligner_out_1_bits[0]), + .io_enqData_2_store (_alignedOps_aligner_out_2_bits[110]), + .io_enqData_2_rd (_alignedOps_aligner_out_2_bits[109:105]), + .io_enqData_2_op (_alignedOps_aligner_out_2_bits[104:100]), + .io_enqData_2_pc (_alignedOps_aligner_out_2_bits[99:68]), + .io_enqData_2_addr (_alignedOps_aligner_out_2_bits[67:36]), + .io_enqData_2_data (_alignedOps_aligner_out_2_bits[35:4]), + .io_enqData_2_unreachableCell (_alignedOps_aligner_out_2_bits[3:1]), + .io_enqData_2_initAsConstStride (_alignedOps_aligner_out_2_bits[0]), + .io_enqData_3_store (_alignedOps_aligner_out_3_bits[110]), + .io_enqData_3_rd (_alignedOps_aligner_out_3_bits[109:105]), + .io_enqData_3_op (_alignedOps_aligner_out_3_bits[104:100]), + .io_enqData_3_pc (_alignedOps_aligner_out_3_bits[99:68]), + .io_enqData_3_addr (_alignedOps_aligner_out_3_bits[67:36]), + .io_enqData_3_data (_alignedOps_aligner_out_3_bits[35:4]), + .io_enqData_3_unreachableCell (_alignedOps_aligner_out_3_bits[3:1]), + .io_enqData_3_initAsConstStride (_alignedOps_aligner_out_3_bits[0]), + .io_nEnqueued (_rs_io_nEnqueued), + .io_nSpace (_rs_io_nSpace), + .io_dataOut_0_store (_rs_io_dataOut_0_store), + .io_dataOut_0_rd (_rs_io_dataOut_0_rd), + .io_dataOut_0_op (_rs_io_dataOut_0_op), + .io_dataOut_0_pc (_rs_io_dataOut_0_pc), + .io_dataOut_0_addr (_rs_io_dataOut_0_addr), + .io_dataOut_0_data (_rs_io_dataOut_0_data), + .io_dataOut_0_unreachableCell (_rs_io_dataOut_0_unreachableCell), + .io_dataOut_0_initAsConstStride (/* unused */), + .io_dataOut_1_store (/* unused */), + .io_dataOut_1_rd (/* unused */), + .io_dataOut_1_op (/* unused */), + .io_dataOut_1_pc (/* unused */), + .io_dataOut_1_addr (/* unused */), + .io_dataOut_1_data (/* unused */), + .io_dataOut_1_unreachableCell (/* unused */), + .io_dataOut_1_initAsConstStride (/* unused */), + .io_dataOut_2_store (/* unused */), + .io_dataOut_2_rd (/* unused */), + .io_dataOut_2_op (/* unused */), + .io_dataOut_2_pc (/* unused */), + .io_dataOut_2_addr (/* unused */), + .io_dataOut_2_data (/* unused */), + .io_dataOut_2_unreachableCell (/* unused */), + .io_dataOut_2_initAsConstStride (/* unused */), + .io_dataOut_3_store (/* unused */), + .io_dataOut_3_rd (/* unused */), + .io_dataOut_3_op (/* unused */), + .io_dataOut_3_pc (/* unused */), + .io_dataOut_3_addr (/* unused */), + .io_dataOut_3_data (/* unused */), + .io_dataOut_3_unreachableCell (/* unused */), + .io_dataOut_3_initAsConstStride (/* unused */), + .io_deqReady ({2'h0, _slot_io_uop_ready & slot_io_uop_valid}), + .io_flush (rs_io_flush) + ); + Aligner_111_4 alignedOps_aligner ( + .in_0_valid (_flushCmd_T_2 & io_req_0_bits_op != 5'hB), + .in_0_bits + ({io_req_0_bits_store, + io_req_0_bits_addr, + io_req_0_bits_op, + io_req_0_bits_pc, + io_busPort_addr_0, + (|{_ops_uop_isScalar2B_WIRE_3, io_req_0_bits_op == 5'hC}) + ? io_busPort_flt_data_0 + : io_busPort_data_0, + ~(|_ops_uop_isScalar1B_T_3) & ~(|_ops_uop_isScalar2B_T_4), + |_ops_uop_isScalar2B_T_4, + |_ops_uop_isScalar1B_T_3, + 1'h0}), + .in_1_valid (io_req_1_ready_0 & io_req_1_valid & io_req_1_bits_op != 5'hB), + .in_1_bits + ({io_req_1_bits_store, + io_req_1_bits_addr, + io_req_1_bits_op, + io_req_1_bits_pc, + io_busPort_addr_1, + (|{_ops_uop_isScalar2B_WIRE_1_3, io_req_1_bits_op == 5'hC}) + ? 32'h0 + : io_busPort_data_1, + ~(|_ops_uop_isScalar1B_T_7) & ~(|_ops_uop_isScalar2B_T_9), + |_ops_uop_isScalar2B_T_9, + |_ops_uop_isScalar1B_T_7, + 1'h0}), + .in_2_valid (io_req_2_ready_0 & io_req_2_valid & io_req_2_bits_op != 5'hB), + .in_2_bits + ({io_req_2_bits_store, + io_req_2_bits_addr, + io_req_2_bits_op, + io_req_2_bits_pc, + io_busPort_addr_2, + (|{_ops_uop_isScalar2B_WIRE_2_3, io_req_2_bits_op == 5'hC}) + ? 32'h0 + : io_busPort_data_2, + ~(|_ops_uop_isScalar1B_T_11) & ~(|_ops_uop_isScalar2B_T_14), + |_ops_uop_isScalar2B_T_14, + |_ops_uop_isScalar1B_T_11, + 1'h0}), + .in_3_valid (io_req_3_ready_0 & io_req_3_valid & io_req_3_bits_op != 5'hB), + .in_3_bits + ({io_req_3_bits_store, + io_req_3_bits_addr, + io_req_3_bits_op, + io_req_3_bits_pc, + io_busPort_addr_3, + (|{_ops_uop_isScalar2B_WIRE_3_3, io_req_3_bits_op == 5'hC}) + ? 32'h0 + : io_busPort_data_3, + ~(|_ops_uop_isScalar1B_T_15) & ~(|_ops_uop_isScalar2B_T_19), + |_ops_uop_isScalar2B_T_19, + |_ops_uop_isScalar1B_T_15, + 1'h0}), + .out_0_valid (_alignedOps_aligner_out_0_valid), + .out_0_bits (_alignedOps_aligner_out_0_bits), + .out_1_valid (_alignedOps_aligner_out_1_valid), + .out_1_bits (_alignedOps_aligner_out_1_bits), + .out_2_valid (_alignedOps_aligner_out_2_valid), + .out_2_bits (_alignedOps_aligner_out_2_bits), + .out_3_valid (_alignedOps_aligner_out_3_valid), + .out_3_bits (_alignedOps_aligner_out_3_bits) + ); + LsuSuperSlot slot ( + .clock (clock), + .reset (reset), + .io_uop_ready (_slot_io_uop_ready), + .io_uop_valid (slot_io_uop_valid), + .io_uop_bits_store (_rs_io_dataOut_0_store), + .io_uop_bits_rd (_rs_io_dataOut_0_rd), + .io_uop_bits_op (_rs_io_dataOut_0_op), + .io_uop_bits_pc (_rs_io_dataOut_0_pc), + .io_uop_bits_addr (_rs_io_dataOut_0_addr), + .io_uop_bits_data (_rs_io_dataOut_0_data), + .io_uop_bits_unreachableCell (_rs_io_dataOut_0_unreachableCell), + .io_busReq_ready + (itcm & (io_ibus_ready | ibusFault_y) | dtcm | ~_slot_io_busReq_ready_defaultSel_T + & io_ebus_dbus_ready), + .io_busReq_valid (_slot_io_busReq_valid), + .io_busReq_bits_txid (_slot_io_busReq_bits_txid), + .io_busReq_bits_req_rowAddr (_slot_io_busReq_bits_req_rowAddr), + .io_busReq_bits_req_offset (_slot_io_busReq_bits_req_offset), + .io_busReq_bits_req_size (io_ebus_dbus_size), + .io_busReq_bits_req_write (_slot_io_busReq_bits_req_write), + .io_busReq_bits_req_wdata (_slot_io_busReq_bits_req_wdata), + .io_busReq_bits_req_wmask (_slot_io_busReq_bits_req_wmask), + .io_busResp_valid (ibusResp | dbusResp | ebusResp), + .io_busResp_bits_txid (respTxid), + .io_busResp_bits_rdata + ((ibusResp ? io_ibus_rdata : 128'h0) | (dbusResp ? io_dbus_rdata : 128'h0) + | (ebusResp ? io_ebus_dbus_rdata : 128'h0)), + .io_busResp_bits_fault (slot_io_busResp_bits_fault_REG), + .io_intWriteback_valid (io_rd_valid), + .io_intWriteback_bits_addr (io_rd_bits_addr), + .io_intWriteback_bits_data (io_rd_bits_data), + .io_floatWriteback_valid (io_rd_flt_valid), + .io_floatWriteback_bits_addr (io_rd_flt_bits_addr), + .io_floatWriteback_bits_data (io_rd_flt_bits_data), + .io_pc (io_storeComplete_bits), + .io_active (_slot_io_active), + .io_storeComplete (io_storeComplete_valid), + .io_fault_valid (_slot_io_fault_valid), + .io_fault_bits_write (io_fault_bits_write), + .io_fault_bits_addr (io_fault_bits_addr), + .io_fault_bits_epc (io_fault_bits_epc) + ); + assign io_req_0_ready = io_req_0_ready_0; + assign io_req_1_ready = io_req_1_ready_0; + assign io_req_2_ready = io_req_2_ready_0; + assign io_req_3_ready = io_req_3_ready_0; + assign io_ibus_valid = io_ibus_valid_0; + assign io_ibus_addr = addr; + assign io_dbus_valid = io_dbus_valid_0; + assign io_dbus_write = _slot_io_busReq_bits_req_write; + assign io_dbus_addr = addr; + assign io_dbus_wdata = _slot_io_busReq_bits_req_wdata; + assign io_dbus_wmask = _slot_io_busReq_bits_req_wmask; + assign io_flush_valid = flushCmd_valid; + assign io_flush_pcNext = flushCmd_bits_pcNext; + assign io_fault_valid = fireNewFault; + assign io_ebus_dbus_valid = io_ebus_dbus_valid_0; + assign io_ebus_dbus_write = _slot_io_busReq_bits_req_write; + assign io_ebus_dbus_addr = + {_slot_io_busReq_bits_req_rowAddr, _slot_io_busReq_bits_req_offset}; + assign io_ebus_dbus_wdata = _slot_io_busReq_bits_req_wdata; + assign io_ebus_dbus_wmask = _slot_io_busReq_bits_req_wmask; + assign io_queueCapacity = _rs_io_nSpace; + assign io_active = + (|_rs_io_nEnqueued) | _slot_io_active | flushCmd_valid | isFaulted | isFlushing; endmodule -module Bru_1( +module FaultManager( + input io_in_fault_0_csr, + io_in_fault_0_jal, + io_in_fault_0_jalr, + io_in_fault_0_bxx, + io_in_fault_0_undef, + io_in_fault_1_jal, + io_in_fault_1_jalr, + io_in_fault_1_bxx, + io_in_fault_2_jal, + io_in_fault_2_jalr, + io_in_fault_2_bxx, + io_in_fault_3_jal, + io_in_fault_3_jalr, + io_in_fault_3_bxx, + input [31:0] io_in_pc_0_pc, + io_in_pc_1_pc, + io_in_pc_2_pc, + io_in_pc_3_pc, + input io_in_memory_fault_valid, + io_in_memory_fault_bits_write, + input [31:0] io_in_memory_fault_bits_addr, + io_in_memory_fault_bits_epc, + io_in_undef_0_inst, + io_in_undef_1_inst, + io_in_undef_2_inst, + io_in_undef_3_inst, + io_in_jal_0_target, + io_in_jal_1_target, + io_in_jal_2_target, + io_in_jal_3_target, + io_in_jalr_0_target, + io_in_jalr_1_target, + io_in_jalr_2_target, + io_in_jalr_3_target, + input io_in_fetchFault_valid, + input [31:0] io_in_fetchFault_bits, + output io_out_valid, + output [31:0] io_out_bits_mepc, + io_out_bits_mtval, + io_out_bits_mcause, + output io_out_bits_decode +); + + wire faults_0 = + io_in_fault_0_csr | io_in_fault_0_jal | io_in_fault_0_jalr | io_in_fault_0_bxx + | io_in_fault_0_undef; + wire faults_1 = io_in_fault_1_jal | io_in_fault_1_jalr | io_in_fault_1_bxx; + wire faults_2 = io_in_fault_2_jal | io_in_fault_2_jalr | io_in_fault_2_bxx; + wire fault = + faults_0 | faults_1 | faults_2 | io_in_fault_3_jal | io_in_fault_3_jalr + | io_in_fault_3_bxx; + wire [1:0] first_fault = faults_0 ? 2'h0 : faults_1 ? 2'h1 : {1'h1, ~faults_2}; + wire [1:0] undef_fault_idx = io_in_fault_0_undef ? 2'h0 : 2'h3; + wire [1:0] csr_fault_idx = io_in_fault_0_csr ? 2'h0 : 2'h3; + wire [1:0] jal_fault_idx = + io_in_fault_0_jal ? 2'h0 : io_in_fault_1_jal ? 2'h1 : {1'h1, ~io_in_fault_2_jal}; + wire [1:0] jalr_fault_idx = + io_in_fault_0_jalr ? 2'h0 : io_in_fault_1_jalr ? 2'h1 : {1'h1, ~io_in_fault_2_jalr}; + wire load_fault = io_in_memory_fault_valid & ~io_in_memory_fault_bits_write; + wire store_fault = io_in_memory_fault_valid & io_in_memory_fault_bits_write; + wire [3:0][31:0] _GEN = + {{io_in_pc_3_pc}, {io_in_pc_2_pc}, {io_in_pc_1_pc}, {io_in_pc_0_pc}}; + wire _GEN_0 = load_fault | store_fault; + wire first_fault_is_csr = io_in_fault_0_csr & csr_fault_idx == first_fault; + wire first_fault_is_jal = + (io_in_fault_0_jal | io_in_fault_1_jal | io_in_fault_2_jal | io_in_fault_3_jal) + & jal_fault_idx == first_fault; + wire first_fault_is_jalr = + (io_in_fault_0_jalr | io_in_fault_1_jalr | io_in_fault_2_jalr | io_in_fault_3_jalr) + & jalr_fault_idx == first_fault; + wire first_fault_is_bxx = + (io_in_fault_0_bxx | io_in_fault_1_bxx | io_in_fault_2_bxx | io_in_fault_3_bxx) + & (io_in_fault_0_bxx + ? 2'h0 + : io_in_fault_1_bxx ? 2'h1 : {1'h1, ~io_in_fault_2_bxx}) == first_fault; + wire first_fault_is_undef = + io_in_fault_0_undef & undef_fault_idx == first_fault; + wire _GEN_1 = first_fault_is_jal | first_fault_is_jalr | first_fault_is_bxx; + wire [3:0][31:0] _GEN_2 = + {{io_in_jalr_3_target}, + {io_in_jalr_2_target}, + {io_in_jalr_1_target}, + {io_in_jalr_0_target}}; + wire [3:0][31:0] _GEN_3 = + {{io_in_undef_3_inst}, + {io_in_undef_2_inst}, + {io_in_undef_1_inst}, + {io_in_undef_0_inst}}; + wire [3:0][31:0] _GEN_4 = + {{io_in_jal_3_target}, + {io_in_jal_2_target}, + {io_in_jal_1_target}, + {io_in_jal_0_target}}; + assign io_out_valid = fault | io_in_fetchFault_valid | load_fault | store_fault; + assign io_out_bits_mepc = + _GEN_0 + ? io_in_memory_fault_bits_epc + : fault + ? _GEN[first_fault] + : io_in_fetchFault_valid ? io_in_fetchFault_bits : 32'h0; + assign io_out_bits_mtval = + _GEN_0 + ? io_in_memory_fault_bits_addr + : first_fault_is_csr + ? _GEN_3[csr_fault_idx] + : first_fault_is_jal + ? _GEN_4[jal_fault_idx] + : first_fault_is_jalr + ? {_GEN_2[jalr_fault_idx][31:1], 1'h0} + : first_fault_is_bxx | ~first_fault_is_undef + ? 32'h0 + : _GEN_3[undef_fault_idx]; + assign io_out_bits_mcause = + load_fault + ? 32'h5 + : store_fault + ? 32'h7 + : first_fault_is_csr + ? 32'h2 + : _GEN_1 + ? 32'h0 + : first_fault_is_undef ? 32'h2 : {31'h0, io_in_fetchFault_valid}; + assign io_out_bits_decode = first_fault_is_csr | _GEN_1 | first_fault_is_undef; +endmodule + +module CircularBufferMulti_2( input clock, reset, - io_req_valid, - io_req_bits_fwd, - input [3:0] io_req_bits_op, - input [31:0] io_req_bits_pc, - io_req_bits_target, - input [4:0] io_req_bits_link, - input io_rs1_valid, - input [31:0] io_rs1_data, - input io_rs2_valid, - input [31:0] io_rs2_data, - output io_rd_valid, - output [4:0] io_rd_bits_addr, - output [31:0] io_rd_bits_data, - output io_taken_valid, - output [31:0] io_taken_value, - input [31:0] io_target_data + input [4:0] io_enqValid, + input [31:0] io_enqData_0_addr, + input [6:0] io_enqData_0_idx, + input io_enqData_0_trap, + io_enqData_0_isControlFlow, + io_enqData_0_isBranch, + io_enqData_0_isVector, + io_enqData_0_resetsVstart, + io_enqData_0_linkOk, + io_enqData_0_isEcall, + io_enqData_0_isMpause, + io_enqData_0_isTile, + input [31:0] io_enqData_1_addr, + input [6:0] io_enqData_1_idx, + input io_enqData_1_trap, + io_enqData_1_isControlFlow, + io_enqData_1_isBranch, + io_enqData_1_isVector, + io_enqData_1_resetsVstart, + io_enqData_1_linkOk, + io_enqData_1_isEcall, + io_enqData_1_isMpause, + io_enqData_1_isTile, + input [31:0] io_enqData_2_addr, + input [6:0] io_enqData_2_idx, + input io_enqData_2_trap, + io_enqData_2_isControlFlow, + io_enqData_2_isBranch, + io_enqData_2_isVector, + io_enqData_2_resetsVstart, + io_enqData_2_linkOk, + io_enqData_2_isEcall, + io_enqData_2_isMpause, + io_enqData_2_isTile, + input [31:0] io_enqData_3_addr, + input [6:0] io_enqData_3_idx, + input io_enqData_3_trap, + io_enqData_3_isControlFlow, + io_enqData_3_isBranch, + io_enqData_3_isVector, + io_enqData_3_resetsVstart, + io_enqData_3_linkOk, + io_enqData_3_isEcall, + io_enqData_3_isMpause, + io_enqData_3_isTile, + input [31:0] io_enqData_4_addr, + input [6:0] io_enqData_4_idx, + input io_enqData_4_trap, + io_enqData_4_isControlFlow, + io_enqData_4_isBranch, + io_enqData_4_isVector, + io_enqData_4_resetsVstart, + io_enqData_4_linkOk, + io_enqData_4_isEcall, + io_enqData_4_isMpause, + io_enqData_4_isTile, + input [31:0] io_enqData_5_addr, + input [6:0] io_enqData_5_idx, + input io_enqData_5_trap, + io_enqData_5_isControlFlow, + io_enqData_5_isBranch, + io_enqData_5_isVector, + io_enqData_5_resetsVstart, + io_enqData_5_linkOk, + io_enqData_5_isEcall, + io_enqData_5_isMpause, + io_enqData_5_isTile, + input [31:0] io_enqData_6_addr, + input [6:0] io_enqData_6_idx, + input io_enqData_6_trap, + io_enqData_6_isControlFlow, + io_enqData_6_isBranch, + io_enqData_6_isVector, + io_enqData_6_resetsVstart, + io_enqData_6_linkOk, + io_enqData_6_isEcall, + io_enqData_6_isMpause, + io_enqData_6_isTile, + input [31:0] io_enqData_7_addr, + input [6:0] io_enqData_7_idx, + input io_enqData_7_trap, + io_enqData_7_isControlFlow, + io_enqData_7_isBranch, + io_enqData_7_isVector, + io_enqData_7_resetsVstart, + io_enqData_7_linkOk, + io_enqData_7_isEcall, + io_enqData_7_isMpause, + io_enqData_7_isTile, + input [31:0] io_enqData_8_addr, + input [6:0] io_enqData_8_idx, + input io_enqData_8_trap, + io_enqData_8_isControlFlow, + io_enqData_8_isBranch, + io_enqData_8_isVector, + io_enqData_8_resetsVstart, + io_enqData_8_linkOk, + io_enqData_8_isEcall, + io_enqData_8_isMpause, + io_enqData_8_isTile, + input [31:0] io_enqData_9_addr, + input [6:0] io_enqData_9_idx, + input io_enqData_9_trap, + io_enqData_9_isControlFlow, + io_enqData_9_isBranch, + io_enqData_9_isVector, + io_enqData_9_resetsVstart, + io_enqData_9_linkOk, + io_enqData_9_isEcall, + io_enqData_9_isMpause, + io_enqData_9_isTile, + input [31:0] io_enqData_10_addr, + input [6:0] io_enqData_10_idx, + input io_enqData_10_trap, + io_enqData_10_isControlFlow, + io_enqData_10_isBranch, + io_enqData_10_isVector, + io_enqData_10_resetsVstart, + io_enqData_10_linkOk, + io_enqData_10_isEcall, + io_enqData_10_isMpause, + io_enqData_10_isTile, + input [31:0] io_enqData_11_addr, + input [6:0] io_enqData_11_idx, + input io_enqData_11_trap, + io_enqData_11_isControlFlow, + io_enqData_11_isBranch, + io_enqData_11_isVector, + io_enqData_11_resetsVstart, + io_enqData_11_linkOk, + io_enqData_11_isEcall, + io_enqData_11_isMpause, + io_enqData_11_isTile, + input [31:0] io_enqData_12_addr, + input [6:0] io_enqData_12_idx, + input io_enqData_12_trap, + io_enqData_12_isControlFlow, + io_enqData_12_isBranch, + io_enqData_12_isVector, + io_enqData_12_resetsVstart, + io_enqData_12_linkOk, + io_enqData_12_isEcall, + io_enqData_12_isMpause, + io_enqData_12_isTile, + input [31:0] io_enqData_13_addr, + input [6:0] io_enqData_13_idx, + input io_enqData_13_trap, + io_enqData_13_isControlFlow, + io_enqData_13_isBranch, + io_enqData_13_isVector, + io_enqData_13_resetsVstart, + io_enqData_13_linkOk, + io_enqData_13_isEcall, + io_enqData_13_isMpause, + io_enqData_13_isTile, + input [31:0] io_enqData_14_addr, + input [6:0] io_enqData_14_idx, + input io_enqData_14_trap, + io_enqData_14_isControlFlow, + io_enqData_14_isBranch, + io_enqData_14_isVector, + io_enqData_14_resetsVstart, + io_enqData_14_linkOk, + io_enqData_14_isEcall, + io_enqData_14_isMpause, + io_enqData_14_isTile, + input [31:0] io_enqData_15_addr, + input [6:0] io_enqData_15_idx, + input io_enqData_15_trap, + io_enqData_15_isControlFlow, + io_enqData_15_isBranch, + io_enqData_15_isVector, + io_enqData_15_resetsVstart, + io_enqData_15_linkOk, + io_enqData_15_isEcall, + io_enqData_15_isMpause, + io_enqData_15_isTile, + output [4:0] io_nEnqueued, + io_nSpace, + output [31:0] io_dataOut_0_addr, + output [6:0] io_dataOut_0_idx, + output io_dataOut_0_trap, + io_dataOut_0_isControlFlow, + io_dataOut_0_isBranch, + io_dataOut_0_isVector, + io_dataOut_0_resetsVstart, + io_dataOut_0_linkOk, + io_dataOut_0_isEcall, + io_dataOut_0_isMpause, + io_dataOut_0_isTile, + output [31:0] io_dataOut_1_addr, + output [6:0] io_dataOut_1_idx, + output io_dataOut_1_trap, + io_dataOut_1_isControlFlow, + io_dataOut_1_isBranch, + io_dataOut_1_isVector, + io_dataOut_1_resetsVstart, + io_dataOut_1_linkOk, + io_dataOut_1_isEcall, + io_dataOut_1_isMpause, + io_dataOut_1_isTile, + output [31:0] io_dataOut_2_addr, + output [6:0] io_dataOut_2_idx, + output io_dataOut_2_trap, + io_dataOut_2_isControlFlow, + io_dataOut_2_isBranch, + io_dataOut_2_isVector, + io_dataOut_2_resetsVstart, + io_dataOut_2_linkOk, + io_dataOut_2_isEcall, + io_dataOut_2_isMpause, + io_dataOut_2_isTile, + output [31:0] io_dataOut_3_addr, + output [6:0] io_dataOut_3_idx, + output io_dataOut_3_trap, + io_dataOut_3_isControlFlow, + io_dataOut_3_isBranch, + io_dataOut_3_isVector, + io_dataOut_3_resetsVstart, + io_dataOut_3_linkOk, + io_dataOut_3_isEcall, + io_dataOut_3_isMpause, + io_dataOut_3_isTile, + output [31:0] io_dataOut_4_addr, + output [6:0] io_dataOut_4_idx, + output io_dataOut_4_trap, + io_dataOut_4_isControlFlow, + io_dataOut_4_isBranch, + io_dataOut_4_isVector, + io_dataOut_4_resetsVstart, + io_dataOut_4_linkOk, + io_dataOut_4_isEcall, + io_dataOut_4_isMpause, + io_dataOut_4_isTile, + output [31:0] io_dataOut_5_addr, + output [6:0] io_dataOut_5_idx, + output io_dataOut_5_trap, + io_dataOut_5_isControlFlow, + io_dataOut_5_isBranch, + io_dataOut_5_isVector, + io_dataOut_5_resetsVstart, + io_dataOut_5_linkOk, + io_dataOut_5_isEcall, + io_dataOut_5_isMpause, + io_dataOut_5_isTile, + output [31:0] io_dataOut_6_addr, + output [6:0] io_dataOut_6_idx, + output io_dataOut_6_trap, + io_dataOut_6_isControlFlow, + io_dataOut_6_isBranch, + io_dataOut_6_isVector, + io_dataOut_6_resetsVstart, + io_dataOut_6_linkOk, + io_dataOut_6_isEcall, + io_dataOut_6_isMpause, + io_dataOut_6_isTile, + output [31:0] io_dataOut_7_addr, + output [6:0] io_dataOut_7_idx, + output io_dataOut_7_trap, + io_dataOut_7_isControlFlow, + io_dataOut_7_isBranch, + io_dataOut_7_isVector, + io_dataOut_7_resetsVstart, + io_dataOut_7_linkOk, + io_dataOut_7_isEcall, + io_dataOut_7_isMpause, + io_dataOut_7_isTile, + output [31:0] io_dataOut_8_addr, + output [6:0] io_dataOut_8_idx, + output io_dataOut_8_trap, + io_dataOut_8_isControlFlow, + io_dataOut_8_isBranch, + io_dataOut_8_isVector, + io_dataOut_8_resetsVstart, + io_dataOut_8_linkOk, + io_dataOut_8_isEcall, + io_dataOut_8_isMpause, + io_dataOut_8_isTile, + output [31:0] io_dataOut_9_addr, + output [6:0] io_dataOut_9_idx, + output io_dataOut_9_trap, + io_dataOut_9_isControlFlow, + io_dataOut_9_isBranch, + io_dataOut_9_isVector, + io_dataOut_9_resetsVstart, + io_dataOut_9_linkOk, + io_dataOut_9_isEcall, + io_dataOut_9_isMpause, + io_dataOut_9_isTile, + output [31:0] io_dataOut_10_addr, + output [6:0] io_dataOut_10_idx, + output io_dataOut_10_trap, + io_dataOut_10_isControlFlow, + io_dataOut_10_isBranch, + io_dataOut_10_isVector, + io_dataOut_10_resetsVstart, + io_dataOut_10_linkOk, + io_dataOut_10_isEcall, + io_dataOut_10_isMpause, + io_dataOut_10_isTile, + output [31:0] io_dataOut_11_addr, + output [6:0] io_dataOut_11_idx, + output io_dataOut_11_trap, + io_dataOut_11_isControlFlow, + io_dataOut_11_isBranch, + io_dataOut_11_isVector, + io_dataOut_11_resetsVstart, + io_dataOut_11_linkOk, + io_dataOut_11_isEcall, + io_dataOut_11_isMpause, + io_dataOut_11_isTile, + output [31:0] io_dataOut_12_addr, + output [6:0] io_dataOut_12_idx, + output io_dataOut_12_trap, + io_dataOut_12_isControlFlow, + io_dataOut_12_isBranch, + io_dataOut_12_isVector, + io_dataOut_12_resetsVstart, + io_dataOut_12_linkOk, + io_dataOut_12_isEcall, + io_dataOut_12_isMpause, + io_dataOut_12_isTile, + output [31:0] io_dataOut_13_addr, + output [6:0] io_dataOut_13_idx, + output io_dataOut_13_trap, + io_dataOut_13_isControlFlow, + io_dataOut_13_isBranch, + io_dataOut_13_isVector, + io_dataOut_13_resetsVstart, + io_dataOut_13_linkOk, + io_dataOut_13_isEcall, + io_dataOut_13_isMpause, + io_dataOut_13_isTile, + output [31:0] io_dataOut_14_addr, + output [6:0] io_dataOut_14_idx, + output io_dataOut_14_trap, + io_dataOut_14_isControlFlow, + io_dataOut_14_isBranch, + io_dataOut_14_isVector, + io_dataOut_14_resetsVstart, + io_dataOut_14_linkOk, + io_dataOut_14_isEcall, + io_dataOut_14_isMpause, + io_dataOut_14_isTile, + output [31:0] io_dataOut_15_addr, + output [6:0] io_dataOut_15_idx, + output io_dataOut_15_trap, + io_dataOut_15_isControlFlow, + io_dataOut_15_isBranch, + io_dataOut_15_isVector, + io_dataOut_15_resetsVstart, + io_dataOut_15_linkOk, + io_dataOut_15_isEcall, + io_dataOut_15_isMpause, + io_dataOut_15_isTile, + input [4:0] io_deqReady, + input io_flush ); - reg stateReg_valid; - reg stateReg_bits_fwd; - reg [3:0] stateReg_bits_op; - reg [31:0] stateReg_bits_target; - reg stateReg_bits_linkValid; - reg [4:0] stateReg_bits_linkAddr; - reg [31:0] stateReg_bits_linkData; - wire _ignore_T_2 = stateReg_bits_op == 4'h8; - wire _ignore_T_3 = stateReg_bits_op == 4'h9; - wire _ignore_T_4 = stateReg_bits_op == 4'hA; - wire _ignore_T_5 = stateReg_bits_op == 4'hB; - wire _ignore_T_6 = stateReg_bits_op == 4'hC; - wire [31:0] nextState_linkData = io_req_bits_pc + 32'h4; - wire _nextState_target_T = io_req_bits_op == 4'h1; + reg [31:0] buffer_0_addr; + reg [6:0] buffer_0_idx; + reg buffer_0_trap; + reg buffer_0_isControlFlow; + reg buffer_0_isBranch; + reg buffer_0_isVector; + reg buffer_0_resetsVstart; + reg buffer_0_linkOk; + reg buffer_0_isEcall; + reg buffer_0_isMpause; + reg buffer_0_isTile; + reg [31:0] buffer_1_addr; + reg [6:0] buffer_1_idx; + reg buffer_1_trap; + reg buffer_1_isControlFlow; + reg buffer_1_isBranch; + reg buffer_1_isVector; + reg buffer_1_resetsVstart; + reg buffer_1_linkOk; + reg buffer_1_isEcall; + reg buffer_1_isMpause; + reg buffer_1_isTile; + reg [31:0] buffer_2_addr; + reg [6:0] buffer_2_idx; + reg buffer_2_trap; + reg buffer_2_isControlFlow; + reg buffer_2_isBranch; + reg buffer_2_isVector; + reg buffer_2_resetsVstart; + reg buffer_2_linkOk; + reg buffer_2_isEcall; + reg buffer_2_isMpause; + reg buffer_2_isTile; + reg [31:0] buffer_3_addr; + reg [6:0] buffer_3_idx; + reg buffer_3_trap; + reg buffer_3_isControlFlow; + reg buffer_3_isBranch; + reg buffer_3_isVector; + reg buffer_3_resetsVstart; + reg buffer_3_linkOk; + reg buffer_3_isEcall; + reg buffer_3_isMpause; + reg buffer_3_isTile; + reg [31:0] buffer_4_addr; + reg [6:0] buffer_4_idx; + reg buffer_4_trap; + reg buffer_4_isControlFlow; + reg buffer_4_isBranch; + reg buffer_4_isVector; + reg buffer_4_resetsVstart; + reg buffer_4_linkOk; + reg buffer_4_isEcall; + reg buffer_4_isMpause; + reg buffer_4_isTile; + reg [31:0] buffer_5_addr; + reg [6:0] buffer_5_idx; + reg buffer_5_trap; + reg buffer_5_isControlFlow; + reg buffer_5_isBranch; + reg buffer_5_isVector; + reg buffer_5_resetsVstart; + reg buffer_5_linkOk; + reg buffer_5_isEcall; + reg buffer_5_isMpause; + reg buffer_5_isTile; + reg [31:0] buffer_6_addr; + reg [6:0] buffer_6_idx; + reg buffer_6_trap; + reg buffer_6_isControlFlow; + reg buffer_6_isBranch; + reg buffer_6_isVector; + reg buffer_6_resetsVstart; + reg buffer_6_linkOk; + reg buffer_6_isEcall; + reg buffer_6_isMpause; + reg buffer_6_isTile; + reg [31:0] buffer_7_addr; + reg [6:0] buffer_7_idx; + reg buffer_7_trap; + reg buffer_7_isControlFlow; + reg buffer_7_isBranch; + reg buffer_7_isVector; + reg buffer_7_resetsVstart; + reg buffer_7_linkOk; + reg buffer_7_isEcall; + reg buffer_7_isMpause; + reg buffer_7_isTile; + reg [31:0] buffer_8_addr; + reg [6:0] buffer_8_idx; + reg buffer_8_trap; + reg buffer_8_isControlFlow; + reg buffer_8_isBranch; + reg buffer_8_isVector; + reg buffer_8_resetsVstart; + reg buffer_8_linkOk; + reg buffer_8_isEcall; + reg buffer_8_isMpause; + reg buffer_8_isTile; + reg [31:0] buffer_9_addr; + reg [6:0] buffer_9_idx; + reg buffer_9_trap; + reg buffer_9_isControlFlow; + reg buffer_9_isBranch; + reg buffer_9_isVector; + reg buffer_9_resetsVstart; + reg buffer_9_linkOk; + reg buffer_9_isEcall; + reg buffer_9_isMpause; + reg buffer_9_isTile; + reg [31:0] buffer_10_addr; + reg [6:0] buffer_10_idx; + reg buffer_10_trap; + reg buffer_10_isControlFlow; + reg buffer_10_isBranch; + reg buffer_10_isVector; + reg buffer_10_resetsVstart; + reg buffer_10_linkOk; + reg buffer_10_isEcall; + reg buffer_10_isMpause; + reg buffer_10_isTile; + reg [31:0] buffer_11_addr; + reg [6:0] buffer_11_idx; + reg buffer_11_trap; + reg buffer_11_isControlFlow; + reg buffer_11_isBranch; + reg buffer_11_isVector; + reg buffer_11_resetsVstart; + reg buffer_11_linkOk; + reg buffer_11_isEcall; + reg buffer_11_isMpause; + reg buffer_11_isTile; + reg [31:0] buffer_12_addr; + reg [6:0] buffer_12_idx; + reg buffer_12_trap; + reg buffer_12_isControlFlow; + reg buffer_12_isBranch; + reg buffer_12_isVector; + reg buffer_12_resetsVstart; + reg buffer_12_linkOk; + reg buffer_12_isEcall; + reg buffer_12_isMpause; + reg buffer_12_isTile; + reg [31:0] buffer_13_addr; + reg [6:0] buffer_13_idx; + reg buffer_13_trap; + reg buffer_13_isControlFlow; + reg buffer_13_isBranch; + reg buffer_13_isVector; + reg buffer_13_resetsVstart; + reg buffer_13_linkOk; + reg buffer_13_isEcall; + reg buffer_13_isMpause; + reg buffer_13_isTile; + reg [31:0] buffer_14_addr; + reg [6:0] buffer_14_idx; + reg buffer_14_trap; + reg buffer_14_isControlFlow; + reg buffer_14_isBranch; + reg buffer_14_isVector; + reg buffer_14_resetsVstart; + reg buffer_14_linkOk; + reg buffer_14_isEcall; + reg buffer_14_isMpause; + reg buffer_14_isTile; + reg [31:0] buffer_15_addr; + reg [6:0] buffer_15_idx; + reg buffer_15_trap; + reg buffer_15_isControlFlow; + reg buffer_15_isBranch; + reg buffer_15_isVector; + reg buffer_15_resetsVstart; + reg buffer_15_linkOk; + reg buffer_15_isEcall; + reg buffer_15_isMpause; + reg buffer_15_isTile; + reg [3:0] enqPtr; + reg [3:0] deqPtr; + reg [4:0] nEnqueued; + wire [31:0] _shifted_T_13_addr = deqPtr[3] ? buffer_12_addr : buffer_4_addr; + wire [6:0] _shifted_T_13_idx = deqPtr[3] ? buffer_12_idx : buffer_4_idx; + wire _shifted_T_13_trap = deqPtr[3] ? buffer_12_trap : buffer_4_trap; + wire _shifted_T_13_isControlFlow = + deqPtr[3] ? buffer_12_isControlFlow : buffer_4_isControlFlow; + wire _shifted_T_13_isBranch = deqPtr[3] ? buffer_12_isBranch : buffer_4_isBranch; + wire _shifted_T_13_isVector = deqPtr[3] ? buffer_12_isVector : buffer_4_isVector; + wire _shifted_T_13_resetsVstart = + deqPtr[3] ? buffer_12_resetsVstart : buffer_4_resetsVstart; + wire _shifted_T_13_linkOk = deqPtr[3] ? buffer_12_linkOk : buffer_4_linkOk; + wire _shifted_T_13_isEcall = deqPtr[3] ? buffer_12_isEcall : buffer_4_isEcall; + wire _shifted_T_13_isMpause = deqPtr[3] ? buffer_12_isMpause : buffer_4_isMpause; + wire _shifted_T_13_isTile = deqPtr[3] ? buffer_12_isTile : buffer_4_isTile; + wire [31:0] _shifted_T_16_addr = deqPtr[3] ? buffer_13_addr : buffer_5_addr; + wire [6:0] _shifted_T_16_idx = deqPtr[3] ? buffer_13_idx : buffer_5_idx; + wire _shifted_T_16_trap = deqPtr[3] ? buffer_13_trap : buffer_5_trap; + wire _shifted_T_16_isControlFlow = + deqPtr[3] ? buffer_13_isControlFlow : buffer_5_isControlFlow; + wire _shifted_T_16_isBranch = deqPtr[3] ? buffer_13_isBranch : buffer_5_isBranch; + wire _shifted_T_16_isVector = deqPtr[3] ? buffer_13_isVector : buffer_5_isVector; + wire _shifted_T_16_resetsVstart = + deqPtr[3] ? buffer_13_resetsVstart : buffer_5_resetsVstart; + wire _shifted_T_16_linkOk = deqPtr[3] ? buffer_13_linkOk : buffer_5_linkOk; + wire _shifted_T_16_isEcall = deqPtr[3] ? buffer_13_isEcall : buffer_5_isEcall; + wire _shifted_T_16_isMpause = deqPtr[3] ? buffer_13_isMpause : buffer_5_isMpause; + wire _shifted_T_16_isTile = deqPtr[3] ? buffer_13_isTile : buffer_5_isTile; + wire [31:0] _shifted_T_19_addr = deqPtr[3] ? buffer_14_addr : buffer_6_addr; + wire [6:0] _shifted_T_19_idx = deqPtr[3] ? buffer_14_idx : buffer_6_idx; + wire _shifted_T_19_trap = deqPtr[3] ? buffer_14_trap : buffer_6_trap; + wire _shifted_T_19_isControlFlow = + deqPtr[3] ? buffer_14_isControlFlow : buffer_6_isControlFlow; + wire _shifted_T_19_isBranch = deqPtr[3] ? buffer_14_isBranch : buffer_6_isBranch; + wire _shifted_T_19_isVector = deqPtr[3] ? buffer_14_isVector : buffer_6_isVector; + wire _shifted_T_19_resetsVstart = + deqPtr[3] ? buffer_14_resetsVstart : buffer_6_resetsVstart; + wire _shifted_T_19_linkOk = deqPtr[3] ? buffer_14_linkOk : buffer_6_linkOk; + wire _shifted_T_19_isEcall = deqPtr[3] ? buffer_14_isEcall : buffer_6_isEcall; + wire _shifted_T_19_isMpause = deqPtr[3] ? buffer_14_isMpause : buffer_6_isMpause; + wire _shifted_T_19_isTile = deqPtr[3] ? buffer_14_isTile : buffer_6_isTile; + wire [31:0] _shifted_WIRE_2_addr = + deqPtr[2] ? _shifted_T_19_addr : deqPtr[3] ? buffer_10_addr : buffer_2_addr; + wire [6:0] _shifted_WIRE_2_idx = + deqPtr[2] ? _shifted_T_19_idx : deqPtr[3] ? buffer_10_idx : buffer_2_idx; + wire _shifted_WIRE_2_trap = + deqPtr[2] ? _shifted_T_19_trap : deqPtr[3] ? buffer_10_trap : buffer_2_trap; + wire _shifted_WIRE_2_isControlFlow = + deqPtr[2] + ? _shifted_T_19_isControlFlow + : deqPtr[3] ? buffer_10_isControlFlow : buffer_2_isControlFlow; + wire _shifted_WIRE_2_isBranch = + deqPtr[2] + ? _shifted_T_19_isBranch + : deqPtr[3] ? buffer_10_isBranch : buffer_2_isBranch; + wire _shifted_WIRE_2_isVector = + deqPtr[2] + ? _shifted_T_19_isVector + : deqPtr[3] ? buffer_10_isVector : buffer_2_isVector; + wire _shifted_WIRE_2_resetsVstart = + deqPtr[2] + ? _shifted_T_19_resetsVstart + : deqPtr[3] ? buffer_10_resetsVstart : buffer_2_resetsVstart; + wire _shifted_WIRE_2_linkOk = + deqPtr[2] ? _shifted_T_19_linkOk : deqPtr[3] ? buffer_10_linkOk : buffer_2_linkOk; + wire _shifted_WIRE_2_isEcall = + deqPtr[2] ? _shifted_T_19_isEcall : deqPtr[3] ? buffer_10_isEcall : buffer_2_isEcall; + wire _shifted_WIRE_2_isMpause = + deqPtr[2] + ? _shifted_T_19_isMpause + : deqPtr[3] ? buffer_10_isMpause : buffer_2_isMpause; + wire _shifted_WIRE_2_isTile = + deqPtr[2] ? _shifted_T_19_isTile : deqPtr[3] ? buffer_10_isTile : buffer_2_isTile; + wire [31:0] _shifted_T_22_addr = deqPtr[3] ? buffer_15_addr : buffer_7_addr; + wire [6:0] _shifted_T_22_idx = deqPtr[3] ? buffer_15_idx : buffer_7_idx; + wire _shifted_T_22_trap = deqPtr[3] ? buffer_15_trap : buffer_7_trap; + wire _shifted_T_22_isControlFlow = + deqPtr[3] ? buffer_15_isControlFlow : buffer_7_isControlFlow; + wire _shifted_T_22_isBranch = deqPtr[3] ? buffer_15_isBranch : buffer_7_isBranch; + wire _shifted_T_22_isVector = deqPtr[3] ? buffer_15_isVector : buffer_7_isVector; + wire _shifted_T_22_resetsVstart = + deqPtr[3] ? buffer_15_resetsVstart : buffer_7_resetsVstart; + wire _shifted_T_22_linkOk = deqPtr[3] ? buffer_15_linkOk : buffer_7_linkOk; + wire _shifted_T_22_isEcall = deqPtr[3] ? buffer_15_isEcall : buffer_7_isEcall; + wire _shifted_T_22_isMpause = deqPtr[3] ? buffer_15_isMpause : buffer_7_isMpause; + wire _shifted_T_22_isTile = deqPtr[3] ? buffer_15_isTile : buffer_7_isTile; + wire [31:0] _shifted_WIRE_3_addr = + deqPtr[2] ? _shifted_T_22_addr : deqPtr[3] ? buffer_11_addr : buffer_3_addr; + wire [6:0] _shifted_WIRE_3_idx = + deqPtr[2] ? _shifted_T_22_idx : deqPtr[3] ? buffer_11_idx : buffer_3_idx; + wire _shifted_WIRE_3_trap = + deqPtr[2] ? _shifted_T_22_trap : deqPtr[3] ? buffer_11_trap : buffer_3_trap; + wire _shifted_WIRE_3_isControlFlow = + deqPtr[2] + ? _shifted_T_22_isControlFlow + : deqPtr[3] ? buffer_11_isControlFlow : buffer_3_isControlFlow; + wire _shifted_WIRE_3_isBranch = + deqPtr[2] + ? _shifted_T_22_isBranch + : deqPtr[3] ? buffer_11_isBranch : buffer_3_isBranch; + wire _shifted_WIRE_3_isVector = + deqPtr[2] + ? _shifted_T_22_isVector + : deqPtr[3] ? buffer_11_isVector : buffer_3_isVector; + wire _shifted_WIRE_3_resetsVstart = + deqPtr[2] + ? _shifted_T_22_resetsVstart + : deqPtr[3] ? buffer_11_resetsVstart : buffer_3_resetsVstart; + wire _shifted_WIRE_3_linkOk = + deqPtr[2] ? _shifted_T_22_linkOk : deqPtr[3] ? buffer_11_linkOk : buffer_3_linkOk; + wire _shifted_WIRE_3_isEcall = + deqPtr[2] ? _shifted_T_22_isEcall : deqPtr[3] ? buffer_11_isEcall : buffer_3_isEcall; + wire _shifted_WIRE_3_isMpause = + deqPtr[2] + ? _shifted_T_22_isMpause + : deqPtr[3] ? buffer_11_isMpause : buffer_3_isMpause; + wire _shifted_WIRE_3_isTile = + deqPtr[2] ? _shifted_T_22_isTile : deqPtr[3] ? buffer_11_isTile : buffer_3_isTile; + wire [31:0] _shifted_T_25_addr = deqPtr[3] ? buffer_0_addr : buffer_8_addr; + wire [6:0] _shifted_T_25_idx = deqPtr[3] ? buffer_0_idx : buffer_8_idx; + wire _shifted_T_25_trap = deqPtr[3] ? buffer_0_trap : buffer_8_trap; + wire _shifted_T_25_isControlFlow = + deqPtr[3] ? buffer_0_isControlFlow : buffer_8_isControlFlow; + wire _shifted_T_25_isBranch = deqPtr[3] ? buffer_0_isBranch : buffer_8_isBranch; + wire _shifted_T_25_isVector = deqPtr[3] ? buffer_0_isVector : buffer_8_isVector; + wire _shifted_T_25_resetsVstart = + deqPtr[3] ? buffer_0_resetsVstart : buffer_8_resetsVstart; + wire _shifted_T_25_linkOk = deqPtr[3] ? buffer_0_linkOk : buffer_8_linkOk; + wire _shifted_T_25_isEcall = deqPtr[3] ? buffer_0_isEcall : buffer_8_isEcall; + wire _shifted_T_25_isMpause = deqPtr[3] ? buffer_0_isMpause : buffer_8_isMpause; + wire _shifted_T_25_isTile = deqPtr[3] ? buffer_0_isTile : buffer_8_isTile; + wire [31:0] _shifted_WIRE_4_addr = deqPtr[2] ? _shifted_T_25_addr : _shifted_T_13_addr; + wire [6:0] _shifted_WIRE_4_idx = deqPtr[2] ? _shifted_T_25_idx : _shifted_T_13_idx; + wire _shifted_WIRE_4_trap = deqPtr[2] ? _shifted_T_25_trap : _shifted_T_13_trap; + wire _shifted_WIRE_4_isControlFlow = + deqPtr[2] ? _shifted_T_25_isControlFlow : _shifted_T_13_isControlFlow; + wire _shifted_WIRE_4_isBranch = + deqPtr[2] ? _shifted_T_25_isBranch : _shifted_T_13_isBranch; + wire _shifted_WIRE_4_isVector = + deqPtr[2] ? _shifted_T_25_isVector : _shifted_T_13_isVector; + wire _shifted_WIRE_4_resetsVstart = + deqPtr[2] ? _shifted_T_25_resetsVstart : _shifted_T_13_resetsVstart; + wire _shifted_WIRE_4_linkOk = + deqPtr[2] ? _shifted_T_25_linkOk : _shifted_T_13_linkOk; + wire _shifted_WIRE_4_isEcall = + deqPtr[2] ? _shifted_T_25_isEcall : _shifted_T_13_isEcall; + wire _shifted_WIRE_4_isMpause = + deqPtr[2] ? _shifted_T_25_isMpause : _shifted_T_13_isMpause; + wire _shifted_WIRE_4_isTile = + deqPtr[2] ? _shifted_T_25_isTile : _shifted_T_13_isTile; + wire [31:0] _shifted_T_28_addr = deqPtr[3] ? buffer_1_addr : buffer_9_addr; + wire [6:0] _shifted_T_28_idx = deqPtr[3] ? buffer_1_idx : buffer_9_idx; + wire _shifted_T_28_trap = deqPtr[3] ? buffer_1_trap : buffer_9_trap; + wire _shifted_T_28_isControlFlow = + deqPtr[3] ? buffer_1_isControlFlow : buffer_9_isControlFlow; + wire _shifted_T_28_isBranch = deqPtr[3] ? buffer_1_isBranch : buffer_9_isBranch; + wire _shifted_T_28_isVector = deqPtr[3] ? buffer_1_isVector : buffer_9_isVector; + wire _shifted_T_28_resetsVstart = + deqPtr[3] ? buffer_1_resetsVstart : buffer_9_resetsVstart; + wire _shifted_T_28_linkOk = deqPtr[3] ? buffer_1_linkOk : buffer_9_linkOk; + wire _shifted_T_28_isEcall = deqPtr[3] ? buffer_1_isEcall : buffer_9_isEcall; + wire _shifted_T_28_isMpause = deqPtr[3] ? buffer_1_isMpause : buffer_9_isMpause; + wire _shifted_T_28_isTile = deqPtr[3] ? buffer_1_isTile : buffer_9_isTile; + wire [31:0] _shifted_WIRE_5_addr = deqPtr[2] ? _shifted_T_28_addr : _shifted_T_16_addr; + wire [6:0] _shifted_WIRE_5_idx = deqPtr[2] ? _shifted_T_28_idx : _shifted_T_16_idx; + wire _shifted_WIRE_5_trap = deqPtr[2] ? _shifted_T_28_trap : _shifted_T_16_trap; + wire _shifted_WIRE_5_isControlFlow = + deqPtr[2] ? _shifted_T_28_isControlFlow : _shifted_T_16_isControlFlow; + wire _shifted_WIRE_5_isBranch = + deqPtr[2] ? _shifted_T_28_isBranch : _shifted_T_16_isBranch; + wire _shifted_WIRE_5_isVector = + deqPtr[2] ? _shifted_T_28_isVector : _shifted_T_16_isVector; + wire _shifted_WIRE_5_resetsVstart = + deqPtr[2] ? _shifted_T_28_resetsVstart : _shifted_T_16_resetsVstart; + wire _shifted_WIRE_5_linkOk = + deqPtr[2] ? _shifted_T_28_linkOk : _shifted_T_16_linkOk; + wire _shifted_WIRE_5_isEcall = + deqPtr[2] ? _shifted_T_28_isEcall : _shifted_T_16_isEcall; + wire _shifted_WIRE_5_isMpause = + deqPtr[2] ? _shifted_T_28_isMpause : _shifted_T_16_isMpause; + wire _shifted_WIRE_5_isTile = + deqPtr[2] ? _shifted_T_28_isTile : _shifted_T_16_isTile; + wire [31:0] _shifted_T_31_addr = deqPtr[3] ? buffer_2_addr : buffer_10_addr; + wire [6:0] _shifted_T_31_idx = deqPtr[3] ? buffer_2_idx : buffer_10_idx; + wire _shifted_T_31_trap = deqPtr[3] ? buffer_2_trap : buffer_10_trap; + wire _shifted_T_31_isControlFlow = + deqPtr[3] ? buffer_2_isControlFlow : buffer_10_isControlFlow; + wire _shifted_T_31_isBranch = deqPtr[3] ? buffer_2_isBranch : buffer_10_isBranch; + wire _shifted_T_31_isVector = deqPtr[3] ? buffer_2_isVector : buffer_10_isVector; + wire _shifted_T_31_resetsVstart = + deqPtr[3] ? buffer_2_resetsVstart : buffer_10_resetsVstart; + wire _shifted_T_31_linkOk = deqPtr[3] ? buffer_2_linkOk : buffer_10_linkOk; + wire _shifted_T_31_isEcall = deqPtr[3] ? buffer_2_isEcall : buffer_10_isEcall; + wire _shifted_T_31_isMpause = deqPtr[3] ? buffer_2_isMpause : buffer_10_isMpause; + wire _shifted_T_31_isTile = deqPtr[3] ? buffer_2_isTile : buffer_10_isTile; + wire [31:0] _shifted_WIRE_6_addr = deqPtr[2] ? _shifted_T_31_addr : _shifted_T_19_addr; + wire [6:0] _shifted_WIRE_6_idx = deqPtr[2] ? _shifted_T_31_idx : _shifted_T_19_idx; + wire _shifted_WIRE_6_trap = deqPtr[2] ? _shifted_T_31_trap : _shifted_T_19_trap; + wire _shifted_WIRE_6_isControlFlow = + deqPtr[2] ? _shifted_T_31_isControlFlow : _shifted_T_19_isControlFlow; + wire _shifted_WIRE_6_isBranch = + deqPtr[2] ? _shifted_T_31_isBranch : _shifted_T_19_isBranch; + wire _shifted_WIRE_6_isVector = + deqPtr[2] ? _shifted_T_31_isVector : _shifted_T_19_isVector; + wire _shifted_WIRE_6_resetsVstart = + deqPtr[2] ? _shifted_T_31_resetsVstart : _shifted_T_19_resetsVstart; + wire _shifted_WIRE_6_linkOk = + deqPtr[2] ? _shifted_T_31_linkOk : _shifted_T_19_linkOk; + wire _shifted_WIRE_6_isEcall = + deqPtr[2] ? _shifted_T_31_isEcall : _shifted_T_19_isEcall; + wire _shifted_WIRE_6_isMpause = + deqPtr[2] ? _shifted_T_31_isMpause : _shifted_T_19_isMpause; + wire _shifted_WIRE_6_isTile = + deqPtr[2] ? _shifted_T_31_isTile : _shifted_T_19_isTile; + wire [31:0] _shifted_T_34_addr = deqPtr[3] ? buffer_3_addr : buffer_11_addr; + wire [6:0] _shifted_T_34_idx = deqPtr[3] ? buffer_3_idx : buffer_11_idx; + wire _shifted_T_34_trap = deqPtr[3] ? buffer_3_trap : buffer_11_trap; + wire _shifted_T_34_isControlFlow = + deqPtr[3] ? buffer_3_isControlFlow : buffer_11_isControlFlow; + wire _shifted_T_34_isBranch = deqPtr[3] ? buffer_3_isBranch : buffer_11_isBranch; + wire _shifted_T_34_isVector = deqPtr[3] ? buffer_3_isVector : buffer_11_isVector; + wire _shifted_T_34_resetsVstart = + deqPtr[3] ? buffer_3_resetsVstart : buffer_11_resetsVstart; + wire _shifted_T_34_linkOk = deqPtr[3] ? buffer_3_linkOk : buffer_11_linkOk; + wire _shifted_T_34_isEcall = deqPtr[3] ? buffer_3_isEcall : buffer_11_isEcall; + wire _shifted_T_34_isMpause = deqPtr[3] ? buffer_3_isMpause : buffer_11_isMpause; + wire _shifted_T_34_isTile = deqPtr[3] ? buffer_3_isTile : buffer_11_isTile; + wire [31:0] _shifted_WIRE_7_addr = deqPtr[2] ? _shifted_T_34_addr : _shifted_T_22_addr; + wire [6:0] _shifted_WIRE_7_idx = deqPtr[2] ? _shifted_T_34_idx : _shifted_T_22_idx; + wire _shifted_WIRE_7_trap = deqPtr[2] ? _shifted_T_34_trap : _shifted_T_22_trap; + wire _shifted_WIRE_7_isControlFlow = + deqPtr[2] ? _shifted_T_34_isControlFlow : _shifted_T_22_isControlFlow; + wire _shifted_WIRE_7_isBranch = + deqPtr[2] ? _shifted_T_34_isBranch : _shifted_T_22_isBranch; + wire _shifted_WIRE_7_isVector = + deqPtr[2] ? _shifted_T_34_isVector : _shifted_T_22_isVector; + wire _shifted_WIRE_7_resetsVstart = + deqPtr[2] ? _shifted_T_34_resetsVstart : _shifted_T_22_resetsVstart; + wire _shifted_WIRE_7_linkOk = + deqPtr[2] ? _shifted_T_34_linkOk : _shifted_T_22_linkOk; + wire _shifted_WIRE_7_isEcall = + deqPtr[2] ? _shifted_T_34_isEcall : _shifted_T_22_isEcall; + wire _shifted_WIRE_7_isMpause = + deqPtr[2] ? _shifted_T_34_isMpause : _shifted_T_22_isMpause; + wire _shifted_WIRE_7_isTile = + deqPtr[2] ? _shifted_T_34_isTile : _shifted_T_22_isTile; + wire [31:0] _shifted_T_37_addr = deqPtr[3] ? buffer_4_addr : buffer_12_addr; + wire [6:0] _shifted_T_37_idx = deqPtr[3] ? buffer_4_idx : buffer_12_idx; + wire _shifted_T_37_trap = deqPtr[3] ? buffer_4_trap : buffer_12_trap; + wire _shifted_T_37_isControlFlow = + deqPtr[3] ? buffer_4_isControlFlow : buffer_12_isControlFlow; + wire _shifted_T_37_isBranch = deqPtr[3] ? buffer_4_isBranch : buffer_12_isBranch; + wire _shifted_T_37_isVector = deqPtr[3] ? buffer_4_isVector : buffer_12_isVector; + wire _shifted_T_37_resetsVstart = + deqPtr[3] ? buffer_4_resetsVstart : buffer_12_resetsVstart; + wire _shifted_T_37_linkOk = deqPtr[3] ? buffer_4_linkOk : buffer_12_linkOk; + wire _shifted_T_37_isEcall = deqPtr[3] ? buffer_4_isEcall : buffer_12_isEcall; + wire _shifted_T_37_isMpause = deqPtr[3] ? buffer_4_isMpause : buffer_12_isMpause; + wire _shifted_T_37_isTile = deqPtr[3] ? buffer_4_isTile : buffer_12_isTile; + wire [31:0] _shifted_WIRE_8_addr = deqPtr[2] ? _shifted_T_37_addr : _shifted_T_25_addr; + wire [6:0] _shifted_WIRE_8_idx = deqPtr[2] ? _shifted_T_37_idx : _shifted_T_25_idx; + wire _shifted_WIRE_8_trap = deqPtr[2] ? _shifted_T_37_trap : _shifted_T_25_trap; + wire _shifted_WIRE_8_isControlFlow = + deqPtr[2] ? _shifted_T_37_isControlFlow : _shifted_T_25_isControlFlow; + wire _shifted_WIRE_8_isBranch = + deqPtr[2] ? _shifted_T_37_isBranch : _shifted_T_25_isBranch; + wire _shifted_WIRE_8_isVector = + deqPtr[2] ? _shifted_T_37_isVector : _shifted_T_25_isVector; + wire _shifted_WIRE_8_resetsVstart = + deqPtr[2] ? _shifted_T_37_resetsVstart : _shifted_T_25_resetsVstart; + wire _shifted_WIRE_8_linkOk = + deqPtr[2] ? _shifted_T_37_linkOk : _shifted_T_25_linkOk; + wire _shifted_WIRE_8_isEcall = + deqPtr[2] ? _shifted_T_37_isEcall : _shifted_T_25_isEcall; + wire _shifted_WIRE_8_isMpause = + deqPtr[2] ? _shifted_T_37_isMpause : _shifted_T_25_isMpause; + wire _shifted_WIRE_8_isTile = + deqPtr[2] ? _shifted_T_37_isTile : _shifted_T_25_isTile; + wire [31:0] _shifted_T_40_addr = deqPtr[3] ? buffer_5_addr : buffer_13_addr; + wire [6:0] _shifted_T_40_idx = deqPtr[3] ? buffer_5_idx : buffer_13_idx; + wire _shifted_T_40_trap = deqPtr[3] ? buffer_5_trap : buffer_13_trap; + wire _shifted_T_40_isControlFlow = + deqPtr[3] ? buffer_5_isControlFlow : buffer_13_isControlFlow; + wire _shifted_T_40_isBranch = deqPtr[3] ? buffer_5_isBranch : buffer_13_isBranch; + wire _shifted_T_40_isVector = deqPtr[3] ? buffer_5_isVector : buffer_13_isVector; + wire _shifted_T_40_resetsVstart = + deqPtr[3] ? buffer_5_resetsVstart : buffer_13_resetsVstart; + wire _shifted_T_40_linkOk = deqPtr[3] ? buffer_5_linkOk : buffer_13_linkOk; + wire _shifted_T_40_isEcall = deqPtr[3] ? buffer_5_isEcall : buffer_13_isEcall; + wire _shifted_T_40_isMpause = deqPtr[3] ? buffer_5_isMpause : buffer_13_isMpause; + wire _shifted_T_40_isTile = deqPtr[3] ? buffer_5_isTile : buffer_13_isTile; + wire [31:0] _shifted_WIRE_9_addr = deqPtr[2] ? _shifted_T_40_addr : _shifted_T_28_addr; + wire [6:0] _shifted_WIRE_9_idx = deqPtr[2] ? _shifted_T_40_idx : _shifted_T_28_idx; + wire _shifted_WIRE_9_trap = deqPtr[2] ? _shifted_T_40_trap : _shifted_T_28_trap; + wire _shifted_WIRE_9_isControlFlow = + deqPtr[2] ? _shifted_T_40_isControlFlow : _shifted_T_28_isControlFlow; + wire _shifted_WIRE_9_isBranch = + deqPtr[2] ? _shifted_T_40_isBranch : _shifted_T_28_isBranch; + wire _shifted_WIRE_9_isVector = + deqPtr[2] ? _shifted_T_40_isVector : _shifted_T_28_isVector; + wire _shifted_WIRE_9_resetsVstart = + deqPtr[2] ? _shifted_T_40_resetsVstart : _shifted_T_28_resetsVstart; + wire _shifted_WIRE_9_linkOk = + deqPtr[2] ? _shifted_T_40_linkOk : _shifted_T_28_linkOk; + wire _shifted_WIRE_9_isEcall = + deqPtr[2] ? _shifted_T_40_isEcall : _shifted_T_28_isEcall; + wire _shifted_WIRE_9_isMpause = + deqPtr[2] ? _shifted_T_40_isMpause : _shifted_T_28_isMpause; + wire _shifted_WIRE_9_isTile = + deqPtr[2] ? _shifted_T_40_isTile : _shifted_T_28_isTile; + wire [31:0] _shifted_T_43_addr = deqPtr[3] ? buffer_6_addr : buffer_14_addr; + wire [6:0] _shifted_T_43_idx = deqPtr[3] ? buffer_6_idx : buffer_14_idx; + wire _shifted_T_43_trap = deqPtr[3] ? buffer_6_trap : buffer_14_trap; + wire _shifted_T_43_isControlFlow = + deqPtr[3] ? buffer_6_isControlFlow : buffer_14_isControlFlow; + wire _shifted_T_43_isBranch = deqPtr[3] ? buffer_6_isBranch : buffer_14_isBranch; + wire _shifted_T_43_isVector = deqPtr[3] ? buffer_6_isVector : buffer_14_isVector; + wire _shifted_T_43_resetsVstart = + deqPtr[3] ? buffer_6_resetsVstart : buffer_14_resetsVstart; + wire _shifted_T_43_linkOk = deqPtr[3] ? buffer_6_linkOk : buffer_14_linkOk; + wire _shifted_T_43_isEcall = deqPtr[3] ? buffer_6_isEcall : buffer_14_isEcall; + wire _shifted_T_43_isMpause = deqPtr[3] ? buffer_6_isMpause : buffer_14_isMpause; + wire _shifted_T_43_isTile = deqPtr[3] ? buffer_6_isTile : buffer_14_isTile; + wire [31:0] _shifted_WIRE_10_addr = deqPtr[2] ? _shifted_T_43_addr : _shifted_T_31_addr; + wire [6:0] _shifted_WIRE_10_idx = deqPtr[2] ? _shifted_T_43_idx : _shifted_T_31_idx; + wire _shifted_WIRE_10_trap = deqPtr[2] ? _shifted_T_43_trap : _shifted_T_31_trap; + wire _shifted_WIRE_10_isControlFlow = + deqPtr[2] ? _shifted_T_43_isControlFlow : _shifted_T_31_isControlFlow; + wire _shifted_WIRE_10_isBranch = + deqPtr[2] ? _shifted_T_43_isBranch : _shifted_T_31_isBranch; + wire _shifted_WIRE_10_isVector = + deqPtr[2] ? _shifted_T_43_isVector : _shifted_T_31_isVector; + wire _shifted_WIRE_10_resetsVstart = + deqPtr[2] ? _shifted_T_43_resetsVstart : _shifted_T_31_resetsVstart; + wire _shifted_WIRE_10_linkOk = + deqPtr[2] ? _shifted_T_43_linkOk : _shifted_T_31_linkOk; + wire _shifted_WIRE_10_isEcall = + deqPtr[2] ? _shifted_T_43_isEcall : _shifted_T_31_isEcall; + wire _shifted_WIRE_10_isMpause = + deqPtr[2] ? _shifted_T_43_isMpause : _shifted_T_31_isMpause; + wire _shifted_WIRE_10_isTile = + deqPtr[2] ? _shifted_T_43_isTile : _shifted_T_31_isTile; + wire [31:0] _shifted_T_46_addr = deqPtr[3] ? buffer_7_addr : buffer_15_addr; + wire [6:0] _shifted_T_46_idx = deqPtr[3] ? buffer_7_idx : buffer_15_idx; + wire _shifted_T_46_trap = deqPtr[3] ? buffer_7_trap : buffer_15_trap; + wire _shifted_T_46_isControlFlow = + deqPtr[3] ? buffer_7_isControlFlow : buffer_15_isControlFlow; + wire _shifted_T_46_isBranch = deqPtr[3] ? buffer_7_isBranch : buffer_15_isBranch; + wire _shifted_T_46_isVector = deqPtr[3] ? buffer_7_isVector : buffer_15_isVector; + wire _shifted_T_46_resetsVstart = + deqPtr[3] ? buffer_7_resetsVstart : buffer_15_resetsVstart; + wire _shifted_T_46_linkOk = deqPtr[3] ? buffer_7_linkOk : buffer_15_linkOk; + wire _shifted_T_46_isEcall = deqPtr[3] ? buffer_7_isEcall : buffer_15_isEcall; + wire _shifted_T_46_isMpause = deqPtr[3] ? buffer_7_isMpause : buffer_15_isMpause; + wire _shifted_T_46_isTile = deqPtr[3] ? buffer_7_isTile : buffer_15_isTile; + wire [31:0] _shifted_WIRE_11_addr = deqPtr[2] ? _shifted_T_46_addr : _shifted_T_34_addr; + wire [6:0] _shifted_WIRE_11_idx = deqPtr[2] ? _shifted_T_46_idx : _shifted_T_34_idx; + wire _shifted_WIRE_11_trap = deqPtr[2] ? _shifted_T_46_trap : _shifted_T_34_trap; + wire _shifted_WIRE_11_isControlFlow = + deqPtr[2] ? _shifted_T_46_isControlFlow : _shifted_T_34_isControlFlow; + wire _shifted_WIRE_11_isBranch = + deqPtr[2] ? _shifted_T_46_isBranch : _shifted_T_34_isBranch; + wire _shifted_WIRE_11_isVector = + deqPtr[2] ? _shifted_T_46_isVector : _shifted_T_34_isVector; + wire _shifted_WIRE_11_resetsVstart = + deqPtr[2] ? _shifted_T_46_resetsVstart : _shifted_T_34_resetsVstart; + wire _shifted_WIRE_11_linkOk = + deqPtr[2] ? _shifted_T_46_linkOk : _shifted_T_34_linkOk; + wire _shifted_WIRE_11_isEcall = + deqPtr[2] ? _shifted_T_46_isEcall : _shifted_T_34_isEcall; + wire _shifted_WIRE_11_isMpause = + deqPtr[2] ? _shifted_T_46_isMpause : _shifted_T_34_isMpause; + wire _shifted_WIRE_11_isTile = + deqPtr[2] ? _shifted_T_46_isTile : _shifted_T_34_isTile; + wire [31:0] _shifted_T_49_addr = deqPtr[3] ? buffer_8_addr : buffer_0_addr; + wire [6:0] _shifted_T_49_idx = deqPtr[3] ? buffer_8_idx : buffer_0_idx; + wire _shifted_T_49_trap = deqPtr[3] ? buffer_8_trap : buffer_0_trap; + wire _shifted_T_49_isControlFlow = + deqPtr[3] ? buffer_8_isControlFlow : buffer_0_isControlFlow; + wire _shifted_T_49_isBranch = deqPtr[3] ? buffer_8_isBranch : buffer_0_isBranch; + wire _shifted_T_49_isVector = deqPtr[3] ? buffer_8_isVector : buffer_0_isVector; + wire _shifted_T_49_resetsVstart = + deqPtr[3] ? buffer_8_resetsVstart : buffer_0_resetsVstart; + wire _shifted_T_49_linkOk = deqPtr[3] ? buffer_8_linkOk : buffer_0_linkOk; + wire _shifted_T_49_isEcall = deqPtr[3] ? buffer_8_isEcall : buffer_0_isEcall; + wire _shifted_T_49_isMpause = deqPtr[3] ? buffer_8_isMpause : buffer_0_isMpause; + wire _shifted_T_49_isTile = deqPtr[3] ? buffer_8_isTile : buffer_0_isTile; + wire [31:0] _shifted_WIRE_12_addr = deqPtr[2] ? _shifted_T_49_addr : _shifted_T_37_addr; + wire [6:0] _shifted_WIRE_12_idx = deqPtr[2] ? _shifted_T_49_idx : _shifted_T_37_idx; + wire _shifted_WIRE_12_trap = deqPtr[2] ? _shifted_T_49_trap : _shifted_T_37_trap; + wire _shifted_WIRE_12_isControlFlow = + deqPtr[2] ? _shifted_T_49_isControlFlow : _shifted_T_37_isControlFlow; + wire _shifted_WIRE_12_isBranch = + deqPtr[2] ? _shifted_T_49_isBranch : _shifted_T_37_isBranch; + wire _shifted_WIRE_12_isVector = + deqPtr[2] ? _shifted_T_49_isVector : _shifted_T_37_isVector; + wire _shifted_WIRE_12_resetsVstart = + deqPtr[2] ? _shifted_T_49_resetsVstart : _shifted_T_37_resetsVstart; + wire _shifted_WIRE_12_linkOk = + deqPtr[2] ? _shifted_T_49_linkOk : _shifted_T_37_linkOk; + wire _shifted_WIRE_12_isEcall = + deqPtr[2] ? _shifted_T_49_isEcall : _shifted_T_37_isEcall; + wire _shifted_WIRE_12_isMpause = + deqPtr[2] ? _shifted_T_49_isMpause : _shifted_T_37_isMpause; + wire _shifted_WIRE_12_isTile = + deqPtr[2] ? _shifted_T_49_isTile : _shifted_T_37_isTile; + wire [31:0] _shifted_T_52_addr = deqPtr[3] ? buffer_9_addr : buffer_1_addr; + wire [6:0] _shifted_T_52_idx = deqPtr[3] ? buffer_9_idx : buffer_1_idx; + wire _shifted_T_52_trap = deqPtr[3] ? buffer_9_trap : buffer_1_trap; + wire _shifted_T_52_isControlFlow = + deqPtr[3] ? buffer_9_isControlFlow : buffer_1_isControlFlow; + wire _shifted_T_52_isBranch = deqPtr[3] ? buffer_9_isBranch : buffer_1_isBranch; + wire _shifted_T_52_isVector = deqPtr[3] ? buffer_9_isVector : buffer_1_isVector; + wire _shifted_T_52_resetsVstart = + deqPtr[3] ? buffer_9_resetsVstart : buffer_1_resetsVstart; + wire _shifted_T_52_linkOk = deqPtr[3] ? buffer_9_linkOk : buffer_1_linkOk; + wire _shifted_T_52_isEcall = deqPtr[3] ? buffer_9_isEcall : buffer_1_isEcall; + wire _shifted_T_52_isMpause = deqPtr[3] ? buffer_9_isMpause : buffer_1_isMpause; + wire _shifted_T_52_isTile = deqPtr[3] ? buffer_9_isTile : buffer_1_isTile; + wire [31:0] _shifted_WIRE_13_addr = deqPtr[2] ? _shifted_T_52_addr : _shifted_T_40_addr; + wire [6:0] _shifted_WIRE_13_idx = deqPtr[2] ? _shifted_T_52_idx : _shifted_T_40_idx; + wire _shifted_WIRE_13_trap = deqPtr[2] ? _shifted_T_52_trap : _shifted_T_40_trap; + wire _shifted_WIRE_13_isControlFlow = + deqPtr[2] ? _shifted_T_52_isControlFlow : _shifted_T_40_isControlFlow; + wire _shifted_WIRE_13_isBranch = + deqPtr[2] ? _shifted_T_52_isBranch : _shifted_T_40_isBranch; + wire _shifted_WIRE_13_isVector = + deqPtr[2] ? _shifted_T_52_isVector : _shifted_T_40_isVector; + wire _shifted_WIRE_13_resetsVstart = + deqPtr[2] ? _shifted_T_52_resetsVstart : _shifted_T_40_resetsVstart; + wire _shifted_WIRE_13_linkOk = + deqPtr[2] ? _shifted_T_52_linkOk : _shifted_T_40_linkOk; + wire _shifted_WIRE_13_isEcall = + deqPtr[2] ? _shifted_T_52_isEcall : _shifted_T_40_isEcall; + wire _shifted_WIRE_13_isMpause = + deqPtr[2] ? _shifted_T_52_isMpause : _shifted_T_40_isMpause; + wire _shifted_WIRE_13_isTile = + deqPtr[2] ? _shifted_T_52_isTile : _shifted_T_40_isTile; + wire [31:0] _shifted_T_55_addr = deqPtr[3] ? buffer_10_addr : buffer_2_addr; + wire [6:0] _shifted_T_55_idx = deqPtr[3] ? buffer_10_idx : buffer_2_idx; + wire _shifted_T_55_trap = deqPtr[3] ? buffer_10_trap : buffer_2_trap; + wire _shifted_T_55_isControlFlow = + deqPtr[3] ? buffer_10_isControlFlow : buffer_2_isControlFlow; + wire _shifted_T_55_isBranch = deqPtr[3] ? buffer_10_isBranch : buffer_2_isBranch; + wire _shifted_T_55_isVector = deqPtr[3] ? buffer_10_isVector : buffer_2_isVector; + wire _shifted_T_55_resetsVstart = + deqPtr[3] ? buffer_10_resetsVstart : buffer_2_resetsVstart; + wire _shifted_T_55_linkOk = deqPtr[3] ? buffer_10_linkOk : buffer_2_linkOk; + wire _shifted_T_55_isEcall = deqPtr[3] ? buffer_10_isEcall : buffer_2_isEcall; + wire _shifted_T_55_isMpause = deqPtr[3] ? buffer_10_isMpause : buffer_2_isMpause; + wire _shifted_T_55_isTile = deqPtr[3] ? buffer_10_isTile : buffer_2_isTile; + wire [31:0] _shifted_WIRE_14_addr = deqPtr[2] ? _shifted_T_55_addr : _shifted_T_43_addr; + wire [6:0] _shifted_WIRE_14_idx = deqPtr[2] ? _shifted_T_55_idx : _shifted_T_43_idx; + wire _shifted_WIRE_14_trap = deqPtr[2] ? _shifted_T_55_trap : _shifted_T_43_trap; + wire _shifted_WIRE_14_isControlFlow = + deqPtr[2] ? _shifted_T_55_isControlFlow : _shifted_T_43_isControlFlow; + wire _shifted_WIRE_14_isBranch = + deqPtr[2] ? _shifted_T_55_isBranch : _shifted_T_43_isBranch; + wire _shifted_WIRE_14_isVector = + deqPtr[2] ? _shifted_T_55_isVector : _shifted_T_43_isVector; + wire _shifted_WIRE_14_resetsVstart = + deqPtr[2] ? _shifted_T_55_resetsVstart : _shifted_T_43_resetsVstart; + wire _shifted_WIRE_14_linkOk = + deqPtr[2] ? _shifted_T_55_linkOk : _shifted_T_43_linkOk; + wire _shifted_WIRE_14_isEcall = + deqPtr[2] ? _shifted_T_55_isEcall : _shifted_T_43_isEcall; + wire _shifted_WIRE_14_isMpause = + deqPtr[2] ? _shifted_T_55_isMpause : _shifted_T_43_isMpause; + wire _shifted_WIRE_14_isTile = + deqPtr[2] ? _shifted_T_55_isTile : _shifted_T_43_isTile; + wire [31:0] _shifted_WIRE_15_addr = + deqPtr[2] ? (deqPtr[3] ? buffer_11_addr : buffer_3_addr) : _shifted_T_46_addr; + wire [6:0] _shifted_WIRE_15_idx = + deqPtr[2] ? (deqPtr[3] ? buffer_11_idx : buffer_3_idx) : _shifted_T_46_idx; + wire _shifted_WIRE_15_trap = + deqPtr[2] ? (deqPtr[3] ? buffer_11_trap : buffer_3_trap) : _shifted_T_46_trap; + wire _shifted_WIRE_15_isControlFlow = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_isControlFlow : buffer_3_isControlFlow) + : _shifted_T_46_isControlFlow; + wire _shifted_WIRE_15_isBranch = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_isBranch : buffer_3_isBranch) + : _shifted_T_46_isBranch; + wire _shifted_WIRE_15_isVector = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_isVector : buffer_3_isVector) + : _shifted_T_46_isVector; + wire _shifted_WIRE_15_resetsVstart = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_resetsVstart : buffer_3_resetsVstart) + : _shifted_T_46_resetsVstart; + wire _shifted_WIRE_15_linkOk = + deqPtr[2] ? (deqPtr[3] ? buffer_11_linkOk : buffer_3_linkOk) : _shifted_T_46_linkOk; + wire _shifted_WIRE_15_isEcall = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_isEcall : buffer_3_isEcall) + : _shifted_T_46_isEcall; + wire _shifted_WIRE_15_isMpause = + deqPtr[2] + ? (deqPtr[3] ? buffer_11_isMpause : buffer_3_isMpause) + : _shifted_T_46_isMpause; + wire _shifted_WIRE_15_isTile = + deqPtr[2] ? (deqPtr[3] ? buffer_11_isTile : buffer_3_isTile) : _shifted_T_46_isTile; + wire [31:0] _shifted_WIRE_16_addr = + deqPtr[2] ? (deqPtr[3] ? buffer_12_addr : buffer_4_addr) : _shifted_T_49_addr; + wire [6:0] _shifted_WIRE_16_idx = + deqPtr[2] ? (deqPtr[3] ? buffer_12_idx : buffer_4_idx) : _shifted_T_49_idx; + wire _shifted_WIRE_16_trap = + deqPtr[2] ? (deqPtr[3] ? buffer_12_trap : buffer_4_trap) : _shifted_T_49_trap; + wire _shifted_WIRE_16_isControlFlow = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_isControlFlow : buffer_4_isControlFlow) + : _shifted_T_49_isControlFlow; + wire _shifted_WIRE_16_isBranch = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_isBranch : buffer_4_isBranch) + : _shifted_T_49_isBranch; + wire _shifted_WIRE_16_isVector = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_isVector : buffer_4_isVector) + : _shifted_T_49_isVector; + wire _shifted_WIRE_16_resetsVstart = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_resetsVstart : buffer_4_resetsVstart) + : _shifted_T_49_resetsVstart; + wire _shifted_WIRE_16_linkOk = + deqPtr[2] ? (deqPtr[3] ? buffer_12_linkOk : buffer_4_linkOk) : _shifted_T_49_linkOk; + wire _shifted_WIRE_16_isEcall = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_isEcall : buffer_4_isEcall) + : _shifted_T_49_isEcall; + wire _shifted_WIRE_16_isMpause = + deqPtr[2] + ? (deqPtr[3] ? buffer_12_isMpause : buffer_4_isMpause) + : _shifted_T_49_isMpause; + wire _shifted_WIRE_16_isTile = + deqPtr[2] ? (deqPtr[3] ? buffer_12_isTile : buffer_4_isTile) : _shifted_T_49_isTile; + wire [31:0] _shifted_T_61_addr = + deqPtr[1] + ? _shifted_WIRE_3_addr + : deqPtr[2] ? _shifted_T_16_addr : deqPtr[3] ? buffer_9_addr : buffer_1_addr; + wire [6:0] _shifted_T_61_idx = + deqPtr[1] + ? _shifted_WIRE_3_idx + : deqPtr[2] ? _shifted_T_16_idx : deqPtr[3] ? buffer_9_idx : buffer_1_idx; + wire _shifted_T_61_trap = + deqPtr[1] + ? _shifted_WIRE_3_trap + : deqPtr[2] ? _shifted_T_16_trap : deqPtr[3] ? buffer_9_trap : buffer_1_trap; + wire _shifted_T_61_isControlFlow = + deqPtr[1] + ? _shifted_WIRE_3_isControlFlow + : deqPtr[2] + ? _shifted_T_16_isControlFlow + : deqPtr[3] ? buffer_9_isControlFlow : buffer_1_isControlFlow; + wire _shifted_T_61_isBranch = + deqPtr[1] + ? _shifted_WIRE_3_isBranch + : deqPtr[2] + ? _shifted_T_16_isBranch + : deqPtr[3] ? buffer_9_isBranch : buffer_1_isBranch; + wire _shifted_T_61_isVector = + deqPtr[1] + ? _shifted_WIRE_3_isVector + : deqPtr[2] + ? _shifted_T_16_isVector + : deqPtr[3] ? buffer_9_isVector : buffer_1_isVector; + wire _shifted_T_61_resetsVstart = + deqPtr[1] + ? _shifted_WIRE_3_resetsVstart + : deqPtr[2] + ? _shifted_T_16_resetsVstart + : deqPtr[3] ? buffer_9_resetsVstart : buffer_1_resetsVstart; + wire _shifted_T_61_linkOk = + deqPtr[1] + ? _shifted_WIRE_3_linkOk + : deqPtr[2] ? _shifted_T_16_linkOk : deqPtr[3] ? buffer_9_linkOk : buffer_1_linkOk; + wire _shifted_T_61_isEcall = + deqPtr[1] + ? _shifted_WIRE_3_isEcall + : deqPtr[2] + ? _shifted_T_16_isEcall + : deqPtr[3] ? buffer_9_isEcall : buffer_1_isEcall; + wire _shifted_T_61_isMpause = + deqPtr[1] + ? _shifted_WIRE_3_isMpause + : deqPtr[2] + ? _shifted_T_16_isMpause + : deqPtr[3] ? buffer_9_isMpause : buffer_1_isMpause; + wire _shifted_T_61_isTile = + deqPtr[1] + ? _shifted_WIRE_3_isTile + : deqPtr[2] ? _shifted_T_16_isTile : deqPtr[3] ? buffer_9_isTile : buffer_1_isTile; + wire [31:0] _shifted_T_64_addr = + deqPtr[1] ? _shifted_WIRE_4_addr : _shifted_WIRE_2_addr; + wire [6:0] _shifted_T_64_idx = deqPtr[1] ? _shifted_WIRE_4_idx : _shifted_WIRE_2_idx; + wire _shifted_T_64_trap = + deqPtr[1] ? _shifted_WIRE_4_trap : _shifted_WIRE_2_trap; + wire _shifted_T_64_isControlFlow = + deqPtr[1] ? _shifted_WIRE_4_isControlFlow : _shifted_WIRE_2_isControlFlow; + wire _shifted_T_64_isBranch = + deqPtr[1] ? _shifted_WIRE_4_isBranch : _shifted_WIRE_2_isBranch; + wire _shifted_T_64_isVector = + deqPtr[1] ? _shifted_WIRE_4_isVector : _shifted_WIRE_2_isVector; + wire _shifted_T_64_resetsVstart = + deqPtr[1] ? _shifted_WIRE_4_resetsVstart : _shifted_WIRE_2_resetsVstart; + wire _shifted_T_64_linkOk = + deqPtr[1] ? _shifted_WIRE_4_linkOk : _shifted_WIRE_2_linkOk; + wire _shifted_T_64_isEcall = + deqPtr[1] ? _shifted_WIRE_4_isEcall : _shifted_WIRE_2_isEcall; + wire _shifted_T_64_isMpause = + deqPtr[1] ? _shifted_WIRE_4_isMpause : _shifted_WIRE_2_isMpause; + wire _shifted_T_64_isTile = + deqPtr[1] ? _shifted_WIRE_4_isTile : _shifted_WIRE_2_isTile; + wire [31:0] _shifted_T_67_addr = + deqPtr[1] ? _shifted_WIRE_5_addr : _shifted_WIRE_3_addr; + wire [6:0] _shifted_T_67_idx = deqPtr[1] ? _shifted_WIRE_5_idx : _shifted_WIRE_3_idx; + wire _shifted_T_67_trap = + deqPtr[1] ? _shifted_WIRE_5_trap : _shifted_WIRE_3_trap; + wire _shifted_T_67_isControlFlow = + deqPtr[1] ? _shifted_WIRE_5_isControlFlow : _shifted_WIRE_3_isControlFlow; + wire _shifted_T_67_isBranch = + deqPtr[1] ? _shifted_WIRE_5_isBranch : _shifted_WIRE_3_isBranch; + wire _shifted_T_67_isVector = + deqPtr[1] ? _shifted_WIRE_5_isVector : _shifted_WIRE_3_isVector; + wire _shifted_T_67_resetsVstart = + deqPtr[1] ? _shifted_WIRE_5_resetsVstart : _shifted_WIRE_3_resetsVstart; + wire _shifted_T_67_linkOk = + deqPtr[1] ? _shifted_WIRE_5_linkOk : _shifted_WIRE_3_linkOk; + wire _shifted_T_67_isEcall = + deqPtr[1] ? _shifted_WIRE_5_isEcall : _shifted_WIRE_3_isEcall; + wire _shifted_T_67_isMpause = + deqPtr[1] ? _shifted_WIRE_5_isMpause : _shifted_WIRE_3_isMpause; + wire _shifted_T_67_isTile = + deqPtr[1] ? _shifted_WIRE_5_isTile : _shifted_WIRE_3_isTile; + wire [31:0] _shifted_T_70_addr = + deqPtr[1] ? _shifted_WIRE_6_addr : _shifted_WIRE_4_addr; + wire [6:0] _shifted_T_70_idx = deqPtr[1] ? _shifted_WIRE_6_idx : _shifted_WIRE_4_idx; + wire _shifted_T_70_trap = + deqPtr[1] ? _shifted_WIRE_6_trap : _shifted_WIRE_4_trap; + wire _shifted_T_70_isControlFlow = + deqPtr[1] ? _shifted_WIRE_6_isControlFlow : _shifted_WIRE_4_isControlFlow; + wire _shifted_T_70_isBranch = + deqPtr[1] ? _shifted_WIRE_6_isBranch : _shifted_WIRE_4_isBranch; + wire _shifted_T_70_isVector = + deqPtr[1] ? _shifted_WIRE_6_isVector : _shifted_WIRE_4_isVector; + wire _shifted_T_70_resetsVstart = + deqPtr[1] ? _shifted_WIRE_6_resetsVstart : _shifted_WIRE_4_resetsVstart; + wire _shifted_T_70_linkOk = + deqPtr[1] ? _shifted_WIRE_6_linkOk : _shifted_WIRE_4_linkOk; + wire _shifted_T_70_isEcall = + deqPtr[1] ? _shifted_WIRE_6_isEcall : _shifted_WIRE_4_isEcall; + wire _shifted_T_70_isMpause = + deqPtr[1] ? _shifted_WIRE_6_isMpause : _shifted_WIRE_4_isMpause; + wire _shifted_T_70_isTile = + deqPtr[1] ? _shifted_WIRE_6_isTile : _shifted_WIRE_4_isTile; + wire [31:0] _shifted_T_73_addr = + deqPtr[1] ? _shifted_WIRE_7_addr : _shifted_WIRE_5_addr; + wire [6:0] _shifted_T_73_idx = deqPtr[1] ? _shifted_WIRE_7_idx : _shifted_WIRE_5_idx; + wire _shifted_T_73_trap = + deqPtr[1] ? _shifted_WIRE_7_trap : _shifted_WIRE_5_trap; + wire _shifted_T_73_isControlFlow = + deqPtr[1] ? _shifted_WIRE_7_isControlFlow : _shifted_WIRE_5_isControlFlow; + wire _shifted_T_73_isBranch = + deqPtr[1] ? _shifted_WIRE_7_isBranch : _shifted_WIRE_5_isBranch; + wire _shifted_T_73_isVector = + deqPtr[1] ? _shifted_WIRE_7_isVector : _shifted_WIRE_5_isVector; + wire _shifted_T_73_resetsVstart = + deqPtr[1] ? _shifted_WIRE_7_resetsVstart : _shifted_WIRE_5_resetsVstart; + wire _shifted_T_73_linkOk = + deqPtr[1] ? _shifted_WIRE_7_linkOk : _shifted_WIRE_5_linkOk; + wire _shifted_T_73_isEcall = + deqPtr[1] ? _shifted_WIRE_7_isEcall : _shifted_WIRE_5_isEcall; + wire _shifted_T_73_isMpause = + deqPtr[1] ? _shifted_WIRE_7_isMpause : _shifted_WIRE_5_isMpause; + wire _shifted_T_73_isTile = + deqPtr[1] ? _shifted_WIRE_7_isTile : _shifted_WIRE_5_isTile; + wire [31:0] _shifted_T_76_addr = + deqPtr[1] ? _shifted_WIRE_8_addr : _shifted_WIRE_6_addr; + wire [6:0] _shifted_T_76_idx = deqPtr[1] ? _shifted_WIRE_8_idx : _shifted_WIRE_6_idx; + wire _shifted_T_76_trap = + deqPtr[1] ? _shifted_WIRE_8_trap : _shifted_WIRE_6_trap; + wire _shifted_T_76_isControlFlow = + deqPtr[1] ? _shifted_WIRE_8_isControlFlow : _shifted_WIRE_6_isControlFlow; + wire _shifted_T_76_isBranch = + deqPtr[1] ? _shifted_WIRE_8_isBranch : _shifted_WIRE_6_isBranch; + wire _shifted_T_76_isVector = + deqPtr[1] ? _shifted_WIRE_8_isVector : _shifted_WIRE_6_isVector; + wire _shifted_T_76_resetsVstart = + deqPtr[1] ? _shifted_WIRE_8_resetsVstart : _shifted_WIRE_6_resetsVstart; + wire _shifted_T_76_linkOk = + deqPtr[1] ? _shifted_WIRE_8_linkOk : _shifted_WIRE_6_linkOk; + wire _shifted_T_76_isEcall = + deqPtr[1] ? _shifted_WIRE_8_isEcall : _shifted_WIRE_6_isEcall; + wire _shifted_T_76_isMpause = + deqPtr[1] ? _shifted_WIRE_8_isMpause : _shifted_WIRE_6_isMpause; + wire _shifted_T_76_isTile = + deqPtr[1] ? _shifted_WIRE_8_isTile : _shifted_WIRE_6_isTile; + wire [31:0] _shifted_T_79_addr = + deqPtr[1] ? _shifted_WIRE_9_addr : _shifted_WIRE_7_addr; + wire [6:0] _shifted_T_79_idx = deqPtr[1] ? _shifted_WIRE_9_idx : _shifted_WIRE_7_idx; + wire _shifted_T_79_trap = + deqPtr[1] ? _shifted_WIRE_9_trap : _shifted_WIRE_7_trap; + wire _shifted_T_79_isControlFlow = + deqPtr[1] ? _shifted_WIRE_9_isControlFlow : _shifted_WIRE_7_isControlFlow; + wire _shifted_T_79_isBranch = + deqPtr[1] ? _shifted_WIRE_9_isBranch : _shifted_WIRE_7_isBranch; + wire _shifted_T_79_isVector = + deqPtr[1] ? _shifted_WIRE_9_isVector : _shifted_WIRE_7_isVector; + wire _shifted_T_79_resetsVstart = + deqPtr[1] ? _shifted_WIRE_9_resetsVstart : _shifted_WIRE_7_resetsVstart; + wire _shifted_T_79_linkOk = + deqPtr[1] ? _shifted_WIRE_9_linkOk : _shifted_WIRE_7_linkOk; + wire _shifted_T_79_isEcall = + deqPtr[1] ? _shifted_WIRE_9_isEcall : _shifted_WIRE_7_isEcall; + wire _shifted_T_79_isMpause = + deqPtr[1] ? _shifted_WIRE_9_isMpause : _shifted_WIRE_7_isMpause; + wire _shifted_T_79_isTile = + deqPtr[1] ? _shifted_WIRE_9_isTile : _shifted_WIRE_7_isTile; + wire [31:0] _shifted_T_82_addr = + deqPtr[1] ? _shifted_WIRE_10_addr : _shifted_WIRE_8_addr; + wire [6:0] _shifted_T_82_idx = deqPtr[1] ? _shifted_WIRE_10_idx : _shifted_WIRE_8_idx; + wire _shifted_T_82_trap = + deqPtr[1] ? _shifted_WIRE_10_trap : _shifted_WIRE_8_trap; + wire _shifted_T_82_isControlFlow = + deqPtr[1] ? _shifted_WIRE_10_isControlFlow : _shifted_WIRE_8_isControlFlow; + wire _shifted_T_82_isBranch = + deqPtr[1] ? _shifted_WIRE_10_isBranch : _shifted_WIRE_8_isBranch; + wire _shifted_T_82_isVector = + deqPtr[1] ? _shifted_WIRE_10_isVector : _shifted_WIRE_8_isVector; + wire _shifted_T_82_resetsVstart = + deqPtr[1] ? _shifted_WIRE_10_resetsVstart : _shifted_WIRE_8_resetsVstart; + wire _shifted_T_82_linkOk = + deqPtr[1] ? _shifted_WIRE_10_linkOk : _shifted_WIRE_8_linkOk; + wire _shifted_T_82_isEcall = + deqPtr[1] ? _shifted_WIRE_10_isEcall : _shifted_WIRE_8_isEcall; + wire _shifted_T_82_isMpause = + deqPtr[1] ? _shifted_WIRE_10_isMpause : _shifted_WIRE_8_isMpause; + wire _shifted_T_82_isTile = + deqPtr[1] ? _shifted_WIRE_10_isTile : _shifted_WIRE_8_isTile; + wire [31:0] _shifted_T_85_addr = + deqPtr[1] ? _shifted_WIRE_11_addr : _shifted_WIRE_9_addr; + wire [6:0] _shifted_T_85_idx = deqPtr[1] ? _shifted_WIRE_11_idx : _shifted_WIRE_9_idx; + wire _shifted_T_85_trap = + deqPtr[1] ? _shifted_WIRE_11_trap : _shifted_WIRE_9_trap; + wire _shifted_T_85_isControlFlow = + deqPtr[1] ? _shifted_WIRE_11_isControlFlow : _shifted_WIRE_9_isControlFlow; + wire _shifted_T_85_isBranch = + deqPtr[1] ? _shifted_WIRE_11_isBranch : _shifted_WIRE_9_isBranch; + wire _shifted_T_85_isVector = + deqPtr[1] ? _shifted_WIRE_11_isVector : _shifted_WIRE_9_isVector; + wire _shifted_T_85_resetsVstart = + deqPtr[1] ? _shifted_WIRE_11_resetsVstart : _shifted_WIRE_9_resetsVstart; + wire _shifted_T_85_linkOk = + deqPtr[1] ? _shifted_WIRE_11_linkOk : _shifted_WIRE_9_linkOk; + wire _shifted_T_85_isEcall = + deqPtr[1] ? _shifted_WIRE_11_isEcall : _shifted_WIRE_9_isEcall; + wire _shifted_T_85_isMpause = + deqPtr[1] ? _shifted_WIRE_11_isMpause : _shifted_WIRE_9_isMpause; + wire _shifted_T_85_isTile = + deqPtr[1] ? _shifted_WIRE_11_isTile : _shifted_WIRE_9_isTile; + wire [31:0] _shifted_T_88_addr = + deqPtr[1] ? _shifted_WIRE_12_addr : _shifted_WIRE_10_addr; + wire [6:0] _shifted_T_88_idx = deqPtr[1] ? _shifted_WIRE_12_idx : _shifted_WIRE_10_idx; + wire _shifted_T_88_trap = + deqPtr[1] ? _shifted_WIRE_12_trap : _shifted_WIRE_10_trap; + wire _shifted_T_88_isControlFlow = + deqPtr[1] ? _shifted_WIRE_12_isControlFlow : _shifted_WIRE_10_isControlFlow; + wire _shifted_T_88_isBranch = + deqPtr[1] ? _shifted_WIRE_12_isBranch : _shifted_WIRE_10_isBranch; + wire _shifted_T_88_isVector = + deqPtr[1] ? _shifted_WIRE_12_isVector : _shifted_WIRE_10_isVector; + wire _shifted_T_88_resetsVstart = + deqPtr[1] ? _shifted_WIRE_12_resetsVstart : _shifted_WIRE_10_resetsVstart; + wire _shifted_T_88_linkOk = + deqPtr[1] ? _shifted_WIRE_12_linkOk : _shifted_WIRE_10_linkOk; + wire _shifted_T_88_isEcall = + deqPtr[1] ? _shifted_WIRE_12_isEcall : _shifted_WIRE_10_isEcall; + wire _shifted_T_88_isMpause = + deqPtr[1] ? _shifted_WIRE_12_isMpause : _shifted_WIRE_10_isMpause; + wire _shifted_T_88_isTile = + deqPtr[1] ? _shifted_WIRE_12_isTile : _shifted_WIRE_10_isTile; + wire [31:0] _shifted_T_91_addr = + deqPtr[1] ? _shifted_WIRE_13_addr : _shifted_WIRE_11_addr; + wire [6:0] _shifted_T_91_idx = deqPtr[1] ? _shifted_WIRE_13_idx : _shifted_WIRE_11_idx; + wire _shifted_T_91_trap = + deqPtr[1] ? _shifted_WIRE_13_trap : _shifted_WIRE_11_trap; + wire _shifted_T_91_isControlFlow = + deqPtr[1] ? _shifted_WIRE_13_isControlFlow : _shifted_WIRE_11_isControlFlow; + wire _shifted_T_91_isBranch = + deqPtr[1] ? _shifted_WIRE_13_isBranch : _shifted_WIRE_11_isBranch; + wire _shifted_T_91_isVector = + deqPtr[1] ? _shifted_WIRE_13_isVector : _shifted_WIRE_11_isVector; + wire _shifted_T_91_resetsVstart = + deqPtr[1] ? _shifted_WIRE_13_resetsVstart : _shifted_WIRE_11_resetsVstart; + wire _shifted_T_91_linkOk = + deqPtr[1] ? _shifted_WIRE_13_linkOk : _shifted_WIRE_11_linkOk; + wire _shifted_T_91_isEcall = + deqPtr[1] ? _shifted_WIRE_13_isEcall : _shifted_WIRE_11_isEcall; + wire _shifted_T_91_isMpause = + deqPtr[1] ? _shifted_WIRE_13_isMpause : _shifted_WIRE_11_isMpause; + wire _shifted_T_91_isTile = + deqPtr[1] ? _shifted_WIRE_13_isTile : _shifted_WIRE_11_isTile; + wire [31:0] _shifted_T_94_addr = + deqPtr[1] ? _shifted_WIRE_14_addr : _shifted_WIRE_12_addr; + wire [6:0] _shifted_T_94_idx = deqPtr[1] ? _shifted_WIRE_14_idx : _shifted_WIRE_12_idx; + wire _shifted_T_94_trap = + deqPtr[1] ? _shifted_WIRE_14_trap : _shifted_WIRE_12_trap; + wire _shifted_T_94_isControlFlow = + deqPtr[1] ? _shifted_WIRE_14_isControlFlow : _shifted_WIRE_12_isControlFlow; + wire _shifted_T_94_isBranch = + deqPtr[1] ? _shifted_WIRE_14_isBranch : _shifted_WIRE_12_isBranch; + wire _shifted_T_94_isVector = + deqPtr[1] ? _shifted_WIRE_14_isVector : _shifted_WIRE_12_isVector; + wire _shifted_T_94_resetsVstart = + deqPtr[1] ? _shifted_WIRE_14_resetsVstart : _shifted_WIRE_12_resetsVstart; + wire _shifted_T_94_linkOk = + deqPtr[1] ? _shifted_WIRE_14_linkOk : _shifted_WIRE_12_linkOk; + wire _shifted_T_94_isEcall = + deqPtr[1] ? _shifted_WIRE_14_isEcall : _shifted_WIRE_12_isEcall; + wire _shifted_T_94_isMpause = + deqPtr[1] ? _shifted_WIRE_14_isMpause : _shifted_WIRE_12_isMpause; + wire _shifted_T_94_isTile = + deqPtr[1] ? _shifted_WIRE_14_isTile : _shifted_WIRE_12_isTile; + wire [31:0] _shifted_T_97_addr = + deqPtr[1] ? _shifted_WIRE_15_addr : _shifted_WIRE_13_addr; + wire [6:0] _shifted_T_97_idx = deqPtr[1] ? _shifted_WIRE_15_idx : _shifted_WIRE_13_idx; + wire _shifted_T_97_trap = + deqPtr[1] ? _shifted_WIRE_15_trap : _shifted_WIRE_13_trap; + wire _shifted_T_97_isControlFlow = + deqPtr[1] ? _shifted_WIRE_15_isControlFlow : _shifted_WIRE_13_isControlFlow; + wire _shifted_T_97_isBranch = + deqPtr[1] ? _shifted_WIRE_15_isBranch : _shifted_WIRE_13_isBranch; + wire _shifted_T_97_isVector = + deqPtr[1] ? _shifted_WIRE_15_isVector : _shifted_WIRE_13_isVector; + wire _shifted_T_97_resetsVstart = + deqPtr[1] ? _shifted_WIRE_15_resetsVstart : _shifted_WIRE_13_resetsVstart; + wire _shifted_T_97_linkOk = + deqPtr[1] ? _shifted_WIRE_15_linkOk : _shifted_WIRE_13_linkOk; + wire _shifted_T_97_isEcall = + deqPtr[1] ? _shifted_WIRE_15_isEcall : _shifted_WIRE_13_isEcall; + wire _shifted_T_97_isMpause = + deqPtr[1] ? _shifted_WIRE_15_isMpause : _shifted_WIRE_13_isMpause; + wire _shifted_T_97_isTile = + deqPtr[1] ? _shifted_WIRE_15_isTile : _shifted_WIRE_13_isTile; + wire [31:0] _shifted_T_100_addr = + deqPtr[1] ? _shifted_WIRE_16_addr : _shifted_WIRE_14_addr; + wire [6:0] _shifted_T_100_idx = + deqPtr[1] ? _shifted_WIRE_16_idx : _shifted_WIRE_14_idx; + wire _shifted_T_100_trap = + deqPtr[1] ? _shifted_WIRE_16_trap : _shifted_WIRE_14_trap; + wire _shifted_T_100_isControlFlow = + deqPtr[1] ? _shifted_WIRE_16_isControlFlow : _shifted_WIRE_14_isControlFlow; + wire _shifted_T_100_isBranch = + deqPtr[1] ? _shifted_WIRE_16_isBranch : _shifted_WIRE_14_isBranch; + wire _shifted_T_100_isVector = + deqPtr[1] ? _shifted_WIRE_16_isVector : _shifted_WIRE_14_isVector; + wire _shifted_T_100_resetsVstart = + deqPtr[1] ? _shifted_WIRE_16_resetsVstart : _shifted_WIRE_14_resetsVstart; + wire _shifted_T_100_linkOk = + deqPtr[1] ? _shifted_WIRE_16_linkOk : _shifted_WIRE_14_linkOk; + wire _shifted_T_100_isEcall = + deqPtr[1] ? _shifted_WIRE_16_isEcall : _shifted_WIRE_14_isEcall; + wire _shifted_T_100_isMpause = + deqPtr[1] ? _shifted_WIRE_16_isMpause : _shifted_WIRE_14_isMpause; + wire _shifted_T_100_isTile = + deqPtr[1] ? _shifted_WIRE_16_isTile : _shifted_WIRE_14_isTile; + wire [31:0] _shifted_T_103_addr = + deqPtr[1] + ? (deqPtr[2] ? (deqPtr[3] ? buffer_13_addr : buffer_5_addr) : _shifted_T_52_addr) + : _shifted_WIRE_15_addr; + wire [6:0] _shifted_T_103_idx = + deqPtr[1] + ? (deqPtr[2] ? (deqPtr[3] ? buffer_13_idx : buffer_5_idx) : _shifted_T_52_idx) + : _shifted_WIRE_15_idx; + wire _shifted_T_103_trap = + deqPtr[1] + ? (deqPtr[2] ? (deqPtr[3] ? buffer_13_trap : buffer_5_trap) : _shifted_T_52_trap) + : _shifted_WIRE_15_trap; + wire _shifted_T_103_isControlFlow = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isControlFlow : buffer_5_isControlFlow) + : _shifted_T_52_isControlFlow) + : _shifted_WIRE_15_isControlFlow; + wire _shifted_T_103_isBranch = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isBranch : buffer_5_isBranch) + : _shifted_T_52_isBranch) + : _shifted_WIRE_15_isBranch; + wire _shifted_T_103_isVector = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isVector : buffer_5_isVector) + : _shifted_T_52_isVector) + : _shifted_WIRE_15_isVector; + wire _shifted_T_103_resetsVstart = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_resetsVstart : buffer_5_resetsVstart) + : _shifted_T_52_resetsVstart) + : _shifted_WIRE_15_resetsVstart; + wire _shifted_T_103_linkOk = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_linkOk : buffer_5_linkOk) + : _shifted_T_52_linkOk) + : _shifted_WIRE_15_linkOk; + wire _shifted_T_103_isEcall = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isEcall : buffer_5_isEcall) + : _shifted_T_52_isEcall) + : _shifted_WIRE_15_isEcall; + wire _shifted_T_103_isMpause = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isMpause : buffer_5_isMpause) + : _shifted_T_52_isMpause) + : _shifted_WIRE_15_isMpause; + wire _shifted_T_103_isTile = + deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_13_isTile : buffer_5_isTile) + : _shifted_T_52_isTile) + : _shifted_WIRE_15_isTile; + wire matches_isTargetSlot = enqPtr == 4'h0; + wire matches_0 = (|io_enqValid) & matches_isTargetSlot; + wire matches_1 = (|(io_enqValid[4:1])) & (&enqPtr); + wire matches_isTargetSlot_2 = enqPtr == 4'hE; + wire _matches_T_484 = io_enqValid > 5'h2; + wire matches_2 = _matches_T_484 & matches_isTargetSlot_2; + wire matches_isTargetSlot_3 = enqPtr == 4'hD; + wire matches_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_3; + wire matches_isTargetSlot_4 = enqPtr == 4'hC; + wire _matches_T_488 = io_enqValid > 5'h4; + wire matches_4 = _matches_T_488 & matches_isTargetSlot_4; + wire matches_isTargetSlot_5 = enqPtr == 4'hB; + wire _matches_T_490 = io_enqValid > 5'h5; + wire matches_5 = _matches_T_490 & matches_isTargetSlot_5; + wire matches_isTargetSlot_6 = enqPtr == 4'hA; + wire _matches_T_492 = io_enqValid > 5'h6; + wire matches_6 = _matches_T_492 & matches_isTargetSlot_6; + wire matches_isTargetSlot_7 = enqPtr == 4'h9; + wire matches_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_7; + wire matches_isTargetSlot_8 = enqPtr == 4'h8; + wire _matches_T_496 = io_enqValid > 5'h8; + wire matches_8 = _matches_T_496 & matches_isTargetSlot_8; + wire matches_isTargetSlot_9 = enqPtr == 4'h7; + wire _matches_T_498 = io_enqValid > 5'h9; + wire matches_9 = _matches_T_498 & matches_isTargetSlot_9; + wire matches_isTargetSlot_10 = enqPtr == 4'h6; + wire _matches_T_500 = io_enqValid > 5'hA; + wire matches_10 = _matches_T_500 & matches_isTargetSlot_10; + wire matches_isTargetSlot_11 = enqPtr == 4'h5; + wire _matches_T_502 = io_enqValid > 5'hB; + wire matches_11 = _matches_T_502 & matches_isTargetSlot_11; + wire matches_isTargetSlot_12 = enqPtr == 4'h4; + wire _matches_T_504 = io_enqValid > 5'hC; + wire matches_12 = _matches_T_504 & matches_isTargetSlot_12; + wire matches_isTargetSlot_13 = enqPtr == 4'h3; + wire _matches_T_506 = io_enqValid > 5'hD; + wire matches_13 = _matches_T_506 & matches_isTargetSlot_13; + wire matches_isTargetSlot_14 = enqPtr == 4'h2; + wire _matches_T_508 = io_enqValid > 5'hE; + wire matches_14 = _matches_T_508 & matches_isTargetSlot_14; + wire matches_isTargetSlot_15 = enqPtr == 4'h1; + wire matches_15 = io_enqValid[4] & matches_isTargetSlot_15; + wire matches_1_0 = (|io_enqValid) & matches_isTargetSlot_15; + wire matches_1_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot; + wire matches_1_2 = _matches_T_484 & (&enqPtr); + wire matches_1_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_2; + wire matches_1_4 = _matches_T_488 & matches_isTargetSlot_3; + wire matches_1_5 = _matches_T_490 & matches_isTargetSlot_4; + wire matches_1_6 = _matches_T_492 & matches_isTargetSlot_5; + wire matches_1_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_6; + wire matches_1_8 = _matches_T_496 & matches_isTargetSlot_7; + wire matches_1_9 = _matches_T_498 & matches_isTargetSlot_8; + wire matches_1_10 = _matches_T_500 & matches_isTargetSlot_9; + wire matches_1_11 = _matches_T_502 & matches_isTargetSlot_10; + wire matches_1_12 = _matches_T_504 & matches_isTargetSlot_11; + wire matches_1_13 = _matches_T_506 & matches_isTargetSlot_12; + wire matches_1_14 = _matches_T_508 & matches_isTargetSlot_13; + wire matches_1_15 = io_enqValid[4] & matches_isTargetSlot_14; + wire matches_2_0 = (|io_enqValid) & matches_isTargetSlot_14; + wire matches_2_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_15; + wire matches_2_2 = _matches_T_484 & matches_isTargetSlot; + wire matches_2_3 = (|(io_enqValid[4:2])) & (&enqPtr); + wire matches_2_4 = _matches_T_488 & matches_isTargetSlot_2; + wire matches_2_5 = _matches_T_490 & matches_isTargetSlot_3; + wire matches_2_6 = _matches_T_492 & matches_isTargetSlot_4; + wire matches_2_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_5; + wire matches_2_8 = _matches_T_496 & matches_isTargetSlot_6; + wire matches_2_9 = _matches_T_498 & matches_isTargetSlot_7; + wire matches_2_10 = _matches_T_500 & matches_isTargetSlot_8; + wire matches_2_11 = _matches_T_502 & matches_isTargetSlot_9; + wire matches_2_12 = _matches_T_504 & matches_isTargetSlot_10; + wire matches_2_13 = _matches_T_506 & matches_isTargetSlot_11; + wire matches_2_14 = _matches_T_508 & matches_isTargetSlot_12; + wire matches_2_15 = io_enqValid[4] & matches_isTargetSlot_13; + wire matches_3_0 = (|io_enqValid) & matches_isTargetSlot_13; + wire matches_3_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_14; + wire matches_3_2 = _matches_T_484 & matches_isTargetSlot_15; + wire matches_3_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot; + wire matches_3_4 = _matches_T_488 & (&enqPtr); + wire matches_3_5 = _matches_T_490 & matches_isTargetSlot_2; + wire matches_3_6 = _matches_T_492 & matches_isTargetSlot_3; + wire matches_3_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_4; + wire matches_3_8 = _matches_T_496 & matches_isTargetSlot_5; + wire matches_3_9 = _matches_T_498 & matches_isTargetSlot_6; + wire matches_3_10 = _matches_T_500 & matches_isTargetSlot_7; + wire matches_3_11 = _matches_T_502 & matches_isTargetSlot_8; + wire matches_3_12 = _matches_T_504 & matches_isTargetSlot_9; + wire matches_3_13 = _matches_T_506 & matches_isTargetSlot_10; + wire matches_3_14 = _matches_T_508 & matches_isTargetSlot_11; + wire matches_3_15 = io_enqValid[4] & matches_isTargetSlot_12; + wire matches_4_0 = (|io_enqValid) & matches_isTargetSlot_12; + wire matches_4_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_13; + wire matches_4_2 = _matches_T_484 & matches_isTargetSlot_14; + wire matches_4_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_15; + wire matches_4_4 = _matches_T_488 & matches_isTargetSlot; + wire matches_4_5 = _matches_T_490 & (&enqPtr); + wire matches_4_6 = _matches_T_492 & matches_isTargetSlot_2; + wire matches_4_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_3; + wire matches_4_8 = _matches_T_496 & matches_isTargetSlot_4; + wire matches_4_9 = _matches_T_498 & matches_isTargetSlot_5; + wire matches_4_10 = _matches_T_500 & matches_isTargetSlot_6; + wire matches_4_11 = _matches_T_502 & matches_isTargetSlot_7; + wire matches_4_12 = _matches_T_504 & matches_isTargetSlot_8; + wire matches_4_13 = _matches_T_506 & matches_isTargetSlot_9; + wire matches_4_14 = _matches_T_508 & matches_isTargetSlot_10; + wire matches_4_15 = io_enqValid[4] & matches_isTargetSlot_11; + wire matches_5_0 = (|io_enqValid) & matches_isTargetSlot_11; + wire matches_5_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_12; + wire matches_5_2 = _matches_T_484 & matches_isTargetSlot_13; + wire matches_5_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_14; + wire matches_5_4 = _matches_T_488 & matches_isTargetSlot_15; + wire matches_5_5 = _matches_T_490 & matches_isTargetSlot; + wire matches_5_6 = _matches_T_492 & (&enqPtr); + wire matches_5_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_2; + wire matches_5_8 = _matches_T_496 & matches_isTargetSlot_3; + wire matches_5_9 = _matches_T_498 & matches_isTargetSlot_4; + wire matches_5_10 = _matches_T_500 & matches_isTargetSlot_5; + wire matches_5_11 = _matches_T_502 & matches_isTargetSlot_6; + wire matches_5_12 = _matches_T_504 & matches_isTargetSlot_7; + wire matches_5_13 = _matches_T_506 & matches_isTargetSlot_8; + wire matches_5_14 = _matches_T_508 & matches_isTargetSlot_9; + wire matches_5_15 = io_enqValid[4] & matches_isTargetSlot_10; + wire matches_6_0 = (|io_enqValid) & matches_isTargetSlot_10; + wire matches_6_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_11; + wire matches_6_2 = _matches_T_484 & matches_isTargetSlot_12; + wire matches_6_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_13; + wire matches_6_4 = _matches_T_488 & matches_isTargetSlot_14; + wire matches_6_5 = _matches_T_490 & matches_isTargetSlot_15; + wire matches_6_6 = _matches_T_492 & matches_isTargetSlot; + wire matches_6_7 = (|(io_enqValid[4:3])) & (&enqPtr); + wire matches_6_8 = _matches_T_496 & matches_isTargetSlot_2; + wire matches_6_9 = _matches_T_498 & matches_isTargetSlot_3; + wire matches_6_10 = _matches_T_500 & matches_isTargetSlot_4; + wire matches_6_11 = _matches_T_502 & matches_isTargetSlot_5; + wire matches_6_12 = _matches_T_504 & matches_isTargetSlot_6; + wire matches_6_13 = _matches_T_506 & matches_isTargetSlot_7; + wire matches_6_14 = _matches_T_508 & matches_isTargetSlot_8; + wire matches_6_15 = io_enqValid[4] & matches_isTargetSlot_9; + wire matches_7_0 = (|io_enqValid) & matches_isTargetSlot_9; + wire matches_7_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_10; + wire matches_7_2 = _matches_T_484 & matches_isTargetSlot_11; + wire matches_7_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_12; + wire matches_7_4 = _matches_T_488 & matches_isTargetSlot_13; + wire matches_7_5 = _matches_T_490 & matches_isTargetSlot_14; + wire matches_7_6 = _matches_T_492 & matches_isTargetSlot_15; + wire matches_7_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot; + wire matches_7_8 = _matches_T_496 & (&enqPtr); + wire matches_7_9 = _matches_T_498 & matches_isTargetSlot_2; + wire matches_7_10 = _matches_T_500 & matches_isTargetSlot_3; + wire matches_7_11 = _matches_T_502 & matches_isTargetSlot_4; + wire matches_7_12 = _matches_T_504 & matches_isTargetSlot_5; + wire matches_7_13 = _matches_T_506 & matches_isTargetSlot_6; + wire matches_7_14 = _matches_T_508 & matches_isTargetSlot_7; + wire matches_7_15 = io_enqValid[4] & matches_isTargetSlot_8; + wire matches_8_0 = (|io_enqValid) & matches_isTargetSlot_8; + wire matches_8_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_9; + wire matches_8_2 = _matches_T_484 & matches_isTargetSlot_10; + wire matches_8_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_11; + wire matches_8_4 = _matches_T_488 & matches_isTargetSlot_12; + wire matches_8_5 = _matches_T_490 & matches_isTargetSlot_13; + wire matches_8_6 = _matches_T_492 & matches_isTargetSlot_14; + wire matches_8_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_15; + wire matches_8_8 = _matches_T_496 & matches_isTargetSlot; + wire matches_8_9 = _matches_T_498 & (&enqPtr); + wire matches_8_10 = _matches_T_500 & matches_isTargetSlot_2; + wire matches_8_11 = _matches_T_502 & matches_isTargetSlot_3; + wire matches_8_12 = _matches_T_504 & matches_isTargetSlot_4; + wire matches_8_13 = _matches_T_506 & matches_isTargetSlot_5; + wire matches_8_14 = _matches_T_508 & matches_isTargetSlot_6; + wire matches_8_15 = io_enqValid[4] & matches_isTargetSlot_7; + wire matches_9_0 = (|io_enqValid) & matches_isTargetSlot_7; + wire matches_9_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_8; + wire matches_9_2 = _matches_T_484 & matches_isTargetSlot_9; + wire matches_9_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_10; + wire matches_9_4 = _matches_T_488 & matches_isTargetSlot_11; + wire matches_9_5 = _matches_T_490 & matches_isTargetSlot_12; + wire matches_9_6 = _matches_T_492 & matches_isTargetSlot_13; + wire matches_9_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_14; + wire matches_9_8 = _matches_T_496 & matches_isTargetSlot_15; + wire matches_9_9 = _matches_T_498 & matches_isTargetSlot; + wire matches_9_10 = _matches_T_500 & (&enqPtr); + wire matches_9_11 = _matches_T_502 & matches_isTargetSlot_2; + wire matches_9_12 = _matches_T_504 & matches_isTargetSlot_3; + wire matches_9_13 = _matches_T_506 & matches_isTargetSlot_4; + wire matches_9_14 = _matches_T_508 & matches_isTargetSlot_5; + wire matches_9_15 = io_enqValid[4] & matches_isTargetSlot_6; + wire matches_10_0 = (|io_enqValid) & matches_isTargetSlot_6; + wire matches_10_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_7; + wire matches_10_2 = _matches_T_484 & matches_isTargetSlot_8; + wire matches_10_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_9; + wire matches_10_4 = _matches_T_488 & matches_isTargetSlot_10; + wire matches_10_5 = _matches_T_490 & matches_isTargetSlot_11; + wire matches_10_6 = _matches_T_492 & matches_isTargetSlot_12; + wire matches_10_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_13; + wire matches_10_8 = _matches_T_496 & matches_isTargetSlot_14; + wire matches_10_9 = _matches_T_498 & matches_isTargetSlot_15; + wire matches_10_10 = _matches_T_500 & matches_isTargetSlot; + wire matches_10_11 = _matches_T_502 & (&enqPtr); + wire matches_10_12 = _matches_T_504 & matches_isTargetSlot_2; + wire matches_10_13 = _matches_T_506 & matches_isTargetSlot_3; + wire matches_10_14 = _matches_T_508 & matches_isTargetSlot_4; + wire matches_10_15 = io_enqValid[4] & matches_isTargetSlot_5; + wire matches_11_0 = (|io_enqValid) & matches_isTargetSlot_5; + wire matches_11_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_6; + wire matches_11_2 = _matches_T_484 & matches_isTargetSlot_7; + wire matches_11_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_8; + wire matches_11_4 = _matches_T_488 & matches_isTargetSlot_9; + wire matches_11_5 = _matches_T_490 & matches_isTargetSlot_10; + wire matches_11_6 = _matches_T_492 & matches_isTargetSlot_11; + wire matches_11_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_12; + wire matches_11_8 = _matches_T_496 & matches_isTargetSlot_13; + wire matches_11_9 = _matches_T_498 & matches_isTargetSlot_14; + wire matches_11_10 = _matches_T_500 & matches_isTargetSlot_15; + wire matches_11_11 = _matches_T_502 & matches_isTargetSlot; + wire matches_11_12 = _matches_T_504 & (&enqPtr); + wire matches_11_13 = _matches_T_506 & matches_isTargetSlot_2; + wire matches_11_14 = _matches_T_508 & matches_isTargetSlot_3; + wire matches_11_15 = io_enqValid[4] & matches_isTargetSlot_4; + wire matches_12_0 = (|io_enqValid) & matches_isTargetSlot_4; + wire matches_12_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_5; + wire matches_12_2 = _matches_T_484 & matches_isTargetSlot_6; + wire matches_12_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_7; + wire matches_12_4 = _matches_T_488 & matches_isTargetSlot_8; + wire matches_12_5 = _matches_T_490 & matches_isTargetSlot_9; + wire matches_12_6 = _matches_T_492 & matches_isTargetSlot_10; + wire matches_12_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_11; + wire matches_12_8 = _matches_T_496 & matches_isTargetSlot_12; + wire matches_12_9 = _matches_T_498 & matches_isTargetSlot_13; + wire matches_12_10 = _matches_T_500 & matches_isTargetSlot_14; + wire matches_12_11 = _matches_T_502 & matches_isTargetSlot_15; + wire matches_12_12 = _matches_T_504 & matches_isTargetSlot; + wire matches_12_13 = _matches_T_506 & (&enqPtr); + wire matches_12_14 = _matches_T_508 & matches_isTargetSlot_2; + wire matches_12_15 = io_enqValid[4] & matches_isTargetSlot_3; + wire matches_13_0 = (|io_enqValid) & matches_isTargetSlot_3; + wire matches_13_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_4; + wire matches_13_2 = _matches_T_484 & matches_isTargetSlot_5; + wire matches_13_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_6; + wire matches_13_4 = _matches_T_488 & matches_isTargetSlot_7; + wire matches_13_5 = _matches_T_490 & matches_isTargetSlot_8; + wire matches_13_6 = _matches_T_492 & matches_isTargetSlot_9; + wire matches_13_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_10; + wire matches_13_8 = _matches_T_496 & matches_isTargetSlot_11; + wire matches_13_9 = _matches_T_498 & matches_isTargetSlot_12; + wire matches_13_10 = _matches_T_500 & matches_isTargetSlot_13; + wire matches_13_11 = _matches_T_502 & matches_isTargetSlot_14; + wire matches_13_12 = _matches_T_504 & matches_isTargetSlot_15; + wire matches_13_13 = _matches_T_506 & matches_isTargetSlot; + wire matches_13_14 = _matches_T_508 & (&enqPtr); + wire matches_13_15 = io_enqValid[4] & matches_isTargetSlot_2; + wire matches_14_0 = (|io_enqValid) & matches_isTargetSlot_2; + wire matches_14_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_3; + wire matches_14_2 = _matches_T_484 & matches_isTargetSlot_4; + wire matches_14_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_5; + wire matches_14_4 = _matches_T_488 & matches_isTargetSlot_6; + wire matches_14_5 = _matches_T_490 & matches_isTargetSlot_7; + wire matches_14_6 = _matches_T_492 & matches_isTargetSlot_8; + wire matches_14_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_9; + wire matches_14_8 = _matches_T_496 & matches_isTargetSlot_10; + wire matches_14_9 = _matches_T_498 & matches_isTargetSlot_11; + wire matches_14_10 = _matches_T_500 & matches_isTargetSlot_12; + wire matches_14_11 = _matches_T_502 & matches_isTargetSlot_13; + wire matches_14_12 = _matches_T_504 & matches_isTargetSlot_14; + wire matches_14_13 = _matches_T_506 & matches_isTargetSlot_15; + wire matches_14_14 = _matches_T_508 & matches_isTargetSlot; + wire matches_14_15 = io_enqValid[4] & (&enqPtr); + wire matches_15_0 = (|io_enqValid) & (&enqPtr); + wire matches_15_1 = (|(io_enqValid[4:1])) & matches_isTargetSlot_2; + wire matches_15_2 = _matches_T_484 & matches_isTargetSlot_3; + wire matches_15_3 = (|(io_enqValid[4:2])) & matches_isTargetSlot_4; + wire matches_15_4 = _matches_T_488 & matches_isTargetSlot_5; + wire matches_15_5 = _matches_T_490 & matches_isTargetSlot_6; + wire matches_15_6 = _matches_T_492 & matches_isTargetSlot_7; + wire matches_15_7 = (|(io_enqValid[4:3])) & matches_isTargetSlot_8; + wire matches_15_8 = _matches_T_496 & matches_isTargetSlot_9; + wire matches_15_9 = _matches_T_498 & matches_isTargetSlot_10; + wire matches_15_10 = _matches_T_500 & matches_isTargetSlot_11; + wire matches_15_11 = _matches_T_502 & matches_isTargetSlot_12; + wire matches_15_12 = _matches_T_504 & matches_isTargetSlot_13; + wire matches_15_13 = _matches_T_506 & matches_isTargetSlot_14; + wire matches_15_14 = _matches_T_508 & matches_isTargetSlot_15; + wire matches_15_15 = io_enqValid[4] & matches_isTargetSlot; always @(posedge clock or posedge reset) begin if (reset) begin - stateReg_valid <= 1'h0; - stateReg_bits_fwd <= 1'h0; - stateReg_bits_op <= 4'h0; - stateReg_bits_target <= 32'h0; - stateReg_bits_linkValid <= 1'h0; - stateReg_bits_linkAddr <= 5'h0; - stateReg_bits_linkData <= 32'h0; + buffer_0_addr <= 32'h0; + buffer_0_idx <= 7'h0; + buffer_0_trap <= 1'h0; + buffer_0_isControlFlow <= 1'h0; + buffer_0_isBranch <= 1'h0; + buffer_0_isVector <= 1'h0; + buffer_0_resetsVstart <= 1'h0; + buffer_0_linkOk <= 1'h0; + buffer_0_isEcall <= 1'h0; + buffer_0_isMpause <= 1'h0; + buffer_0_isTile <= 1'h0; + buffer_1_addr <= 32'h0; + buffer_1_idx <= 7'h0; + buffer_1_trap <= 1'h0; + buffer_1_isControlFlow <= 1'h0; + buffer_1_isBranch <= 1'h0; + buffer_1_isVector <= 1'h0; + buffer_1_resetsVstart <= 1'h0; + buffer_1_linkOk <= 1'h0; + buffer_1_isEcall <= 1'h0; + buffer_1_isMpause <= 1'h0; + buffer_1_isTile <= 1'h0; + buffer_2_addr <= 32'h0; + buffer_2_idx <= 7'h0; + buffer_2_trap <= 1'h0; + buffer_2_isControlFlow <= 1'h0; + buffer_2_isBranch <= 1'h0; + buffer_2_isVector <= 1'h0; + buffer_2_resetsVstart <= 1'h0; + buffer_2_linkOk <= 1'h0; + buffer_2_isEcall <= 1'h0; + buffer_2_isMpause <= 1'h0; + buffer_2_isTile <= 1'h0; + buffer_3_addr <= 32'h0; + buffer_3_idx <= 7'h0; + buffer_3_trap <= 1'h0; + buffer_3_isControlFlow <= 1'h0; + buffer_3_isBranch <= 1'h0; + buffer_3_isVector <= 1'h0; + buffer_3_resetsVstart <= 1'h0; + buffer_3_linkOk <= 1'h0; + buffer_3_isEcall <= 1'h0; + buffer_3_isMpause <= 1'h0; + buffer_3_isTile <= 1'h0; + buffer_4_addr <= 32'h0; + buffer_4_idx <= 7'h0; + buffer_4_trap <= 1'h0; + buffer_4_isControlFlow <= 1'h0; + buffer_4_isBranch <= 1'h0; + buffer_4_isVector <= 1'h0; + buffer_4_resetsVstart <= 1'h0; + buffer_4_linkOk <= 1'h0; + buffer_4_isEcall <= 1'h0; + buffer_4_isMpause <= 1'h0; + buffer_4_isTile <= 1'h0; + buffer_5_addr <= 32'h0; + buffer_5_idx <= 7'h0; + buffer_5_trap <= 1'h0; + buffer_5_isControlFlow <= 1'h0; + buffer_5_isBranch <= 1'h0; + buffer_5_isVector <= 1'h0; + buffer_5_resetsVstart <= 1'h0; + buffer_5_linkOk <= 1'h0; + buffer_5_isEcall <= 1'h0; + buffer_5_isMpause <= 1'h0; + buffer_5_isTile <= 1'h0; + buffer_6_addr <= 32'h0; + buffer_6_idx <= 7'h0; + buffer_6_trap <= 1'h0; + buffer_6_isControlFlow <= 1'h0; + buffer_6_isBranch <= 1'h0; + buffer_6_isVector <= 1'h0; + buffer_6_resetsVstart <= 1'h0; + buffer_6_linkOk <= 1'h0; + buffer_6_isEcall <= 1'h0; + buffer_6_isMpause <= 1'h0; + buffer_6_isTile <= 1'h0; + buffer_7_addr <= 32'h0; + buffer_7_idx <= 7'h0; + buffer_7_trap <= 1'h0; + buffer_7_isControlFlow <= 1'h0; + buffer_7_isBranch <= 1'h0; + buffer_7_isVector <= 1'h0; + buffer_7_resetsVstart <= 1'h0; + buffer_7_linkOk <= 1'h0; + buffer_7_isEcall <= 1'h0; + buffer_7_isMpause <= 1'h0; + buffer_7_isTile <= 1'h0; + buffer_8_addr <= 32'h0; + buffer_8_idx <= 7'h0; + buffer_8_trap <= 1'h0; + buffer_8_isControlFlow <= 1'h0; + buffer_8_isBranch <= 1'h0; + buffer_8_isVector <= 1'h0; + buffer_8_resetsVstart <= 1'h0; + buffer_8_linkOk <= 1'h0; + buffer_8_isEcall <= 1'h0; + buffer_8_isMpause <= 1'h0; + buffer_8_isTile <= 1'h0; + buffer_9_addr <= 32'h0; + buffer_9_idx <= 7'h0; + buffer_9_trap <= 1'h0; + buffer_9_isControlFlow <= 1'h0; + buffer_9_isBranch <= 1'h0; + buffer_9_isVector <= 1'h0; + buffer_9_resetsVstart <= 1'h0; + buffer_9_linkOk <= 1'h0; + buffer_9_isEcall <= 1'h0; + buffer_9_isMpause <= 1'h0; + buffer_9_isTile <= 1'h0; + buffer_10_addr <= 32'h0; + buffer_10_idx <= 7'h0; + buffer_10_trap <= 1'h0; + buffer_10_isControlFlow <= 1'h0; + buffer_10_isBranch <= 1'h0; + buffer_10_isVector <= 1'h0; + buffer_10_resetsVstart <= 1'h0; + buffer_10_linkOk <= 1'h0; + buffer_10_isEcall <= 1'h0; + buffer_10_isMpause <= 1'h0; + buffer_10_isTile <= 1'h0; + buffer_11_addr <= 32'h0; + buffer_11_idx <= 7'h0; + buffer_11_trap <= 1'h0; + buffer_11_isControlFlow <= 1'h0; + buffer_11_isBranch <= 1'h0; + buffer_11_isVector <= 1'h0; + buffer_11_resetsVstart <= 1'h0; + buffer_11_linkOk <= 1'h0; + buffer_11_isEcall <= 1'h0; + buffer_11_isMpause <= 1'h0; + buffer_11_isTile <= 1'h0; + buffer_12_addr <= 32'h0; + buffer_12_idx <= 7'h0; + buffer_12_trap <= 1'h0; + buffer_12_isControlFlow <= 1'h0; + buffer_12_isBranch <= 1'h0; + buffer_12_isVector <= 1'h0; + buffer_12_resetsVstart <= 1'h0; + buffer_12_linkOk <= 1'h0; + buffer_12_isEcall <= 1'h0; + buffer_12_isMpause <= 1'h0; + buffer_12_isTile <= 1'h0; + buffer_13_addr <= 32'h0; + buffer_13_idx <= 7'h0; + buffer_13_trap <= 1'h0; + buffer_13_isControlFlow <= 1'h0; + buffer_13_isBranch <= 1'h0; + buffer_13_isVector <= 1'h0; + buffer_13_resetsVstart <= 1'h0; + buffer_13_linkOk <= 1'h0; + buffer_13_isEcall <= 1'h0; + buffer_13_isMpause <= 1'h0; + buffer_13_isTile <= 1'h0; + buffer_14_addr <= 32'h0; + buffer_14_idx <= 7'h0; + buffer_14_trap <= 1'h0; + buffer_14_isControlFlow <= 1'h0; + buffer_14_isBranch <= 1'h0; + buffer_14_isVector <= 1'h0; + buffer_14_resetsVstart <= 1'h0; + buffer_14_linkOk <= 1'h0; + buffer_14_isEcall <= 1'h0; + buffer_14_isMpause <= 1'h0; + buffer_14_isTile <= 1'h0; + buffer_15_addr <= 32'h0; + buffer_15_idx <= 7'h0; + buffer_15_trap <= 1'h0; + buffer_15_isControlFlow <= 1'h0; + buffer_15_isBranch <= 1'h0; + buffer_15_isVector <= 1'h0; + buffer_15_resetsVstart <= 1'h0; + buffer_15_linkOk <= 1'h0; + buffer_15_isEcall <= 1'h0; + buffer_15_isMpause <= 1'h0; + buffer_15_isTile <= 1'h0; + enqPtr <= 4'h0; + deqPtr <= 4'h0; + nEnqueued <= 5'h0; end else begin - stateReg_valid <= io_req_valid; - if (io_req_valid) begin - stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; - stateReg_bits_op <= io_req_bits_op; - stateReg_bits_target <= - io_req_bits_fwd - ? nextState_linkData - : _nextState_target_T ? io_target_data & 32'hFFFFFFFE : io_req_bits_target; - stateReg_bits_linkValid <= - io_req_valid & (|io_req_bits_link) - & (|{_nextState_target_T, io_req_bits_op == 4'h0}); - stateReg_bits_linkAddr <= io_req_bits_link; - stateReg_bits_linkData <= nextState_linkData; + if (|{matches_15, + matches_14, + matches_13, + matches_12, + matches_11, + matches_10, + matches_9, + matches_8, + matches_7, + matches_6, + matches_5, + matches_4, + matches_3, + matches_2, + matches_1, + matches_0}) begin + buffer_0_addr <= + (matches_0 ? io_enqData_0_addr : 32'h0) + | (matches_1 ? io_enqData_1_addr : 32'h0) + | (matches_2 ? io_enqData_2_addr : 32'h0) + | (matches_3 ? io_enqData_3_addr : 32'h0) + | (matches_4 ? io_enqData_4_addr : 32'h0) + | (matches_5 ? io_enqData_5_addr : 32'h0) + | (matches_6 ? io_enqData_6_addr : 32'h0) + | (matches_7 ? io_enqData_7_addr : 32'h0) + | (matches_8 ? io_enqData_8_addr : 32'h0) + | (matches_9 ? io_enqData_9_addr : 32'h0) + | (matches_10 ? io_enqData_10_addr : 32'h0) + | (matches_11 ? io_enqData_11_addr : 32'h0) + | (matches_12 ? io_enqData_12_addr : 32'h0) + | (matches_13 ? io_enqData_13_addr : 32'h0) + | (matches_14 ? io_enqData_14_addr : 32'h0) + | (matches_15 ? io_enqData_15_addr : 32'h0); + buffer_0_idx <= + (matches_0 ? io_enqData_0_idx : 7'h0) | (matches_1 ? io_enqData_1_idx : 7'h0) + | (matches_2 ? io_enqData_2_idx : 7'h0) | (matches_3 ? io_enqData_3_idx : 7'h0) + | (matches_4 ? io_enqData_4_idx : 7'h0) | (matches_5 ? io_enqData_5_idx : 7'h0) + | (matches_6 ? io_enqData_6_idx : 7'h0) | (matches_7 ? io_enqData_7_idx : 7'h0) + | (matches_8 ? io_enqData_8_idx : 7'h0) | (matches_9 ? io_enqData_9_idx : 7'h0) + | (matches_10 ? io_enqData_10_idx : 7'h0) + | (matches_11 ? io_enqData_11_idx : 7'h0) + | (matches_12 ? io_enqData_12_idx : 7'h0) + | (matches_13 ? io_enqData_13_idx : 7'h0) + | (matches_14 ? io_enqData_14_idx : 7'h0) + | (matches_15 ? io_enqData_15_idx : 7'h0); + buffer_0_trap <= + matches_0 & io_enqData_0_trap | matches_1 & io_enqData_1_trap | matches_2 + & io_enqData_2_trap | matches_3 & io_enqData_3_trap | matches_4 + & io_enqData_4_trap | matches_5 & io_enqData_5_trap | matches_6 + & io_enqData_6_trap | matches_7 & io_enqData_7_trap | matches_8 + & io_enqData_8_trap | matches_9 & io_enqData_9_trap | matches_10 + & io_enqData_10_trap | matches_11 & io_enqData_11_trap | matches_12 + & io_enqData_12_trap | matches_13 & io_enqData_13_trap | matches_14 + & io_enqData_14_trap | matches_15 & io_enqData_15_trap; + buffer_0_isControlFlow <= + matches_0 & io_enqData_0_isControlFlow | matches_1 & io_enqData_1_isControlFlow + | matches_2 & io_enqData_2_isControlFlow | matches_3 + & io_enqData_3_isControlFlow | matches_4 & io_enqData_4_isControlFlow + | matches_5 & io_enqData_5_isControlFlow | matches_6 + & io_enqData_6_isControlFlow | matches_7 & io_enqData_7_isControlFlow + | matches_8 & io_enqData_8_isControlFlow | matches_9 + & io_enqData_9_isControlFlow | matches_10 & io_enqData_10_isControlFlow + | matches_11 & io_enqData_11_isControlFlow | matches_12 + & io_enqData_12_isControlFlow | matches_13 & io_enqData_13_isControlFlow + | matches_14 & io_enqData_14_isControlFlow | matches_15 + & io_enqData_15_isControlFlow; + buffer_0_isBranch <= + matches_0 & io_enqData_0_isBranch | matches_1 & io_enqData_1_isBranch + | matches_2 & io_enqData_2_isBranch | matches_3 & io_enqData_3_isBranch + | matches_4 & io_enqData_4_isBranch | matches_5 & io_enqData_5_isBranch + | matches_6 & io_enqData_6_isBranch | matches_7 & io_enqData_7_isBranch + | matches_8 & io_enqData_8_isBranch | matches_9 & io_enqData_9_isBranch + | matches_10 & io_enqData_10_isBranch | matches_11 & io_enqData_11_isBranch + | matches_12 & io_enqData_12_isBranch | matches_13 & io_enqData_13_isBranch + | matches_14 & io_enqData_14_isBranch | matches_15 & io_enqData_15_isBranch; + buffer_0_isVector <= + matches_0 & io_enqData_0_isVector | matches_1 & io_enqData_1_isVector + | matches_2 & io_enqData_2_isVector | matches_3 & io_enqData_3_isVector + | matches_4 & io_enqData_4_isVector | matches_5 & io_enqData_5_isVector + | matches_6 & io_enqData_6_isVector | matches_7 & io_enqData_7_isVector + | matches_8 & io_enqData_8_isVector | matches_9 & io_enqData_9_isVector + | matches_10 & io_enqData_10_isVector | matches_11 & io_enqData_11_isVector + | matches_12 & io_enqData_12_isVector | matches_13 & io_enqData_13_isVector + | matches_14 & io_enqData_14_isVector | matches_15 & io_enqData_15_isVector; + buffer_0_resetsVstart <= + matches_0 & io_enqData_0_resetsVstart | matches_1 & io_enqData_1_resetsVstart + | matches_2 & io_enqData_2_resetsVstart | matches_3 & io_enqData_3_resetsVstart + | matches_4 & io_enqData_4_resetsVstart | matches_5 & io_enqData_5_resetsVstart + | matches_6 & io_enqData_6_resetsVstart | matches_7 & io_enqData_7_resetsVstart + | matches_8 & io_enqData_8_resetsVstart | matches_9 & io_enqData_9_resetsVstart + | matches_10 & io_enqData_10_resetsVstart | matches_11 + & io_enqData_11_resetsVstart | matches_12 & io_enqData_12_resetsVstart + | matches_13 & io_enqData_13_resetsVstart | matches_14 + & io_enqData_14_resetsVstart | matches_15 & io_enqData_15_resetsVstart; + buffer_0_linkOk <= + matches_0 & io_enqData_0_linkOk | matches_1 & io_enqData_1_linkOk | matches_2 + & io_enqData_2_linkOk | matches_3 & io_enqData_3_linkOk | matches_4 + & io_enqData_4_linkOk | matches_5 & io_enqData_5_linkOk | matches_6 + & io_enqData_6_linkOk | matches_7 & io_enqData_7_linkOk | matches_8 + & io_enqData_8_linkOk | matches_9 & io_enqData_9_linkOk | matches_10 + & io_enqData_10_linkOk | matches_11 & io_enqData_11_linkOk | matches_12 + & io_enqData_12_linkOk | matches_13 & io_enqData_13_linkOk | matches_14 + & io_enqData_14_linkOk | matches_15 & io_enqData_15_linkOk; + buffer_0_isEcall <= + matches_0 & io_enqData_0_isEcall | matches_1 & io_enqData_1_isEcall | matches_2 + & io_enqData_2_isEcall | matches_3 & io_enqData_3_isEcall | matches_4 + & io_enqData_4_isEcall | matches_5 & io_enqData_5_isEcall | matches_6 + & io_enqData_6_isEcall | matches_7 & io_enqData_7_isEcall | matches_8 + & io_enqData_8_isEcall | matches_9 & io_enqData_9_isEcall | matches_10 + & io_enqData_10_isEcall | matches_11 & io_enqData_11_isEcall | matches_12 + & io_enqData_12_isEcall | matches_13 & io_enqData_13_isEcall | matches_14 + & io_enqData_14_isEcall | matches_15 & io_enqData_15_isEcall; + buffer_0_isMpause <= + matches_0 & io_enqData_0_isMpause | matches_1 & io_enqData_1_isMpause + | matches_2 & io_enqData_2_isMpause | matches_3 & io_enqData_3_isMpause + | matches_4 & io_enqData_4_isMpause | matches_5 & io_enqData_5_isMpause + | matches_6 & io_enqData_6_isMpause | matches_7 & io_enqData_7_isMpause + | matches_8 & io_enqData_8_isMpause | matches_9 & io_enqData_9_isMpause + | matches_10 & io_enqData_10_isMpause | matches_11 & io_enqData_11_isMpause + | matches_12 & io_enqData_12_isMpause | matches_13 & io_enqData_13_isMpause + | matches_14 & io_enqData_14_isMpause | matches_15 & io_enqData_15_isMpause; + buffer_0_isTile <= + matches_0 & io_enqData_0_isTile | matches_1 & io_enqData_1_isTile | matches_2 + & io_enqData_2_isTile | matches_3 & io_enqData_3_isTile | matches_4 + & io_enqData_4_isTile | matches_5 & io_enqData_5_isTile | matches_6 + & io_enqData_6_isTile | matches_7 & io_enqData_7_isTile | matches_8 + & io_enqData_8_isTile | matches_9 & io_enqData_9_isTile | matches_10 + & io_enqData_10_isTile | matches_11 & io_enqData_11_isTile | matches_12 + & io_enqData_12_isTile | matches_13 & io_enqData_13_isTile | matches_14 + & io_enqData_14_isTile | matches_15 & io_enqData_15_isTile; + end + if (|{matches_1_15, + matches_1_14, + matches_1_13, + matches_1_12, + matches_1_11, + matches_1_10, + matches_1_9, + matches_1_8, + matches_1_7, + matches_1_6, + matches_1_5, + matches_1_4, + matches_1_3, + matches_1_2, + matches_1_1, + matches_1_0}) begin + buffer_1_addr <= + (matches_1_0 ? io_enqData_0_addr : 32'h0) + | (matches_1_1 ? io_enqData_1_addr : 32'h0) + | (matches_1_2 ? io_enqData_2_addr : 32'h0) + | (matches_1_3 ? io_enqData_3_addr : 32'h0) + | (matches_1_4 ? io_enqData_4_addr : 32'h0) + | (matches_1_5 ? io_enqData_5_addr : 32'h0) + | (matches_1_6 ? io_enqData_6_addr : 32'h0) + | (matches_1_7 ? io_enqData_7_addr : 32'h0) + | (matches_1_8 ? io_enqData_8_addr : 32'h0) + | (matches_1_9 ? io_enqData_9_addr : 32'h0) + | (matches_1_10 ? io_enqData_10_addr : 32'h0) + | (matches_1_11 ? io_enqData_11_addr : 32'h0) + | (matches_1_12 ? io_enqData_12_addr : 32'h0) + | (matches_1_13 ? io_enqData_13_addr : 32'h0) + | (matches_1_14 ? io_enqData_14_addr : 32'h0) + | (matches_1_15 ? io_enqData_15_addr : 32'h0); + buffer_1_idx <= + (matches_1_0 ? io_enqData_0_idx : 7'h0) + | (matches_1_1 ? io_enqData_1_idx : 7'h0) + | (matches_1_2 ? io_enqData_2_idx : 7'h0) + | (matches_1_3 ? io_enqData_3_idx : 7'h0) + | (matches_1_4 ? io_enqData_4_idx : 7'h0) + | (matches_1_5 ? io_enqData_5_idx : 7'h0) + | (matches_1_6 ? io_enqData_6_idx : 7'h0) + | (matches_1_7 ? io_enqData_7_idx : 7'h0) + | (matches_1_8 ? io_enqData_8_idx : 7'h0) + | (matches_1_9 ? io_enqData_9_idx : 7'h0) + | (matches_1_10 ? io_enqData_10_idx : 7'h0) + | (matches_1_11 ? io_enqData_11_idx : 7'h0) + | (matches_1_12 ? io_enqData_12_idx : 7'h0) + | (matches_1_13 ? io_enqData_13_idx : 7'h0) + | (matches_1_14 ? io_enqData_14_idx : 7'h0) + | (matches_1_15 ? io_enqData_15_idx : 7'h0); + buffer_1_trap <= + matches_1_0 & io_enqData_0_trap | matches_1_1 & io_enqData_1_trap | matches_1_2 + & io_enqData_2_trap | matches_1_3 & io_enqData_3_trap | matches_1_4 + & io_enqData_4_trap | matches_1_5 & io_enqData_5_trap | matches_1_6 + & io_enqData_6_trap | matches_1_7 & io_enqData_7_trap | matches_1_8 + & io_enqData_8_trap | matches_1_9 & io_enqData_9_trap | matches_1_10 + & io_enqData_10_trap | matches_1_11 & io_enqData_11_trap | matches_1_12 + & io_enqData_12_trap | matches_1_13 & io_enqData_13_trap | matches_1_14 + & io_enqData_14_trap | matches_1_15 & io_enqData_15_trap; + buffer_1_isControlFlow <= + matches_1_0 & io_enqData_0_isControlFlow | matches_1_1 + & io_enqData_1_isControlFlow | matches_1_2 & io_enqData_2_isControlFlow + | matches_1_3 & io_enqData_3_isControlFlow | matches_1_4 + & io_enqData_4_isControlFlow | matches_1_5 & io_enqData_5_isControlFlow + | matches_1_6 & io_enqData_6_isControlFlow | matches_1_7 + & io_enqData_7_isControlFlow | matches_1_8 & io_enqData_8_isControlFlow + | matches_1_9 & io_enqData_9_isControlFlow | matches_1_10 + & io_enqData_10_isControlFlow | matches_1_11 & io_enqData_11_isControlFlow + | matches_1_12 & io_enqData_12_isControlFlow | matches_1_13 + & io_enqData_13_isControlFlow | matches_1_14 & io_enqData_14_isControlFlow + | matches_1_15 & io_enqData_15_isControlFlow; + buffer_1_isBranch <= + matches_1_0 & io_enqData_0_isBranch | matches_1_1 & io_enqData_1_isBranch + | matches_1_2 & io_enqData_2_isBranch | matches_1_3 & io_enqData_3_isBranch + | matches_1_4 & io_enqData_4_isBranch | matches_1_5 & io_enqData_5_isBranch + | matches_1_6 & io_enqData_6_isBranch | matches_1_7 & io_enqData_7_isBranch + | matches_1_8 & io_enqData_8_isBranch | matches_1_9 & io_enqData_9_isBranch + | matches_1_10 & io_enqData_10_isBranch | matches_1_11 & io_enqData_11_isBranch + | matches_1_12 & io_enqData_12_isBranch | matches_1_13 & io_enqData_13_isBranch + | matches_1_14 & io_enqData_14_isBranch | matches_1_15 & io_enqData_15_isBranch; + buffer_1_isVector <= + matches_1_0 & io_enqData_0_isVector | matches_1_1 & io_enqData_1_isVector + | matches_1_2 & io_enqData_2_isVector | matches_1_3 & io_enqData_3_isVector + | matches_1_4 & io_enqData_4_isVector | matches_1_5 & io_enqData_5_isVector + | matches_1_6 & io_enqData_6_isVector | matches_1_7 & io_enqData_7_isVector + | matches_1_8 & io_enqData_8_isVector | matches_1_9 & io_enqData_9_isVector + | matches_1_10 & io_enqData_10_isVector | matches_1_11 & io_enqData_11_isVector + | matches_1_12 & io_enqData_12_isVector | matches_1_13 & io_enqData_13_isVector + | matches_1_14 & io_enqData_14_isVector | matches_1_15 & io_enqData_15_isVector; + buffer_1_resetsVstart <= + matches_1_0 & io_enqData_0_resetsVstart | matches_1_1 + & io_enqData_1_resetsVstart | matches_1_2 & io_enqData_2_resetsVstart + | matches_1_3 & io_enqData_3_resetsVstart | matches_1_4 + & io_enqData_4_resetsVstart | matches_1_5 & io_enqData_5_resetsVstart + | matches_1_6 & io_enqData_6_resetsVstart | matches_1_7 + & io_enqData_7_resetsVstart | matches_1_8 & io_enqData_8_resetsVstart + | matches_1_9 & io_enqData_9_resetsVstart | matches_1_10 + & io_enqData_10_resetsVstart | matches_1_11 & io_enqData_11_resetsVstart + | matches_1_12 & io_enqData_12_resetsVstart | matches_1_13 + & io_enqData_13_resetsVstart | matches_1_14 & io_enqData_14_resetsVstart + | matches_1_15 & io_enqData_15_resetsVstart; + buffer_1_linkOk <= + matches_1_0 & io_enqData_0_linkOk | matches_1_1 & io_enqData_1_linkOk + | matches_1_2 & io_enqData_2_linkOk | matches_1_3 & io_enqData_3_linkOk + | matches_1_4 & io_enqData_4_linkOk | matches_1_5 & io_enqData_5_linkOk + | matches_1_6 & io_enqData_6_linkOk | matches_1_7 & io_enqData_7_linkOk + | matches_1_8 & io_enqData_8_linkOk | matches_1_9 & io_enqData_9_linkOk + | matches_1_10 & io_enqData_10_linkOk | matches_1_11 & io_enqData_11_linkOk + | matches_1_12 & io_enqData_12_linkOk | matches_1_13 & io_enqData_13_linkOk + | matches_1_14 & io_enqData_14_linkOk | matches_1_15 & io_enqData_15_linkOk; + buffer_1_isEcall <= + matches_1_0 & io_enqData_0_isEcall | matches_1_1 & io_enqData_1_isEcall + | matches_1_2 & io_enqData_2_isEcall | matches_1_3 & io_enqData_3_isEcall + | matches_1_4 & io_enqData_4_isEcall | matches_1_5 & io_enqData_5_isEcall + | matches_1_6 & io_enqData_6_isEcall | matches_1_7 & io_enqData_7_isEcall + | matches_1_8 & io_enqData_8_isEcall | matches_1_9 & io_enqData_9_isEcall + | matches_1_10 & io_enqData_10_isEcall | matches_1_11 & io_enqData_11_isEcall + | matches_1_12 & io_enqData_12_isEcall | matches_1_13 & io_enqData_13_isEcall + | matches_1_14 & io_enqData_14_isEcall | matches_1_15 & io_enqData_15_isEcall; + buffer_1_isMpause <= + matches_1_0 & io_enqData_0_isMpause | matches_1_1 & io_enqData_1_isMpause + | matches_1_2 & io_enqData_2_isMpause | matches_1_3 & io_enqData_3_isMpause + | matches_1_4 & io_enqData_4_isMpause | matches_1_5 & io_enqData_5_isMpause + | matches_1_6 & io_enqData_6_isMpause | matches_1_7 & io_enqData_7_isMpause + | matches_1_8 & io_enqData_8_isMpause | matches_1_9 & io_enqData_9_isMpause + | matches_1_10 & io_enqData_10_isMpause | matches_1_11 & io_enqData_11_isMpause + | matches_1_12 & io_enqData_12_isMpause | matches_1_13 & io_enqData_13_isMpause + | matches_1_14 & io_enqData_14_isMpause | matches_1_15 & io_enqData_15_isMpause; + buffer_1_isTile <= + matches_1_0 & io_enqData_0_isTile | matches_1_1 & io_enqData_1_isTile + | matches_1_2 & io_enqData_2_isTile | matches_1_3 & io_enqData_3_isTile + | matches_1_4 & io_enqData_4_isTile | matches_1_5 & io_enqData_5_isTile + | matches_1_6 & io_enqData_6_isTile | matches_1_7 & io_enqData_7_isTile + | matches_1_8 & io_enqData_8_isTile | matches_1_9 & io_enqData_9_isTile + | matches_1_10 & io_enqData_10_isTile | matches_1_11 & io_enqData_11_isTile + | matches_1_12 & io_enqData_12_isTile | matches_1_13 & io_enqData_13_isTile + | matches_1_14 & io_enqData_14_isTile | matches_1_15 & io_enqData_15_isTile; + end + if (|{matches_2_15, + matches_2_14, + matches_2_13, + matches_2_12, + matches_2_11, + matches_2_10, + matches_2_9, + matches_2_8, + matches_2_7, + matches_2_6, + matches_2_5, + matches_2_4, + matches_2_3, + matches_2_2, + matches_2_1, + matches_2_0}) begin + buffer_2_addr <= + (matches_2_0 ? io_enqData_0_addr : 32'h0) + | (matches_2_1 ? io_enqData_1_addr : 32'h0) + | (matches_2_2 ? io_enqData_2_addr : 32'h0) + | (matches_2_3 ? io_enqData_3_addr : 32'h0) + | (matches_2_4 ? io_enqData_4_addr : 32'h0) + | (matches_2_5 ? io_enqData_5_addr : 32'h0) + | (matches_2_6 ? io_enqData_6_addr : 32'h0) + | (matches_2_7 ? io_enqData_7_addr : 32'h0) + | (matches_2_8 ? io_enqData_8_addr : 32'h0) + | (matches_2_9 ? io_enqData_9_addr : 32'h0) + | (matches_2_10 ? io_enqData_10_addr : 32'h0) + | (matches_2_11 ? io_enqData_11_addr : 32'h0) + | (matches_2_12 ? io_enqData_12_addr : 32'h0) + | (matches_2_13 ? io_enqData_13_addr : 32'h0) + | (matches_2_14 ? io_enqData_14_addr : 32'h0) + | (matches_2_15 ? io_enqData_15_addr : 32'h0); + buffer_2_idx <= + (matches_2_0 ? io_enqData_0_idx : 7'h0) + | (matches_2_1 ? io_enqData_1_idx : 7'h0) + | (matches_2_2 ? io_enqData_2_idx : 7'h0) + | (matches_2_3 ? io_enqData_3_idx : 7'h0) + | (matches_2_4 ? io_enqData_4_idx : 7'h0) + | (matches_2_5 ? io_enqData_5_idx : 7'h0) + | (matches_2_6 ? io_enqData_6_idx : 7'h0) + | (matches_2_7 ? io_enqData_7_idx : 7'h0) + | (matches_2_8 ? io_enqData_8_idx : 7'h0) + | (matches_2_9 ? io_enqData_9_idx : 7'h0) + | (matches_2_10 ? io_enqData_10_idx : 7'h0) + | (matches_2_11 ? io_enqData_11_idx : 7'h0) + | (matches_2_12 ? io_enqData_12_idx : 7'h0) + | (matches_2_13 ? io_enqData_13_idx : 7'h0) + | (matches_2_14 ? io_enqData_14_idx : 7'h0) + | (matches_2_15 ? io_enqData_15_idx : 7'h0); + buffer_2_trap <= + matches_2_0 & io_enqData_0_trap | matches_2_1 & io_enqData_1_trap | matches_2_2 + & io_enqData_2_trap | matches_2_3 & io_enqData_3_trap | matches_2_4 + & io_enqData_4_trap | matches_2_5 & io_enqData_5_trap | matches_2_6 + & io_enqData_6_trap | matches_2_7 & io_enqData_7_trap | matches_2_8 + & io_enqData_8_trap | matches_2_9 & io_enqData_9_trap | matches_2_10 + & io_enqData_10_trap | matches_2_11 & io_enqData_11_trap | matches_2_12 + & io_enqData_12_trap | matches_2_13 & io_enqData_13_trap | matches_2_14 + & io_enqData_14_trap | matches_2_15 & io_enqData_15_trap; + buffer_2_isControlFlow <= + matches_2_0 & io_enqData_0_isControlFlow | matches_2_1 + & io_enqData_1_isControlFlow | matches_2_2 & io_enqData_2_isControlFlow + | matches_2_3 & io_enqData_3_isControlFlow | matches_2_4 + & io_enqData_4_isControlFlow | matches_2_5 & io_enqData_5_isControlFlow + | matches_2_6 & io_enqData_6_isControlFlow | matches_2_7 + & io_enqData_7_isControlFlow | matches_2_8 & io_enqData_8_isControlFlow + | matches_2_9 & io_enqData_9_isControlFlow | matches_2_10 + & io_enqData_10_isControlFlow | matches_2_11 & io_enqData_11_isControlFlow + | matches_2_12 & io_enqData_12_isControlFlow | matches_2_13 + & io_enqData_13_isControlFlow | matches_2_14 & io_enqData_14_isControlFlow + | matches_2_15 & io_enqData_15_isControlFlow; + buffer_2_isBranch <= + matches_2_0 & io_enqData_0_isBranch | matches_2_1 & io_enqData_1_isBranch + | matches_2_2 & io_enqData_2_isBranch | matches_2_3 & io_enqData_3_isBranch + | matches_2_4 & io_enqData_4_isBranch | matches_2_5 & io_enqData_5_isBranch + | matches_2_6 & io_enqData_6_isBranch | matches_2_7 & io_enqData_7_isBranch + | matches_2_8 & io_enqData_8_isBranch | matches_2_9 & io_enqData_9_isBranch + | matches_2_10 & io_enqData_10_isBranch | matches_2_11 & io_enqData_11_isBranch + | matches_2_12 & io_enqData_12_isBranch | matches_2_13 & io_enqData_13_isBranch + | matches_2_14 & io_enqData_14_isBranch | matches_2_15 & io_enqData_15_isBranch; + buffer_2_isVector <= + matches_2_0 & io_enqData_0_isVector | matches_2_1 & io_enqData_1_isVector + | matches_2_2 & io_enqData_2_isVector | matches_2_3 & io_enqData_3_isVector + | matches_2_4 & io_enqData_4_isVector | matches_2_5 & io_enqData_5_isVector + | matches_2_6 & io_enqData_6_isVector | matches_2_7 & io_enqData_7_isVector + | matches_2_8 & io_enqData_8_isVector | matches_2_9 & io_enqData_9_isVector + | matches_2_10 & io_enqData_10_isVector | matches_2_11 & io_enqData_11_isVector + | matches_2_12 & io_enqData_12_isVector | matches_2_13 & io_enqData_13_isVector + | matches_2_14 & io_enqData_14_isVector | matches_2_15 & io_enqData_15_isVector; + buffer_2_resetsVstart <= + matches_2_0 & io_enqData_0_resetsVstart | matches_2_1 + & io_enqData_1_resetsVstart | matches_2_2 & io_enqData_2_resetsVstart + | matches_2_3 & io_enqData_3_resetsVstart | matches_2_4 + & io_enqData_4_resetsVstart | matches_2_5 & io_enqData_5_resetsVstart + | matches_2_6 & io_enqData_6_resetsVstart | matches_2_7 + & io_enqData_7_resetsVstart | matches_2_8 & io_enqData_8_resetsVstart + | matches_2_9 & io_enqData_9_resetsVstart | matches_2_10 + & io_enqData_10_resetsVstart | matches_2_11 & io_enqData_11_resetsVstart + | matches_2_12 & io_enqData_12_resetsVstart | matches_2_13 + & io_enqData_13_resetsVstart | matches_2_14 & io_enqData_14_resetsVstart + | matches_2_15 & io_enqData_15_resetsVstart; + buffer_2_linkOk <= + matches_2_0 & io_enqData_0_linkOk | matches_2_1 & io_enqData_1_linkOk + | matches_2_2 & io_enqData_2_linkOk | matches_2_3 & io_enqData_3_linkOk + | matches_2_4 & io_enqData_4_linkOk | matches_2_5 & io_enqData_5_linkOk + | matches_2_6 & io_enqData_6_linkOk | matches_2_7 & io_enqData_7_linkOk + | matches_2_8 & io_enqData_8_linkOk | matches_2_9 & io_enqData_9_linkOk + | matches_2_10 & io_enqData_10_linkOk | matches_2_11 & io_enqData_11_linkOk + | matches_2_12 & io_enqData_12_linkOk | matches_2_13 & io_enqData_13_linkOk + | matches_2_14 & io_enqData_14_linkOk | matches_2_15 & io_enqData_15_linkOk; + buffer_2_isEcall <= + matches_2_0 & io_enqData_0_isEcall | matches_2_1 & io_enqData_1_isEcall + | matches_2_2 & io_enqData_2_isEcall | matches_2_3 & io_enqData_3_isEcall + | matches_2_4 & io_enqData_4_isEcall | matches_2_5 & io_enqData_5_isEcall + | matches_2_6 & io_enqData_6_isEcall | matches_2_7 & io_enqData_7_isEcall + | matches_2_8 & io_enqData_8_isEcall | matches_2_9 & io_enqData_9_isEcall + | matches_2_10 & io_enqData_10_isEcall | matches_2_11 & io_enqData_11_isEcall + | matches_2_12 & io_enqData_12_isEcall | matches_2_13 & io_enqData_13_isEcall + | matches_2_14 & io_enqData_14_isEcall | matches_2_15 & io_enqData_15_isEcall; + buffer_2_isMpause <= + matches_2_0 & io_enqData_0_isMpause | matches_2_1 & io_enqData_1_isMpause + | matches_2_2 & io_enqData_2_isMpause | matches_2_3 & io_enqData_3_isMpause + | matches_2_4 & io_enqData_4_isMpause | matches_2_5 & io_enqData_5_isMpause + | matches_2_6 & io_enqData_6_isMpause | matches_2_7 & io_enqData_7_isMpause + | matches_2_8 & io_enqData_8_isMpause | matches_2_9 & io_enqData_9_isMpause + | matches_2_10 & io_enqData_10_isMpause | matches_2_11 & io_enqData_11_isMpause + | matches_2_12 & io_enqData_12_isMpause | matches_2_13 & io_enqData_13_isMpause + | matches_2_14 & io_enqData_14_isMpause | matches_2_15 & io_enqData_15_isMpause; + buffer_2_isTile <= + matches_2_0 & io_enqData_0_isTile | matches_2_1 & io_enqData_1_isTile + | matches_2_2 & io_enqData_2_isTile | matches_2_3 & io_enqData_3_isTile + | matches_2_4 & io_enqData_4_isTile | matches_2_5 & io_enqData_5_isTile + | matches_2_6 & io_enqData_6_isTile | matches_2_7 & io_enqData_7_isTile + | matches_2_8 & io_enqData_8_isTile | matches_2_9 & io_enqData_9_isTile + | matches_2_10 & io_enqData_10_isTile | matches_2_11 & io_enqData_11_isTile + | matches_2_12 & io_enqData_12_isTile | matches_2_13 & io_enqData_13_isTile + | matches_2_14 & io_enqData_14_isTile | matches_2_15 & io_enqData_15_isTile; + end + if (|{matches_3_15, + matches_3_14, + matches_3_13, + matches_3_12, + matches_3_11, + matches_3_10, + matches_3_9, + matches_3_8, + matches_3_7, + matches_3_6, + matches_3_5, + matches_3_4, + matches_3_3, + matches_3_2, + matches_3_1, + matches_3_0}) begin + buffer_3_addr <= + (matches_3_0 ? io_enqData_0_addr : 32'h0) + | (matches_3_1 ? io_enqData_1_addr : 32'h0) + | (matches_3_2 ? io_enqData_2_addr : 32'h0) + | (matches_3_3 ? io_enqData_3_addr : 32'h0) + | (matches_3_4 ? io_enqData_4_addr : 32'h0) + | (matches_3_5 ? io_enqData_5_addr : 32'h0) + | (matches_3_6 ? io_enqData_6_addr : 32'h0) + | (matches_3_7 ? io_enqData_7_addr : 32'h0) + | (matches_3_8 ? io_enqData_8_addr : 32'h0) + | (matches_3_9 ? io_enqData_9_addr : 32'h0) + | (matches_3_10 ? io_enqData_10_addr : 32'h0) + | (matches_3_11 ? io_enqData_11_addr : 32'h0) + | (matches_3_12 ? io_enqData_12_addr : 32'h0) + | (matches_3_13 ? io_enqData_13_addr : 32'h0) + | (matches_3_14 ? io_enqData_14_addr : 32'h0) + | (matches_3_15 ? io_enqData_15_addr : 32'h0); + buffer_3_idx <= + (matches_3_0 ? io_enqData_0_idx : 7'h0) + | (matches_3_1 ? io_enqData_1_idx : 7'h0) + | (matches_3_2 ? io_enqData_2_idx : 7'h0) + | (matches_3_3 ? io_enqData_3_idx : 7'h0) + | (matches_3_4 ? io_enqData_4_idx : 7'h0) + | (matches_3_5 ? io_enqData_5_idx : 7'h0) + | (matches_3_6 ? io_enqData_6_idx : 7'h0) + | (matches_3_7 ? io_enqData_7_idx : 7'h0) + | (matches_3_8 ? io_enqData_8_idx : 7'h0) + | (matches_3_9 ? io_enqData_9_idx : 7'h0) + | (matches_3_10 ? io_enqData_10_idx : 7'h0) + | (matches_3_11 ? io_enqData_11_idx : 7'h0) + | (matches_3_12 ? io_enqData_12_idx : 7'h0) + | (matches_3_13 ? io_enqData_13_idx : 7'h0) + | (matches_3_14 ? io_enqData_14_idx : 7'h0) + | (matches_3_15 ? io_enqData_15_idx : 7'h0); + buffer_3_trap <= + matches_3_0 & io_enqData_0_trap | matches_3_1 & io_enqData_1_trap | matches_3_2 + & io_enqData_2_trap | matches_3_3 & io_enqData_3_trap | matches_3_4 + & io_enqData_4_trap | matches_3_5 & io_enqData_5_trap | matches_3_6 + & io_enqData_6_trap | matches_3_7 & io_enqData_7_trap | matches_3_8 + & io_enqData_8_trap | matches_3_9 & io_enqData_9_trap | matches_3_10 + & io_enqData_10_trap | matches_3_11 & io_enqData_11_trap | matches_3_12 + & io_enqData_12_trap | matches_3_13 & io_enqData_13_trap | matches_3_14 + & io_enqData_14_trap | matches_3_15 & io_enqData_15_trap; + buffer_3_isControlFlow <= + matches_3_0 & io_enqData_0_isControlFlow | matches_3_1 + & io_enqData_1_isControlFlow | matches_3_2 & io_enqData_2_isControlFlow + | matches_3_3 & io_enqData_3_isControlFlow | matches_3_4 + & io_enqData_4_isControlFlow | matches_3_5 & io_enqData_5_isControlFlow + | matches_3_6 & io_enqData_6_isControlFlow | matches_3_7 + & io_enqData_7_isControlFlow | matches_3_8 & io_enqData_8_isControlFlow + | matches_3_9 & io_enqData_9_isControlFlow | matches_3_10 + & io_enqData_10_isControlFlow | matches_3_11 & io_enqData_11_isControlFlow + | matches_3_12 & io_enqData_12_isControlFlow | matches_3_13 + & io_enqData_13_isControlFlow | matches_3_14 & io_enqData_14_isControlFlow + | matches_3_15 & io_enqData_15_isControlFlow; + buffer_3_isBranch <= + matches_3_0 & io_enqData_0_isBranch | matches_3_1 & io_enqData_1_isBranch + | matches_3_2 & io_enqData_2_isBranch | matches_3_3 & io_enqData_3_isBranch + | matches_3_4 & io_enqData_4_isBranch | matches_3_5 & io_enqData_5_isBranch + | matches_3_6 & io_enqData_6_isBranch | matches_3_7 & io_enqData_7_isBranch + | matches_3_8 & io_enqData_8_isBranch | matches_3_9 & io_enqData_9_isBranch + | matches_3_10 & io_enqData_10_isBranch | matches_3_11 & io_enqData_11_isBranch + | matches_3_12 & io_enqData_12_isBranch | matches_3_13 & io_enqData_13_isBranch + | matches_3_14 & io_enqData_14_isBranch | matches_3_15 & io_enqData_15_isBranch; + buffer_3_isVector <= + matches_3_0 & io_enqData_0_isVector | matches_3_1 & io_enqData_1_isVector + | matches_3_2 & io_enqData_2_isVector | matches_3_3 & io_enqData_3_isVector + | matches_3_4 & io_enqData_4_isVector | matches_3_5 & io_enqData_5_isVector + | matches_3_6 & io_enqData_6_isVector | matches_3_7 & io_enqData_7_isVector + | matches_3_8 & io_enqData_8_isVector | matches_3_9 & io_enqData_9_isVector + | matches_3_10 & io_enqData_10_isVector | matches_3_11 & io_enqData_11_isVector + | matches_3_12 & io_enqData_12_isVector | matches_3_13 & io_enqData_13_isVector + | matches_3_14 & io_enqData_14_isVector | matches_3_15 & io_enqData_15_isVector; + buffer_3_resetsVstart <= + matches_3_0 & io_enqData_0_resetsVstart | matches_3_1 + & io_enqData_1_resetsVstart | matches_3_2 & io_enqData_2_resetsVstart + | matches_3_3 & io_enqData_3_resetsVstart | matches_3_4 + & io_enqData_4_resetsVstart | matches_3_5 & io_enqData_5_resetsVstart + | matches_3_6 & io_enqData_6_resetsVstart | matches_3_7 + & io_enqData_7_resetsVstart | matches_3_8 & io_enqData_8_resetsVstart + | matches_3_9 & io_enqData_9_resetsVstart | matches_3_10 + & io_enqData_10_resetsVstart | matches_3_11 & io_enqData_11_resetsVstart + | matches_3_12 & io_enqData_12_resetsVstart | matches_3_13 + & io_enqData_13_resetsVstart | matches_3_14 & io_enqData_14_resetsVstart + | matches_3_15 & io_enqData_15_resetsVstart; + buffer_3_linkOk <= + matches_3_0 & io_enqData_0_linkOk | matches_3_1 & io_enqData_1_linkOk + | matches_3_2 & io_enqData_2_linkOk | matches_3_3 & io_enqData_3_linkOk + | matches_3_4 & io_enqData_4_linkOk | matches_3_5 & io_enqData_5_linkOk + | matches_3_6 & io_enqData_6_linkOk | matches_3_7 & io_enqData_7_linkOk + | matches_3_8 & io_enqData_8_linkOk | matches_3_9 & io_enqData_9_linkOk + | matches_3_10 & io_enqData_10_linkOk | matches_3_11 & io_enqData_11_linkOk + | matches_3_12 & io_enqData_12_linkOk | matches_3_13 & io_enqData_13_linkOk + | matches_3_14 & io_enqData_14_linkOk | matches_3_15 & io_enqData_15_linkOk; + buffer_3_isEcall <= + matches_3_0 & io_enqData_0_isEcall | matches_3_1 & io_enqData_1_isEcall + | matches_3_2 & io_enqData_2_isEcall | matches_3_3 & io_enqData_3_isEcall + | matches_3_4 & io_enqData_4_isEcall | matches_3_5 & io_enqData_5_isEcall + | matches_3_6 & io_enqData_6_isEcall | matches_3_7 & io_enqData_7_isEcall + | matches_3_8 & io_enqData_8_isEcall | matches_3_9 & io_enqData_9_isEcall + | matches_3_10 & io_enqData_10_isEcall | matches_3_11 & io_enqData_11_isEcall + | matches_3_12 & io_enqData_12_isEcall | matches_3_13 & io_enqData_13_isEcall + | matches_3_14 & io_enqData_14_isEcall | matches_3_15 & io_enqData_15_isEcall; + buffer_3_isMpause <= + matches_3_0 & io_enqData_0_isMpause | matches_3_1 & io_enqData_1_isMpause + | matches_3_2 & io_enqData_2_isMpause | matches_3_3 & io_enqData_3_isMpause + | matches_3_4 & io_enqData_4_isMpause | matches_3_5 & io_enqData_5_isMpause + | matches_3_6 & io_enqData_6_isMpause | matches_3_7 & io_enqData_7_isMpause + | matches_3_8 & io_enqData_8_isMpause | matches_3_9 & io_enqData_9_isMpause + | matches_3_10 & io_enqData_10_isMpause | matches_3_11 & io_enqData_11_isMpause + | matches_3_12 & io_enqData_12_isMpause | matches_3_13 & io_enqData_13_isMpause + | matches_3_14 & io_enqData_14_isMpause | matches_3_15 & io_enqData_15_isMpause; + buffer_3_isTile <= + matches_3_0 & io_enqData_0_isTile | matches_3_1 & io_enqData_1_isTile + | matches_3_2 & io_enqData_2_isTile | matches_3_3 & io_enqData_3_isTile + | matches_3_4 & io_enqData_4_isTile | matches_3_5 & io_enqData_5_isTile + | matches_3_6 & io_enqData_6_isTile | matches_3_7 & io_enqData_7_isTile + | matches_3_8 & io_enqData_8_isTile | matches_3_9 & io_enqData_9_isTile + | matches_3_10 & io_enqData_10_isTile | matches_3_11 & io_enqData_11_isTile + | matches_3_12 & io_enqData_12_isTile | matches_3_13 & io_enqData_13_isTile + | matches_3_14 & io_enqData_14_isTile | matches_3_15 & io_enqData_15_isTile; + end + if (|{matches_4_15, + matches_4_14, + matches_4_13, + matches_4_12, + matches_4_11, + matches_4_10, + matches_4_9, + matches_4_8, + matches_4_7, + matches_4_6, + matches_4_5, + matches_4_4, + matches_4_3, + matches_4_2, + matches_4_1, + matches_4_0}) begin + buffer_4_addr <= + (matches_4_0 ? io_enqData_0_addr : 32'h0) + | (matches_4_1 ? io_enqData_1_addr : 32'h0) + | (matches_4_2 ? io_enqData_2_addr : 32'h0) + | (matches_4_3 ? io_enqData_3_addr : 32'h0) + | (matches_4_4 ? io_enqData_4_addr : 32'h0) + | (matches_4_5 ? io_enqData_5_addr : 32'h0) + | (matches_4_6 ? io_enqData_6_addr : 32'h0) + | (matches_4_7 ? io_enqData_7_addr : 32'h0) + | (matches_4_8 ? io_enqData_8_addr : 32'h0) + | (matches_4_9 ? io_enqData_9_addr : 32'h0) + | (matches_4_10 ? io_enqData_10_addr : 32'h0) + | (matches_4_11 ? io_enqData_11_addr : 32'h0) + | (matches_4_12 ? io_enqData_12_addr : 32'h0) + | (matches_4_13 ? io_enqData_13_addr : 32'h0) + | (matches_4_14 ? io_enqData_14_addr : 32'h0) + | (matches_4_15 ? io_enqData_15_addr : 32'h0); + buffer_4_idx <= + (matches_4_0 ? io_enqData_0_idx : 7'h0) + | (matches_4_1 ? io_enqData_1_idx : 7'h0) + | (matches_4_2 ? io_enqData_2_idx : 7'h0) + | (matches_4_3 ? io_enqData_3_idx : 7'h0) + | (matches_4_4 ? io_enqData_4_idx : 7'h0) + | (matches_4_5 ? io_enqData_5_idx : 7'h0) + | (matches_4_6 ? io_enqData_6_idx : 7'h0) + | (matches_4_7 ? io_enqData_7_idx : 7'h0) + | (matches_4_8 ? io_enqData_8_idx : 7'h0) + | (matches_4_9 ? io_enqData_9_idx : 7'h0) + | (matches_4_10 ? io_enqData_10_idx : 7'h0) + | (matches_4_11 ? io_enqData_11_idx : 7'h0) + | (matches_4_12 ? io_enqData_12_idx : 7'h0) + | (matches_4_13 ? io_enqData_13_idx : 7'h0) + | (matches_4_14 ? io_enqData_14_idx : 7'h0) + | (matches_4_15 ? io_enqData_15_idx : 7'h0); + buffer_4_trap <= + matches_4_0 & io_enqData_0_trap | matches_4_1 & io_enqData_1_trap | matches_4_2 + & io_enqData_2_trap | matches_4_3 & io_enqData_3_trap | matches_4_4 + & io_enqData_4_trap | matches_4_5 & io_enqData_5_trap | matches_4_6 + & io_enqData_6_trap | matches_4_7 & io_enqData_7_trap | matches_4_8 + & io_enqData_8_trap | matches_4_9 & io_enqData_9_trap | matches_4_10 + & io_enqData_10_trap | matches_4_11 & io_enqData_11_trap | matches_4_12 + & io_enqData_12_trap | matches_4_13 & io_enqData_13_trap | matches_4_14 + & io_enqData_14_trap | matches_4_15 & io_enqData_15_trap; + buffer_4_isControlFlow <= + matches_4_0 & io_enqData_0_isControlFlow | matches_4_1 + & io_enqData_1_isControlFlow | matches_4_2 & io_enqData_2_isControlFlow + | matches_4_3 & io_enqData_3_isControlFlow | matches_4_4 + & io_enqData_4_isControlFlow | matches_4_5 & io_enqData_5_isControlFlow + | matches_4_6 & io_enqData_6_isControlFlow | matches_4_7 + & io_enqData_7_isControlFlow | matches_4_8 & io_enqData_8_isControlFlow + | matches_4_9 & io_enqData_9_isControlFlow | matches_4_10 + & io_enqData_10_isControlFlow | matches_4_11 & io_enqData_11_isControlFlow + | matches_4_12 & io_enqData_12_isControlFlow | matches_4_13 + & io_enqData_13_isControlFlow | matches_4_14 & io_enqData_14_isControlFlow + | matches_4_15 & io_enqData_15_isControlFlow; + buffer_4_isBranch <= + matches_4_0 & io_enqData_0_isBranch | matches_4_1 & io_enqData_1_isBranch + | matches_4_2 & io_enqData_2_isBranch | matches_4_3 & io_enqData_3_isBranch + | matches_4_4 & io_enqData_4_isBranch | matches_4_5 & io_enqData_5_isBranch + | matches_4_6 & io_enqData_6_isBranch | matches_4_7 & io_enqData_7_isBranch + | matches_4_8 & io_enqData_8_isBranch | matches_4_9 & io_enqData_9_isBranch + | matches_4_10 & io_enqData_10_isBranch | matches_4_11 & io_enqData_11_isBranch + | matches_4_12 & io_enqData_12_isBranch | matches_4_13 & io_enqData_13_isBranch + | matches_4_14 & io_enqData_14_isBranch | matches_4_15 & io_enqData_15_isBranch; + buffer_4_isVector <= + matches_4_0 & io_enqData_0_isVector | matches_4_1 & io_enqData_1_isVector + | matches_4_2 & io_enqData_2_isVector | matches_4_3 & io_enqData_3_isVector + | matches_4_4 & io_enqData_4_isVector | matches_4_5 & io_enqData_5_isVector + | matches_4_6 & io_enqData_6_isVector | matches_4_7 & io_enqData_7_isVector + | matches_4_8 & io_enqData_8_isVector | matches_4_9 & io_enqData_9_isVector + | matches_4_10 & io_enqData_10_isVector | matches_4_11 & io_enqData_11_isVector + | matches_4_12 & io_enqData_12_isVector | matches_4_13 & io_enqData_13_isVector + | matches_4_14 & io_enqData_14_isVector | matches_4_15 & io_enqData_15_isVector; + buffer_4_resetsVstart <= + matches_4_0 & io_enqData_0_resetsVstart | matches_4_1 + & io_enqData_1_resetsVstart | matches_4_2 & io_enqData_2_resetsVstart + | matches_4_3 & io_enqData_3_resetsVstart | matches_4_4 + & io_enqData_4_resetsVstart | matches_4_5 & io_enqData_5_resetsVstart + | matches_4_6 & io_enqData_6_resetsVstart | matches_4_7 + & io_enqData_7_resetsVstart | matches_4_8 & io_enqData_8_resetsVstart + | matches_4_9 & io_enqData_9_resetsVstart | matches_4_10 + & io_enqData_10_resetsVstart | matches_4_11 & io_enqData_11_resetsVstart + | matches_4_12 & io_enqData_12_resetsVstart | matches_4_13 + & io_enqData_13_resetsVstart | matches_4_14 & io_enqData_14_resetsVstart + | matches_4_15 & io_enqData_15_resetsVstart; + buffer_4_linkOk <= + matches_4_0 & io_enqData_0_linkOk | matches_4_1 & io_enqData_1_linkOk + | matches_4_2 & io_enqData_2_linkOk | matches_4_3 & io_enqData_3_linkOk + | matches_4_4 & io_enqData_4_linkOk | matches_4_5 & io_enqData_5_linkOk + | matches_4_6 & io_enqData_6_linkOk | matches_4_7 & io_enqData_7_linkOk + | matches_4_8 & io_enqData_8_linkOk | matches_4_9 & io_enqData_9_linkOk + | matches_4_10 & io_enqData_10_linkOk | matches_4_11 & io_enqData_11_linkOk + | matches_4_12 & io_enqData_12_linkOk | matches_4_13 & io_enqData_13_linkOk + | matches_4_14 & io_enqData_14_linkOk | matches_4_15 & io_enqData_15_linkOk; + buffer_4_isEcall <= + matches_4_0 & io_enqData_0_isEcall | matches_4_1 & io_enqData_1_isEcall + | matches_4_2 & io_enqData_2_isEcall | matches_4_3 & io_enqData_3_isEcall + | matches_4_4 & io_enqData_4_isEcall | matches_4_5 & io_enqData_5_isEcall + | matches_4_6 & io_enqData_6_isEcall | matches_4_7 & io_enqData_7_isEcall + | matches_4_8 & io_enqData_8_isEcall | matches_4_9 & io_enqData_9_isEcall + | matches_4_10 & io_enqData_10_isEcall | matches_4_11 & io_enqData_11_isEcall + | matches_4_12 & io_enqData_12_isEcall | matches_4_13 & io_enqData_13_isEcall + | matches_4_14 & io_enqData_14_isEcall | matches_4_15 & io_enqData_15_isEcall; + buffer_4_isMpause <= + matches_4_0 & io_enqData_0_isMpause | matches_4_1 & io_enqData_1_isMpause + | matches_4_2 & io_enqData_2_isMpause | matches_4_3 & io_enqData_3_isMpause + | matches_4_4 & io_enqData_4_isMpause | matches_4_5 & io_enqData_5_isMpause + | matches_4_6 & io_enqData_6_isMpause | matches_4_7 & io_enqData_7_isMpause + | matches_4_8 & io_enqData_8_isMpause | matches_4_9 & io_enqData_9_isMpause + | matches_4_10 & io_enqData_10_isMpause | matches_4_11 & io_enqData_11_isMpause + | matches_4_12 & io_enqData_12_isMpause | matches_4_13 & io_enqData_13_isMpause + | matches_4_14 & io_enqData_14_isMpause | matches_4_15 & io_enqData_15_isMpause; + buffer_4_isTile <= + matches_4_0 & io_enqData_0_isTile | matches_4_1 & io_enqData_1_isTile + | matches_4_2 & io_enqData_2_isTile | matches_4_3 & io_enqData_3_isTile + | matches_4_4 & io_enqData_4_isTile | matches_4_5 & io_enqData_5_isTile + | matches_4_6 & io_enqData_6_isTile | matches_4_7 & io_enqData_7_isTile + | matches_4_8 & io_enqData_8_isTile | matches_4_9 & io_enqData_9_isTile + | matches_4_10 & io_enqData_10_isTile | matches_4_11 & io_enqData_11_isTile + | matches_4_12 & io_enqData_12_isTile | matches_4_13 & io_enqData_13_isTile + | matches_4_14 & io_enqData_14_isTile | matches_4_15 & io_enqData_15_isTile; end + if (|{matches_5_15, + matches_5_14, + matches_5_13, + matches_5_12, + matches_5_11, + matches_5_10, + matches_5_9, + matches_5_8, + matches_5_7, + matches_5_6, + matches_5_5, + matches_5_4, + matches_5_3, + matches_5_2, + matches_5_1, + matches_5_0}) begin + buffer_5_addr <= + (matches_5_0 ? io_enqData_0_addr : 32'h0) + | (matches_5_1 ? io_enqData_1_addr : 32'h0) + | (matches_5_2 ? io_enqData_2_addr : 32'h0) + | (matches_5_3 ? io_enqData_3_addr : 32'h0) + | (matches_5_4 ? io_enqData_4_addr : 32'h0) + | (matches_5_5 ? io_enqData_5_addr : 32'h0) + | (matches_5_6 ? io_enqData_6_addr : 32'h0) + | (matches_5_7 ? io_enqData_7_addr : 32'h0) + | (matches_5_8 ? io_enqData_8_addr : 32'h0) + | (matches_5_9 ? io_enqData_9_addr : 32'h0) + | (matches_5_10 ? io_enqData_10_addr : 32'h0) + | (matches_5_11 ? io_enqData_11_addr : 32'h0) + | (matches_5_12 ? io_enqData_12_addr : 32'h0) + | (matches_5_13 ? io_enqData_13_addr : 32'h0) + | (matches_5_14 ? io_enqData_14_addr : 32'h0) + | (matches_5_15 ? io_enqData_15_addr : 32'h0); + buffer_5_idx <= + (matches_5_0 ? io_enqData_0_idx : 7'h0) + | (matches_5_1 ? io_enqData_1_idx : 7'h0) + | (matches_5_2 ? io_enqData_2_idx : 7'h0) + | (matches_5_3 ? io_enqData_3_idx : 7'h0) + | (matches_5_4 ? io_enqData_4_idx : 7'h0) + | (matches_5_5 ? io_enqData_5_idx : 7'h0) + | (matches_5_6 ? io_enqData_6_idx : 7'h0) + | (matches_5_7 ? io_enqData_7_idx : 7'h0) + | (matches_5_8 ? io_enqData_8_idx : 7'h0) + | (matches_5_9 ? io_enqData_9_idx : 7'h0) + | (matches_5_10 ? io_enqData_10_idx : 7'h0) + | (matches_5_11 ? io_enqData_11_idx : 7'h0) + | (matches_5_12 ? io_enqData_12_idx : 7'h0) + | (matches_5_13 ? io_enqData_13_idx : 7'h0) + | (matches_5_14 ? io_enqData_14_idx : 7'h0) + | (matches_5_15 ? io_enqData_15_idx : 7'h0); + buffer_5_trap <= + matches_5_0 & io_enqData_0_trap | matches_5_1 & io_enqData_1_trap | matches_5_2 + & io_enqData_2_trap | matches_5_3 & io_enqData_3_trap | matches_5_4 + & io_enqData_4_trap | matches_5_5 & io_enqData_5_trap | matches_5_6 + & io_enqData_6_trap | matches_5_7 & io_enqData_7_trap | matches_5_8 + & io_enqData_8_trap | matches_5_9 & io_enqData_9_trap | matches_5_10 + & io_enqData_10_trap | matches_5_11 & io_enqData_11_trap | matches_5_12 + & io_enqData_12_trap | matches_5_13 & io_enqData_13_trap | matches_5_14 + & io_enqData_14_trap | matches_5_15 & io_enqData_15_trap; + buffer_5_isControlFlow <= + matches_5_0 & io_enqData_0_isControlFlow | matches_5_1 + & io_enqData_1_isControlFlow | matches_5_2 & io_enqData_2_isControlFlow + | matches_5_3 & io_enqData_3_isControlFlow | matches_5_4 + & io_enqData_4_isControlFlow | matches_5_5 & io_enqData_5_isControlFlow + | matches_5_6 & io_enqData_6_isControlFlow | matches_5_7 + & io_enqData_7_isControlFlow | matches_5_8 & io_enqData_8_isControlFlow + | matches_5_9 & io_enqData_9_isControlFlow | matches_5_10 + & io_enqData_10_isControlFlow | matches_5_11 & io_enqData_11_isControlFlow + | matches_5_12 & io_enqData_12_isControlFlow | matches_5_13 + & io_enqData_13_isControlFlow | matches_5_14 & io_enqData_14_isControlFlow + | matches_5_15 & io_enqData_15_isControlFlow; + buffer_5_isBranch <= + matches_5_0 & io_enqData_0_isBranch | matches_5_1 & io_enqData_1_isBranch + | matches_5_2 & io_enqData_2_isBranch | matches_5_3 & io_enqData_3_isBranch + | matches_5_4 & io_enqData_4_isBranch | matches_5_5 & io_enqData_5_isBranch + | matches_5_6 & io_enqData_6_isBranch | matches_5_7 & io_enqData_7_isBranch + | matches_5_8 & io_enqData_8_isBranch | matches_5_9 & io_enqData_9_isBranch + | matches_5_10 & io_enqData_10_isBranch | matches_5_11 & io_enqData_11_isBranch + | matches_5_12 & io_enqData_12_isBranch | matches_5_13 & io_enqData_13_isBranch + | matches_5_14 & io_enqData_14_isBranch | matches_5_15 & io_enqData_15_isBranch; + buffer_5_isVector <= + matches_5_0 & io_enqData_0_isVector | matches_5_1 & io_enqData_1_isVector + | matches_5_2 & io_enqData_2_isVector | matches_5_3 & io_enqData_3_isVector + | matches_5_4 & io_enqData_4_isVector | matches_5_5 & io_enqData_5_isVector + | matches_5_6 & io_enqData_6_isVector | matches_5_7 & io_enqData_7_isVector + | matches_5_8 & io_enqData_8_isVector | matches_5_9 & io_enqData_9_isVector + | matches_5_10 & io_enqData_10_isVector | matches_5_11 & io_enqData_11_isVector + | matches_5_12 & io_enqData_12_isVector | matches_5_13 & io_enqData_13_isVector + | matches_5_14 & io_enqData_14_isVector | matches_5_15 & io_enqData_15_isVector; + buffer_5_resetsVstart <= + matches_5_0 & io_enqData_0_resetsVstart | matches_5_1 + & io_enqData_1_resetsVstart | matches_5_2 & io_enqData_2_resetsVstart + | matches_5_3 & io_enqData_3_resetsVstart | matches_5_4 + & io_enqData_4_resetsVstart | matches_5_5 & io_enqData_5_resetsVstart + | matches_5_6 & io_enqData_6_resetsVstart | matches_5_7 + & io_enqData_7_resetsVstart | matches_5_8 & io_enqData_8_resetsVstart + | matches_5_9 & io_enqData_9_resetsVstart | matches_5_10 + & io_enqData_10_resetsVstart | matches_5_11 & io_enqData_11_resetsVstart + | matches_5_12 & io_enqData_12_resetsVstart | matches_5_13 + & io_enqData_13_resetsVstart | matches_5_14 & io_enqData_14_resetsVstart + | matches_5_15 & io_enqData_15_resetsVstart; + buffer_5_linkOk <= + matches_5_0 & io_enqData_0_linkOk | matches_5_1 & io_enqData_1_linkOk + | matches_5_2 & io_enqData_2_linkOk | matches_5_3 & io_enqData_3_linkOk + | matches_5_4 & io_enqData_4_linkOk | matches_5_5 & io_enqData_5_linkOk + | matches_5_6 & io_enqData_6_linkOk | matches_5_7 & io_enqData_7_linkOk + | matches_5_8 & io_enqData_8_linkOk | matches_5_9 & io_enqData_9_linkOk + | matches_5_10 & io_enqData_10_linkOk | matches_5_11 & io_enqData_11_linkOk + | matches_5_12 & io_enqData_12_linkOk | matches_5_13 & io_enqData_13_linkOk + | matches_5_14 & io_enqData_14_linkOk | matches_5_15 & io_enqData_15_linkOk; + buffer_5_isEcall <= + matches_5_0 & io_enqData_0_isEcall | matches_5_1 & io_enqData_1_isEcall + | matches_5_2 & io_enqData_2_isEcall | matches_5_3 & io_enqData_3_isEcall + | matches_5_4 & io_enqData_4_isEcall | matches_5_5 & io_enqData_5_isEcall + | matches_5_6 & io_enqData_6_isEcall | matches_5_7 & io_enqData_7_isEcall + | matches_5_8 & io_enqData_8_isEcall | matches_5_9 & io_enqData_9_isEcall + | matches_5_10 & io_enqData_10_isEcall | matches_5_11 & io_enqData_11_isEcall + | matches_5_12 & io_enqData_12_isEcall | matches_5_13 & io_enqData_13_isEcall + | matches_5_14 & io_enqData_14_isEcall | matches_5_15 & io_enqData_15_isEcall; + buffer_5_isMpause <= + matches_5_0 & io_enqData_0_isMpause | matches_5_1 & io_enqData_1_isMpause + | matches_5_2 & io_enqData_2_isMpause | matches_5_3 & io_enqData_3_isMpause + | matches_5_4 & io_enqData_4_isMpause | matches_5_5 & io_enqData_5_isMpause + | matches_5_6 & io_enqData_6_isMpause | matches_5_7 & io_enqData_7_isMpause + | matches_5_8 & io_enqData_8_isMpause | matches_5_9 & io_enqData_9_isMpause + | matches_5_10 & io_enqData_10_isMpause | matches_5_11 & io_enqData_11_isMpause + | matches_5_12 & io_enqData_12_isMpause | matches_5_13 & io_enqData_13_isMpause + | matches_5_14 & io_enqData_14_isMpause | matches_5_15 & io_enqData_15_isMpause; + buffer_5_isTile <= + matches_5_0 & io_enqData_0_isTile | matches_5_1 & io_enqData_1_isTile + | matches_5_2 & io_enqData_2_isTile | matches_5_3 & io_enqData_3_isTile + | matches_5_4 & io_enqData_4_isTile | matches_5_5 & io_enqData_5_isTile + | matches_5_6 & io_enqData_6_isTile | matches_5_7 & io_enqData_7_isTile + | matches_5_8 & io_enqData_8_isTile | matches_5_9 & io_enqData_9_isTile + | matches_5_10 & io_enqData_10_isTile | matches_5_11 & io_enqData_11_isTile + | matches_5_12 & io_enqData_12_isTile | matches_5_13 & io_enqData_13_isTile + | matches_5_14 & io_enqData_14_isTile | matches_5_15 & io_enqData_15_isTile; + end + if (|{matches_6_15, + matches_6_14, + matches_6_13, + matches_6_12, + matches_6_11, + matches_6_10, + matches_6_9, + matches_6_8, + matches_6_7, + matches_6_6, + matches_6_5, + matches_6_4, + matches_6_3, + matches_6_2, + matches_6_1, + matches_6_0}) begin + buffer_6_addr <= + (matches_6_0 ? io_enqData_0_addr : 32'h0) + | (matches_6_1 ? io_enqData_1_addr : 32'h0) + | (matches_6_2 ? io_enqData_2_addr : 32'h0) + | (matches_6_3 ? io_enqData_3_addr : 32'h0) + | (matches_6_4 ? io_enqData_4_addr : 32'h0) + | (matches_6_5 ? io_enqData_5_addr : 32'h0) + | (matches_6_6 ? io_enqData_6_addr : 32'h0) + | (matches_6_7 ? io_enqData_7_addr : 32'h0) + | (matches_6_8 ? io_enqData_8_addr : 32'h0) + | (matches_6_9 ? io_enqData_9_addr : 32'h0) + | (matches_6_10 ? io_enqData_10_addr : 32'h0) + | (matches_6_11 ? io_enqData_11_addr : 32'h0) + | (matches_6_12 ? io_enqData_12_addr : 32'h0) + | (matches_6_13 ? io_enqData_13_addr : 32'h0) + | (matches_6_14 ? io_enqData_14_addr : 32'h0) + | (matches_6_15 ? io_enqData_15_addr : 32'h0); + buffer_6_idx <= + (matches_6_0 ? io_enqData_0_idx : 7'h0) + | (matches_6_1 ? io_enqData_1_idx : 7'h0) + | (matches_6_2 ? io_enqData_2_idx : 7'h0) + | (matches_6_3 ? io_enqData_3_idx : 7'h0) + | (matches_6_4 ? io_enqData_4_idx : 7'h0) + | (matches_6_5 ? io_enqData_5_idx : 7'h0) + | (matches_6_6 ? io_enqData_6_idx : 7'h0) + | (matches_6_7 ? io_enqData_7_idx : 7'h0) + | (matches_6_8 ? io_enqData_8_idx : 7'h0) + | (matches_6_9 ? io_enqData_9_idx : 7'h0) + | (matches_6_10 ? io_enqData_10_idx : 7'h0) + | (matches_6_11 ? io_enqData_11_idx : 7'h0) + | (matches_6_12 ? io_enqData_12_idx : 7'h0) + | (matches_6_13 ? io_enqData_13_idx : 7'h0) + | (matches_6_14 ? io_enqData_14_idx : 7'h0) + | (matches_6_15 ? io_enqData_15_idx : 7'h0); + buffer_6_trap <= + matches_6_0 & io_enqData_0_trap | matches_6_1 & io_enqData_1_trap | matches_6_2 + & io_enqData_2_trap | matches_6_3 & io_enqData_3_trap | matches_6_4 + & io_enqData_4_trap | matches_6_5 & io_enqData_5_trap | matches_6_6 + & io_enqData_6_trap | matches_6_7 & io_enqData_7_trap | matches_6_8 + & io_enqData_8_trap | matches_6_9 & io_enqData_9_trap | matches_6_10 + & io_enqData_10_trap | matches_6_11 & io_enqData_11_trap | matches_6_12 + & io_enqData_12_trap | matches_6_13 & io_enqData_13_trap | matches_6_14 + & io_enqData_14_trap | matches_6_15 & io_enqData_15_trap; + buffer_6_isControlFlow <= + matches_6_0 & io_enqData_0_isControlFlow | matches_6_1 + & io_enqData_1_isControlFlow | matches_6_2 & io_enqData_2_isControlFlow + | matches_6_3 & io_enqData_3_isControlFlow | matches_6_4 + & io_enqData_4_isControlFlow | matches_6_5 & io_enqData_5_isControlFlow + | matches_6_6 & io_enqData_6_isControlFlow | matches_6_7 + & io_enqData_7_isControlFlow | matches_6_8 & io_enqData_8_isControlFlow + | matches_6_9 & io_enqData_9_isControlFlow | matches_6_10 + & io_enqData_10_isControlFlow | matches_6_11 & io_enqData_11_isControlFlow + | matches_6_12 & io_enqData_12_isControlFlow | matches_6_13 + & io_enqData_13_isControlFlow | matches_6_14 & io_enqData_14_isControlFlow + | matches_6_15 & io_enqData_15_isControlFlow; + buffer_6_isBranch <= + matches_6_0 & io_enqData_0_isBranch | matches_6_1 & io_enqData_1_isBranch + | matches_6_2 & io_enqData_2_isBranch | matches_6_3 & io_enqData_3_isBranch + | matches_6_4 & io_enqData_4_isBranch | matches_6_5 & io_enqData_5_isBranch + | matches_6_6 & io_enqData_6_isBranch | matches_6_7 & io_enqData_7_isBranch + | matches_6_8 & io_enqData_8_isBranch | matches_6_9 & io_enqData_9_isBranch + | matches_6_10 & io_enqData_10_isBranch | matches_6_11 & io_enqData_11_isBranch + | matches_6_12 & io_enqData_12_isBranch | matches_6_13 & io_enqData_13_isBranch + | matches_6_14 & io_enqData_14_isBranch | matches_6_15 & io_enqData_15_isBranch; + buffer_6_isVector <= + matches_6_0 & io_enqData_0_isVector | matches_6_1 & io_enqData_1_isVector + | matches_6_2 & io_enqData_2_isVector | matches_6_3 & io_enqData_3_isVector + | matches_6_4 & io_enqData_4_isVector | matches_6_5 & io_enqData_5_isVector + | matches_6_6 & io_enqData_6_isVector | matches_6_7 & io_enqData_7_isVector + | matches_6_8 & io_enqData_8_isVector | matches_6_9 & io_enqData_9_isVector + | matches_6_10 & io_enqData_10_isVector | matches_6_11 & io_enqData_11_isVector + | matches_6_12 & io_enqData_12_isVector | matches_6_13 & io_enqData_13_isVector + | matches_6_14 & io_enqData_14_isVector | matches_6_15 & io_enqData_15_isVector; + buffer_6_resetsVstart <= + matches_6_0 & io_enqData_0_resetsVstart | matches_6_1 + & io_enqData_1_resetsVstart | matches_6_2 & io_enqData_2_resetsVstart + | matches_6_3 & io_enqData_3_resetsVstart | matches_6_4 + & io_enqData_4_resetsVstart | matches_6_5 & io_enqData_5_resetsVstart + | matches_6_6 & io_enqData_6_resetsVstart | matches_6_7 + & io_enqData_7_resetsVstart | matches_6_8 & io_enqData_8_resetsVstart + | matches_6_9 & io_enqData_9_resetsVstart | matches_6_10 + & io_enqData_10_resetsVstart | matches_6_11 & io_enqData_11_resetsVstart + | matches_6_12 & io_enqData_12_resetsVstart | matches_6_13 + & io_enqData_13_resetsVstart | matches_6_14 & io_enqData_14_resetsVstart + | matches_6_15 & io_enqData_15_resetsVstart; + buffer_6_linkOk <= + matches_6_0 & io_enqData_0_linkOk | matches_6_1 & io_enqData_1_linkOk + | matches_6_2 & io_enqData_2_linkOk | matches_6_3 & io_enqData_3_linkOk + | matches_6_4 & io_enqData_4_linkOk | matches_6_5 & io_enqData_5_linkOk + | matches_6_6 & io_enqData_6_linkOk | matches_6_7 & io_enqData_7_linkOk + | matches_6_8 & io_enqData_8_linkOk | matches_6_9 & io_enqData_9_linkOk + | matches_6_10 & io_enqData_10_linkOk | matches_6_11 & io_enqData_11_linkOk + | matches_6_12 & io_enqData_12_linkOk | matches_6_13 & io_enqData_13_linkOk + | matches_6_14 & io_enqData_14_linkOk | matches_6_15 & io_enqData_15_linkOk; + buffer_6_isEcall <= + matches_6_0 & io_enqData_0_isEcall | matches_6_1 & io_enqData_1_isEcall + | matches_6_2 & io_enqData_2_isEcall | matches_6_3 & io_enqData_3_isEcall + | matches_6_4 & io_enqData_4_isEcall | matches_6_5 & io_enqData_5_isEcall + | matches_6_6 & io_enqData_6_isEcall | matches_6_7 & io_enqData_7_isEcall + | matches_6_8 & io_enqData_8_isEcall | matches_6_9 & io_enqData_9_isEcall + | matches_6_10 & io_enqData_10_isEcall | matches_6_11 & io_enqData_11_isEcall + | matches_6_12 & io_enqData_12_isEcall | matches_6_13 & io_enqData_13_isEcall + | matches_6_14 & io_enqData_14_isEcall | matches_6_15 & io_enqData_15_isEcall; + buffer_6_isMpause <= + matches_6_0 & io_enqData_0_isMpause | matches_6_1 & io_enqData_1_isMpause + | matches_6_2 & io_enqData_2_isMpause | matches_6_3 & io_enqData_3_isMpause + | matches_6_4 & io_enqData_4_isMpause | matches_6_5 & io_enqData_5_isMpause + | matches_6_6 & io_enqData_6_isMpause | matches_6_7 & io_enqData_7_isMpause + | matches_6_8 & io_enqData_8_isMpause | matches_6_9 & io_enqData_9_isMpause + | matches_6_10 & io_enqData_10_isMpause | matches_6_11 & io_enqData_11_isMpause + | matches_6_12 & io_enqData_12_isMpause | matches_6_13 & io_enqData_13_isMpause + | matches_6_14 & io_enqData_14_isMpause | matches_6_15 & io_enqData_15_isMpause; + buffer_6_isTile <= + matches_6_0 & io_enqData_0_isTile | matches_6_1 & io_enqData_1_isTile + | matches_6_2 & io_enqData_2_isTile | matches_6_3 & io_enqData_3_isTile + | matches_6_4 & io_enqData_4_isTile | matches_6_5 & io_enqData_5_isTile + | matches_6_6 & io_enqData_6_isTile | matches_6_7 & io_enqData_7_isTile + | matches_6_8 & io_enqData_8_isTile | matches_6_9 & io_enqData_9_isTile + | matches_6_10 & io_enqData_10_isTile | matches_6_11 & io_enqData_11_isTile + | matches_6_12 & io_enqData_12_isTile | matches_6_13 & io_enqData_13_isTile + | matches_6_14 & io_enqData_14_isTile | matches_6_15 & io_enqData_15_isTile; + end + if (|{matches_7_15, + matches_7_14, + matches_7_13, + matches_7_12, + matches_7_11, + matches_7_10, + matches_7_9, + matches_7_8, + matches_7_7, + matches_7_6, + matches_7_5, + matches_7_4, + matches_7_3, + matches_7_2, + matches_7_1, + matches_7_0}) begin + buffer_7_addr <= + (matches_7_0 ? io_enqData_0_addr : 32'h0) + | (matches_7_1 ? io_enqData_1_addr : 32'h0) + | (matches_7_2 ? io_enqData_2_addr : 32'h0) + | (matches_7_3 ? io_enqData_3_addr : 32'h0) + | (matches_7_4 ? io_enqData_4_addr : 32'h0) + | (matches_7_5 ? io_enqData_5_addr : 32'h0) + | (matches_7_6 ? io_enqData_6_addr : 32'h0) + | (matches_7_7 ? io_enqData_7_addr : 32'h0) + | (matches_7_8 ? io_enqData_8_addr : 32'h0) + | (matches_7_9 ? io_enqData_9_addr : 32'h0) + | (matches_7_10 ? io_enqData_10_addr : 32'h0) + | (matches_7_11 ? io_enqData_11_addr : 32'h0) + | (matches_7_12 ? io_enqData_12_addr : 32'h0) + | (matches_7_13 ? io_enqData_13_addr : 32'h0) + | (matches_7_14 ? io_enqData_14_addr : 32'h0) + | (matches_7_15 ? io_enqData_15_addr : 32'h0); + buffer_7_idx <= + (matches_7_0 ? io_enqData_0_idx : 7'h0) + | (matches_7_1 ? io_enqData_1_idx : 7'h0) + | (matches_7_2 ? io_enqData_2_idx : 7'h0) + | (matches_7_3 ? io_enqData_3_idx : 7'h0) + | (matches_7_4 ? io_enqData_4_idx : 7'h0) + | (matches_7_5 ? io_enqData_5_idx : 7'h0) + | (matches_7_6 ? io_enqData_6_idx : 7'h0) + | (matches_7_7 ? io_enqData_7_idx : 7'h0) + | (matches_7_8 ? io_enqData_8_idx : 7'h0) + | (matches_7_9 ? io_enqData_9_idx : 7'h0) + | (matches_7_10 ? io_enqData_10_idx : 7'h0) + | (matches_7_11 ? io_enqData_11_idx : 7'h0) + | (matches_7_12 ? io_enqData_12_idx : 7'h0) + | (matches_7_13 ? io_enqData_13_idx : 7'h0) + | (matches_7_14 ? io_enqData_14_idx : 7'h0) + | (matches_7_15 ? io_enqData_15_idx : 7'h0); + buffer_7_trap <= + matches_7_0 & io_enqData_0_trap | matches_7_1 & io_enqData_1_trap | matches_7_2 + & io_enqData_2_trap | matches_7_3 & io_enqData_3_trap | matches_7_4 + & io_enqData_4_trap | matches_7_5 & io_enqData_5_trap | matches_7_6 + & io_enqData_6_trap | matches_7_7 & io_enqData_7_trap | matches_7_8 + & io_enqData_8_trap | matches_7_9 & io_enqData_9_trap | matches_7_10 + & io_enqData_10_trap | matches_7_11 & io_enqData_11_trap | matches_7_12 + & io_enqData_12_trap | matches_7_13 & io_enqData_13_trap | matches_7_14 + & io_enqData_14_trap | matches_7_15 & io_enqData_15_trap; + buffer_7_isControlFlow <= + matches_7_0 & io_enqData_0_isControlFlow | matches_7_1 + & io_enqData_1_isControlFlow | matches_7_2 & io_enqData_2_isControlFlow + | matches_7_3 & io_enqData_3_isControlFlow | matches_7_4 + & io_enqData_4_isControlFlow | matches_7_5 & io_enqData_5_isControlFlow + | matches_7_6 & io_enqData_6_isControlFlow | matches_7_7 + & io_enqData_7_isControlFlow | matches_7_8 & io_enqData_8_isControlFlow + | matches_7_9 & io_enqData_9_isControlFlow | matches_7_10 + & io_enqData_10_isControlFlow | matches_7_11 & io_enqData_11_isControlFlow + | matches_7_12 & io_enqData_12_isControlFlow | matches_7_13 + & io_enqData_13_isControlFlow | matches_7_14 & io_enqData_14_isControlFlow + | matches_7_15 & io_enqData_15_isControlFlow; + buffer_7_isBranch <= + matches_7_0 & io_enqData_0_isBranch | matches_7_1 & io_enqData_1_isBranch + | matches_7_2 & io_enqData_2_isBranch | matches_7_3 & io_enqData_3_isBranch + | matches_7_4 & io_enqData_4_isBranch | matches_7_5 & io_enqData_5_isBranch + | matches_7_6 & io_enqData_6_isBranch | matches_7_7 & io_enqData_7_isBranch + | matches_7_8 & io_enqData_8_isBranch | matches_7_9 & io_enqData_9_isBranch + | matches_7_10 & io_enqData_10_isBranch | matches_7_11 & io_enqData_11_isBranch + | matches_7_12 & io_enqData_12_isBranch | matches_7_13 & io_enqData_13_isBranch + | matches_7_14 & io_enqData_14_isBranch | matches_7_15 & io_enqData_15_isBranch; + buffer_7_isVector <= + matches_7_0 & io_enqData_0_isVector | matches_7_1 & io_enqData_1_isVector + | matches_7_2 & io_enqData_2_isVector | matches_7_3 & io_enqData_3_isVector + | matches_7_4 & io_enqData_4_isVector | matches_7_5 & io_enqData_5_isVector + | matches_7_6 & io_enqData_6_isVector | matches_7_7 & io_enqData_7_isVector + | matches_7_8 & io_enqData_8_isVector | matches_7_9 & io_enqData_9_isVector + | matches_7_10 & io_enqData_10_isVector | matches_7_11 & io_enqData_11_isVector + | matches_7_12 & io_enqData_12_isVector | matches_7_13 & io_enqData_13_isVector + | matches_7_14 & io_enqData_14_isVector | matches_7_15 & io_enqData_15_isVector; + buffer_7_resetsVstart <= + matches_7_0 & io_enqData_0_resetsVstart | matches_7_1 + & io_enqData_1_resetsVstart | matches_7_2 & io_enqData_2_resetsVstart + | matches_7_3 & io_enqData_3_resetsVstart | matches_7_4 + & io_enqData_4_resetsVstart | matches_7_5 & io_enqData_5_resetsVstart + | matches_7_6 & io_enqData_6_resetsVstart | matches_7_7 + & io_enqData_7_resetsVstart | matches_7_8 & io_enqData_8_resetsVstart + | matches_7_9 & io_enqData_9_resetsVstart | matches_7_10 + & io_enqData_10_resetsVstart | matches_7_11 & io_enqData_11_resetsVstart + | matches_7_12 & io_enqData_12_resetsVstart | matches_7_13 + & io_enqData_13_resetsVstart | matches_7_14 & io_enqData_14_resetsVstart + | matches_7_15 & io_enqData_15_resetsVstart; + buffer_7_linkOk <= + matches_7_0 & io_enqData_0_linkOk | matches_7_1 & io_enqData_1_linkOk + | matches_7_2 & io_enqData_2_linkOk | matches_7_3 & io_enqData_3_linkOk + | matches_7_4 & io_enqData_4_linkOk | matches_7_5 & io_enqData_5_linkOk + | matches_7_6 & io_enqData_6_linkOk | matches_7_7 & io_enqData_7_linkOk + | matches_7_8 & io_enqData_8_linkOk | matches_7_9 & io_enqData_9_linkOk + | matches_7_10 & io_enqData_10_linkOk | matches_7_11 & io_enqData_11_linkOk + | matches_7_12 & io_enqData_12_linkOk | matches_7_13 & io_enqData_13_linkOk + | matches_7_14 & io_enqData_14_linkOk | matches_7_15 & io_enqData_15_linkOk; + buffer_7_isEcall <= + matches_7_0 & io_enqData_0_isEcall | matches_7_1 & io_enqData_1_isEcall + | matches_7_2 & io_enqData_2_isEcall | matches_7_3 & io_enqData_3_isEcall + | matches_7_4 & io_enqData_4_isEcall | matches_7_5 & io_enqData_5_isEcall + | matches_7_6 & io_enqData_6_isEcall | matches_7_7 & io_enqData_7_isEcall + | matches_7_8 & io_enqData_8_isEcall | matches_7_9 & io_enqData_9_isEcall + | matches_7_10 & io_enqData_10_isEcall | matches_7_11 & io_enqData_11_isEcall + | matches_7_12 & io_enqData_12_isEcall | matches_7_13 & io_enqData_13_isEcall + | matches_7_14 & io_enqData_14_isEcall | matches_7_15 & io_enqData_15_isEcall; + buffer_7_isMpause <= + matches_7_0 & io_enqData_0_isMpause | matches_7_1 & io_enqData_1_isMpause + | matches_7_2 & io_enqData_2_isMpause | matches_7_3 & io_enqData_3_isMpause + | matches_7_4 & io_enqData_4_isMpause | matches_7_5 & io_enqData_5_isMpause + | matches_7_6 & io_enqData_6_isMpause | matches_7_7 & io_enqData_7_isMpause + | matches_7_8 & io_enqData_8_isMpause | matches_7_9 & io_enqData_9_isMpause + | matches_7_10 & io_enqData_10_isMpause | matches_7_11 & io_enqData_11_isMpause + | matches_7_12 & io_enqData_12_isMpause | matches_7_13 & io_enqData_13_isMpause + | matches_7_14 & io_enqData_14_isMpause | matches_7_15 & io_enqData_15_isMpause; + buffer_7_isTile <= + matches_7_0 & io_enqData_0_isTile | matches_7_1 & io_enqData_1_isTile + | matches_7_2 & io_enqData_2_isTile | matches_7_3 & io_enqData_3_isTile + | matches_7_4 & io_enqData_4_isTile | matches_7_5 & io_enqData_5_isTile + | matches_7_6 & io_enqData_6_isTile | matches_7_7 & io_enqData_7_isTile + | matches_7_8 & io_enqData_8_isTile | matches_7_9 & io_enqData_9_isTile + | matches_7_10 & io_enqData_10_isTile | matches_7_11 & io_enqData_11_isTile + | matches_7_12 & io_enqData_12_isTile | matches_7_13 & io_enqData_13_isTile + | matches_7_14 & io_enqData_14_isTile | matches_7_15 & io_enqData_15_isTile; + end + if (|{matches_8_15, + matches_8_14, + matches_8_13, + matches_8_12, + matches_8_11, + matches_8_10, + matches_8_9, + matches_8_8, + matches_8_7, + matches_8_6, + matches_8_5, + matches_8_4, + matches_8_3, + matches_8_2, + matches_8_1, + matches_8_0}) begin + buffer_8_addr <= + (matches_8_0 ? io_enqData_0_addr : 32'h0) + | (matches_8_1 ? io_enqData_1_addr : 32'h0) + | (matches_8_2 ? io_enqData_2_addr : 32'h0) + | (matches_8_3 ? io_enqData_3_addr : 32'h0) + | (matches_8_4 ? io_enqData_4_addr : 32'h0) + | (matches_8_5 ? io_enqData_5_addr : 32'h0) + | (matches_8_6 ? io_enqData_6_addr : 32'h0) + | (matches_8_7 ? io_enqData_7_addr : 32'h0) + | (matches_8_8 ? io_enqData_8_addr : 32'h0) + | (matches_8_9 ? io_enqData_9_addr : 32'h0) + | (matches_8_10 ? io_enqData_10_addr : 32'h0) + | (matches_8_11 ? io_enqData_11_addr : 32'h0) + | (matches_8_12 ? io_enqData_12_addr : 32'h0) + | (matches_8_13 ? io_enqData_13_addr : 32'h0) + | (matches_8_14 ? io_enqData_14_addr : 32'h0) + | (matches_8_15 ? io_enqData_15_addr : 32'h0); + buffer_8_idx <= + (matches_8_0 ? io_enqData_0_idx : 7'h0) + | (matches_8_1 ? io_enqData_1_idx : 7'h0) + | (matches_8_2 ? io_enqData_2_idx : 7'h0) + | (matches_8_3 ? io_enqData_3_idx : 7'h0) + | (matches_8_4 ? io_enqData_4_idx : 7'h0) + | (matches_8_5 ? io_enqData_5_idx : 7'h0) + | (matches_8_6 ? io_enqData_6_idx : 7'h0) + | (matches_8_7 ? io_enqData_7_idx : 7'h0) + | (matches_8_8 ? io_enqData_8_idx : 7'h0) + | (matches_8_9 ? io_enqData_9_idx : 7'h0) + | (matches_8_10 ? io_enqData_10_idx : 7'h0) + | (matches_8_11 ? io_enqData_11_idx : 7'h0) + | (matches_8_12 ? io_enqData_12_idx : 7'h0) + | (matches_8_13 ? io_enqData_13_idx : 7'h0) + | (matches_8_14 ? io_enqData_14_idx : 7'h0) + | (matches_8_15 ? io_enqData_15_idx : 7'h0); + buffer_8_trap <= + matches_8_0 & io_enqData_0_trap | matches_8_1 & io_enqData_1_trap | matches_8_2 + & io_enqData_2_trap | matches_8_3 & io_enqData_3_trap | matches_8_4 + & io_enqData_4_trap | matches_8_5 & io_enqData_5_trap | matches_8_6 + & io_enqData_6_trap | matches_8_7 & io_enqData_7_trap | matches_8_8 + & io_enqData_8_trap | matches_8_9 & io_enqData_9_trap | matches_8_10 + & io_enqData_10_trap | matches_8_11 & io_enqData_11_trap | matches_8_12 + & io_enqData_12_trap | matches_8_13 & io_enqData_13_trap | matches_8_14 + & io_enqData_14_trap | matches_8_15 & io_enqData_15_trap; + buffer_8_isControlFlow <= + matches_8_0 & io_enqData_0_isControlFlow | matches_8_1 + & io_enqData_1_isControlFlow | matches_8_2 & io_enqData_2_isControlFlow + | matches_8_3 & io_enqData_3_isControlFlow | matches_8_4 + & io_enqData_4_isControlFlow | matches_8_5 & io_enqData_5_isControlFlow + | matches_8_6 & io_enqData_6_isControlFlow | matches_8_7 + & io_enqData_7_isControlFlow | matches_8_8 & io_enqData_8_isControlFlow + | matches_8_9 & io_enqData_9_isControlFlow | matches_8_10 + & io_enqData_10_isControlFlow | matches_8_11 & io_enqData_11_isControlFlow + | matches_8_12 & io_enqData_12_isControlFlow | matches_8_13 + & io_enqData_13_isControlFlow | matches_8_14 & io_enqData_14_isControlFlow + | matches_8_15 & io_enqData_15_isControlFlow; + buffer_8_isBranch <= + matches_8_0 & io_enqData_0_isBranch | matches_8_1 & io_enqData_1_isBranch + | matches_8_2 & io_enqData_2_isBranch | matches_8_3 & io_enqData_3_isBranch + | matches_8_4 & io_enqData_4_isBranch | matches_8_5 & io_enqData_5_isBranch + | matches_8_6 & io_enqData_6_isBranch | matches_8_7 & io_enqData_7_isBranch + | matches_8_8 & io_enqData_8_isBranch | matches_8_9 & io_enqData_9_isBranch + | matches_8_10 & io_enqData_10_isBranch | matches_8_11 & io_enqData_11_isBranch + | matches_8_12 & io_enqData_12_isBranch | matches_8_13 & io_enqData_13_isBranch + | matches_8_14 & io_enqData_14_isBranch | matches_8_15 & io_enqData_15_isBranch; + buffer_8_isVector <= + matches_8_0 & io_enqData_0_isVector | matches_8_1 & io_enqData_1_isVector + | matches_8_2 & io_enqData_2_isVector | matches_8_3 & io_enqData_3_isVector + | matches_8_4 & io_enqData_4_isVector | matches_8_5 & io_enqData_5_isVector + | matches_8_6 & io_enqData_6_isVector | matches_8_7 & io_enqData_7_isVector + | matches_8_8 & io_enqData_8_isVector | matches_8_9 & io_enqData_9_isVector + | matches_8_10 & io_enqData_10_isVector | matches_8_11 & io_enqData_11_isVector + | matches_8_12 & io_enqData_12_isVector | matches_8_13 & io_enqData_13_isVector + | matches_8_14 & io_enqData_14_isVector | matches_8_15 & io_enqData_15_isVector; + buffer_8_resetsVstart <= + matches_8_0 & io_enqData_0_resetsVstart | matches_8_1 + & io_enqData_1_resetsVstart | matches_8_2 & io_enqData_2_resetsVstart + | matches_8_3 & io_enqData_3_resetsVstart | matches_8_4 + & io_enqData_4_resetsVstart | matches_8_5 & io_enqData_5_resetsVstart + | matches_8_6 & io_enqData_6_resetsVstart | matches_8_7 + & io_enqData_7_resetsVstart | matches_8_8 & io_enqData_8_resetsVstart + | matches_8_9 & io_enqData_9_resetsVstart | matches_8_10 + & io_enqData_10_resetsVstart | matches_8_11 & io_enqData_11_resetsVstart + | matches_8_12 & io_enqData_12_resetsVstart | matches_8_13 + & io_enqData_13_resetsVstart | matches_8_14 & io_enqData_14_resetsVstart + | matches_8_15 & io_enqData_15_resetsVstart; + buffer_8_linkOk <= + matches_8_0 & io_enqData_0_linkOk | matches_8_1 & io_enqData_1_linkOk + | matches_8_2 & io_enqData_2_linkOk | matches_8_3 & io_enqData_3_linkOk + | matches_8_4 & io_enqData_4_linkOk | matches_8_5 & io_enqData_5_linkOk + | matches_8_6 & io_enqData_6_linkOk | matches_8_7 & io_enqData_7_linkOk + | matches_8_8 & io_enqData_8_linkOk | matches_8_9 & io_enqData_9_linkOk + | matches_8_10 & io_enqData_10_linkOk | matches_8_11 & io_enqData_11_linkOk + | matches_8_12 & io_enqData_12_linkOk | matches_8_13 & io_enqData_13_linkOk + | matches_8_14 & io_enqData_14_linkOk | matches_8_15 & io_enqData_15_linkOk; + buffer_8_isEcall <= + matches_8_0 & io_enqData_0_isEcall | matches_8_1 & io_enqData_1_isEcall + | matches_8_2 & io_enqData_2_isEcall | matches_8_3 & io_enqData_3_isEcall + | matches_8_4 & io_enqData_4_isEcall | matches_8_5 & io_enqData_5_isEcall + | matches_8_6 & io_enqData_6_isEcall | matches_8_7 & io_enqData_7_isEcall + | matches_8_8 & io_enqData_8_isEcall | matches_8_9 & io_enqData_9_isEcall + | matches_8_10 & io_enqData_10_isEcall | matches_8_11 & io_enqData_11_isEcall + | matches_8_12 & io_enqData_12_isEcall | matches_8_13 & io_enqData_13_isEcall + | matches_8_14 & io_enqData_14_isEcall | matches_8_15 & io_enqData_15_isEcall; + buffer_8_isMpause <= + matches_8_0 & io_enqData_0_isMpause | matches_8_1 & io_enqData_1_isMpause + | matches_8_2 & io_enqData_2_isMpause | matches_8_3 & io_enqData_3_isMpause + | matches_8_4 & io_enqData_4_isMpause | matches_8_5 & io_enqData_5_isMpause + | matches_8_6 & io_enqData_6_isMpause | matches_8_7 & io_enqData_7_isMpause + | matches_8_8 & io_enqData_8_isMpause | matches_8_9 & io_enqData_9_isMpause + | matches_8_10 & io_enqData_10_isMpause | matches_8_11 & io_enqData_11_isMpause + | matches_8_12 & io_enqData_12_isMpause | matches_8_13 & io_enqData_13_isMpause + | matches_8_14 & io_enqData_14_isMpause | matches_8_15 & io_enqData_15_isMpause; + buffer_8_isTile <= + matches_8_0 & io_enqData_0_isTile | matches_8_1 & io_enqData_1_isTile + | matches_8_2 & io_enqData_2_isTile | matches_8_3 & io_enqData_3_isTile + | matches_8_4 & io_enqData_4_isTile | matches_8_5 & io_enqData_5_isTile + | matches_8_6 & io_enqData_6_isTile | matches_8_7 & io_enqData_7_isTile + | matches_8_8 & io_enqData_8_isTile | matches_8_9 & io_enqData_9_isTile + | matches_8_10 & io_enqData_10_isTile | matches_8_11 & io_enqData_11_isTile + | matches_8_12 & io_enqData_12_isTile | matches_8_13 & io_enqData_13_isTile + | matches_8_14 & io_enqData_14_isTile | matches_8_15 & io_enqData_15_isTile; + end + if (|{matches_9_15, + matches_9_14, + matches_9_13, + matches_9_12, + matches_9_11, + matches_9_10, + matches_9_9, + matches_9_8, + matches_9_7, + matches_9_6, + matches_9_5, + matches_9_4, + matches_9_3, + matches_9_2, + matches_9_1, + matches_9_0}) begin + buffer_9_addr <= + (matches_9_0 ? io_enqData_0_addr : 32'h0) + | (matches_9_1 ? io_enqData_1_addr : 32'h0) + | (matches_9_2 ? io_enqData_2_addr : 32'h0) + | (matches_9_3 ? io_enqData_3_addr : 32'h0) + | (matches_9_4 ? io_enqData_4_addr : 32'h0) + | (matches_9_5 ? io_enqData_5_addr : 32'h0) + | (matches_9_6 ? io_enqData_6_addr : 32'h0) + | (matches_9_7 ? io_enqData_7_addr : 32'h0) + | (matches_9_8 ? io_enqData_8_addr : 32'h0) + | (matches_9_9 ? io_enqData_9_addr : 32'h0) + | (matches_9_10 ? io_enqData_10_addr : 32'h0) + | (matches_9_11 ? io_enqData_11_addr : 32'h0) + | (matches_9_12 ? io_enqData_12_addr : 32'h0) + | (matches_9_13 ? io_enqData_13_addr : 32'h0) + | (matches_9_14 ? io_enqData_14_addr : 32'h0) + | (matches_9_15 ? io_enqData_15_addr : 32'h0); + buffer_9_idx <= + (matches_9_0 ? io_enqData_0_idx : 7'h0) + | (matches_9_1 ? io_enqData_1_idx : 7'h0) + | (matches_9_2 ? io_enqData_2_idx : 7'h0) + | (matches_9_3 ? io_enqData_3_idx : 7'h0) + | (matches_9_4 ? io_enqData_4_idx : 7'h0) + | (matches_9_5 ? io_enqData_5_idx : 7'h0) + | (matches_9_6 ? io_enqData_6_idx : 7'h0) + | (matches_9_7 ? io_enqData_7_idx : 7'h0) + | (matches_9_8 ? io_enqData_8_idx : 7'h0) + | (matches_9_9 ? io_enqData_9_idx : 7'h0) + | (matches_9_10 ? io_enqData_10_idx : 7'h0) + | (matches_9_11 ? io_enqData_11_idx : 7'h0) + | (matches_9_12 ? io_enqData_12_idx : 7'h0) + | (matches_9_13 ? io_enqData_13_idx : 7'h0) + | (matches_9_14 ? io_enqData_14_idx : 7'h0) + | (matches_9_15 ? io_enqData_15_idx : 7'h0); + buffer_9_trap <= + matches_9_0 & io_enqData_0_trap | matches_9_1 & io_enqData_1_trap | matches_9_2 + & io_enqData_2_trap | matches_9_3 & io_enqData_3_trap | matches_9_4 + & io_enqData_4_trap | matches_9_5 & io_enqData_5_trap | matches_9_6 + & io_enqData_6_trap | matches_9_7 & io_enqData_7_trap | matches_9_8 + & io_enqData_8_trap | matches_9_9 & io_enqData_9_trap | matches_9_10 + & io_enqData_10_trap | matches_9_11 & io_enqData_11_trap | matches_9_12 + & io_enqData_12_trap | matches_9_13 & io_enqData_13_trap | matches_9_14 + & io_enqData_14_trap | matches_9_15 & io_enqData_15_trap; + buffer_9_isControlFlow <= + matches_9_0 & io_enqData_0_isControlFlow | matches_9_1 + & io_enqData_1_isControlFlow | matches_9_2 & io_enqData_2_isControlFlow + | matches_9_3 & io_enqData_3_isControlFlow | matches_9_4 + & io_enqData_4_isControlFlow | matches_9_5 & io_enqData_5_isControlFlow + | matches_9_6 & io_enqData_6_isControlFlow | matches_9_7 + & io_enqData_7_isControlFlow | matches_9_8 & io_enqData_8_isControlFlow + | matches_9_9 & io_enqData_9_isControlFlow | matches_9_10 + & io_enqData_10_isControlFlow | matches_9_11 & io_enqData_11_isControlFlow + | matches_9_12 & io_enqData_12_isControlFlow | matches_9_13 + & io_enqData_13_isControlFlow | matches_9_14 & io_enqData_14_isControlFlow + | matches_9_15 & io_enqData_15_isControlFlow; + buffer_9_isBranch <= + matches_9_0 & io_enqData_0_isBranch | matches_9_1 & io_enqData_1_isBranch + | matches_9_2 & io_enqData_2_isBranch | matches_9_3 & io_enqData_3_isBranch + | matches_9_4 & io_enqData_4_isBranch | matches_9_5 & io_enqData_5_isBranch + | matches_9_6 & io_enqData_6_isBranch | matches_9_7 & io_enqData_7_isBranch + | matches_9_8 & io_enqData_8_isBranch | matches_9_9 & io_enqData_9_isBranch + | matches_9_10 & io_enqData_10_isBranch | matches_9_11 & io_enqData_11_isBranch + | matches_9_12 & io_enqData_12_isBranch | matches_9_13 & io_enqData_13_isBranch + | matches_9_14 & io_enqData_14_isBranch | matches_9_15 & io_enqData_15_isBranch; + buffer_9_isVector <= + matches_9_0 & io_enqData_0_isVector | matches_9_1 & io_enqData_1_isVector + | matches_9_2 & io_enqData_2_isVector | matches_9_3 & io_enqData_3_isVector + | matches_9_4 & io_enqData_4_isVector | matches_9_5 & io_enqData_5_isVector + | matches_9_6 & io_enqData_6_isVector | matches_9_7 & io_enqData_7_isVector + | matches_9_8 & io_enqData_8_isVector | matches_9_9 & io_enqData_9_isVector + | matches_9_10 & io_enqData_10_isVector | matches_9_11 & io_enqData_11_isVector + | matches_9_12 & io_enqData_12_isVector | matches_9_13 & io_enqData_13_isVector + | matches_9_14 & io_enqData_14_isVector | matches_9_15 & io_enqData_15_isVector; + buffer_9_resetsVstart <= + matches_9_0 & io_enqData_0_resetsVstart | matches_9_1 + & io_enqData_1_resetsVstart | matches_9_2 & io_enqData_2_resetsVstart + | matches_9_3 & io_enqData_3_resetsVstart | matches_9_4 + & io_enqData_4_resetsVstart | matches_9_5 & io_enqData_5_resetsVstart + | matches_9_6 & io_enqData_6_resetsVstart | matches_9_7 + & io_enqData_7_resetsVstart | matches_9_8 & io_enqData_8_resetsVstart + | matches_9_9 & io_enqData_9_resetsVstart | matches_9_10 + & io_enqData_10_resetsVstart | matches_9_11 & io_enqData_11_resetsVstart + | matches_9_12 & io_enqData_12_resetsVstart | matches_9_13 + & io_enqData_13_resetsVstart | matches_9_14 & io_enqData_14_resetsVstart + | matches_9_15 & io_enqData_15_resetsVstart; + buffer_9_linkOk <= + matches_9_0 & io_enqData_0_linkOk | matches_9_1 & io_enqData_1_linkOk + | matches_9_2 & io_enqData_2_linkOk | matches_9_3 & io_enqData_3_linkOk + | matches_9_4 & io_enqData_4_linkOk | matches_9_5 & io_enqData_5_linkOk + | matches_9_6 & io_enqData_6_linkOk | matches_9_7 & io_enqData_7_linkOk + | matches_9_8 & io_enqData_8_linkOk | matches_9_9 & io_enqData_9_linkOk + | matches_9_10 & io_enqData_10_linkOk | matches_9_11 & io_enqData_11_linkOk + | matches_9_12 & io_enqData_12_linkOk | matches_9_13 & io_enqData_13_linkOk + | matches_9_14 & io_enqData_14_linkOk | matches_9_15 & io_enqData_15_linkOk; + buffer_9_isEcall <= + matches_9_0 & io_enqData_0_isEcall | matches_9_1 & io_enqData_1_isEcall + | matches_9_2 & io_enqData_2_isEcall | matches_9_3 & io_enqData_3_isEcall + | matches_9_4 & io_enqData_4_isEcall | matches_9_5 & io_enqData_5_isEcall + | matches_9_6 & io_enqData_6_isEcall | matches_9_7 & io_enqData_7_isEcall + | matches_9_8 & io_enqData_8_isEcall | matches_9_9 & io_enqData_9_isEcall + | matches_9_10 & io_enqData_10_isEcall | matches_9_11 & io_enqData_11_isEcall + | matches_9_12 & io_enqData_12_isEcall | matches_9_13 & io_enqData_13_isEcall + | matches_9_14 & io_enqData_14_isEcall | matches_9_15 & io_enqData_15_isEcall; + buffer_9_isMpause <= + matches_9_0 & io_enqData_0_isMpause | matches_9_1 & io_enqData_1_isMpause + | matches_9_2 & io_enqData_2_isMpause | matches_9_3 & io_enqData_3_isMpause + | matches_9_4 & io_enqData_4_isMpause | matches_9_5 & io_enqData_5_isMpause + | matches_9_6 & io_enqData_6_isMpause | matches_9_7 & io_enqData_7_isMpause + | matches_9_8 & io_enqData_8_isMpause | matches_9_9 & io_enqData_9_isMpause + | matches_9_10 & io_enqData_10_isMpause | matches_9_11 & io_enqData_11_isMpause + | matches_9_12 & io_enqData_12_isMpause | matches_9_13 & io_enqData_13_isMpause + | matches_9_14 & io_enqData_14_isMpause | matches_9_15 & io_enqData_15_isMpause; + buffer_9_isTile <= + matches_9_0 & io_enqData_0_isTile | matches_9_1 & io_enqData_1_isTile + | matches_9_2 & io_enqData_2_isTile | matches_9_3 & io_enqData_3_isTile + | matches_9_4 & io_enqData_4_isTile | matches_9_5 & io_enqData_5_isTile + | matches_9_6 & io_enqData_6_isTile | matches_9_7 & io_enqData_7_isTile + | matches_9_8 & io_enqData_8_isTile | matches_9_9 & io_enqData_9_isTile + | matches_9_10 & io_enqData_10_isTile | matches_9_11 & io_enqData_11_isTile + | matches_9_12 & io_enqData_12_isTile | matches_9_13 & io_enqData_13_isTile + | matches_9_14 & io_enqData_14_isTile | matches_9_15 & io_enqData_15_isTile; + end + if (|{matches_10_15, + matches_10_14, + matches_10_13, + matches_10_12, + matches_10_11, + matches_10_10, + matches_10_9, + matches_10_8, + matches_10_7, + matches_10_6, + matches_10_5, + matches_10_4, + matches_10_3, + matches_10_2, + matches_10_1, + matches_10_0}) begin + buffer_10_addr <= + (matches_10_0 ? io_enqData_0_addr : 32'h0) + | (matches_10_1 ? io_enqData_1_addr : 32'h0) + | (matches_10_2 ? io_enqData_2_addr : 32'h0) + | (matches_10_3 ? io_enqData_3_addr : 32'h0) + | (matches_10_4 ? io_enqData_4_addr : 32'h0) + | (matches_10_5 ? io_enqData_5_addr : 32'h0) + | (matches_10_6 ? io_enqData_6_addr : 32'h0) + | (matches_10_7 ? io_enqData_7_addr : 32'h0) + | (matches_10_8 ? io_enqData_8_addr : 32'h0) + | (matches_10_9 ? io_enqData_9_addr : 32'h0) + | (matches_10_10 ? io_enqData_10_addr : 32'h0) + | (matches_10_11 ? io_enqData_11_addr : 32'h0) + | (matches_10_12 ? io_enqData_12_addr : 32'h0) + | (matches_10_13 ? io_enqData_13_addr : 32'h0) + | (matches_10_14 ? io_enqData_14_addr : 32'h0) + | (matches_10_15 ? io_enqData_15_addr : 32'h0); + buffer_10_idx <= + (matches_10_0 ? io_enqData_0_idx : 7'h0) + | (matches_10_1 ? io_enqData_1_idx : 7'h0) + | (matches_10_2 ? io_enqData_2_idx : 7'h0) + | (matches_10_3 ? io_enqData_3_idx : 7'h0) + | (matches_10_4 ? io_enqData_4_idx : 7'h0) + | (matches_10_5 ? io_enqData_5_idx : 7'h0) + | (matches_10_6 ? io_enqData_6_idx : 7'h0) + | (matches_10_7 ? io_enqData_7_idx : 7'h0) + | (matches_10_8 ? io_enqData_8_idx : 7'h0) + | (matches_10_9 ? io_enqData_9_idx : 7'h0) + | (matches_10_10 ? io_enqData_10_idx : 7'h0) + | (matches_10_11 ? io_enqData_11_idx : 7'h0) + | (matches_10_12 ? io_enqData_12_idx : 7'h0) + | (matches_10_13 ? io_enqData_13_idx : 7'h0) + | (matches_10_14 ? io_enqData_14_idx : 7'h0) + | (matches_10_15 ? io_enqData_15_idx : 7'h0); + buffer_10_trap <= + matches_10_0 & io_enqData_0_trap | matches_10_1 & io_enqData_1_trap + | matches_10_2 & io_enqData_2_trap | matches_10_3 & io_enqData_3_trap + | matches_10_4 & io_enqData_4_trap | matches_10_5 & io_enqData_5_trap + | matches_10_6 & io_enqData_6_trap | matches_10_7 & io_enqData_7_trap + | matches_10_8 & io_enqData_8_trap | matches_10_9 & io_enqData_9_trap + | matches_10_10 & io_enqData_10_trap | matches_10_11 & io_enqData_11_trap + | matches_10_12 & io_enqData_12_trap | matches_10_13 & io_enqData_13_trap + | matches_10_14 & io_enqData_14_trap | matches_10_15 & io_enqData_15_trap; + buffer_10_isControlFlow <= + matches_10_0 & io_enqData_0_isControlFlow | matches_10_1 + & io_enqData_1_isControlFlow | matches_10_2 & io_enqData_2_isControlFlow + | matches_10_3 & io_enqData_3_isControlFlow | matches_10_4 + & io_enqData_4_isControlFlow | matches_10_5 & io_enqData_5_isControlFlow + | matches_10_6 & io_enqData_6_isControlFlow | matches_10_7 + & io_enqData_7_isControlFlow | matches_10_8 & io_enqData_8_isControlFlow + | matches_10_9 & io_enqData_9_isControlFlow | matches_10_10 + & io_enqData_10_isControlFlow | matches_10_11 & io_enqData_11_isControlFlow + | matches_10_12 & io_enqData_12_isControlFlow | matches_10_13 + & io_enqData_13_isControlFlow | matches_10_14 & io_enqData_14_isControlFlow + | matches_10_15 & io_enqData_15_isControlFlow; + buffer_10_isBranch <= + matches_10_0 & io_enqData_0_isBranch | matches_10_1 & io_enqData_1_isBranch + | matches_10_2 & io_enqData_2_isBranch | matches_10_3 & io_enqData_3_isBranch + | matches_10_4 & io_enqData_4_isBranch | matches_10_5 & io_enqData_5_isBranch + | matches_10_6 & io_enqData_6_isBranch | matches_10_7 & io_enqData_7_isBranch + | matches_10_8 & io_enqData_8_isBranch | matches_10_9 & io_enqData_9_isBranch + | matches_10_10 & io_enqData_10_isBranch | matches_10_11 + & io_enqData_11_isBranch | matches_10_12 & io_enqData_12_isBranch + | matches_10_13 & io_enqData_13_isBranch | matches_10_14 + & io_enqData_14_isBranch | matches_10_15 & io_enqData_15_isBranch; + buffer_10_isVector <= + matches_10_0 & io_enqData_0_isVector | matches_10_1 & io_enqData_1_isVector + | matches_10_2 & io_enqData_2_isVector | matches_10_3 & io_enqData_3_isVector + | matches_10_4 & io_enqData_4_isVector | matches_10_5 & io_enqData_5_isVector + | matches_10_6 & io_enqData_6_isVector | matches_10_7 & io_enqData_7_isVector + | matches_10_8 & io_enqData_8_isVector | matches_10_9 & io_enqData_9_isVector + | matches_10_10 & io_enqData_10_isVector | matches_10_11 + & io_enqData_11_isVector | matches_10_12 & io_enqData_12_isVector + | matches_10_13 & io_enqData_13_isVector | matches_10_14 + & io_enqData_14_isVector | matches_10_15 & io_enqData_15_isVector; + buffer_10_resetsVstart <= + matches_10_0 & io_enqData_0_resetsVstart | matches_10_1 + & io_enqData_1_resetsVstart | matches_10_2 & io_enqData_2_resetsVstart + | matches_10_3 & io_enqData_3_resetsVstart | matches_10_4 + & io_enqData_4_resetsVstart | matches_10_5 & io_enqData_5_resetsVstart + | matches_10_6 & io_enqData_6_resetsVstart | matches_10_7 + & io_enqData_7_resetsVstart | matches_10_8 & io_enqData_8_resetsVstart + | matches_10_9 & io_enqData_9_resetsVstart | matches_10_10 + & io_enqData_10_resetsVstart | matches_10_11 & io_enqData_11_resetsVstart + | matches_10_12 & io_enqData_12_resetsVstart | matches_10_13 + & io_enqData_13_resetsVstart | matches_10_14 & io_enqData_14_resetsVstart + | matches_10_15 & io_enqData_15_resetsVstart; + buffer_10_linkOk <= + matches_10_0 & io_enqData_0_linkOk | matches_10_1 & io_enqData_1_linkOk + | matches_10_2 & io_enqData_2_linkOk | matches_10_3 & io_enqData_3_linkOk + | matches_10_4 & io_enqData_4_linkOk | matches_10_5 & io_enqData_5_linkOk + | matches_10_6 & io_enqData_6_linkOk | matches_10_7 & io_enqData_7_linkOk + | matches_10_8 & io_enqData_8_linkOk | matches_10_9 & io_enqData_9_linkOk + | matches_10_10 & io_enqData_10_linkOk | matches_10_11 & io_enqData_11_linkOk + | matches_10_12 & io_enqData_12_linkOk | matches_10_13 & io_enqData_13_linkOk + | matches_10_14 & io_enqData_14_linkOk | matches_10_15 & io_enqData_15_linkOk; + buffer_10_isEcall <= + matches_10_0 & io_enqData_0_isEcall | matches_10_1 & io_enqData_1_isEcall + | matches_10_2 & io_enqData_2_isEcall | matches_10_3 & io_enqData_3_isEcall + | matches_10_4 & io_enqData_4_isEcall | matches_10_5 & io_enqData_5_isEcall + | matches_10_6 & io_enqData_6_isEcall | matches_10_7 & io_enqData_7_isEcall + | matches_10_8 & io_enqData_8_isEcall | matches_10_9 & io_enqData_9_isEcall + | matches_10_10 & io_enqData_10_isEcall | matches_10_11 & io_enqData_11_isEcall + | matches_10_12 & io_enqData_12_isEcall | matches_10_13 & io_enqData_13_isEcall + | matches_10_14 & io_enqData_14_isEcall | matches_10_15 & io_enqData_15_isEcall; + buffer_10_isMpause <= + matches_10_0 & io_enqData_0_isMpause | matches_10_1 & io_enqData_1_isMpause + | matches_10_2 & io_enqData_2_isMpause | matches_10_3 & io_enqData_3_isMpause + | matches_10_4 & io_enqData_4_isMpause | matches_10_5 & io_enqData_5_isMpause + | matches_10_6 & io_enqData_6_isMpause | matches_10_7 & io_enqData_7_isMpause + | matches_10_8 & io_enqData_8_isMpause | matches_10_9 & io_enqData_9_isMpause + | matches_10_10 & io_enqData_10_isMpause | matches_10_11 + & io_enqData_11_isMpause | matches_10_12 & io_enqData_12_isMpause + | matches_10_13 & io_enqData_13_isMpause | matches_10_14 + & io_enqData_14_isMpause | matches_10_15 & io_enqData_15_isMpause; + buffer_10_isTile <= + matches_10_0 & io_enqData_0_isTile | matches_10_1 & io_enqData_1_isTile + | matches_10_2 & io_enqData_2_isTile | matches_10_3 & io_enqData_3_isTile + | matches_10_4 & io_enqData_4_isTile | matches_10_5 & io_enqData_5_isTile + | matches_10_6 & io_enqData_6_isTile | matches_10_7 & io_enqData_7_isTile + | matches_10_8 & io_enqData_8_isTile | matches_10_9 & io_enqData_9_isTile + | matches_10_10 & io_enqData_10_isTile | matches_10_11 & io_enqData_11_isTile + | matches_10_12 & io_enqData_12_isTile | matches_10_13 & io_enqData_13_isTile + | matches_10_14 & io_enqData_14_isTile | matches_10_15 & io_enqData_15_isTile; + end + if (|{matches_11_15, + matches_11_14, + matches_11_13, + matches_11_12, + matches_11_11, + matches_11_10, + matches_11_9, + matches_11_8, + matches_11_7, + matches_11_6, + matches_11_5, + matches_11_4, + matches_11_3, + matches_11_2, + matches_11_1, + matches_11_0}) begin + buffer_11_addr <= + (matches_11_0 ? io_enqData_0_addr : 32'h0) + | (matches_11_1 ? io_enqData_1_addr : 32'h0) + | (matches_11_2 ? io_enqData_2_addr : 32'h0) + | (matches_11_3 ? io_enqData_3_addr : 32'h0) + | (matches_11_4 ? io_enqData_4_addr : 32'h0) + | (matches_11_5 ? io_enqData_5_addr : 32'h0) + | (matches_11_6 ? io_enqData_6_addr : 32'h0) + | (matches_11_7 ? io_enqData_7_addr : 32'h0) + | (matches_11_8 ? io_enqData_8_addr : 32'h0) + | (matches_11_9 ? io_enqData_9_addr : 32'h0) + | (matches_11_10 ? io_enqData_10_addr : 32'h0) + | (matches_11_11 ? io_enqData_11_addr : 32'h0) + | (matches_11_12 ? io_enqData_12_addr : 32'h0) + | (matches_11_13 ? io_enqData_13_addr : 32'h0) + | (matches_11_14 ? io_enqData_14_addr : 32'h0) + | (matches_11_15 ? io_enqData_15_addr : 32'h0); + buffer_11_idx <= + (matches_11_0 ? io_enqData_0_idx : 7'h0) + | (matches_11_1 ? io_enqData_1_idx : 7'h0) + | (matches_11_2 ? io_enqData_2_idx : 7'h0) + | (matches_11_3 ? io_enqData_3_idx : 7'h0) + | (matches_11_4 ? io_enqData_4_idx : 7'h0) + | (matches_11_5 ? io_enqData_5_idx : 7'h0) + | (matches_11_6 ? io_enqData_6_idx : 7'h0) + | (matches_11_7 ? io_enqData_7_idx : 7'h0) + | (matches_11_8 ? io_enqData_8_idx : 7'h0) + | (matches_11_9 ? io_enqData_9_idx : 7'h0) + | (matches_11_10 ? io_enqData_10_idx : 7'h0) + | (matches_11_11 ? io_enqData_11_idx : 7'h0) + | (matches_11_12 ? io_enqData_12_idx : 7'h0) + | (matches_11_13 ? io_enqData_13_idx : 7'h0) + | (matches_11_14 ? io_enqData_14_idx : 7'h0) + | (matches_11_15 ? io_enqData_15_idx : 7'h0); + buffer_11_trap <= + matches_11_0 & io_enqData_0_trap | matches_11_1 & io_enqData_1_trap + | matches_11_2 & io_enqData_2_trap | matches_11_3 & io_enqData_3_trap + | matches_11_4 & io_enqData_4_trap | matches_11_5 & io_enqData_5_trap + | matches_11_6 & io_enqData_6_trap | matches_11_7 & io_enqData_7_trap + | matches_11_8 & io_enqData_8_trap | matches_11_9 & io_enqData_9_trap + | matches_11_10 & io_enqData_10_trap | matches_11_11 & io_enqData_11_trap + | matches_11_12 & io_enqData_12_trap | matches_11_13 & io_enqData_13_trap + | matches_11_14 & io_enqData_14_trap | matches_11_15 & io_enqData_15_trap; + buffer_11_isControlFlow <= + matches_11_0 & io_enqData_0_isControlFlow | matches_11_1 + & io_enqData_1_isControlFlow | matches_11_2 & io_enqData_2_isControlFlow + | matches_11_3 & io_enqData_3_isControlFlow | matches_11_4 + & io_enqData_4_isControlFlow | matches_11_5 & io_enqData_5_isControlFlow + | matches_11_6 & io_enqData_6_isControlFlow | matches_11_7 + & io_enqData_7_isControlFlow | matches_11_8 & io_enqData_8_isControlFlow + | matches_11_9 & io_enqData_9_isControlFlow | matches_11_10 + & io_enqData_10_isControlFlow | matches_11_11 & io_enqData_11_isControlFlow + | matches_11_12 & io_enqData_12_isControlFlow | matches_11_13 + & io_enqData_13_isControlFlow | matches_11_14 & io_enqData_14_isControlFlow + | matches_11_15 & io_enqData_15_isControlFlow; + buffer_11_isBranch <= + matches_11_0 & io_enqData_0_isBranch | matches_11_1 & io_enqData_1_isBranch + | matches_11_2 & io_enqData_2_isBranch | matches_11_3 & io_enqData_3_isBranch + | matches_11_4 & io_enqData_4_isBranch | matches_11_5 & io_enqData_5_isBranch + | matches_11_6 & io_enqData_6_isBranch | matches_11_7 & io_enqData_7_isBranch + | matches_11_8 & io_enqData_8_isBranch | matches_11_9 & io_enqData_9_isBranch + | matches_11_10 & io_enqData_10_isBranch | matches_11_11 + & io_enqData_11_isBranch | matches_11_12 & io_enqData_12_isBranch + | matches_11_13 & io_enqData_13_isBranch | matches_11_14 + & io_enqData_14_isBranch | matches_11_15 & io_enqData_15_isBranch; + buffer_11_isVector <= + matches_11_0 & io_enqData_0_isVector | matches_11_1 & io_enqData_1_isVector + | matches_11_2 & io_enqData_2_isVector | matches_11_3 & io_enqData_3_isVector + | matches_11_4 & io_enqData_4_isVector | matches_11_5 & io_enqData_5_isVector + | matches_11_6 & io_enqData_6_isVector | matches_11_7 & io_enqData_7_isVector + | matches_11_8 & io_enqData_8_isVector | matches_11_9 & io_enqData_9_isVector + | matches_11_10 & io_enqData_10_isVector | matches_11_11 + & io_enqData_11_isVector | matches_11_12 & io_enqData_12_isVector + | matches_11_13 & io_enqData_13_isVector | matches_11_14 + & io_enqData_14_isVector | matches_11_15 & io_enqData_15_isVector; + buffer_11_resetsVstart <= + matches_11_0 & io_enqData_0_resetsVstart | matches_11_1 + & io_enqData_1_resetsVstart | matches_11_2 & io_enqData_2_resetsVstart + | matches_11_3 & io_enqData_3_resetsVstart | matches_11_4 + & io_enqData_4_resetsVstart | matches_11_5 & io_enqData_5_resetsVstart + | matches_11_6 & io_enqData_6_resetsVstart | matches_11_7 + & io_enqData_7_resetsVstart | matches_11_8 & io_enqData_8_resetsVstart + | matches_11_9 & io_enqData_9_resetsVstart | matches_11_10 + & io_enqData_10_resetsVstart | matches_11_11 & io_enqData_11_resetsVstart + | matches_11_12 & io_enqData_12_resetsVstart | matches_11_13 + & io_enqData_13_resetsVstart | matches_11_14 & io_enqData_14_resetsVstart + | matches_11_15 & io_enqData_15_resetsVstart; + buffer_11_linkOk <= + matches_11_0 & io_enqData_0_linkOk | matches_11_1 & io_enqData_1_linkOk + | matches_11_2 & io_enqData_2_linkOk | matches_11_3 & io_enqData_3_linkOk + | matches_11_4 & io_enqData_4_linkOk | matches_11_5 & io_enqData_5_linkOk + | matches_11_6 & io_enqData_6_linkOk | matches_11_7 & io_enqData_7_linkOk + | matches_11_8 & io_enqData_8_linkOk | matches_11_9 & io_enqData_9_linkOk + | matches_11_10 & io_enqData_10_linkOk | matches_11_11 & io_enqData_11_linkOk + | matches_11_12 & io_enqData_12_linkOk | matches_11_13 & io_enqData_13_linkOk + | matches_11_14 & io_enqData_14_linkOk | matches_11_15 & io_enqData_15_linkOk; + buffer_11_isEcall <= + matches_11_0 & io_enqData_0_isEcall | matches_11_1 & io_enqData_1_isEcall + | matches_11_2 & io_enqData_2_isEcall | matches_11_3 & io_enqData_3_isEcall + | matches_11_4 & io_enqData_4_isEcall | matches_11_5 & io_enqData_5_isEcall + | matches_11_6 & io_enqData_6_isEcall | matches_11_7 & io_enqData_7_isEcall + | matches_11_8 & io_enqData_8_isEcall | matches_11_9 & io_enqData_9_isEcall + | matches_11_10 & io_enqData_10_isEcall | matches_11_11 & io_enqData_11_isEcall + | matches_11_12 & io_enqData_12_isEcall | matches_11_13 & io_enqData_13_isEcall + | matches_11_14 & io_enqData_14_isEcall | matches_11_15 & io_enqData_15_isEcall; + buffer_11_isMpause <= + matches_11_0 & io_enqData_0_isMpause | matches_11_1 & io_enqData_1_isMpause + | matches_11_2 & io_enqData_2_isMpause | matches_11_3 & io_enqData_3_isMpause + | matches_11_4 & io_enqData_4_isMpause | matches_11_5 & io_enqData_5_isMpause + | matches_11_6 & io_enqData_6_isMpause | matches_11_7 & io_enqData_7_isMpause + | matches_11_8 & io_enqData_8_isMpause | matches_11_9 & io_enqData_9_isMpause + | matches_11_10 & io_enqData_10_isMpause | matches_11_11 + & io_enqData_11_isMpause | matches_11_12 & io_enqData_12_isMpause + | matches_11_13 & io_enqData_13_isMpause | matches_11_14 + & io_enqData_14_isMpause | matches_11_15 & io_enqData_15_isMpause; + buffer_11_isTile <= + matches_11_0 & io_enqData_0_isTile | matches_11_1 & io_enqData_1_isTile + | matches_11_2 & io_enqData_2_isTile | matches_11_3 & io_enqData_3_isTile + | matches_11_4 & io_enqData_4_isTile | matches_11_5 & io_enqData_5_isTile + | matches_11_6 & io_enqData_6_isTile | matches_11_7 & io_enqData_7_isTile + | matches_11_8 & io_enqData_8_isTile | matches_11_9 & io_enqData_9_isTile + | matches_11_10 & io_enqData_10_isTile | matches_11_11 & io_enqData_11_isTile + | matches_11_12 & io_enqData_12_isTile | matches_11_13 & io_enqData_13_isTile + | matches_11_14 & io_enqData_14_isTile | matches_11_15 & io_enqData_15_isTile; + end + if (|{matches_12_15, + matches_12_14, + matches_12_13, + matches_12_12, + matches_12_11, + matches_12_10, + matches_12_9, + matches_12_8, + matches_12_7, + matches_12_6, + matches_12_5, + matches_12_4, + matches_12_3, + matches_12_2, + matches_12_1, + matches_12_0}) begin + buffer_12_addr <= + (matches_12_0 ? io_enqData_0_addr : 32'h0) + | (matches_12_1 ? io_enqData_1_addr : 32'h0) + | (matches_12_2 ? io_enqData_2_addr : 32'h0) + | (matches_12_3 ? io_enqData_3_addr : 32'h0) + | (matches_12_4 ? io_enqData_4_addr : 32'h0) + | (matches_12_5 ? io_enqData_5_addr : 32'h0) + | (matches_12_6 ? io_enqData_6_addr : 32'h0) + | (matches_12_7 ? io_enqData_7_addr : 32'h0) + | (matches_12_8 ? io_enqData_8_addr : 32'h0) + | (matches_12_9 ? io_enqData_9_addr : 32'h0) + | (matches_12_10 ? io_enqData_10_addr : 32'h0) + | (matches_12_11 ? io_enqData_11_addr : 32'h0) + | (matches_12_12 ? io_enqData_12_addr : 32'h0) + | (matches_12_13 ? io_enqData_13_addr : 32'h0) + | (matches_12_14 ? io_enqData_14_addr : 32'h0) + | (matches_12_15 ? io_enqData_15_addr : 32'h0); + buffer_12_idx <= + (matches_12_0 ? io_enqData_0_idx : 7'h0) + | (matches_12_1 ? io_enqData_1_idx : 7'h0) + | (matches_12_2 ? io_enqData_2_idx : 7'h0) + | (matches_12_3 ? io_enqData_3_idx : 7'h0) + | (matches_12_4 ? io_enqData_4_idx : 7'h0) + | (matches_12_5 ? io_enqData_5_idx : 7'h0) + | (matches_12_6 ? io_enqData_6_idx : 7'h0) + | (matches_12_7 ? io_enqData_7_idx : 7'h0) + | (matches_12_8 ? io_enqData_8_idx : 7'h0) + | (matches_12_9 ? io_enqData_9_idx : 7'h0) + | (matches_12_10 ? io_enqData_10_idx : 7'h0) + | (matches_12_11 ? io_enqData_11_idx : 7'h0) + | (matches_12_12 ? io_enqData_12_idx : 7'h0) + | (matches_12_13 ? io_enqData_13_idx : 7'h0) + | (matches_12_14 ? io_enqData_14_idx : 7'h0) + | (matches_12_15 ? io_enqData_15_idx : 7'h0); + buffer_12_trap <= + matches_12_0 & io_enqData_0_trap | matches_12_1 & io_enqData_1_trap + | matches_12_2 & io_enqData_2_trap | matches_12_3 & io_enqData_3_trap + | matches_12_4 & io_enqData_4_trap | matches_12_5 & io_enqData_5_trap + | matches_12_6 & io_enqData_6_trap | matches_12_7 & io_enqData_7_trap + | matches_12_8 & io_enqData_8_trap | matches_12_9 & io_enqData_9_trap + | matches_12_10 & io_enqData_10_trap | matches_12_11 & io_enqData_11_trap + | matches_12_12 & io_enqData_12_trap | matches_12_13 & io_enqData_13_trap + | matches_12_14 & io_enqData_14_trap | matches_12_15 & io_enqData_15_trap; + buffer_12_isControlFlow <= + matches_12_0 & io_enqData_0_isControlFlow | matches_12_1 + & io_enqData_1_isControlFlow | matches_12_2 & io_enqData_2_isControlFlow + | matches_12_3 & io_enqData_3_isControlFlow | matches_12_4 + & io_enqData_4_isControlFlow | matches_12_5 & io_enqData_5_isControlFlow + | matches_12_6 & io_enqData_6_isControlFlow | matches_12_7 + & io_enqData_7_isControlFlow | matches_12_8 & io_enqData_8_isControlFlow + | matches_12_9 & io_enqData_9_isControlFlow | matches_12_10 + & io_enqData_10_isControlFlow | matches_12_11 & io_enqData_11_isControlFlow + | matches_12_12 & io_enqData_12_isControlFlow | matches_12_13 + & io_enqData_13_isControlFlow | matches_12_14 & io_enqData_14_isControlFlow + | matches_12_15 & io_enqData_15_isControlFlow; + buffer_12_isBranch <= + matches_12_0 & io_enqData_0_isBranch | matches_12_1 & io_enqData_1_isBranch + | matches_12_2 & io_enqData_2_isBranch | matches_12_3 & io_enqData_3_isBranch + | matches_12_4 & io_enqData_4_isBranch | matches_12_5 & io_enqData_5_isBranch + | matches_12_6 & io_enqData_6_isBranch | matches_12_7 & io_enqData_7_isBranch + | matches_12_8 & io_enqData_8_isBranch | matches_12_9 & io_enqData_9_isBranch + | matches_12_10 & io_enqData_10_isBranch | matches_12_11 + & io_enqData_11_isBranch | matches_12_12 & io_enqData_12_isBranch + | matches_12_13 & io_enqData_13_isBranch | matches_12_14 + & io_enqData_14_isBranch | matches_12_15 & io_enqData_15_isBranch; + buffer_12_isVector <= + matches_12_0 & io_enqData_0_isVector | matches_12_1 & io_enqData_1_isVector + | matches_12_2 & io_enqData_2_isVector | matches_12_3 & io_enqData_3_isVector + | matches_12_4 & io_enqData_4_isVector | matches_12_5 & io_enqData_5_isVector + | matches_12_6 & io_enqData_6_isVector | matches_12_7 & io_enqData_7_isVector + | matches_12_8 & io_enqData_8_isVector | matches_12_9 & io_enqData_9_isVector + | matches_12_10 & io_enqData_10_isVector | matches_12_11 + & io_enqData_11_isVector | matches_12_12 & io_enqData_12_isVector + | matches_12_13 & io_enqData_13_isVector | matches_12_14 + & io_enqData_14_isVector | matches_12_15 & io_enqData_15_isVector; + buffer_12_resetsVstart <= + matches_12_0 & io_enqData_0_resetsVstart | matches_12_1 + & io_enqData_1_resetsVstart | matches_12_2 & io_enqData_2_resetsVstart + | matches_12_3 & io_enqData_3_resetsVstart | matches_12_4 + & io_enqData_4_resetsVstart | matches_12_5 & io_enqData_5_resetsVstart + | matches_12_6 & io_enqData_6_resetsVstart | matches_12_7 + & io_enqData_7_resetsVstart | matches_12_8 & io_enqData_8_resetsVstart + | matches_12_9 & io_enqData_9_resetsVstart | matches_12_10 + & io_enqData_10_resetsVstart | matches_12_11 & io_enqData_11_resetsVstart + | matches_12_12 & io_enqData_12_resetsVstart | matches_12_13 + & io_enqData_13_resetsVstart | matches_12_14 & io_enqData_14_resetsVstart + | matches_12_15 & io_enqData_15_resetsVstart; + buffer_12_linkOk <= + matches_12_0 & io_enqData_0_linkOk | matches_12_1 & io_enqData_1_linkOk + | matches_12_2 & io_enqData_2_linkOk | matches_12_3 & io_enqData_3_linkOk + | matches_12_4 & io_enqData_4_linkOk | matches_12_5 & io_enqData_5_linkOk + | matches_12_6 & io_enqData_6_linkOk | matches_12_7 & io_enqData_7_linkOk + | matches_12_8 & io_enqData_8_linkOk | matches_12_9 & io_enqData_9_linkOk + | matches_12_10 & io_enqData_10_linkOk | matches_12_11 & io_enqData_11_linkOk + | matches_12_12 & io_enqData_12_linkOk | matches_12_13 & io_enqData_13_linkOk + | matches_12_14 & io_enqData_14_linkOk | matches_12_15 & io_enqData_15_linkOk; + buffer_12_isEcall <= + matches_12_0 & io_enqData_0_isEcall | matches_12_1 & io_enqData_1_isEcall + | matches_12_2 & io_enqData_2_isEcall | matches_12_3 & io_enqData_3_isEcall + | matches_12_4 & io_enqData_4_isEcall | matches_12_5 & io_enqData_5_isEcall + | matches_12_6 & io_enqData_6_isEcall | matches_12_7 & io_enqData_7_isEcall + | matches_12_8 & io_enqData_8_isEcall | matches_12_9 & io_enqData_9_isEcall + | matches_12_10 & io_enqData_10_isEcall | matches_12_11 & io_enqData_11_isEcall + | matches_12_12 & io_enqData_12_isEcall | matches_12_13 & io_enqData_13_isEcall + | matches_12_14 & io_enqData_14_isEcall | matches_12_15 & io_enqData_15_isEcall; + buffer_12_isMpause <= + matches_12_0 & io_enqData_0_isMpause | matches_12_1 & io_enqData_1_isMpause + | matches_12_2 & io_enqData_2_isMpause | matches_12_3 & io_enqData_3_isMpause + | matches_12_4 & io_enqData_4_isMpause | matches_12_5 & io_enqData_5_isMpause + | matches_12_6 & io_enqData_6_isMpause | matches_12_7 & io_enqData_7_isMpause + | matches_12_8 & io_enqData_8_isMpause | matches_12_9 & io_enqData_9_isMpause + | matches_12_10 & io_enqData_10_isMpause | matches_12_11 + & io_enqData_11_isMpause | matches_12_12 & io_enqData_12_isMpause + | matches_12_13 & io_enqData_13_isMpause | matches_12_14 + & io_enqData_14_isMpause | matches_12_15 & io_enqData_15_isMpause; + buffer_12_isTile <= + matches_12_0 & io_enqData_0_isTile | matches_12_1 & io_enqData_1_isTile + | matches_12_2 & io_enqData_2_isTile | matches_12_3 & io_enqData_3_isTile + | matches_12_4 & io_enqData_4_isTile | matches_12_5 & io_enqData_5_isTile + | matches_12_6 & io_enqData_6_isTile | matches_12_7 & io_enqData_7_isTile + | matches_12_8 & io_enqData_8_isTile | matches_12_9 & io_enqData_9_isTile + | matches_12_10 & io_enqData_10_isTile | matches_12_11 & io_enqData_11_isTile + | matches_12_12 & io_enqData_12_isTile | matches_12_13 & io_enqData_13_isTile + | matches_12_14 & io_enqData_14_isTile | matches_12_15 & io_enqData_15_isTile; + end + if (|{matches_13_15, + matches_13_14, + matches_13_13, + matches_13_12, + matches_13_11, + matches_13_10, + matches_13_9, + matches_13_8, + matches_13_7, + matches_13_6, + matches_13_5, + matches_13_4, + matches_13_3, + matches_13_2, + matches_13_1, + matches_13_0}) begin + buffer_13_addr <= + (matches_13_0 ? io_enqData_0_addr : 32'h0) + | (matches_13_1 ? io_enqData_1_addr : 32'h0) + | (matches_13_2 ? io_enqData_2_addr : 32'h0) + | (matches_13_3 ? io_enqData_3_addr : 32'h0) + | (matches_13_4 ? io_enqData_4_addr : 32'h0) + | (matches_13_5 ? io_enqData_5_addr : 32'h0) + | (matches_13_6 ? io_enqData_6_addr : 32'h0) + | (matches_13_7 ? io_enqData_7_addr : 32'h0) + | (matches_13_8 ? io_enqData_8_addr : 32'h0) + | (matches_13_9 ? io_enqData_9_addr : 32'h0) + | (matches_13_10 ? io_enqData_10_addr : 32'h0) + | (matches_13_11 ? io_enqData_11_addr : 32'h0) + | (matches_13_12 ? io_enqData_12_addr : 32'h0) + | (matches_13_13 ? io_enqData_13_addr : 32'h0) + | (matches_13_14 ? io_enqData_14_addr : 32'h0) + | (matches_13_15 ? io_enqData_15_addr : 32'h0); + buffer_13_idx <= + (matches_13_0 ? io_enqData_0_idx : 7'h0) + | (matches_13_1 ? io_enqData_1_idx : 7'h0) + | (matches_13_2 ? io_enqData_2_idx : 7'h0) + | (matches_13_3 ? io_enqData_3_idx : 7'h0) + | (matches_13_4 ? io_enqData_4_idx : 7'h0) + | (matches_13_5 ? io_enqData_5_idx : 7'h0) + | (matches_13_6 ? io_enqData_6_idx : 7'h0) + | (matches_13_7 ? io_enqData_7_idx : 7'h0) + | (matches_13_8 ? io_enqData_8_idx : 7'h0) + | (matches_13_9 ? io_enqData_9_idx : 7'h0) + | (matches_13_10 ? io_enqData_10_idx : 7'h0) + | (matches_13_11 ? io_enqData_11_idx : 7'h0) + | (matches_13_12 ? io_enqData_12_idx : 7'h0) + | (matches_13_13 ? io_enqData_13_idx : 7'h0) + | (matches_13_14 ? io_enqData_14_idx : 7'h0) + | (matches_13_15 ? io_enqData_15_idx : 7'h0); + buffer_13_trap <= + matches_13_0 & io_enqData_0_trap | matches_13_1 & io_enqData_1_trap + | matches_13_2 & io_enqData_2_trap | matches_13_3 & io_enqData_3_trap + | matches_13_4 & io_enqData_4_trap | matches_13_5 & io_enqData_5_trap + | matches_13_6 & io_enqData_6_trap | matches_13_7 & io_enqData_7_trap + | matches_13_8 & io_enqData_8_trap | matches_13_9 & io_enqData_9_trap + | matches_13_10 & io_enqData_10_trap | matches_13_11 & io_enqData_11_trap + | matches_13_12 & io_enqData_12_trap | matches_13_13 & io_enqData_13_trap + | matches_13_14 & io_enqData_14_trap | matches_13_15 & io_enqData_15_trap; + buffer_13_isControlFlow <= + matches_13_0 & io_enqData_0_isControlFlow | matches_13_1 + & io_enqData_1_isControlFlow | matches_13_2 & io_enqData_2_isControlFlow + | matches_13_3 & io_enqData_3_isControlFlow | matches_13_4 + & io_enqData_4_isControlFlow | matches_13_5 & io_enqData_5_isControlFlow + | matches_13_6 & io_enqData_6_isControlFlow | matches_13_7 + & io_enqData_7_isControlFlow | matches_13_8 & io_enqData_8_isControlFlow + | matches_13_9 & io_enqData_9_isControlFlow | matches_13_10 + & io_enqData_10_isControlFlow | matches_13_11 & io_enqData_11_isControlFlow + | matches_13_12 & io_enqData_12_isControlFlow | matches_13_13 + & io_enqData_13_isControlFlow | matches_13_14 & io_enqData_14_isControlFlow + | matches_13_15 & io_enqData_15_isControlFlow; + buffer_13_isBranch <= + matches_13_0 & io_enqData_0_isBranch | matches_13_1 & io_enqData_1_isBranch + | matches_13_2 & io_enqData_2_isBranch | matches_13_3 & io_enqData_3_isBranch + | matches_13_4 & io_enqData_4_isBranch | matches_13_5 & io_enqData_5_isBranch + | matches_13_6 & io_enqData_6_isBranch | matches_13_7 & io_enqData_7_isBranch + | matches_13_8 & io_enqData_8_isBranch | matches_13_9 & io_enqData_9_isBranch + | matches_13_10 & io_enqData_10_isBranch | matches_13_11 + & io_enqData_11_isBranch | matches_13_12 & io_enqData_12_isBranch + | matches_13_13 & io_enqData_13_isBranch | matches_13_14 + & io_enqData_14_isBranch | matches_13_15 & io_enqData_15_isBranch; + buffer_13_isVector <= + matches_13_0 & io_enqData_0_isVector | matches_13_1 & io_enqData_1_isVector + | matches_13_2 & io_enqData_2_isVector | matches_13_3 & io_enqData_3_isVector + | matches_13_4 & io_enqData_4_isVector | matches_13_5 & io_enqData_5_isVector + | matches_13_6 & io_enqData_6_isVector | matches_13_7 & io_enqData_7_isVector + | matches_13_8 & io_enqData_8_isVector | matches_13_9 & io_enqData_9_isVector + | matches_13_10 & io_enqData_10_isVector | matches_13_11 + & io_enqData_11_isVector | matches_13_12 & io_enqData_12_isVector + | matches_13_13 & io_enqData_13_isVector | matches_13_14 + & io_enqData_14_isVector | matches_13_15 & io_enqData_15_isVector; + buffer_13_resetsVstart <= + matches_13_0 & io_enqData_0_resetsVstart | matches_13_1 + & io_enqData_1_resetsVstart | matches_13_2 & io_enqData_2_resetsVstart + | matches_13_3 & io_enqData_3_resetsVstart | matches_13_4 + & io_enqData_4_resetsVstart | matches_13_5 & io_enqData_5_resetsVstart + | matches_13_6 & io_enqData_6_resetsVstart | matches_13_7 + & io_enqData_7_resetsVstart | matches_13_8 & io_enqData_8_resetsVstart + | matches_13_9 & io_enqData_9_resetsVstart | matches_13_10 + & io_enqData_10_resetsVstart | matches_13_11 & io_enqData_11_resetsVstart + | matches_13_12 & io_enqData_12_resetsVstart | matches_13_13 + & io_enqData_13_resetsVstart | matches_13_14 & io_enqData_14_resetsVstart + | matches_13_15 & io_enqData_15_resetsVstart; + buffer_13_linkOk <= + matches_13_0 & io_enqData_0_linkOk | matches_13_1 & io_enqData_1_linkOk + | matches_13_2 & io_enqData_2_linkOk | matches_13_3 & io_enqData_3_linkOk + | matches_13_4 & io_enqData_4_linkOk | matches_13_5 & io_enqData_5_linkOk + | matches_13_6 & io_enqData_6_linkOk | matches_13_7 & io_enqData_7_linkOk + | matches_13_8 & io_enqData_8_linkOk | matches_13_9 & io_enqData_9_linkOk + | matches_13_10 & io_enqData_10_linkOk | matches_13_11 & io_enqData_11_linkOk + | matches_13_12 & io_enqData_12_linkOk | matches_13_13 & io_enqData_13_linkOk + | matches_13_14 & io_enqData_14_linkOk | matches_13_15 & io_enqData_15_linkOk; + buffer_13_isEcall <= + matches_13_0 & io_enqData_0_isEcall | matches_13_1 & io_enqData_1_isEcall + | matches_13_2 & io_enqData_2_isEcall | matches_13_3 & io_enqData_3_isEcall + | matches_13_4 & io_enqData_4_isEcall | matches_13_5 & io_enqData_5_isEcall + | matches_13_6 & io_enqData_6_isEcall | matches_13_7 & io_enqData_7_isEcall + | matches_13_8 & io_enqData_8_isEcall | matches_13_9 & io_enqData_9_isEcall + | matches_13_10 & io_enqData_10_isEcall | matches_13_11 & io_enqData_11_isEcall + | matches_13_12 & io_enqData_12_isEcall | matches_13_13 & io_enqData_13_isEcall + | matches_13_14 & io_enqData_14_isEcall | matches_13_15 & io_enqData_15_isEcall; + buffer_13_isMpause <= + matches_13_0 & io_enqData_0_isMpause | matches_13_1 & io_enqData_1_isMpause + | matches_13_2 & io_enqData_2_isMpause | matches_13_3 & io_enqData_3_isMpause + | matches_13_4 & io_enqData_4_isMpause | matches_13_5 & io_enqData_5_isMpause + | matches_13_6 & io_enqData_6_isMpause | matches_13_7 & io_enqData_7_isMpause + | matches_13_8 & io_enqData_8_isMpause | matches_13_9 & io_enqData_9_isMpause + | matches_13_10 & io_enqData_10_isMpause | matches_13_11 + & io_enqData_11_isMpause | matches_13_12 & io_enqData_12_isMpause + | matches_13_13 & io_enqData_13_isMpause | matches_13_14 + & io_enqData_14_isMpause | matches_13_15 & io_enqData_15_isMpause; + buffer_13_isTile <= + matches_13_0 & io_enqData_0_isTile | matches_13_1 & io_enqData_1_isTile + | matches_13_2 & io_enqData_2_isTile | matches_13_3 & io_enqData_3_isTile + | matches_13_4 & io_enqData_4_isTile | matches_13_5 & io_enqData_5_isTile + | matches_13_6 & io_enqData_6_isTile | matches_13_7 & io_enqData_7_isTile + | matches_13_8 & io_enqData_8_isTile | matches_13_9 & io_enqData_9_isTile + | matches_13_10 & io_enqData_10_isTile | matches_13_11 & io_enqData_11_isTile + | matches_13_12 & io_enqData_12_isTile | matches_13_13 & io_enqData_13_isTile + | matches_13_14 & io_enqData_14_isTile | matches_13_15 & io_enqData_15_isTile; + end + if (|{matches_14_15, + matches_14_14, + matches_14_13, + matches_14_12, + matches_14_11, + matches_14_10, + matches_14_9, + matches_14_8, + matches_14_7, + matches_14_6, + matches_14_5, + matches_14_4, + matches_14_3, + matches_14_2, + matches_14_1, + matches_14_0}) begin + buffer_14_addr <= + (matches_14_0 ? io_enqData_0_addr : 32'h0) + | (matches_14_1 ? io_enqData_1_addr : 32'h0) + | (matches_14_2 ? io_enqData_2_addr : 32'h0) + | (matches_14_3 ? io_enqData_3_addr : 32'h0) + | (matches_14_4 ? io_enqData_4_addr : 32'h0) + | (matches_14_5 ? io_enqData_5_addr : 32'h0) + | (matches_14_6 ? io_enqData_6_addr : 32'h0) + | (matches_14_7 ? io_enqData_7_addr : 32'h0) + | (matches_14_8 ? io_enqData_8_addr : 32'h0) + | (matches_14_9 ? io_enqData_9_addr : 32'h0) + | (matches_14_10 ? io_enqData_10_addr : 32'h0) + | (matches_14_11 ? io_enqData_11_addr : 32'h0) + | (matches_14_12 ? io_enqData_12_addr : 32'h0) + | (matches_14_13 ? io_enqData_13_addr : 32'h0) + | (matches_14_14 ? io_enqData_14_addr : 32'h0) + | (matches_14_15 ? io_enqData_15_addr : 32'h0); + buffer_14_idx <= + (matches_14_0 ? io_enqData_0_idx : 7'h0) + | (matches_14_1 ? io_enqData_1_idx : 7'h0) + | (matches_14_2 ? io_enqData_2_idx : 7'h0) + | (matches_14_3 ? io_enqData_3_idx : 7'h0) + | (matches_14_4 ? io_enqData_4_idx : 7'h0) + | (matches_14_5 ? io_enqData_5_idx : 7'h0) + | (matches_14_6 ? io_enqData_6_idx : 7'h0) + | (matches_14_7 ? io_enqData_7_idx : 7'h0) + | (matches_14_8 ? io_enqData_8_idx : 7'h0) + | (matches_14_9 ? io_enqData_9_idx : 7'h0) + | (matches_14_10 ? io_enqData_10_idx : 7'h0) + | (matches_14_11 ? io_enqData_11_idx : 7'h0) + | (matches_14_12 ? io_enqData_12_idx : 7'h0) + | (matches_14_13 ? io_enqData_13_idx : 7'h0) + | (matches_14_14 ? io_enqData_14_idx : 7'h0) + | (matches_14_15 ? io_enqData_15_idx : 7'h0); + buffer_14_trap <= + matches_14_0 & io_enqData_0_trap | matches_14_1 & io_enqData_1_trap + | matches_14_2 & io_enqData_2_trap | matches_14_3 & io_enqData_3_trap + | matches_14_4 & io_enqData_4_trap | matches_14_5 & io_enqData_5_trap + | matches_14_6 & io_enqData_6_trap | matches_14_7 & io_enqData_7_trap + | matches_14_8 & io_enqData_8_trap | matches_14_9 & io_enqData_9_trap + | matches_14_10 & io_enqData_10_trap | matches_14_11 & io_enqData_11_trap + | matches_14_12 & io_enqData_12_trap | matches_14_13 & io_enqData_13_trap + | matches_14_14 & io_enqData_14_trap | matches_14_15 & io_enqData_15_trap; + buffer_14_isControlFlow <= + matches_14_0 & io_enqData_0_isControlFlow | matches_14_1 + & io_enqData_1_isControlFlow | matches_14_2 & io_enqData_2_isControlFlow + | matches_14_3 & io_enqData_3_isControlFlow | matches_14_4 + & io_enqData_4_isControlFlow | matches_14_5 & io_enqData_5_isControlFlow + | matches_14_6 & io_enqData_6_isControlFlow | matches_14_7 + & io_enqData_7_isControlFlow | matches_14_8 & io_enqData_8_isControlFlow + | matches_14_9 & io_enqData_9_isControlFlow | matches_14_10 + & io_enqData_10_isControlFlow | matches_14_11 & io_enqData_11_isControlFlow + | matches_14_12 & io_enqData_12_isControlFlow | matches_14_13 + & io_enqData_13_isControlFlow | matches_14_14 & io_enqData_14_isControlFlow + | matches_14_15 & io_enqData_15_isControlFlow; + buffer_14_isBranch <= + matches_14_0 & io_enqData_0_isBranch | matches_14_1 & io_enqData_1_isBranch + | matches_14_2 & io_enqData_2_isBranch | matches_14_3 & io_enqData_3_isBranch + | matches_14_4 & io_enqData_4_isBranch | matches_14_5 & io_enqData_5_isBranch + | matches_14_6 & io_enqData_6_isBranch | matches_14_7 & io_enqData_7_isBranch + | matches_14_8 & io_enqData_8_isBranch | matches_14_9 & io_enqData_9_isBranch + | matches_14_10 & io_enqData_10_isBranch | matches_14_11 + & io_enqData_11_isBranch | matches_14_12 & io_enqData_12_isBranch + | matches_14_13 & io_enqData_13_isBranch | matches_14_14 + & io_enqData_14_isBranch | matches_14_15 & io_enqData_15_isBranch; + buffer_14_isVector <= + matches_14_0 & io_enqData_0_isVector | matches_14_1 & io_enqData_1_isVector + | matches_14_2 & io_enqData_2_isVector | matches_14_3 & io_enqData_3_isVector + | matches_14_4 & io_enqData_4_isVector | matches_14_5 & io_enqData_5_isVector + | matches_14_6 & io_enqData_6_isVector | matches_14_7 & io_enqData_7_isVector + | matches_14_8 & io_enqData_8_isVector | matches_14_9 & io_enqData_9_isVector + | matches_14_10 & io_enqData_10_isVector | matches_14_11 + & io_enqData_11_isVector | matches_14_12 & io_enqData_12_isVector + | matches_14_13 & io_enqData_13_isVector | matches_14_14 + & io_enqData_14_isVector | matches_14_15 & io_enqData_15_isVector; + buffer_14_resetsVstart <= + matches_14_0 & io_enqData_0_resetsVstart | matches_14_1 + & io_enqData_1_resetsVstart | matches_14_2 & io_enqData_2_resetsVstart + | matches_14_3 & io_enqData_3_resetsVstart | matches_14_4 + & io_enqData_4_resetsVstart | matches_14_5 & io_enqData_5_resetsVstart + | matches_14_6 & io_enqData_6_resetsVstart | matches_14_7 + & io_enqData_7_resetsVstart | matches_14_8 & io_enqData_8_resetsVstart + | matches_14_9 & io_enqData_9_resetsVstart | matches_14_10 + & io_enqData_10_resetsVstart | matches_14_11 & io_enqData_11_resetsVstart + | matches_14_12 & io_enqData_12_resetsVstart | matches_14_13 + & io_enqData_13_resetsVstart | matches_14_14 & io_enqData_14_resetsVstart + | matches_14_15 & io_enqData_15_resetsVstart; + buffer_14_linkOk <= + matches_14_0 & io_enqData_0_linkOk | matches_14_1 & io_enqData_1_linkOk + | matches_14_2 & io_enqData_2_linkOk | matches_14_3 & io_enqData_3_linkOk + | matches_14_4 & io_enqData_4_linkOk | matches_14_5 & io_enqData_5_linkOk + | matches_14_6 & io_enqData_6_linkOk | matches_14_7 & io_enqData_7_linkOk + | matches_14_8 & io_enqData_8_linkOk | matches_14_9 & io_enqData_9_linkOk + | matches_14_10 & io_enqData_10_linkOk | matches_14_11 & io_enqData_11_linkOk + | matches_14_12 & io_enqData_12_linkOk | matches_14_13 & io_enqData_13_linkOk + | matches_14_14 & io_enqData_14_linkOk | matches_14_15 & io_enqData_15_linkOk; + buffer_14_isEcall <= + matches_14_0 & io_enqData_0_isEcall | matches_14_1 & io_enqData_1_isEcall + | matches_14_2 & io_enqData_2_isEcall | matches_14_3 & io_enqData_3_isEcall + | matches_14_4 & io_enqData_4_isEcall | matches_14_5 & io_enqData_5_isEcall + | matches_14_6 & io_enqData_6_isEcall | matches_14_7 & io_enqData_7_isEcall + | matches_14_8 & io_enqData_8_isEcall | matches_14_9 & io_enqData_9_isEcall + | matches_14_10 & io_enqData_10_isEcall | matches_14_11 & io_enqData_11_isEcall + | matches_14_12 & io_enqData_12_isEcall | matches_14_13 & io_enqData_13_isEcall + | matches_14_14 & io_enqData_14_isEcall | matches_14_15 & io_enqData_15_isEcall; + buffer_14_isMpause <= + matches_14_0 & io_enqData_0_isMpause | matches_14_1 & io_enqData_1_isMpause + | matches_14_2 & io_enqData_2_isMpause | matches_14_3 & io_enqData_3_isMpause + | matches_14_4 & io_enqData_4_isMpause | matches_14_5 & io_enqData_5_isMpause + | matches_14_6 & io_enqData_6_isMpause | matches_14_7 & io_enqData_7_isMpause + | matches_14_8 & io_enqData_8_isMpause | matches_14_9 & io_enqData_9_isMpause + | matches_14_10 & io_enqData_10_isMpause | matches_14_11 + & io_enqData_11_isMpause | matches_14_12 & io_enqData_12_isMpause + | matches_14_13 & io_enqData_13_isMpause | matches_14_14 + & io_enqData_14_isMpause | matches_14_15 & io_enqData_15_isMpause; + buffer_14_isTile <= + matches_14_0 & io_enqData_0_isTile | matches_14_1 & io_enqData_1_isTile + | matches_14_2 & io_enqData_2_isTile | matches_14_3 & io_enqData_3_isTile + | matches_14_4 & io_enqData_4_isTile | matches_14_5 & io_enqData_5_isTile + | matches_14_6 & io_enqData_6_isTile | matches_14_7 & io_enqData_7_isTile + | matches_14_8 & io_enqData_8_isTile | matches_14_9 & io_enqData_9_isTile + | matches_14_10 & io_enqData_10_isTile | matches_14_11 & io_enqData_11_isTile + | matches_14_12 & io_enqData_12_isTile | matches_14_13 & io_enqData_13_isTile + | matches_14_14 & io_enqData_14_isTile | matches_14_15 & io_enqData_15_isTile; + end + if (|{matches_15_15, + matches_15_14, + matches_15_13, + matches_15_12, + matches_15_11, + matches_15_10, + matches_15_9, + matches_15_8, + matches_15_7, + matches_15_6, + matches_15_5, + matches_15_4, + matches_15_3, + matches_15_2, + matches_15_1, + matches_15_0}) begin + buffer_15_addr <= + (matches_15_0 ? io_enqData_0_addr : 32'h0) + | (matches_15_1 ? io_enqData_1_addr : 32'h0) + | (matches_15_2 ? io_enqData_2_addr : 32'h0) + | (matches_15_3 ? io_enqData_3_addr : 32'h0) + | (matches_15_4 ? io_enqData_4_addr : 32'h0) + | (matches_15_5 ? io_enqData_5_addr : 32'h0) + | (matches_15_6 ? io_enqData_6_addr : 32'h0) + | (matches_15_7 ? io_enqData_7_addr : 32'h0) + | (matches_15_8 ? io_enqData_8_addr : 32'h0) + | (matches_15_9 ? io_enqData_9_addr : 32'h0) + | (matches_15_10 ? io_enqData_10_addr : 32'h0) + | (matches_15_11 ? io_enqData_11_addr : 32'h0) + | (matches_15_12 ? io_enqData_12_addr : 32'h0) + | (matches_15_13 ? io_enqData_13_addr : 32'h0) + | (matches_15_14 ? io_enqData_14_addr : 32'h0) + | (matches_15_15 ? io_enqData_15_addr : 32'h0); + buffer_15_idx <= + (matches_15_0 ? io_enqData_0_idx : 7'h0) + | (matches_15_1 ? io_enqData_1_idx : 7'h0) + | (matches_15_2 ? io_enqData_2_idx : 7'h0) + | (matches_15_3 ? io_enqData_3_idx : 7'h0) + | (matches_15_4 ? io_enqData_4_idx : 7'h0) + | (matches_15_5 ? io_enqData_5_idx : 7'h0) + | (matches_15_6 ? io_enqData_6_idx : 7'h0) + | (matches_15_7 ? io_enqData_7_idx : 7'h0) + | (matches_15_8 ? io_enqData_8_idx : 7'h0) + | (matches_15_9 ? io_enqData_9_idx : 7'h0) + | (matches_15_10 ? io_enqData_10_idx : 7'h0) + | (matches_15_11 ? io_enqData_11_idx : 7'h0) + | (matches_15_12 ? io_enqData_12_idx : 7'h0) + | (matches_15_13 ? io_enqData_13_idx : 7'h0) + | (matches_15_14 ? io_enqData_14_idx : 7'h0) + | (matches_15_15 ? io_enqData_15_idx : 7'h0); + buffer_15_trap <= + matches_15_0 & io_enqData_0_trap | matches_15_1 & io_enqData_1_trap + | matches_15_2 & io_enqData_2_trap | matches_15_3 & io_enqData_3_trap + | matches_15_4 & io_enqData_4_trap | matches_15_5 & io_enqData_5_trap + | matches_15_6 & io_enqData_6_trap | matches_15_7 & io_enqData_7_trap + | matches_15_8 & io_enqData_8_trap | matches_15_9 & io_enqData_9_trap + | matches_15_10 & io_enqData_10_trap | matches_15_11 & io_enqData_11_trap + | matches_15_12 & io_enqData_12_trap | matches_15_13 & io_enqData_13_trap + | matches_15_14 & io_enqData_14_trap | matches_15_15 & io_enqData_15_trap; + buffer_15_isControlFlow <= + matches_15_0 & io_enqData_0_isControlFlow | matches_15_1 + & io_enqData_1_isControlFlow | matches_15_2 & io_enqData_2_isControlFlow + | matches_15_3 & io_enqData_3_isControlFlow | matches_15_4 + & io_enqData_4_isControlFlow | matches_15_5 & io_enqData_5_isControlFlow + | matches_15_6 & io_enqData_6_isControlFlow | matches_15_7 + & io_enqData_7_isControlFlow | matches_15_8 & io_enqData_8_isControlFlow + | matches_15_9 & io_enqData_9_isControlFlow | matches_15_10 + & io_enqData_10_isControlFlow | matches_15_11 & io_enqData_11_isControlFlow + | matches_15_12 & io_enqData_12_isControlFlow | matches_15_13 + & io_enqData_13_isControlFlow | matches_15_14 & io_enqData_14_isControlFlow + | matches_15_15 & io_enqData_15_isControlFlow; + buffer_15_isBranch <= + matches_15_0 & io_enqData_0_isBranch | matches_15_1 & io_enqData_1_isBranch + | matches_15_2 & io_enqData_2_isBranch | matches_15_3 & io_enqData_3_isBranch + | matches_15_4 & io_enqData_4_isBranch | matches_15_5 & io_enqData_5_isBranch + | matches_15_6 & io_enqData_6_isBranch | matches_15_7 & io_enqData_7_isBranch + | matches_15_8 & io_enqData_8_isBranch | matches_15_9 & io_enqData_9_isBranch + | matches_15_10 & io_enqData_10_isBranch | matches_15_11 + & io_enqData_11_isBranch | matches_15_12 & io_enqData_12_isBranch + | matches_15_13 & io_enqData_13_isBranch | matches_15_14 + & io_enqData_14_isBranch | matches_15_15 & io_enqData_15_isBranch; + buffer_15_isVector <= + matches_15_0 & io_enqData_0_isVector | matches_15_1 & io_enqData_1_isVector + | matches_15_2 & io_enqData_2_isVector | matches_15_3 & io_enqData_3_isVector + | matches_15_4 & io_enqData_4_isVector | matches_15_5 & io_enqData_5_isVector + | matches_15_6 & io_enqData_6_isVector | matches_15_7 & io_enqData_7_isVector + | matches_15_8 & io_enqData_8_isVector | matches_15_9 & io_enqData_9_isVector + | matches_15_10 & io_enqData_10_isVector | matches_15_11 + & io_enqData_11_isVector | matches_15_12 & io_enqData_12_isVector + | matches_15_13 & io_enqData_13_isVector | matches_15_14 + & io_enqData_14_isVector | matches_15_15 & io_enqData_15_isVector; + buffer_15_resetsVstart <= + matches_15_0 & io_enqData_0_resetsVstart | matches_15_1 + & io_enqData_1_resetsVstart | matches_15_2 & io_enqData_2_resetsVstart + | matches_15_3 & io_enqData_3_resetsVstart | matches_15_4 + & io_enqData_4_resetsVstart | matches_15_5 & io_enqData_5_resetsVstart + | matches_15_6 & io_enqData_6_resetsVstart | matches_15_7 + & io_enqData_7_resetsVstart | matches_15_8 & io_enqData_8_resetsVstart + | matches_15_9 & io_enqData_9_resetsVstart | matches_15_10 + & io_enqData_10_resetsVstart | matches_15_11 & io_enqData_11_resetsVstart + | matches_15_12 & io_enqData_12_resetsVstart | matches_15_13 + & io_enqData_13_resetsVstart | matches_15_14 & io_enqData_14_resetsVstart + | matches_15_15 & io_enqData_15_resetsVstart; + buffer_15_linkOk <= + matches_15_0 & io_enqData_0_linkOk | matches_15_1 & io_enqData_1_linkOk + | matches_15_2 & io_enqData_2_linkOk | matches_15_3 & io_enqData_3_linkOk + | matches_15_4 & io_enqData_4_linkOk | matches_15_5 & io_enqData_5_linkOk + | matches_15_6 & io_enqData_6_linkOk | matches_15_7 & io_enqData_7_linkOk + | matches_15_8 & io_enqData_8_linkOk | matches_15_9 & io_enqData_9_linkOk + | matches_15_10 & io_enqData_10_linkOk | matches_15_11 & io_enqData_11_linkOk + | matches_15_12 & io_enqData_12_linkOk | matches_15_13 & io_enqData_13_linkOk + | matches_15_14 & io_enqData_14_linkOk | matches_15_15 & io_enqData_15_linkOk; + buffer_15_isEcall <= + matches_15_0 & io_enqData_0_isEcall | matches_15_1 & io_enqData_1_isEcall + | matches_15_2 & io_enqData_2_isEcall | matches_15_3 & io_enqData_3_isEcall + | matches_15_4 & io_enqData_4_isEcall | matches_15_5 & io_enqData_5_isEcall + | matches_15_6 & io_enqData_6_isEcall | matches_15_7 & io_enqData_7_isEcall + | matches_15_8 & io_enqData_8_isEcall | matches_15_9 & io_enqData_9_isEcall + | matches_15_10 & io_enqData_10_isEcall | matches_15_11 & io_enqData_11_isEcall + | matches_15_12 & io_enqData_12_isEcall | matches_15_13 & io_enqData_13_isEcall + | matches_15_14 & io_enqData_14_isEcall | matches_15_15 & io_enqData_15_isEcall; + buffer_15_isMpause <= + matches_15_0 & io_enqData_0_isMpause | matches_15_1 & io_enqData_1_isMpause + | matches_15_2 & io_enqData_2_isMpause | matches_15_3 & io_enqData_3_isMpause + | matches_15_4 & io_enqData_4_isMpause | matches_15_5 & io_enqData_5_isMpause + | matches_15_6 & io_enqData_6_isMpause | matches_15_7 & io_enqData_7_isMpause + | matches_15_8 & io_enqData_8_isMpause | matches_15_9 & io_enqData_9_isMpause + | matches_15_10 & io_enqData_10_isMpause | matches_15_11 + & io_enqData_11_isMpause | matches_15_12 & io_enqData_12_isMpause + | matches_15_13 & io_enqData_13_isMpause | matches_15_14 + & io_enqData_14_isMpause | matches_15_15 & io_enqData_15_isMpause; + buffer_15_isTile <= + matches_15_0 & io_enqData_0_isTile | matches_15_1 & io_enqData_1_isTile + | matches_15_2 & io_enqData_2_isTile | matches_15_3 & io_enqData_3_isTile + | matches_15_4 & io_enqData_4_isTile | matches_15_5 & io_enqData_5_isTile + | matches_15_6 & io_enqData_6_isTile | matches_15_7 & io_enqData_7_isTile + | matches_15_8 & io_enqData_8_isTile | matches_15_9 & io_enqData_9_isTile + | matches_15_10 & io_enqData_10_isTile | matches_15_11 & io_enqData_11_isTile + | matches_15_12 & io_enqData_12_isTile | matches_15_13 & io_enqData_13_isTile + | matches_15_14 & io_enqData_14_isTile | matches_15_15 & io_enqData_15_isTile; + end + enqPtr <= io_flush ? 4'h0 : enqPtr + io_enqValid[3:0]; + deqPtr <= io_flush ? 4'h0 : deqPtr + io_deqReady[3:0]; + nEnqueued <= io_flush ? 5'h0 : nEnqueued + io_enqValid - io_deqReady; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; - end - stateReg_valid = _RANDOM[2'h0][0]; - stateReg_bits_fwd = _RANDOM[2'h0][1]; - stateReg_bits_op = _RANDOM[2'h0][5:2]; - stateReg_bits_target = {_RANDOM[2'h0][31:6], _RANDOM[2'h1][5:0]}; - stateReg_bits_linkValid = _RANDOM[2'h1][6]; - stateReg_bits_linkAddr = _RANDOM[2'h1][11:7]; - stateReg_bits_linkData = {_RANDOM[2'h1][31:12], _RANDOM[2'h2][11:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - stateReg_valid = 1'h0; - stateReg_bits_fwd = 1'h0; - stateReg_bits_op = 4'h0; - stateReg_bits_target = 32'h0; - stateReg_bits_linkValid = 1'h0; - stateReg_bits_linkAddr = 5'h0; - stateReg_bits_linkData = 32'h0; + buffer_0_addr = 32'h0; + buffer_0_idx = 7'h0; + buffer_0_trap = 1'h0; + buffer_0_isControlFlow = 1'h0; + buffer_0_isBranch = 1'h0; + buffer_0_isVector = 1'h0; + buffer_0_resetsVstart = 1'h0; + buffer_0_linkOk = 1'h0; + buffer_0_isEcall = 1'h0; + buffer_0_isMpause = 1'h0; + buffer_0_isTile = 1'h0; + buffer_1_addr = 32'h0; + buffer_1_idx = 7'h0; + buffer_1_trap = 1'h0; + buffer_1_isControlFlow = 1'h0; + buffer_1_isBranch = 1'h0; + buffer_1_isVector = 1'h0; + buffer_1_resetsVstart = 1'h0; + buffer_1_linkOk = 1'h0; + buffer_1_isEcall = 1'h0; + buffer_1_isMpause = 1'h0; + buffer_1_isTile = 1'h0; + buffer_2_addr = 32'h0; + buffer_2_idx = 7'h0; + buffer_2_trap = 1'h0; + buffer_2_isControlFlow = 1'h0; + buffer_2_isBranch = 1'h0; + buffer_2_isVector = 1'h0; + buffer_2_resetsVstart = 1'h0; + buffer_2_linkOk = 1'h0; + buffer_2_isEcall = 1'h0; + buffer_2_isMpause = 1'h0; + buffer_2_isTile = 1'h0; + buffer_3_addr = 32'h0; + buffer_3_idx = 7'h0; + buffer_3_trap = 1'h0; + buffer_3_isControlFlow = 1'h0; + buffer_3_isBranch = 1'h0; + buffer_3_isVector = 1'h0; + buffer_3_resetsVstart = 1'h0; + buffer_3_linkOk = 1'h0; + buffer_3_isEcall = 1'h0; + buffer_3_isMpause = 1'h0; + buffer_3_isTile = 1'h0; + buffer_4_addr = 32'h0; + buffer_4_idx = 7'h0; + buffer_4_trap = 1'h0; + buffer_4_isControlFlow = 1'h0; + buffer_4_isBranch = 1'h0; + buffer_4_isVector = 1'h0; + buffer_4_resetsVstart = 1'h0; + buffer_4_linkOk = 1'h0; + buffer_4_isEcall = 1'h0; + buffer_4_isMpause = 1'h0; + buffer_4_isTile = 1'h0; + buffer_5_addr = 32'h0; + buffer_5_idx = 7'h0; + buffer_5_trap = 1'h0; + buffer_5_isControlFlow = 1'h0; + buffer_5_isBranch = 1'h0; + buffer_5_isVector = 1'h0; + buffer_5_resetsVstart = 1'h0; + buffer_5_linkOk = 1'h0; + buffer_5_isEcall = 1'h0; + buffer_5_isMpause = 1'h0; + buffer_5_isTile = 1'h0; + buffer_6_addr = 32'h0; + buffer_6_idx = 7'h0; + buffer_6_trap = 1'h0; + buffer_6_isControlFlow = 1'h0; + buffer_6_isBranch = 1'h0; + buffer_6_isVector = 1'h0; + buffer_6_resetsVstart = 1'h0; + buffer_6_linkOk = 1'h0; + buffer_6_isEcall = 1'h0; + buffer_6_isMpause = 1'h0; + buffer_6_isTile = 1'h0; + buffer_7_addr = 32'h0; + buffer_7_idx = 7'h0; + buffer_7_trap = 1'h0; + buffer_7_isControlFlow = 1'h0; + buffer_7_isBranch = 1'h0; + buffer_7_isVector = 1'h0; + buffer_7_resetsVstart = 1'h0; + buffer_7_linkOk = 1'h0; + buffer_7_isEcall = 1'h0; + buffer_7_isMpause = 1'h0; + buffer_7_isTile = 1'h0; + buffer_8_addr = 32'h0; + buffer_8_idx = 7'h0; + buffer_8_trap = 1'h0; + buffer_8_isControlFlow = 1'h0; + buffer_8_isBranch = 1'h0; + buffer_8_isVector = 1'h0; + buffer_8_resetsVstart = 1'h0; + buffer_8_linkOk = 1'h0; + buffer_8_isEcall = 1'h0; + buffer_8_isMpause = 1'h0; + buffer_8_isTile = 1'h0; + buffer_9_addr = 32'h0; + buffer_9_idx = 7'h0; + buffer_9_trap = 1'h0; + buffer_9_isControlFlow = 1'h0; + buffer_9_isBranch = 1'h0; + buffer_9_isVector = 1'h0; + buffer_9_resetsVstart = 1'h0; + buffer_9_linkOk = 1'h0; + buffer_9_isEcall = 1'h0; + buffer_9_isMpause = 1'h0; + buffer_9_isTile = 1'h0; + buffer_10_addr = 32'h0; + buffer_10_idx = 7'h0; + buffer_10_trap = 1'h0; + buffer_10_isControlFlow = 1'h0; + buffer_10_isBranch = 1'h0; + buffer_10_isVector = 1'h0; + buffer_10_resetsVstart = 1'h0; + buffer_10_linkOk = 1'h0; + buffer_10_isEcall = 1'h0; + buffer_10_isMpause = 1'h0; + buffer_10_isTile = 1'h0; + buffer_11_addr = 32'h0; + buffer_11_idx = 7'h0; + buffer_11_trap = 1'h0; + buffer_11_isControlFlow = 1'h0; + buffer_11_isBranch = 1'h0; + buffer_11_isVector = 1'h0; + buffer_11_resetsVstart = 1'h0; + buffer_11_linkOk = 1'h0; + buffer_11_isEcall = 1'h0; + buffer_11_isMpause = 1'h0; + buffer_11_isTile = 1'h0; + buffer_12_addr = 32'h0; + buffer_12_idx = 7'h0; + buffer_12_trap = 1'h0; + buffer_12_isControlFlow = 1'h0; + buffer_12_isBranch = 1'h0; + buffer_12_isVector = 1'h0; + buffer_12_resetsVstart = 1'h0; + buffer_12_linkOk = 1'h0; + buffer_12_isEcall = 1'h0; + buffer_12_isMpause = 1'h0; + buffer_12_isTile = 1'h0; + buffer_13_addr = 32'h0; + buffer_13_idx = 7'h0; + buffer_13_trap = 1'h0; + buffer_13_isControlFlow = 1'h0; + buffer_13_isBranch = 1'h0; + buffer_13_isVector = 1'h0; + buffer_13_resetsVstart = 1'h0; + buffer_13_linkOk = 1'h0; + buffer_13_isEcall = 1'h0; + buffer_13_isMpause = 1'h0; + buffer_13_isTile = 1'h0; + buffer_14_addr = 32'h0; + buffer_14_idx = 7'h0; + buffer_14_trap = 1'h0; + buffer_14_isControlFlow = 1'h0; + buffer_14_isBranch = 1'h0; + buffer_14_isVector = 1'h0; + buffer_14_resetsVstart = 1'h0; + buffer_14_linkOk = 1'h0; + buffer_14_isEcall = 1'h0; + buffer_14_isMpause = 1'h0; + buffer_14_isTile = 1'h0; + buffer_15_addr = 32'h0; + buffer_15_idx = 7'h0; + buffer_15_trap = 1'h0; + buffer_15_isControlFlow = 1'h0; + buffer_15_isBranch = 1'h0; + buffer_15_isVector = 1'h0; + buffer_15_resetsVstart = 1'h0; + buffer_15_linkOk = 1'h0; + buffer_15_isEcall = 1'h0; + buffer_15_isMpause = 1'h0; + buffer_15_isTile = 1'h0; + enqPtr = 4'h0; + deqPtr = 4'h0; + nEnqueued = 5'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; - assign io_rd_bits_addr = stateReg_bits_linkAddr; - assign io_rd_bits_data = stateReg_bits_linkData; - assign io_taken_valid = - stateReg_valid - & (stateReg_bits_op == 4'hD - | (stateReg_bits_op == 4'h7 - ? io_rs1_data >= io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h6 - ? io_rs1_data < io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h5 - ? $signed(io_rs1_data) >= $signed(io_rs2_data) != stateReg_bits_fwd - : stateReg_bits_op == 4'h4 - ? $signed(io_rs1_data) < $signed(io_rs2_data) != stateReg_bits_fwd - : stateReg_bits_op == 4'h3 - ? io_rs1_data != io_rs2_data != stateReg_bits_fwd - : stateReg_bits_op == 4'h2 - ? io_rs1_data == io_rs2_data != stateReg_bits_fwd - : (stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op)) - & ~stateReg_bits_fwd)); - assign io_taken_value = stateReg_bits_target; + `endif // ENABLE_INITIAL_REG_ + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 5'h10 - nEnqueued; + assign io_dataOut_0_addr = + deqPtr[0] + ? _shifted_T_61_addr + : deqPtr[1] + ? _shifted_WIRE_2_addr + : deqPtr[2] ? _shifted_T_13_addr : deqPtr[3] ? buffer_8_addr : buffer_0_addr; + assign io_dataOut_0_idx = + deqPtr[0] + ? _shifted_T_61_idx + : deqPtr[1] + ? _shifted_WIRE_2_idx + : deqPtr[2] ? _shifted_T_13_idx : deqPtr[3] ? buffer_8_idx : buffer_0_idx; + assign io_dataOut_0_trap = + deqPtr[0] + ? _shifted_T_61_trap + : deqPtr[1] + ? _shifted_WIRE_2_trap + : deqPtr[2] ? _shifted_T_13_trap : deqPtr[3] ? buffer_8_trap : buffer_0_trap; + assign io_dataOut_0_isControlFlow = + deqPtr[0] + ? _shifted_T_61_isControlFlow + : deqPtr[1] + ? _shifted_WIRE_2_isControlFlow + : deqPtr[2] + ? _shifted_T_13_isControlFlow + : deqPtr[3] ? buffer_8_isControlFlow : buffer_0_isControlFlow; + assign io_dataOut_0_isBranch = + deqPtr[0] + ? _shifted_T_61_isBranch + : deqPtr[1] + ? _shifted_WIRE_2_isBranch + : deqPtr[2] + ? _shifted_T_13_isBranch + : deqPtr[3] ? buffer_8_isBranch : buffer_0_isBranch; + assign io_dataOut_0_isVector = + deqPtr[0] + ? _shifted_T_61_isVector + : deqPtr[1] + ? _shifted_WIRE_2_isVector + : deqPtr[2] + ? _shifted_T_13_isVector + : deqPtr[3] ? buffer_8_isVector : buffer_0_isVector; + assign io_dataOut_0_resetsVstart = + deqPtr[0] + ? _shifted_T_61_resetsVstart + : deqPtr[1] + ? _shifted_WIRE_2_resetsVstart + : deqPtr[2] + ? _shifted_T_13_resetsVstart + : deqPtr[3] ? buffer_8_resetsVstart : buffer_0_resetsVstart; + assign io_dataOut_0_linkOk = + deqPtr[0] + ? _shifted_T_61_linkOk + : deqPtr[1] + ? _shifted_WIRE_2_linkOk + : deqPtr[2] + ? _shifted_T_13_linkOk + : deqPtr[3] ? buffer_8_linkOk : buffer_0_linkOk; + assign io_dataOut_0_isEcall = + deqPtr[0] + ? _shifted_T_61_isEcall + : deqPtr[1] + ? _shifted_WIRE_2_isEcall + : deqPtr[2] + ? _shifted_T_13_isEcall + : deqPtr[3] ? buffer_8_isEcall : buffer_0_isEcall; + assign io_dataOut_0_isMpause = + deqPtr[0] + ? _shifted_T_61_isMpause + : deqPtr[1] + ? _shifted_WIRE_2_isMpause + : deqPtr[2] + ? _shifted_T_13_isMpause + : deqPtr[3] ? buffer_8_isMpause : buffer_0_isMpause; + assign io_dataOut_0_isTile = + deqPtr[0] + ? _shifted_T_61_isTile + : deqPtr[1] + ? _shifted_WIRE_2_isTile + : deqPtr[2] + ? _shifted_T_13_isTile + : deqPtr[3] ? buffer_8_isTile : buffer_0_isTile; + assign io_dataOut_1_addr = deqPtr[0] ? _shifted_T_64_addr : _shifted_T_61_addr; + assign io_dataOut_1_idx = deqPtr[0] ? _shifted_T_64_idx : _shifted_T_61_idx; + assign io_dataOut_1_trap = deqPtr[0] ? _shifted_T_64_trap : _shifted_T_61_trap; + assign io_dataOut_1_isControlFlow = + deqPtr[0] ? _shifted_T_64_isControlFlow : _shifted_T_61_isControlFlow; + assign io_dataOut_1_isBranch = + deqPtr[0] ? _shifted_T_64_isBranch : _shifted_T_61_isBranch; + assign io_dataOut_1_isVector = + deqPtr[0] ? _shifted_T_64_isVector : _shifted_T_61_isVector; + assign io_dataOut_1_resetsVstart = + deqPtr[0] ? _shifted_T_64_resetsVstart : _shifted_T_61_resetsVstart; + assign io_dataOut_1_linkOk = deqPtr[0] ? _shifted_T_64_linkOk : _shifted_T_61_linkOk; + assign io_dataOut_1_isEcall = deqPtr[0] ? _shifted_T_64_isEcall : _shifted_T_61_isEcall; + assign io_dataOut_1_isMpause = + deqPtr[0] ? _shifted_T_64_isMpause : _shifted_T_61_isMpause; + assign io_dataOut_1_isTile = deqPtr[0] ? _shifted_T_64_isTile : _shifted_T_61_isTile; + assign io_dataOut_2_addr = deqPtr[0] ? _shifted_T_67_addr : _shifted_T_64_addr; + assign io_dataOut_2_idx = deqPtr[0] ? _shifted_T_67_idx : _shifted_T_64_idx; + assign io_dataOut_2_trap = deqPtr[0] ? _shifted_T_67_trap : _shifted_T_64_trap; + assign io_dataOut_2_isControlFlow = + deqPtr[0] ? _shifted_T_67_isControlFlow : _shifted_T_64_isControlFlow; + assign io_dataOut_2_isBranch = + deqPtr[0] ? _shifted_T_67_isBranch : _shifted_T_64_isBranch; + assign io_dataOut_2_isVector = + deqPtr[0] ? _shifted_T_67_isVector : _shifted_T_64_isVector; + assign io_dataOut_2_resetsVstart = + deqPtr[0] ? _shifted_T_67_resetsVstart : _shifted_T_64_resetsVstart; + assign io_dataOut_2_linkOk = deqPtr[0] ? _shifted_T_67_linkOk : _shifted_T_64_linkOk; + assign io_dataOut_2_isEcall = deqPtr[0] ? _shifted_T_67_isEcall : _shifted_T_64_isEcall; + assign io_dataOut_2_isMpause = + deqPtr[0] ? _shifted_T_67_isMpause : _shifted_T_64_isMpause; + assign io_dataOut_2_isTile = deqPtr[0] ? _shifted_T_67_isTile : _shifted_T_64_isTile; + assign io_dataOut_3_addr = deqPtr[0] ? _shifted_T_70_addr : _shifted_T_67_addr; + assign io_dataOut_3_idx = deqPtr[0] ? _shifted_T_70_idx : _shifted_T_67_idx; + assign io_dataOut_3_trap = deqPtr[0] ? _shifted_T_70_trap : _shifted_T_67_trap; + assign io_dataOut_3_isControlFlow = + deqPtr[0] ? _shifted_T_70_isControlFlow : _shifted_T_67_isControlFlow; + assign io_dataOut_3_isBranch = + deqPtr[0] ? _shifted_T_70_isBranch : _shifted_T_67_isBranch; + assign io_dataOut_3_isVector = + deqPtr[0] ? _shifted_T_70_isVector : _shifted_T_67_isVector; + assign io_dataOut_3_resetsVstart = + deqPtr[0] ? _shifted_T_70_resetsVstart : _shifted_T_67_resetsVstart; + assign io_dataOut_3_linkOk = deqPtr[0] ? _shifted_T_70_linkOk : _shifted_T_67_linkOk; + assign io_dataOut_3_isEcall = deqPtr[0] ? _shifted_T_70_isEcall : _shifted_T_67_isEcall; + assign io_dataOut_3_isMpause = + deqPtr[0] ? _shifted_T_70_isMpause : _shifted_T_67_isMpause; + assign io_dataOut_3_isTile = deqPtr[0] ? _shifted_T_70_isTile : _shifted_T_67_isTile; + assign io_dataOut_4_addr = deqPtr[0] ? _shifted_T_73_addr : _shifted_T_70_addr; + assign io_dataOut_4_idx = deqPtr[0] ? _shifted_T_73_idx : _shifted_T_70_idx; + assign io_dataOut_4_trap = deqPtr[0] ? _shifted_T_73_trap : _shifted_T_70_trap; + assign io_dataOut_4_isControlFlow = + deqPtr[0] ? _shifted_T_73_isControlFlow : _shifted_T_70_isControlFlow; + assign io_dataOut_4_isBranch = + deqPtr[0] ? _shifted_T_73_isBranch : _shifted_T_70_isBranch; + assign io_dataOut_4_isVector = + deqPtr[0] ? _shifted_T_73_isVector : _shifted_T_70_isVector; + assign io_dataOut_4_resetsVstart = + deqPtr[0] ? _shifted_T_73_resetsVstart : _shifted_T_70_resetsVstart; + assign io_dataOut_4_linkOk = deqPtr[0] ? _shifted_T_73_linkOk : _shifted_T_70_linkOk; + assign io_dataOut_4_isEcall = deqPtr[0] ? _shifted_T_73_isEcall : _shifted_T_70_isEcall; + assign io_dataOut_4_isMpause = + deqPtr[0] ? _shifted_T_73_isMpause : _shifted_T_70_isMpause; + assign io_dataOut_4_isTile = deqPtr[0] ? _shifted_T_73_isTile : _shifted_T_70_isTile; + assign io_dataOut_5_addr = deqPtr[0] ? _shifted_T_76_addr : _shifted_T_73_addr; + assign io_dataOut_5_idx = deqPtr[0] ? _shifted_T_76_idx : _shifted_T_73_idx; + assign io_dataOut_5_trap = deqPtr[0] ? _shifted_T_76_trap : _shifted_T_73_trap; + assign io_dataOut_5_isControlFlow = + deqPtr[0] ? _shifted_T_76_isControlFlow : _shifted_T_73_isControlFlow; + assign io_dataOut_5_isBranch = + deqPtr[0] ? _shifted_T_76_isBranch : _shifted_T_73_isBranch; + assign io_dataOut_5_isVector = + deqPtr[0] ? _shifted_T_76_isVector : _shifted_T_73_isVector; + assign io_dataOut_5_resetsVstart = + deqPtr[0] ? _shifted_T_76_resetsVstart : _shifted_T_73_resetsVstart; + assign io_dataOut_5_linkOk = deqPtr[0] ? _shifted_T_76_linkOk : _shifted_T_73_linkOk; + assign io_dataOut_5_isEcall = deqPtr[0] ? _shifted_T_76_isEcall : _shifted_T_73_isEcall; + assign io_dataOut_5_isMpause = + deqPtr[0] ? _shifted_T_76_isMpause : _shifted_T_73_isMpause; + assign io_dataOut_5_isTile = deqPtr[0] ? _shifted_T_76_isTile : _shifted_T_73_isTile; + assign io_dataOut_6_addr = deqPtr[0] ? _shifted_T_79_addr : _shifted_T_76_addr; + assign io_dataOut_6_idx = deqPtr[0] ? _shifted_T_79_idx : _shifted_T_76_idx; + assign io_dataOut_6_trap = deqPtr[0] ? _shifted_T_79_trap : _shifted_T_76_trap; + assign io_dataOut_6_isControlFlow = + deqPtr[0] ? _shifted_T_79_isControlFlow : _shifted_T_76_isControlFlow; + assign io_dataOut_6_isBranch = + deqPtr[0] ? _shifted_T_79_isBranch : _shifted_T_76_isBranch; + assign io_dataOut_6_isVector = + deqPtr[0] ? _shifted_T_79_isVector : _shifted_T_76_isVector; + assign io_dataOut_6_resetsVstart = + deqPtr[0] ? _shifted_T_79_resetsVstart : _shifted_T_76_resetsVstart; + assign io_dataOut_6_linkOk = deqPtr[0] ? _shifted_T_79_linkOk : _shifted_T_76_linkOk; + assign io_dataOut_6_isEcall = deqPtr[0] ? _shifted_T_79_isEcall : _shifted_T_76_isEcall; + assign io_dataOut_6_isMpause = + deqPtr[0] ? _shifted_T_79_isMpause : _shifted_T_76_isMpause; + assign io_dataOut_6_isTile = deqPtr[0] ? _shifted_T_79_isTile : _shifted_T_76_isTile; + assign io_dataOut_7_addr = deqPtr[0] ? _shifted_T_82_addr : _shifted_T_79_addr; + assign io_dataOut_7_idx = deqPtr[0] ? _shifted_T_82_idx : _shifted_T_79_idx; + assign io_dataOut_7_trap = deqPtr[0] ? _shifted_T_82_trap : _shifted_T_79_trap; + assign io_dataOut_7_isControlFlow = + deqPtr[0] ? _shifted_T_82_isControlFlow : _shifted_T_79_isControlFlow; + assign io_dataOut_7_isBranch = + deqPtr[0] ? _shifted_T_82_isBranch : _shifted_T_79_isBranch; + assign io_dataOut_7_isVector = + deqPtr[0] ? _shifted_T_82_isVector : _shifted_T_79_isVector; + assign io_dataOut_7_resetsVstart = + deqPtr[0] ? _shifted_T_82_resetsVstart : _shifted_T_79_resetsVstart; + assign io_dataOut_7_linkOk = deqPtr[0] ? _shifted_T_82_linkOk : _shifted_T_79_linkOk; + assign io_dataOut_7_isEcall = deqPtr[0] ? _shifted_T_82_isEcall : _shifted_T_79_isEcall; + assign io_dataOut_7_isMpause = + deqPtr[0] ? _shifted_T_82_isMpause : _shifted_T_79_isMpause; + assign io_dataOut_7_isTile = deqPtr[0] ? _shifted_T_82_isTile : _shifted_T_79_isTile; + assign io_dataOut_8_addr = deqPtr[0] ? _shifted_T_85_addr : _shifted_T_82_addr; + assign io_dataOut_8_idx = deqPtr[0] ? _shifted_T_85_idx : _shifted_T_82_idx; + assign io_dataOut_8_trap = deqPtr[0] ? _shifted_T_85_trap : _shifted_T_82_trap; + assign io_dataOut_8_isControlFlow = + deqPtr[0] ? _shifted_T_85_isControlFlow : _shifted_T_82_isControlFlow; + assign io_dataOut_8_isBranch = + deqPtr[0] ? _shifted_T_85_isBranch : _shifted_T_82_isBranch; + assign io_dataOut_8_isVector = + deqPtr[0] ? _shifted_T_85_isVector : _shifted_T_82_isVector; + assign io_dataOut_8_resetsVstart = + deqPtr[0] ? _shifted_T_85_resetsVstart : _shifted_T_82_resetsVstart; + assign io_dataOut_8_linkOk = deqPtr[0] ? _shifted_T_85_linkOk : _shifted_T_82_linkOk; + assign io_dataOut_8_isEcall = deqPtr[0] ? _shifted_T_85_isEcall : _shifted_T_82_isEcall; + assign io_dataOut_8_isMpause = + deqPtr[0] ? _shifted_T_85_isMpause : _shifted_T_82_isMpause; + assign io_dataOut_8_isTile = deqPtr[0] ? _shifted_T_85_isTile : _shifted_T_82_isTile; + assign io_dataOut_9_addr = deqPtr[0] ? _shifted_T_88_addr : _shifted_T_85_addr; + assign io_dataOut_9_idx = deqPtr[0] ? _shifted_T_88_idx : _shifted_T_85_idx; + assign io_dataOut_9_trap = deqPtr[0] ? _shifted_T_88_trap : _shifted_T_85_trap; + assign io_dataOut_9_isControlFlow = + deqPtr[0] ? _shifted_T_88_isControlFlow : _shifted_T_85_isControlFlow; + assign io_dataOut_9_isBranch = + deqPtr[0] ? _shifted_T_88_isBranch : _shifted_T_85_isBranch; + assign io_dataOut_9_isVector = + deqPtr[0] ? _shifted_T_88_isVector : _shifted_T_85_isVector; + assign io_dataOut_9_resetsVstart = + deqPtr[0] ? _shifted_T_88_resetsVstart : _shifted_T_85_resetsVstart; + assign io_dataOut_9_linkOk = deqPtr[0] ? _shifted_T_88_linkOk : _shifted_T_85_linkOk; + assign io_dataOut_9_isEcall = deqPtr[0] ? _shifted_T_88_isEcall : _shifted_T_85_isEcall; + assign io_dataOut_9_isMpause = + deqPtr[0] ? _shifted_T_88_isMpause : _shifted_T_85_isMpause; + assign io_dataOut_9_isTile = deqPtr[0] ? _shifted_T_88_isTile : _shifted_T_85_isTile; + assign io_dataOut_10_addr = deqPtr[0] ? _shifted_T_91_addr : _shifted_T_88_addr; + assign io_dataOut_10_idx = deqPtr[0] ? _shifted_T_91_idx : _shifted_T_88_idx; + assign io_dataOut_10_trap = deqPtr[0] ? _shifted_T_91_trap : _shifted_T_88_trap; + assign io_dataOut_10_isControlFlow = + deqPtr[0] ? _shifted_T_91_isControlFlow : _shifted_T_88_isControlFlow; + assign io_dataOut_10_isBranch = + deqPtr[0] ? _shifted_T_91_isBranch : _shifted_T_88_isBranch; + assign io_dataOut_10_isVector = + deqPtr[0] ? _shifted_T_91_isVector : _shifted_T_88_isVector; + assign io_dataOut_10_resetsVstart = + deqPtr[0] ? _shifted_T_91_resetsVstart : _shifted_T_88_resetsVstart; + assign io_dataOut_10_linkOk = deqPtr[0] ? _shifted_T_91_linkOk : _shifted_T_88_linkOk; + assign io_dataOut_10_isEcall = + deqPtr[0] ? _shifted_T_91_isEcall : _shifted_T_88_isEcall; + assign io_dataOut_10_isMpause = + deqPtr[0] ? _shifted_T_91_isMpause : _shifted_T_88_isMpause; + assign io_dataOut_10_isTile = deqPtr[0] ? _shifted_T_91_isTile : _shifted_T_88_isTile; + assign io_dataOut_11_addr = deqPtr[0] ? _shifted_T_94_addr : _shifted_T_91_addr; + assign io_dataOut_11_idx = deqPtr[0] ? _shifted_T_94_idx : _shifted_T_91_idx; + assign io_dataOut_11_trap = deqPtr[0] ? _shifted_T_94_trap : _shifted_T_91_trap; + assign io_dataOut_11_isControlFlow = + deqPtr[0] ? _shifted_T_94_isControlFlow : _shifted_T_91_isControlFlow; + assign io_dataOut_11_isBranch = + deqPtr[0] ? _shifted_T_94_isBranch : _shifted_T_91_isBranch; + assign io_dataOut_11_isVector = + deqPtr[0] ? _shifted_T_94_isVector : _shifted_T_91_isVector; + assign io_dataOut_11_resetsVstart = + deqPtr[0] ? _shifted_T_94_resetsVstart : _shifted_T_91_resetsVstart; + assign io_dataOut_11_linkOk = deqPtr[0] ? _shifted_T_94_linkOk : _shifted_T_91_linkOk; + assign io_dataOut_11_isEcall = + deqPtr[0] ? _shifted_T_94_isEcall : _shifted_T_91_isEcall; + assign io_dataOut_11_isMpause = + deqPtr[0] ? _shifted_T_94_isMpause : _shifted_T_91_isMpause; + assign io_dataOut_11_isTile = deqPtr[0] ? _shifted_T_94_isTile : _shifted_T_91_isTile; + assign io_dataOut_12_addr = deqPtr[0] ? _shifted_T_97_addr : _shifted_T_94_addr; + assign io_dataOut_12_idx = deqPtr[0] ? _shifted_T_97_idx : _shifted_T_94_idx; + assign io_dataOut_12_trap = deqPtr[0] ? _shifted_T_97_trap : _shifted_T_94_trap; + assign io_dataOut_12_isControlFlow = + deqPtr[0] ? _shifted_T_97_isControlFlow : _shifted_T_94_isControlFlow; + assign io_dataOut_12_isBranch = + deqPtr[0] ? _shifted_T_97_isBranch : _shifted_T_94_isBranch; + assign io_dataOut_12_isVector = + deqPtr[0] ? _shifted_T_97_isVector : _shifted_T_94_isVector; + assign io_dataOut_12_resetsVstart = + deqPtr[0] ? _shifted_T_97_resetsVstart : _shifted_T_94_resetsVstart; + assign io_dataOut_12_linkOk = deqPtr[0] ? _shifted_T_97_linkOk : _shifted_T_94_linkOk; + assign io_dataOut_12_isEcall = + deqPtr[0] ? _shifted_T_97_isEcall : _shifted_T_94_isEcall; + assign io_dataOut_12_isMpause = + deqPtr[0] ? _shifted_T_97_isMpause : _shifted_T_94_isMpause; + assign io_dataOut_12_isTile = deqPtr[0] ? _shifted_T_97_isTile : _shifted_T_94_isTile; + assign io_dataOut_13_addr = deqPtr[0] ? _shifted_T_100_addr : _shifted_T_97_addr; + assign io_dataOut_13_idx = deqPtr[0] ? _shifted_T_100_idx : _shifted_T_97_idx; + assign io_dataOut_13_trap = deqPtr[0] ? _shifted_T_100_trap : _shifted_T_97_trap; + assign io_dataOut_13_isControlFlow = + deqPtr[0] ? _shifted_T_100_isControlFlow : _shifted_T_97_isControlFlow; + assign io_dataOut_13_isBranch = + deqPtr[0] ? _shifted_T_100_isBranch : _shifted_T_97_isBranch; + assign io_dataOut_13_isVector = + deqPtr[0] ? _shifted_T_100_isVector : _shifted_T_97_isVector; + assign io_dataOut_13_resetsVstart = + deqPtr[0] ? _shifted_T_100_resetsVstart : _shifted_T_97_resetsVstart; + assign io_dataOut_13_linkOk = deqPtr[0] ? _shifted_T_100_linkOk : _shifted_T_97_linkOk; + assign io_dataOut_13_isEcall = + deqPtr[0] ? _shifted_T_100_isEcall : _shifted_T_97_isEcall; + assign io_dataOut_13_isMpause = + deqPtr[0] ? _shifted_T_100_isMpause : _shifted_T_97_isMpause; + assign io_dataOut_13_isTile = deqPtr[0] ? _shifted_T_100_isTile : _shifted_T_97_isTile; + assign io_dataOut_14_addr = deqPtr[0] ? _shifted_T_103_addr : _shifted_T_100_addr; + assign io_dataOut_14_idx = deqPtr[0] ? _shifted_T_103_idx : _shifted_T_100_idx; + assign io_dataOut_14_trap = deqPtr[0] ? _shifted_T_103_trap : _shifted_T_100_trap; + assign io_dataOut_14_isControlFlow = + deqPtr[0] ? _shifted_T_103_isControlFlow : _shifted_T_100_isControlFlow; + assign io_dataOut_14_isBranch = + deqPtr[0] ? _shifted_T_103_isBranch : _shifted_T_100_isBranch; + assign io_dataOut_14_isVector = + deqPtr[0] ? _shifted_T_103_isVector : _shifted_T_100_isVector; + assign io_dataOut_14_resetsVstart = + deqPtr[0] ? _shifted_T_103_resetsVstart : _shifted_T_100_resetsVstart; + assign io_dataOut_14_linkOk = deqPtr[0] ? _shifted_T_103_linkOk : _shifted_T_100_linkOk; + assign io_dataOut_14_isEcall = + deqPtr[0] ? _shifted_T_103_isEcall : _shifted_T_100_isEcall; + assign io_dataOut_14_isMpause = + deqPtr[0] ? _shifted_T_103_isMpause : _shifted_T_100_isMpause; + assign io_dataOut_14_isTile = deqPtr[0] ? _shifted_T_103_isTile : _shifted_T_100_isTile; + assign io_dataOut_15_addr = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_addr : buffer_6_addr) + : _shifted_T_55_addr) + : _shifted_WIRE_16_addr) + : _shifted_T_103_addr; + assign io_dataOut_15_idx = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] ? (deqPtr[3] ? buffer_14_idx : buffer_6_idx) : _shifted_T_55_idx) + : _shifted_WIRE_16_idx) + : _shifted_T_103_idx; + assign io_dataOut_15_trap = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_trap : buffer_6_trap) + : _shifted_T_55_trap) + : _shifted_WIRE_16_trap) + : _shifted_T_103_trap; + assign io_dataOut_15_isControlFlow = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isControlFlow : buffer_6_isControlFlow) + : _shifted_T_55_isControlFlow) + : _shifted_WIRE_16_isControlFlow) + : _shifted_T_103_isControlFlow; + assign io_dataOut_15_isBranch = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isBranch : buffer_6_isBranch) + : _shifted_T_55_isBranch) + : _shifted_WIRE_16_isBranch) + : _shifted_T_103_isBranch; + assign io_dataOut_15_isVector = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isVector : buffer_6_isVector) + : _shifted_T_55_isVector) + : _shifted_WIRE_16_isVector) + : _shifted_T_103_isVector; + assign io_dataOut_15_resetsVstart = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_resetsVstart : buffer_6_resetsVstart) + : _shifted_T_55_resetsVstart) + : _shifted_WIRE_16_resetsVstart) + : _shifted_T_103_resetsVstart; + assign io_dataOut_15_linkOk = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_linkOk : buffer_6_linkOk) + : _shifted_T_55_linkOk) + : _shifted_WIRE_16_linkOk) + : _shifted_T_103_linkOk; + assign io_dataOut_15_isEcall = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isEcall : buffer_6_isEcall) + : _shifted_T_55_isEcall) + : _shifted_WIRE_16_isEcall) + : _shifted_T_103_isEcall; + assign io_dataOut_15_isMpause = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isMpause : buffer_6_isMpause) + : _shifted_T_55_isMpause) + : _shifted_WIRE_16_isMpause) + : _shifted_T_103_isMpause; + assign io_dataOut_15_isTile = + deqPtr[0] + ? (deqPtr[1] + ? (deqPtr[2] + ? (deqPtr[3] ? buffer_14_isTile : buffer_6_isTile) + : _shifted_T_55_isTile) + : _shifted_WIRE_16_isTile) + : _shifted_T_103_isTile; endmodule -module Slice( +module RetirementBuffer( input clock, reset, - output io_in_ready, - input io_in_valid, - input [31:0] io_in_bits_pc, - io_in_bits_addr, - io_in_bits_adrx, - io_in_bits_data, - input [4:0] io_in_bits_index, - io_in_bits_size, - io_in_bits_fullsize, - input io_in_bits_write, - io_in_bits_sext, - io_in_bits_iload, - io_in_bits_fencei, - io_in_bits_flushat, - io_in_bits_flushall, - io_in_bits_sldst, - io_in_bits_vldst, - io_in_bits_fldst, - input [1:0] io_in_bits_regionType, - input [15:0] io_in_bits_mask, - input io_in_bits_last, - io_out_ready, - output io_out_valid, - output [31:0] io_out_bits_pc, - io_out_bits_addr, - io_out_bits_adrx, - io_out_bits_data, - output [4:0] io_out_bits_index, - io_out_bits_size, - io_out_bits_fullsize, - output io_out_bits_write, - io_out_bits_sext, - io_out_bits_iload, - io_out_bits_fencei, - io_out_bits_flushat, - io_out_bits_flushall, - io_out_bits_sldst, - io_out_bits_vldst, - io_out_bits_fldst, - output [1:0] io_out_bits_regionType, - output [15:0] io_out_bits_mask, - output io_out_bits_last + io_inst_0_ready, + io_inst_0_valid, + input [31:0] io_inst_0_bits_addr, + io_inst_0_bits_inst, + input io_inst_1_ready, + io_inst_1_valid, + input [31:0] io_inst_1_bits_addr, + io_inst_1_bits_inst, + input io_inst_2_ready, + io_inst_2_valid, + input [31:0] io_inst_2_bits_addr, + io_inst_2_bits_inst, + input io_inst_3_ready, + io_inst_3_valid, + input [31:0] io_inst_3_bits_addr, + io_inst_3_bits_inst, + io_targets_0, + io_targets_1, + io_targets_2, + io_targets_3, + io_jalrTargets_0, + io_jalrTargets_1, + io_jalrTargets_2, + io_jalrTargets_3, + input io_jump_0, + io_jump_1, + io_jump_2, + io_jump_3, + io_branch_0, + io_branch_1, + io_branch_2, + io_branch_3, + io_storeComplete_valid, + input [31:0] io_storeComplete_bits, + input io_writeAddrScalar_0_valid, + input [4:0] io_writeAddrScalar_0_addr, + input io_writeAddrScalar_1_valid, + input [4:0] io_writeAddrScalar_1_addr, + input io_writeAddrScalar_2_valid, + input [4:0] io_writeAddrScalar_2_addr, + input io_writeAddrScalar_3_valid, + input [4:0] io_writeAddrScalar_3_addr, + input io_writeDataScalar_0_valid, + input [4:0] io_writeDataScalar_0_bits_addr, + input io_writeDataScalar_1_valid, + input [4:0] io_writeDataScalar_1_bits_addr, + input io_writeDataScalar_2_valid, + input [4:0] io_writeDataScalar_2_bits_addr, + input io_writeDataScalar_3_valid, + input [4:0] io_writeDataScalar_3_bits_addr, + input io_writeDataScalar_4_valid, + input [4:0] io_writeDataScalar_4_bits_addr, + input io_writeDataScalar_5_valid, + input [4:0] io_writeDataScalar_5_bits_addr, + input io_writeAddrFloat_valid, + input [4:0] io_writeAddrFloat_addr, + input io_writeDataFloat_0_valid, + input [4:0] io_writeDataFloat_0_bits_addr, + input io_writeDataFloat_1_valid, + input [4:0] io_writeDataFloat_1_bits_addr, + input io_fault_valid, + input [31:0] io_fault_bits_mepc, + io_fault_bits_mcause, + input io_fault_bits_decode, + output [4:0] io_nSpace, + output [3:0] io_nRetired, + output io_empty, + io_trapPending, + io_trapRetired ); - reg ipos; - reg opos; - reg [31:0] mem_0_pc; - reg [31:0] mem_0_addr; - reg [31:0] mem_0_adrx; - reg [31:0] mem_0_data; - reg [4:0] mem_0_index; - reg [4:0] mem_0_size; - reg [4:0] mem_0_fullsize; - reg mem_0_write; - reg mem_0_sext; - reg mem_0_iload; - reg mem_0_fencei; - reg mem_0_flushat; - reg mem_0_flushall; - reg mem_0_sldst; - reg mem_0_vldst; - reg mem_0_fldst; - reg [1:0] mem_0_regionType; - reg [15:0] mem_0_mask; - reg mem_0_last; - wire io_in_ready_0 = ipos == opos | io_out_ready; - wire io_out_valid_0 = ipos != opos; + wire [4:0] _instBuffer_io_nEnqueued; + wire [4:0] _instBuffer_io_nSpace; + wire [31:0] _instBuffer_io_dataOut_0_addr; + wire [6:0] _instBuffer_io_dataOut_0_idx; + wire _instBuffer_io_dataOut_0_trap; + wire _instBuffer_io_dataOut_0_isControlFlow; + wire _instBuffer_io_dataOut_0_isBranch; + wire _instBuffer_io_dataOut_0_isVector; + wire _instBuffer_io_dataOut_0_isEcall; + wire _instBuffer_io_dataOut_0_isMpause; + wire _instBuffer_io_dataOut_0_isTile; + wire [31:0] _instBuffer_io_dataOut_1_addr; + wire [6:0] _instBuffer_io_dataOut_1_idx; + wire _instBuffer_io_dataOut_1_trap; + wire _instBuffer_io_dataOut_1_isControlFlow; + wire _instBuffer_io_dataOut_1_isBranch; + wire _instBuffer_io_dataOut_1_isVector; + wire _instBuffer_io_dataOut_1_linkOk; + wire _instBuffer_io_dataOut_1_isEcall; + wire _instBuffer_io_dataOut_1_isMpause; + wire _instBuffer_io_dataOut_1_isTile; + wire [31:0] _instBuffer_io_dataOut_2_addr; + wire [6:0] _instBuffer_io_dataOut_2_idx; + wire _instBuffer_io_dataOut_2_trap; + wire _instBuffer_io_dataOut_2_isControlFlow; + wire _instBuffer_io_dataOut_2_isBranch; + wire _instBuffer_io_dataOut_2_isVector; + wire _instBuffer_io_dataOut_2_linkOk; + wire _instBuffer_io_dataOut_2_isEcall; + wire _instBuffer_io_dataOut_2_isMpause; + wire _instBuffer_io_dataOut_2_isTile; + wire [31:0] _instBuffer_io_dataOut_3_addr; + wire [6:0] _instBuffer_io_dataOut_3_idx; + wire _instBuffer_io_dataOut_3_trap; + wire _instBuffer_io_dataOut_3_isControlFlow; + wire _instBuffer_io_dataOut_3_isBranch; + wire _instBuffer_io_dataOut_3_isVector; + wire _instBuffer_io_dataOut_3_linkOk; + wire _instBuffer_io_dataOut_3_isEcall; + wire _instBuffer_io_dataOut_3_isMpause; + wire _instBuffer_io_dataOut_3_isTile; + wire [31:0] _instBuffer_io_dataOut_4_addr; + wire [6:0] _instBuffer_io_dataOut_4_idx; + wire _instBuffer_io_dataOut_4_trap; + wire _instBuffer_io_dataOut_4_isControlFlow; + wire _instBuffer_io_dataOut_4_isBranch; + wire _instBuffer_io_dataOut_4_isVector; + wire _instBuffer_io_dataOut_4_linkOk; + wire _instBuffer_io_dataOut_4_isEcall; + wire _instBuffer_io_dataOut_4_isMpause; + wire _instBuffer_io_dataOut_4_isTile; + wire [31:0] _instBuffer_io_dataOut_5_addr; + wire [6:0] _instBuffer_io_dataOut_5_idx; + wire _instBuffer_io_dataOut_5_trap; + wire _instBuffer_io_dataOut_5_isControlFlow; + wire _instBuffer_io_dataOut_5_isBranch; + wire _instBuffer_io_dataOut_5_isVector; + wire _instBuffer_io_dataOut_5_linkOk; + wire _instBuffer_io_dataOut_5_isEcall; + wire _instBuffer_io_dataOut_5_isMpause; + wire _instBuffer_io_dataOut_5_isTile; + wire [31:0] _instBuffer_io_dataOut_6_addr; + wire [6:0] _instBuffer_io_dataOut_6_idx; + wire _instBuffer_io_dataOut_6_trap; + wire _instBuffer_io_dataOut_6_isControlFlow; + wire _instBuffer_io_dataOut_6_isBranch; + wire _instBuffer_io_dataOut_6_isVector; + wire _instBuffer_io_dataOut_6_linkOk; + wire _instBuffer_io_dataOut_6_isEcall; + wire _instBuffer_io_dataOut_6_isMpause; + wire _instBuffer_io_dataOut_6_isTile; + wire [31:0] _instBuffer_io_dataOut_7_addr; + wire [6:0] _instBuffer_io_dataOut_7_idx; + wire _instBuffer_io_dataOut_7_trap; + wire _instBuffer_io_dataOut_7_isControlFlow; + wire _instBuffer_io_dataOut_7_isBranch; + wire _instBuffer_io_dataOut_7_isVector; + wire _instBuffer_io_dataOut_7_linkOk; + wire _instBuffer_io_dataOut_7_isEcall; + wire _instBuffer_io_dataOut_7_isMpause; + wire _instBuffer_io_dataOut_7_isTile; + wire [31:0] _instBuffer_io_dataOut_8_addr; + wire [6:0] _instBuffer_io_dataOut_8_idx; + wire _instBuffer_io_dataOut_8_trap; + wire _instBuffer_io_dataOut_8_isControlFlow; + wire _instBuffer_io_dataOut_8_isBranch; + wire _instBuffer_io_dataOut_8_isVector; + wire _instBuffer_io_dataOut_8_linkOk; + wire _instBuffer_io_dataOut_8_isMpause; + wire _instBuffer_io_dataOut_8_isTile; + wire [31:0] _instBuffer_io_dataOut_9_addr; + wire [6:0] _instBuffer_io_dataOut_9_idx; + wire _instBuffer_io_dataOut_9_trap; + wire _instBuffer_io_dataOut_9_isControlFlow; + wire _instBuffer_io_dataOut_9_isBranch; + wire _instBuffer_io_dataOut_9_isVector; + wire _instBuffer_io_dataOut_9_linkOk; + wire _instBuffer_io_dataOut_9_isMpause; + wire _instBuffer_io_dataOut_9_isTile; + wire [31:0] _instBuffer_io_dataOut_10_addr; + wire [6:0] _instBuffer_io_dataOut_10_idx; + wire _instBuffer_io_dataOut_10_trap; + wire _instBuffer_io_dataOut_10_isControlFlow; + wire _instBuffer_io_dataOut_10_isBranch; + wire _instBuffer_io_dataOut_10_isVector; + wire _instBuffer_io_dataOut_10_linkOk; + wire _instBuffer_io_dataOut_10_isMpause; + wire _instBuffer_io_dataOut_10_isTile; + wire [31:0] _instBuffer_io_dataOut_11_addr; + wire [6:0] _instBuffer_io_dataOut_11_idx; + wire _instBuffer_io_dataOut_11_trap; + wire _instBuffer_io_dataOut_11_isControlFlow; + wire _instBuffer_io_dataOut_11_isBranch; + wire _instBuffer_io_dataOut_11_isVector; + wire _instBuffer_io_dataOut_11_linkOk; + wire _instBuffer_io_dataOut_11_isMpause; + wire _instBuffer_io_dataOut_11_isTile; + wire [31:0] _instBuffer_io_dataOut_12_addr; + wire [6:0] _instBuffer_io_dataOut_12_idx; + wire _instBuffer_io_dataOut_12_trap; + wire _instBuffer_io_dataOut_12_isControlFlow; + wire _instBuffer_io_dataOut_12_isBranch; + wire _instBuffer_io_dataOut_12_isVector; + wire _instBuffer_io_dataOut_12_linkOk; + wire _instBuffer_io_dataOut_12_isMpause; + wire _instBuffer_io_dataOut_12_isTile; + wire [31:0] _instBuffer_io_dataOut_13_addr; + wire [6:0] _instBuffer_io_dataOut_13_idx; + wire _instBuffer_io_dataOut_13_trap; + wire _instBuffer_io_dataOut_13_isControlFlow; + wire _instBuffer_io_dataOut_13_isBranch; + wire _instBuffer_io_dataOut_13_isVector; + wire _instBuffer_io_dataOut_13_linkOk; + wire _instBuffer_io_dataOut_13_isMpause; + wire _instBuffer_io_dataOut_13_isTile; + wire [31:0] _instBuffer_io_dataOut_14_addr; + wire [6:0] _instBuffer_io_dataOut_14_idx; + wire _instBuffer_io_dataOut_14_trap; + wire _instBuffer_io_dataOut_14_isControlFlow; + wire _instBuffer_io_dataOut_14_isBranch; + wire _instBuffer_io_dataOut_14_isVector; + wire _instBuffer_io_dataOut_14_linkOk; + wire _instBuffer_io_dataOut_14_isMpause; + wire _instBuffer_io_dataOut_14_isTile; + wire [31:0] _instBuffer_io_dataOut_15_addr; + wire [6:0] _instBuffer_io_dataOut_15_idx; + wire _instBuffer_io_dataOut_15_trap; + wire _instBuffer_io_dataOut_15_isControlFlow; + wire _instBuffer_io_dataOut_15_isBranch; + wire _instBuffer_io_dataOut_15_isVector; + wire _instBuffer_io_dataOut_15_linkOk; + wire _instBuffer_io_dataOut_15_isMpause; + wire _instBuffer_io_dataOut_15_isTile; + reg storeComplete_pipe_v; + reg [31:0] storeComplete_pipe_b; + wire instFires_0 = io_inst_0_ready & io_inst_0_valid; + wire instFires_1 = io_inst_1_ready & io_inst_1_valid; + wire instFires_2 = io_inst_2_ready & io_inst_2_valid; + wire instFires_3 = io_inst_3_ready & io_inst_3_valid; + wire decodeFaultValid = io_fault_valid & io_fault_bits_decode; + wire noFire0Fault = + decodeFaultValid & ~instFires_0 & io_fault_bits_mcause != 32'h7 + & io_fault_bits_mcause != 32'h5; + reg faultRetire_pipe_v; + reg [31:0] faultRetire_pipe_b_mepc; + reg [31:0] regLastTarget; + reg [31:0] regLastAddr; + reg regLastIsBranch; + reg regAfterFlush; + wire _lane0LinkOk_T_90 = io_inst_0_bits_addr == regLastTarget; + wire [31:0] _lane0LinkOk_T_92 = regLastAddr + 32'h4; + wire [6:0] _GEN = {2'h0, io_writeAddrScalar_0_addr}; + wire [31:0] _targetsList_T_1 = io_inst_0_bits_addr + 32'h4; + wire [31:0] _targetsList_T_5 = io_inst_1_bits_addr + 32'h4; + wire [31:0] _targetsList_T_9 = io_inst_2_bits_addr + 32'h4; + wire [2:0] instsWithWriteFired = + {1'h0, {1'h0, instFires_0} + {1'h0, instFires_1}} + + {1'h0, {1'h0, instFires_2} + {1'h0, instFires_3}}; + reg resultBuffer_0_valid; + reg resultBuffer_0_bits_trap; + reg resultBuffer_0_bits_cfDone; + reg resultBuffer_1_valid; + reg resultBuffer_1_bits_trap; + reg resultBuffer_1_bits_cfDone; + reg resultBuffer_2_valid; + reg resultBuffer_2_bits_trap; + reg resultBuffer_2_bits_cfDone; + reg resultBuffer_3_valid; + reg resultBuffer_3_bits_trap; + reg resultBuffer_3_bits_cfDone; + reg resultBuffer_4_valid; + reg resultBuffer_4_bits_trap; + reg resultBuffer_4_bits_cfDone; + reg resultBuffer_5_valid; + reg resultBuffer_5_bits_trap; + reg resultBuffer_5_bits_cfDone; + reg resultBuffer_6_valid; + reg resultBuffer_6_bits_trap; + reg resultBuffer_6_bits_cfDone; + reg resultBuffer_7_valid; + reg resultBuffer_7_bits_trap; + reg resultBuffer_7_bits_cfDone; + reg resultBuffer_8_valid; + reg resultBuffer_8_bits_trap; + reg resultBuffer_8_bits_cfDone; + reg resultBuffer_9_valid; + reg resultBuffer_9_bits_trap; + reg resultBuffer_9_bits_cfDone; + reg resultBuffer_10_valid; + reg resultBuffer_10_bits_trap; + reg resultBuffer_10_bits_cfDone; + reg resultBuffer_11_valid; + reg resultBuffer_11_bits_trap; + reg resultBuffer_11_bits_cfDone; + reg resultBuffer_12_valid; + reg resultBuffer_12_bits_trap; + reg resultBuffer_12_bits_cfDone; + reg resultBuffer_13_valid; + reg resultBuffer_13_bits_trap; + reg resultBuffer_13_bits_cfDone; + reg resultBuffer_14_valid; + reg resultBuffer_14_bits_trap; + reg resultBuffer_14_bits_cfDone; + reg resultBuffer_15_valid; + reg resultBuffer_15_bits_trap; + reg resultBuffer_15_bits_cfDone; + wire [6:0] _GEN_0 = {2'h0, io_writeDataScalar_0_bits_addr}; + wire [6:0] _GEN_1 = {2'h0, io_writeDataScalar_1_bits_addr}; + wire [6:0] _GEN_2 = {2'h0, io_writeDataScalar_2_bits_addr}; + wire [6:0] _GEN_3 = {2'h0, io_writeDataScalar_3_bits_addr}; + wire [6:0] _GEN_4 = {2'h0, io_writeDataScalar_4_bits_addr}; + wire [6:0] _GEN_5 = {2'h0, io_writeDataScalar_5_bits_addr}; + wire [6:0] _floatWriteIdxMap_T_60 = {2'h0, io_writeDataFloat_0_bits_addr} + 7'h20; + wire [6:0] _floatWriteIdxMap_T_62 = {2'h0, io_writeDataFloat_1_bits_addr} + 7'h20; + wire faultingInstr = + faultRetire_pipe_v & _instBuffer_io_dataOut_0_addr == faultRetire_pipe_b_mepc; + wire nextAddrValid = (|(_instBuffer_io_nEnqueued[4:1])) | io_inst_0_valid; + wire newCfDone = + (|_instBuffer_io_nEnqueued) + & (~_instBuffer_io_dataOut_0_isControlFlow | nextAddrValid); + wire currentTrap = + resultBuffer_0_bits_trap | faultingInstr | (|_instBuffer_io_nEnqueued) + & _instBuffer_io_dataOut_0_trap | _instBuffer_io_dataOut_0_isControlFlow & newCfDone + & ~(nextAddrValid + & (((|(_instBuffer_io_nEnqueued[4:1])) + ? _instBuffer_io_dataOut_1_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_0_isBranch + & ((|(_instBuffer_io_nEnqueued[4:1])) | ~io_inst_0_valid + ? _instBuffer_io_dataOut_1_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_0_addr + 32'h4)) + & ~_instBuffer_io_dataOut_0_isMpause; + wire currentDataDone = + resultBuffer_0_valid | (|_instBuffer_io_nEnqueued) & ~resultBuffer_0_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_0_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_0_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_0_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_0_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_0_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_0_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_0_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_0_idx + | (&_instBuffer_io_dataOut_0_idx) & ~_instBuffer_io_dataOut_0_isTile + | _instBuffer_io_dataOut_0_isTile | _instBuffer_io_dataOut_0_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_0_addr + | _instBuffer_io_dataOut_0_trap | _instBuffer_io_dataOut_0_isControlFlow + & newCfDone | faultingInstr & ~_instBuffer_io_dataOut_0_isVector); + wire currentCfDone = + resultBuffer_0_valid & resultBuffer_0_bits_cfDone | newCfDone; + wire faultingInstr_1 = + faultRetire_pipe_v & _instBuffer_io_dataOut_1_addr == faultRetire_pipe_b_mepc; + wire nextValid_1 = _instBuffer_io_nEnqueued > 5'h2; + wire nextAddrValid_1 = nextValid_1 | io_inst_0_valid; + wire newCfDone_1 = + (|(_instBuffer_io_nEnqueued[4:1])) + & (~_instBuffer_io_dataOut_1_isControlFlow | nextAddrValid_1); + wire currentTrap_1 = + resultBuffer_1_bits_trap | faultingInstr_1 | (|(_instBuffer_io_nEnqueued[4:1])) + & _instBuffer_io_dataOut_1_trap | _instBuffer_io_dataOut_1_isControlFlow & newCfDone_1 + & ~(nextAddrValid_1 + & ((nextValid_1 + ? _instBuffer_io_dataOut_2_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_1_isBranch + & (nextValid_1 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_2_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_1_addr + 32'h4)) + & ~_instBuffer_io_dataOut_1_isMpause; + wire currentDataDone_1 = + resultBuffer_1_valid | (|(_instBuffer_io_nEnqueued[4:1])) & ~resultBuffer_1_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_1_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_1_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_1_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_1_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_1_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_1_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_1_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_1_idx + | (&_instBuffer_io_dataOut_1_idx) & ~_instBuffer_io_dataOut_1_isTile + | _instBuffer_io_dataOut_1_isTile | _instBuffer_io_dataOut_1_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_1_addr + | _instBuffer_io_dataOut_1_trap | _instBuffer_io_dataOut_1_isControlFlow + & newCfDone_1 | faultingInstr_1 & ~_instBuffer_io_dataOut_1_isVector); + wire currentCfDone_1 = + resultBuffer_1_valid & resultBuffer_1_bits_cfDone | newCfDone_1; + wire faultingInstr_2 = + faultRetire_pipe_v & _instBuffer_io_dataOut_2_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_2 = _instBuffer_io_nEnqueued > 5'h2; + wire nextAddrValid_2 = (|(_instBuffer_io_nEnqueued[4:2])) | io_inst_0_valid; + wire newCfDone_2 = + validBufferEntry_2 & (~_instBuffer_io_dataOut_2_isControlFlow | nextAddrValid_2); + wire currentTrap_2 = + resultBuffer_2_bits_trap | faultingInstr_2 | validBufferEntry_2 + & _instBuffer_io_dataOut_2_trap | _instBuffer_io_dataOut_2_isControlFlow & newCfDone_2 + & ~(nextAddrValid_2 + & (((|(_instBuffer_io_nEnqueued[4:2])) + ? _instBuffer_io_dataOut_3_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_2_isBranch + & ((|(_instBuffer_io_nEnqueued[4:2])) | ~io_inst_0_valid + ? _instBuffer_io_dataOut_3_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_2_addr + 32'h4)) + & ~_instBuffer_io_dataOut_2_isMpause; + wire currentDataDone_2 = + resultBuffer_2_valid | validBufferEntry_2 & ~resultBuffer_2_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_2_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_2_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_2_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_2_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_2_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_2_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_2_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_2_idx + | (&_instBuffer_io_dataOut_2_idx) & ~_instBuffer_io_dataOut_2_isTile + | _instBuffer_io_dataOut_2_isTile | _instBuffer_io_dataOut_2_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_2_addr + | _instBuffer_io_dataOut_2_trap | _instBuffer_io_dataOut_2_isControlFlow + & newCfDone_2 | faultingInstr_2 & ~_instBuffer_io_dataOut_2_isVector); + wire currentCfDone_2 = + resultBuffer_2_valid & resultBuffer_2_bits_cfDone | newCfDone_2; + wire faultingInstr_3 = + faultRetire_pipe_v & _instBuffer_io_dataOut_3_addr == faultRetire_pipe_b_mepc; + wire nextValid_3 = _instBuffer_io_nEnqueued > 5'h4; + wire nextAddrValid_3 = nextValid_3 | io_inst_0_valid; + wire newCfDone_3 = + (|(_instBuffer_io_nEnqueued[4:2])) + & (~_instBuffer_io_dataOut_3_isControlFlow | nextAddrValid_3); + wire currentTrap_3 = + resultBuffer_3_bits_trap | faultingInstr_3 | (|(_instBuffer_io_nEnqueued[4:2])) + & _instBuffer_io_dataOut_3_trap | _instBuffer_io_dataOut_3_isControlFlow & newCfDone_3 + & ~(nextAddrValid_3 + & ((nextValid_3 + ? _instBuffer_io_dataOut_4_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_3_isBranch + & (nextValid_3 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_4_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_3_addr + 32'h4)) + & ~_instBuffer_io_dataOut_3_isMpause; + wire currentDataDone_3 = + resultBuffer_3_valid | (|(_instBuffer_io_nEnqueued[4:2])) & ~resultBuffer_3_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_3_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_3_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_3_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_3_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_3_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_3_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_3_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_3_idx + | (&_instBuffer_io_dataOut_3_idx) & ~_instBuffer_io_dataOut_3_isTile + | _instBuffer_io_dataOut_3_isTile | _instBuffer_io_dataOut_3_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_3_addr + | _instBuffer_io_dataOut_3_trap | _instBuffer_io_dataOut_3_isControlFlow + & newCfDone_3 | faultingInstr_3 & ~_instBuffer_io_dataOut_3_isVector); + wire currentCfDone_3 = + resultBuffer_3_valid & resultBuffer_3_bits_cfDone | newCfDone_3; + wire faultingInstr_4 = + faultRetire_pipe_v & _instBuffer_io_dataOut_4_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_4 = _instBuffer_io_nEnqueued > 5'h4; + wire nextValid_4 = _instBuffer_io_nEnqueued > 5'h5; + wire nextAddrValid_4 = nextValid_4 | io_inst_0_valid; + wire newCfDone_4 = + validBufferEntry_4 & (~_instBuffer_io_dataOut_4_isControlFlow | nextAddrValid_4); + wire currentTrap_4 = + resultBuffer_4_bits_trap | faultingInstr_4 | validBufferEntry_4 + & _instBuffer_io_dataOut_4_trap | _instBuffer_io_dataOut_4_isControlFlow & newCfDone_4 + & ~(nextAddrValid_4 + & ((nextValid_4 + ? _instBuffer_io_dataOut_5_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_4_isBranch + & (nextValid_4 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_5_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_4_addr + 32'h4)) + & ~_instBuffer_io_dataOut_4_isMpause; + wire currentDataDone_4 = + resultBuffer_4_valid | validBufferEntry_4 & ~resultBuffer_4_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_4_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_4_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_4_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_4_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_4_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_4_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_4_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_4_idx + | (&_instBuffer_io_dataOut_4_idx) & ~_instBuffer_io_dataOut_4_isTile + | _instBuffer_io_dataOut_4_isTile | _instBuffer_io_dataOut_4_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_4_addr + | _instBuffer_io_dataOut_4_trap | _instBuffer_io_dataOut_4_isControlFlow + & newCfDone_4 | faultingInstr_4 & ~_instBuffer_io_dataOut_4_isVector); + wire currentCfDone_4 = + resultBuffer_4_valid & resultBuffer_4_bits_cfDone | newCfDone_4; + wire faultingInstr_5 = + faultRetire_pipe_v & _instBuffer_io_dataOut_5_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_5 = _instBuffer_io_nEnqueued > 5'h5; + wire nextValid_5 = _instBuffer_io_nEnqueued > 5'h6; + wire nextAddrValid_5 = nextValid_5 | io_inst_0_valid; + wire newCfDone_5 = + validBufferEntry_5 & (~_instBuffer_io_dataOut_5_isControlFlow | nextAddrValid_5); + wire currentTrap_5 = + resultBuffer_5_bits_trap | faultingInstr_5 | validBufferEntry_5 + & _instBuffer_io_dataOut_5_trap | _instBuffer_io_dataOut_5_isControlFlow & newCfDone_5 + & ~(nextAddrValid_5 + & ((nextValid_5 + ? _instBuffer_io_dataOut_6_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_5_isBranch + & (nextValid_5 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_6_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_5_addr + 32'h4)) + & ~_instBuffer_io_dataOut_5_isMpause; + wire currentDataDone_5 = + resultBuffer_5_valid | validBufferEntry_5 & ~resultBuffer_5_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_5_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_5_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_5_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_5_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_5_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_5_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_5_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_5_idx + | (&_instBuffer_io_dataOut_5_idx) & ~_instBuffer_io_dataOut_5_isTile + | _instBuffer_io_dataOut_5_isTile | _instBuffer_io_dataOut_5_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_5_addr + | _instBuffer_io_dataOut_5_trap | _instBuffer_io_dataOut_5_isControlFlow + & newCfDone_5 | faultingInstr_5 & ~_instBuffer_io_dataOut_5_isVector); + wire currentCfDone_5 = + resultBuffer_5_valid & resultBuffer_5_bits_cfDone | newCfDone_5; + wire faultingInstr_6 = + faultRetire_pipe_v & _instBuffer_io_dataOut_6_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_6 = _instBuffer_io_nEnqueued > 5'h6; + wire nextAddrValid_6 = (|(_instBuffer_io_nEnqueued[4:3])) | io_inst_0_valid; + wire newCfDone_6 = + validBufferEntry_6 & (~_instBuffer_io_dataOut_6_isControlFlow | nextAddrValid_6); + wire currentTrap_6 = + resultBuffer_6_bits_trap | faultingInstr_6 | validBufferEntry_6 + & _instBuffer_io_dataOut_6_trap | _instBuffer_io_dataOut_6_isControlFlow & newCfDone_6 + & ~(nextAddrValid_6 + & (((|(_instBuffer_io_nEnqueued[4:3])) + ? _instBuffer_io_dataOut_7_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_6_isBranch + & ((|(_instBuffer_io_nEnqueued[4:3])) | ~io_inst_0_valid + ? _instBuffer_io_dataOut_7_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_6_addr + 32'h4)) + & ~_instBuffer_io_dataOut_6_isMpause; + wire currentDataDone_6 = + resultBuffer_6_valid | validBufferEntry_6 & ~resultBuffer_6_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_6_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_6_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_6_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_6_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_6_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_6_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_6_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_6_idx + | (&_instBuffer_io_dataOut_6_idx) & ~_instBuffer_io_dataOut_6_isTile + | _instBuffer_io_dataOut_6_isTile | _instBuffer_io_dataOut_6_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_6_addr + | _instBuffer_io_dataOut_6_trap | _instBuffer_io_dataOut_6_isControlFlow + & newCfDone_6 | faultingInstr_6 & ~_instBuffer_io_dataOut_6_isVector); + wire currentCfDone_6 = + resultBuffer_6_valid & resultBuffer_6_bits_cfDone | newCfDone_6; + wire faultingInstr_7 = + faultRetire_pipe_v & _instBuffer_io_dataOut_7_addr == faultRetire_pipe_b_mepc; + wire nextValid_7 = _instBuffer_io_nEnqueued > 5'h8; + wire nextAddrValid_7 = nextValid_7 | io_inst_0_valid; + wire newCfDone_7 = + (|(_instBuffer_io_nEnqueued[4:3])) + & (~_instBuffer_io_dataOut_7_isControlFlow | nextAddrValid_7); + wire currentTrap_7 = + resultBuffer_7_bits_trap | faultingInstr_7 | (|(_instBuffer_io_nEnqueued[4:3])) + & _instBuffer_io_dataOut_7_trap | _instBuffer_io_dataOut_7_isControlFlow & newCfDone_7 + & ~(nextAddrValid_7 + & ((nextValid_7 + ? _instBuffer_io_dataOut_8_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_7_isBranch + & (nextValid_7 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_8_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_7_addr + 32'h4)) + & ~_instBuffer_io_dataOut_7_isMpause; + wire currentDataDone_7 = + resultBuffer_7_valid | (|(_instBuffer_io_nEnqueued[4:3])) & ~resultBuffer_7_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_7_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_7_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_7_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_7_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_7_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_7_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_7_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_7_idx + | (&_instBuffer_io_dataOut_7_idx) & ~_instBuffer_io_dataOut_7_isTile + | _instBuffer_io_dataOut_7_isTile | _instBuffer_io_dataOut_7_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_7_addr + | _instBuffer_io_dataOut_7_trap | _instBuffer_io_dataOut_7_isControlFlow + & newCfDone_7 | faultingInstr_7 & ~_instBuffer_io_dataOut_7_isVector); + wire currentCfDone_7 = + resultBuffer_7_valid & resultBuffer_7_bits_cfDone | newCfDone_7; + wire [3:0] deqReady = + currentDataDone & currentCfDone + ? (~currentDataDone_1 | ~currentCfDone_1 | currentTrap + ? 4'h1 + : ~currentDataDone_2 | ~currentCfDone_2 | currentTrap_1 + ? 4'h2 + : ~currentDataDone_3 | ~currentCfDone_3 | currentTrap_2 + ? 4'h3 + : ~currentDataDone_4 | ~currentCfDone_4 | currentTrap_3 + ? 4'h4 + : ~currentDataDone_5 | ~currentCfDone_5 | currentTrap_4 + ? 4'h5 + : ~currentDataDone_6 | ~currentCfDone_6 | currentTrap_5 + ? 4'h6 + : ~currentDataDone_7 | ~currentCfDone_7 | currentTrap_6 + ? 4'h7 + : 4'h8) + : 4'h0; + wire trapRetired_laneReady_0 = currentDataDone & currentCfDone; + wire trapRetired_laneCanTrap_1 = + trapRetired_laneReady_0 & currentDataDone_1 & currentCfDone_1; + wire trapRetired_laneCanTrap_2 = + trapRetired_laneCanTrap_1 & currentDataDone_2 & currentCfDone_2; + wire trapRetired_laneCanTrap_3 = + trapRetired_laneCanTrap_2 & currentDataDone_3 & currentCfDone_3; + wire trapRetired_laneCanTrap_4 = + trapRetired_laneCanTrap_3 & currentDataDone_4 & currentCfDone_4; + wire trapRetired_laneCanTrap_5 = + trapRetired_laneCanTrap_4 & currentDataDone_5 & currentCfDone_5; + wire trapRetired_laneCanTrap_6 = + trapRetired_laneCanTrap_5 & currentDataDone_6 & currentCfDone_6; + wire trapRetired = + trapRetired_laneReady_0 & currentTrap | trapRetired_laneCanTrap_1 & currentTrap_1 + | trapRetired_laneCanTrap_2 & currentTrap_2 | trapRetired_laneCanTrap_3 + & currentTrap_3 | trapRetired_laneCanTrap_4 & currentTrap_4 + | trapRetired_laneCanTrap_5 & currentTrap_5 | trapRetired_laneCanTrap_6 + & currentTrap_6 | trapRetired_laneCanTrap_6 & currentDataDone_7 & currentCfDone_7 + & currentTrap_7; + reg [3:0] deqReady_reg; + reg [7:0] instIsEcallMask_reg; + reg io_trapPending_REG; + wire hasFire = instFires_0 | instFires_1 | instFires_2 | instFires_3; + wire faultingInstr_8 = + faultRetire_pipe_v & _instBuffer_io_dataOut_8_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_8 = _instBuffer_io_nEnqueued > 5'h8; + wire nextValid_8 = _instBuffer_io_nEnqueued > 5'h9; + wire nextAddrValid_8 = nextValid_8 | io_inst_0_valid; + wire newCfDone_8 = + validBufferEntry_8 & (~_instBuffer_io_dataOut_8_isControlFlow | nextAddrValid_8); + wire currentTrap_8 = + resultBuffer_8_bits_trap | faultingInstr_8 | validBufferEntry_8 + & _instBuffer_io_dataOut_8_trap | _instBuffer_io_dataOut_8_isControlFlow & newCfDone_8 + & ~(nextAddrValid_8 + & ((nextValid_8 + ? _instBuffer_io_dataOut_9_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_8_isBranch + & (nextValid_8 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_9_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_8_addr + 32'h4)) + & ~_instBuffer_io_dataOut_8_isMpause; + wire currentDataDone_8 = + resultBuffer_8_valid | validBufferEntry_8 & ~resultBuffer_8_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_8_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_8_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_8_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_8_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_8_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_8_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_8_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_8_idx + | (&_instBuffer_io_dataOut_8_idx) & ~_instBuffer_io_dataOut_8_isTile + | _instBuffer_io_dataOut_8_isTile | _instBuffer_io_dataOut_8_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_8_addr + | _instBuffer_io_dataOut_8_trap | _instBuffer_io_dataOut_8_isControlFlow + & newCfDone_8 | faultingInstr_8 & ~_instBuffer_io_dataOut_8_isVector); + wire faultingInstr_9 = + faultRetire_pipe_v & _instBuffer_io_dataOut_9_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_9 = _instBuffer_io_nEnqueued > 5'h9; + wire nextValid_9 = _instBuffer_io_nEnqueued > 5'hA; + wire nextAddrValid_9 = nextValid_9 | io_inst_0_valid; + wire newCfDone_9 = + validBufferEntry_9 & (~_instBuffer_io_dataOut_9_isControlFlow | nextAddrValid_9); + wire currentTrap_9 = + resultBuffer_9_bits_trap | faultingInstr_9 | validBufferEntry_9 + & _instBuffer_io_dataOut_9_trap | _instBuffer_io_dataOut_9_isControlFlow & newCfDone_9 + & ~(nextAddrValid_9 + & ((nextValid_9 + ? _instBuffer_io_dataOut_10_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_9_isBranch + & (nextValid_9 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_10_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_9_addr + 32'h4)) + & ~_instBuffer_io_dataOut_9_isMpause; + wire currentDataDone_9 = + resultBuffer_9_valid | validBufferEntry_9 & ~resultBuffer_9_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_9_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_9_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_9_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_9_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_9_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_9_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_9_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_9_idx + | (&_instBuffer_io_dataOut_9_idx) & ~_instBuffer_io_dataOut_9_isTile + | _instBuffer_io_dataOut_9_isTile | _instBuffer_io_dataOut_9_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_9_addr + | _instBuffer_io_dataOut_9_trap | _instBuffer_io_dataOut_9_isControlFlow + & newCfDone_9 | faultingInstr_9 & ~_instBuffer_io_dataOut_9_isVector); + wire faultingInstr_10 = + faultRetire_pipe_v & _instBuffer_io_dataOut_10_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_10 = _instBuffer_io_nEnqueued > 5'hA; + wire nextValid_10 = _instBuffer_io_nEnqueued > 5'hB; + wire nextAddrValid_10 = nextValid_10 | io_inst_0_valid; + wire newCfDone_10 = + validBufferEntry_10 & (~_instBuffer_io_dataOut_10_isControlFlow | nextAddrValid_10); + wire currentTrap_10 = + resultBuffer_10_bits_trap | faultingInstr_10 | validBufferEntry_10 + & _instBuffer_io_dataOut_10_trap | _instBuffer_io_dataOut_10_isControlFlow + & newCfDone_10 + & ~(nextAddrValid_10 + & ((nextValid_10 + ? _instBuffer_io_dataOut_11_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_10_isBranch + & (nextValid_10 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_11_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_10_addr + 32'h4)) + & ~_instBuffer_io_dataOut_10_isMpause; + wire currentDataDone_10 = + resultBuffer_10_valid | validBufferEntry_10 & ~resultBuffer_10_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_10_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_10_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_10_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_10_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_10_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_10_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_10_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_10_idx + | (&_instBuffer_io_dataOut_10_idx) & ~_instBuffer_io_dataOut_10_isTile + | _instBuffer_io_dataOut_10_isTile | _instBuffer_io_dataOut_10_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_10_addr + | _instBuffer_io_dataOut_10_trap | _instBuffer_io_dataOut_10_isControlFlow + & newCfDone_10 | faultingInstr_10 & ~_instBuffer_io_dataOut_10_isVector); + wire faultingInstr_11 = + faultRetire_pipe_v & _instBuffer_io_dataOut_11_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_11 = _instBuffer_io_nEnqueued > 5'hB; + wire nextValid_11 = _instBuffer_io_nEnqueued > 5'hC; + wire nextAddrValid_11 = nextValid_11 | io_inst_0_valid; + wire newCfDone_11 = + validBufferEntry_11 & (~_instBuffer_io_dataOut_11_isControlFlow | nextAddrValid_11); + wire currentTrap_11 = + resultBuffer_11_bits_trap | faultingInstr_11 | validBufferEntry_11 + & _instBuffer_io_dataOut_11_trap | _instBuffer_io_dataOut_11_isControlFlow + & newCfDone_11 + & ~(nextAddrValid_11 + & ((nextValid_11 + ? _instBuffer_io_dataOut_12_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_11_isBranch + & (nextValid_11 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_12_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_11_addr + 32'h4)) + & ~_instBuffer_io_dataOut_11_isMpause; + wire currentDataDone_11 = + resultBuffer_11_valid | validBufferEntry_11 & ~resultBuffer_11_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_11_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_11_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_11_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_11_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_11_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_11_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_11_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_11_idx + | (&_instBuffer_io_dataOut_11_idx) & ~_instBuffer_io_dataOut_11_isTile + | _instBuffer_io_dataOut_11_isTile | _instBuffer_io_dataOut_11_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_11_addr + | _instBuffer_io_dataOut_11_trap | _instBuffer_io_dataOut_11_isControlFlow + & newCfDone_11 | faultingInstr_11 & ~_instBuffer_io_dataOut_11_isVector); + wire faultingInstr_12 = + faultRetire_pipe_v & _instBuffer_io_dataOut_12_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_12 = _instBuffer_io_nEnqueued > 5'hC; + wire nextValid_12 = _instBuffer_io_nEnqueued > 5'hD; + wire nextAddrValid_12 = nextValid_12 | io_inst_0_valid; + wire newCfDone_12 = + validBufferEntry_12 & (~_instBuffer_io_dataOut_12_isControlFlow | nextAddrValid_12); + wire currentTrap_12 = + resultBuffer_12_bits_trap | faultingInstr_12 | validBufferEntry_12 + & _instBuffer_io_dataOut_12_trap | _instBuffer_io_dataOut_12_isControlFlow + & newCfDone_12 + & ~(nextAddrValid_12 + & ((nextValid_12 + ? _instBuffer_io_dataOut_13_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_12_isBranch + & (nextValid_12 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_13_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_12_addr + 32'h4)) + & ~_instBuffer_io_dataOut_12_isMpause; + wire currentDataDone_12 = + resultBuffer_12_valid | validBufferEntry_12 & ~resultBuffer_12_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_12_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_12_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_12_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_12_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_12_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_12_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_12_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_12_idx + | (&_instBuffer_io_dataOut_12_idx) & ~_instBuffer_io_dataOut_12_isTile + | _instBuffer_io_dataOut_12_isTile | _instBuffer_io_dataOut_12_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_12_addr + | _instBuffer_io_dataOut_12_trap | _instBuffer_io_dataOut_12_isControlFlow + & newCfDone_12 | faultingInstr_12 & ~_instBuffer_io_dataOut_12_isVector); + wire faultingInstr_13 = + faultRetire_pipe_v & _instBuffer_io_dataOut_13_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_13 = _instBuffer_io_nEnqueued > 5'hD; + wire nextValid_13 = _instBuffer_io_nEnqueued > 5'hE; + wire nextAddrValid_13 = nextValid_13 | io_inst_0_valid; + wire newCfDone_13 = + validBufferEntry_13 & (~_instBuffer_io_dataOut_13_isControlFlow | nextAddrValid_13); + wire currentTrap_13 = + resultBuffer_13_bits_trap | faultingInstr_13 | validBufferEntry_13 + & _instBuffer_io_dataOut_13_trap | _instBuffer_io_dataOut_13_isControlFlow + & newCfDone_13 + & ~(nextAddrValid_13 + & ((nextValid_13 + ? _instBuffer_io_dataOut_14_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_13_isBranch + & (nextValid_13 | ~io_inst_0_valid + ? _instBuffer_io_dataOut_14_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_13_addr + 32'h4)) + & ~_instBuffer_io_dataOut_13_isMpause; + wire currentDataDone_13 = + resultBuffer_13_valid | validBufferEntry_13 & ~resultBuffer_13_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_13_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_13_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_13_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_13_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_13_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_13_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_13_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_13_idx + | (&_instBuffer_io_dataOut_13_idx) & ~_instBuffer_io_dataOut_13_isTile + | _instBuffer_io_dataOut_13_isTile | _instBuffer_io_dataOut_13_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_13_addr + | _instBuffer_io_dataOut_13_trap | _instBuffer_io_dataOut_13_isControlFlow + & newCfDone_13 | faultingInstr_13 & ~_instBuffer_io_dataOut_13_isVector); + wire faultingInstr_14 = + faultRetire_pipe_v & _instBuffer_io_dataOut_14_addr == faultRetire_pipe_b_mepc; + wire validBufferEntry_14 = _instBuffer_io_nEnqueued > 5'hE; + wire nextAddrValid_14 = _instBuffer_io_nEnqueued[4] | io_inst_0_valid; + wire newCfDone_14 = + validBufferEntry_14 & (~_instBuffer_io_dataOut_14_isControlFlow | nextAddrValid_14); + wire currentTrap_14 = + resultBuffer_14_bits_trap | faultingInstr_14 | validBufferEntry_14 + & _instBuffer_io_dataOut_14_trap | _instBuffer_io_dataOut_14_isControlFlow + & newCfDone_14 + & ~(nextAddrValid_14 + & ((_instBuffer_io_nEnqueued[4] + ? _instBuffer_io_dataOut_15_linkOk + : ~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92) + | _instBuffer_io_dataOut_14_isBranch + & (_instBuffer_io_nEnqueued[4] | ~io_inst_0_valid + ? _instBuffer_io_dataOut_15_addr + : io_inst_0_bits_addr) == _instBuffer_io_dataOut_14_addr + 32'h4)) + & ~_instBuffer_io_dataOut_14_isMpause; + wire currentDataDone_14 = + resultBuffer_14_valid | validBufferEntry_14 & ~resultBuffer_14_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_14_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_14_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_14_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_14_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_14_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_14_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_14_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_14_idx + | (&_instBuffer_io_dataOut_14_idx) & ~_instBuffer_io_dataOut_14_isTile + | _instBuffer_io_dataOut_14_isTile | _instBuffer_io_dataOut_14_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_14_addr + | _instBuffer_io_dataOut_14_trap | _instBuffer_io_dataOut_14_isControlFlow + & newCfDone_14 | faultingInstr_14 & ~_instBuffer_io_dataOut_14_isVector); + wire faultingInstr_15 = + faultRetire_pipe_v & _instBuffer_io_dataOut_15_addr == faultRetire_pipe_b_mepc; + wire newCfDone_15 = + _instBuffer_io_nEnqueued[4] + & (~_instBuffer_io_dataOut_15_isControlFlow | io_inst_0_valid); + wire currentTrap_15 = + resultBuffer_15_bits_trap | faultingInstr_15 | _instBuffer_io_nEnqueued[4] + & _instBuffer_io_dataOut_15_trap | _instBuffer_io_dataOut_15_isControlFlow + & newCfDone_15 + & ~(io_inst_0_valid + & (~io_inst_0_valid | regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92 | _instBuffer_io_dataOut_15_isBranch + & (io_inst_0_valid + ? io_inst_0_bits_addr + : 32'h0) == _instBuffer_io_dataOut_15_addr + 32'h4)) + & ~_instBuffer_io_dataOut_15_isMpause; + wire currentDataDone_15 = + resultBuffer_15_valid | _instBuffer_io_nEnqueued[4] & ~resultBuffer_15_valid + & (io_writeDataScalar_0_valid & _GEN_0 == _instBuffer_io_dataOut_15_idx + | io_writeDataScalar_1_valid & _GEN_1 == _instBuffer_io_dataOut_15_idx + | io_writeDataScalar_2_valid & _GEN_2 == _instBuffer_io_dataOut_15_idx + | io_writeDataScalar_3_valid & _GEN_3 == _instBuffer_io_dataOut_15_idx + | io_writeDataScalar_4_valid & _GEN_4 == _instBuffer_io_dataOut_15_idx + | io_writeDataScalar_5_valid & _GEN_5 == _instBuffer_io_dataOut_15_idx + | io_writeDataFloat_0_valid + & _floatWriteIdxMap_T_60 == _instBuffer_io_dataOut_15_idx + | io_writeDataFloat_1_valid + & _floatWriteIdxMap_T_62 == _instBuffer_io_dataOut_15_idx + | (&_instBuffer_io_dataOut_15_idx) & ~_instBuffer_io_dataOut_15_isTile + | _instBuffer_io_dataOut_15_isTile | _instBuffer_io_dataOut_15_idx == 7'h7E + & storeComplete_pipe_v & storeComplete_pipe_b == _instBuffer_io_dataOut_15_addr + | _instBuffer_io_dataOut_15_trap | _instBuffer_io_dataOut_15_isControlFlow + & newCfDone_15 | faultingInstr_15 & ~_instBuffer_io_dataOut_15_isVector); + wire [47:0] shifted = + {currentDataDone_15, + currentTrap_15, + resultBuffer_15_valid & resultBuffer_15_bits_cfDone | newCfDone_15, + currentDataDone_14, + currentTrap_14, + resultBuffer_14_valid & resultBuffer_14_bits_cfDone | newCfDone_14, + currentDataDone_13, + currentTrap_13, + resultBuffer_13_valid & resultBuffer_13_bits_cfDone | newCfDone_13, + currentDataDone_12, + currentTrap_12, + resultBuffer_12_valid & resultBuffer_12_bits_cfDone | newCfDone_12, + currentDataDone_11, + currentTrap_11, + resultBuffer_11_valid & resultBuffer_11_bits_cfDone | newCfDone_11, + currentDataDone_10, + currentTrap_10, + resultBuffer_10_valid & resultBuffer_10_bits_cfDone | newCfDone_10, + currentDataDone_9, + currentTrap_9, + resultBuffer_9_valid & resultBuffer_9_bits_cfDone | newCfDone_9, + currentDataDone_8, + currentTrap_8, + resultBuffer_8_valid & resultBuffer_8_bits_cfDone | newCfDone_8, + currentDataDone_7, + currentTrap_7, + currentCfDone_7, + currentDataDone_6, + currentTrap_6, + currentCfDone_6, + currentDataDone_5, + currentTrap_5, + currentCfDone_5, + currentDataDone_4, + currentTrap_4, + currentCfDone_4, + currentDataDone_3, + currentTrap_3, + currentCfDone_3, + currentDataDone_2, + currentTrap_2, + currentCfDone_2, + currentDataDone_1, + currentTrap_1, + currentCfDone_1, + currentDataDone, + currentTrap, + currentCfDone} >> {2'h0, deqReady} * 6'h3; always @(posedge clock or posedge reset) begin if (reset) begin - ipos <= 1'h0; - opos <= 1'h0; - mem_0_pc <= 32'h0; - mem_0_addr <= 32'h0; - mem_0_adrx <= 32'h0; - mem_0_data <= 32'h0; - mem_0_index <= 5'h0; - mem_0_size <= 5'h0; - mem_0_fullsize <= 5'h0; - mem_0_write <= 1'h0; - mem_0_sext <= 1'h0; - mem_0_iload <= 1'h0; - mem_0_fencei <= 1'h0; - mem_0_flushat <= 1'h0; - mem_0_flushall <= 1'h0; - mem_0_sldst <= 1'h0; - mem_0_vldst <= 1'h0; - mem_0_fldst <= 1'h0; - mem_0_regionType <= 2'h0; - mem_0_mask <= 16'h0; - mem_0_last <= 1'h0; + storeComplete_pipe_v <= 1'h0; + faultRetire_pipe_v <= 1'h0; + regLastTarget <= 32'h0; + regLastAddr <= 32'h0; + regLastIsBranch <= 1'h0; + regAfterFlush <= 1'h1; + resultBuffer_0_valid <= 1'h0; + resultBuffer_0_bits_trap <= 1'h0; + resultBuffer_0_bits_cfDone <= 1'h0; + resultBuffer_1_valid <= 1'h0; + resultBuffer_1_bits_trap <= 1'h0; + resultBuffer_1_bits_cfDone <= 1'h0; + resultBuffer_2_valid <= 1'h0; + resultBuffer_2_bits_trap <= 1'h0; + resultBuffer_2_bits_cfDone <= 1'h0; + resultBuffer_3_valid <= 1'h0; + resultBuffer_3_bits_trap <= 1'h0; + resultBuffer_3_bits_cfDone <= 1'h0; + resultBuffer_4_valid <= 1'h0; + resultBuffer_4_bits_trap <= 1'h0; + resultBuffer_4_bits_cfDone <= 1'h0; + resultBuffer_5_valid <= 1'h0; + resultBuffer_5_bits_trap <= 1'h0; + resultBuffer_5_bits_cfDone <= 1'h0; + resultBuffer_6_valid <= 1'h0; + resultBuffer_6_bits_trap <= 1'h0; + resultBuffer_6_bits_cfDone <= 1'h0; + resultBuffer_7_valid <= 1'h0; + resultBuffer_7_bits_trap <= 1'h0; + resultBuffer_7_bits_cfDone <= 1'h0; + resultBuffer_8_valid <= 1'h0; + resultBuffer_8_bits_trap <= 1'h0; + resultBuffer_8_bits_cfDone <= 1'h0; + resultBuffer_9_valid <= 1'h0; + resultBuffer_9_bits_trap <= 1'h0; + resultBuffer_9_bits_cfDone <= 1'h0; + resultBuffer_10_valid <= 1'h0; + resultBuffer_10_bits_trap <= 1'h0; + resultBuffer_10_bits_cfDone <= 1'h0; + resultBuffer_11_valid <= 1'h0; + resultBuffer_11_bits_trap <= 1'h0; + resultBuffer_11_bits_cfDone <= 1'h0; + resultBuffer_12_valid <= 1'h0; + resultBuffer_12_bits_trap <= 1'h0; + resultBuffer_12_bits_cfDone <= 1'h0; + resultBuffer_13_valid <= 1'h0; + resultBuffer_13_bits_trap <= 1'h0; + resultBuffer_13_bits_cfDone <= 1'h0; + resultBuffer_14_valid <= 1'h0; + resultBuffer_14_bits_trap <= 1'h0; + resultBuffer_14_bits_cfDone <= 1'h0; + resultBuffer_15_valid <= 1'h0; + resultBuffer_15_bits_trap <= 1'h0; + resultBuffer_15_bits_cfDone <= 1'h0; + deqReady_reg <= 4'h0; + instIsEcallMask_reg <= 8'h0; + io_trapPending_REG <= 1'h0; end else begin - if (io_in_valid & io_in_ready_0) begin - ipos <= ipos - 1'h1; - mem_0_pc <= io_in_bits_pc; - mem_0_addr <= io_in_bits_addr; - mem_0_adrx <= io_in_bits_adrx; - mem_0_data <= io_in_bits_data; - mem_0_index <= io_in_bits_index; - mem_0_size <= io_in_bits_size; - mem_0_fullsize <= io_in_bits_fullsize; - mem_0_write <= io_in_bits_write; - mem_0_sext <= io_in_bits_sext; - mem_0_iload <= io_in_bits_iload; - mem_0_fencei <= io_in_bits_fencei; - mem_0_flushat <= io_in_bits_flushat; - mem_0_flushall <= io_in_bits_flushall; - mem_0_sldst <= io_in_bits_sldst; - mem_0_vldst <= io_in_bits_vldst; - mem_0_fldst <= io_in_bits_fldst; - mem_0_regionType <= io_in_bits_regionType; - mem_0_mask <= io_in_bits_mask; - mem_0_last <= io_in_bits_last; + storeComplete_pipe_v <= io_storeComplete_valid; + faultRetire_pipe_v <= io_fault_valid; + if (hasFire) begin + regLastTarget <= + instFires_3 + ? (io_inst_3_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_3[31:1], 1'h0} + : io_inst_3_bits_inst[6:0] == 7'h6F | io_branch_3 + ? io_targets_3 + : io_inst_3_bits_addr + 32'h4) + : instFires_2 + ? (io_inst_2_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_2[31:1], 1'h0} + : io_inst_2_bits_inst[6:0] == 7'h6F | io_branch_2 + ? io_targets_2 + : _targetsList_T_9) + : instFires_1 + ? (io_inst_1_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_1[31:1], 1'h0} + : io_inst_1_bits_inst[6:0] == 7'h6F | io_branch_1 + ? io_targets_1 + : _targetsList_T_5) + : io_inst_0_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_0[31:1], 1'h0} + : io_inst_0_bits_inst[6:0] == 7'h6F | io_branch_0 + ? io_targets_0 + : _targetsList_T_1; + regLastAddr <= + instFires_3 + ? io_inst_3_bits_addr + : instFires_2 + ? io_inst_2_bits_addr + : instFires_1 ? io_inst_1_bits_addr : io_inst_0_bits_addr; + regLastIsBranch <= + instFires_3 + ? io_branch_3 + : instFires_2 ? io_branch_2 : instFires_1 ? io_branch_1 : io_branch_0; end - if (io_out_valid_0 & io_out_ready) - opos <= opos - 1'h1; + regAfterFlush <= trapRetired | ~hasFire & regAfterFlush; + resultBuffer_0_valid <= ~trapRetired & shifted[2]; + resultBuffer_0_bits_trap <= ~trapRetired & shifted[1]; + resultBuffer_0_bits_cfDone <= ~trapRetired & shifted[0]; + resultBuffer_1_valid <= ~trapRetired & shifted[5]; + resultBuffer_1_bits_trap <= ~trapRetired & shifted[4]; + resultBuffer_1_bits_cfDone <= ~trapRetired & shifted[3]; + resultBuffer_2_valid <= ~trapRetired & shifted[8]; + resultBuffer_2_bits_trap <= ~trapRetired & shifted[7]; + resultBuffer_2_bits_cfDone <= ~trapRetired & shifted[6]; + resultBuffer_3_valid <= ~trapRetired & shifted[11]; + resultBuffer_3_bits_trap <= ~trapRetired & shifted[10]; + resultBuffer_3_bits_cfDone <= ~trapRetired & shifted[9]; + resultBuffer_4_valid <= ~trapRetired & shifted[14]; + resultBuffer_4_bits_trap <= ~trapRetired & shifted[13]; + resultBuffer_4_bits_cfDone <= ~trapRetired & shifted[12]; + resultBuffer_5_valid <= ~trapRetired & shifted[17]; + resultBuffer_5_bits_trap <= ~trapRetired & shifted[16]; + resultBuffer_5_bits_cfDone <= ~trapRetired & shifted[15]; + resultBuffer_6_valid <= ~trapRetired & shifted[20]; + resultBuffer_6_bits_trap <= ~trapRetired & shifted[19]; + resultBuffer_6_bits_cfDone <= ~trapRetired & shifted[18]; + resultBuffer_7_valid <= ~trapRetired & shifted[23]; + resultBuffer_7_bits_trap <= ~trapRetired & shifted[22]; + resultBuffer_7_bits_cfDone <= ~trapRetired & shifted[21]; + resultBuffer_8_valid <= ~trapRetired & shifted[26]; + resultBuffer_8_bits_trap <= ~trapRetired & shifted[25]; + resultBuffer_8_bits_cfDone <= ~trapRetired & shifted[24]; + resultBuffer_9_valid <= ~trapRetired & shifted[29]; + resultBuffer_9_bits_trap <= ~trapRetired & shifted[28]; + resultBuffer_9_bits_cfDone <= ~trapRetired & shifted[27]; + resultBuffer_10_valid <= ~trapRetired & shifted[32]; + resultBuffer_10_bits_trap <= ~trapRetired & shifted[31]; + resultBuffer_10_bits_cfDone <= ~trapRetired & shifted[30]; + resultBuffer_11_valid <= ~trapRetired & shifted[35]; + resultBuffer_11_bits_trap <= ~trapRetired & shifted[34]; + resultBuffer_11_bits_cfDone <= ~trapRetired & shifted[33]; + resultBuffer_12_valid <= ~trapRetired & shifted[38]; + resultBuffer_12_bits_trap <= ~trapRetired & shifted[37]; + resultBuffer_12_bits_cfDone <= ~trapRetired & shifted[36]; + resultBuffer_13_valid <= ~trapRetired & shifted[41]; + resultBuffer_13_bits_trap <= ~trapRetired & shifted[40]; + resultBuffer_13_bits_cfDone <= ~trapRetired & shifted[39]; + resultBuffer_14_valid <= ~trapRetired & shifted[44]; + resultBuffer_14_bits_trap <= ~trapRetired & shifted[43]; + resultBuffer_14_bits_cfDone <= ~trapRetired & shifted[42]; + resultBuffer_15_valid <= ~trapRetired & shifted[47]; + resultBuffer_15_bits_trap <= ~trapRetired & shifted[46]; + resultBuffer_15_bits_cfDone <= ~trapRetired & shifted[45]; + deqReady_reg <= deqReady; + instIsEcallMask_reg <= + {_instBuffer_io_dataOut_7_isEcall, + _instBuffer_io_dataOut_6_isEcall, + _instBuffer_io_dataOut_5_isEcall, + _instBuffer_io_dataOut_4_isEcall, + _instBuffer_io_dataOut_3_isEcall, + _instBuffer_io_dataOut_2_isEcall, + _instBuffer_io_dataOut_1_isEcall, + _instBuffer_io_dataOut_0_isEcall}; + io_trapPending_REG <= + (currentDataDone & currentTrap | currentDataDone_1 & currentTrap_1 + | currentDataDone_2 & currentTrap_2 | currentDataDone_3 & currentTrap_3 + | currentDataDone_4 & currentTrap_4 | currentDataDone_5 & currentTrap_5 + | currentDataDone_6 & currentTrap_6 | currentDataDone_7 & currentTrap_7 + | currentDataDone_8 & currentTrap_8 | currentDataDone_9 & currentTrap_9 + | currentDataDone_10 & currentTrap_10 | currentDataDone_11 & currentTrap_11 + | currentDataDone_12 & currentTrap_12 | currentDataDone_13 & currentTrap_13 + | currentDataDone_14 & currentTrap_14 | currentDataDone_15 & currentTrap_15) + & ~trapRetired; end end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_storeComplete_valid) + storeComplete_pipe_b <= io_storeComplete_bits; + if (io_fault_valid) + faultRetire_pipe_b_mepc <= io_fault_bits_mepc; + end // always @(posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:5]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - ipos = _RANDOM[3'h0][0]; - opos = _RANDOM[3'h0][1]; - mem_0_pc = {_RANDOM[3'h0][31:3], _RANDOM[3'h1][2:0]}; - mem_0_addr = {_RANDOM[3'h1][31:3], _RANDOM[3'h2][2:0]}; - mem_0_adrx = {_RANDOM[3'h2][31:3], _RANDOM[3'h3][2:0]}; - mem_0_data = {_RANDOM[3'h3][31:3], _RANDOM[3'h4][2:0]}; - mem_0_index = _RANDOM[3'h4][7:3]; - mem_0_size = _RANDOM[3'h4][12:8]; - mem_0_fullsize = _RANDOM[3'h4][17:13]; - mem_0_write = _RANDOM[3'h4][18]; - mem_0_sext = _RANDOM[3'h4][19]; - mem_0_iload = _RANDOM[3'h4][20]; - mem_0_fencei = _RANDOM[3'h4][21]; - mem_0_flushat = _RANDOM[3'h4][22]; - mem_0_flushall = _RANDOM[3'h4][23]; - mem_0_sldst = _RANDOM[3'h4][24]; - mem_0_vldst = _RANDOM[3'h4][25]; - mem_0_fldst = _RANDOM[3'h4][26]; - mem_0_regionType = _RANDOM[3'h4][28:27]; - mem_0_mask = {_RANDOM[3'h4][31:29], _RANDOM[3'h5][12:0]}; - mem_0_last = _RANDOM[3'h5][13]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - ipos = 1'h0; - opos = 1'h0; - mem_0_pc = 32'h0; - mem_0_addr = 32'h0; - mem_0_adrx = 32'h0; - mem_0_data = 32'h0; - mem_0_index = 5'h0; - mem_0_size = 5'h0; - mem_0_fullsize = 5'h0; - mem_0_write = 1'h0; - mem_0_sext = 1'h0; - mem_0_iload = 1'h0; - mem_0_fencei = 1'h0; - mem_0_flushat = 1'h0; - mem_0_flushall = 1'h0; - mem_0_sldst = 1'h0; - mem_0_vldst = 1'h0; - mem_0_fldst = 1'h0; - mem_0_regionType = 2'h0; - mem_0_mask = 16'h0; - mem_0_last = 1'h0; + storeComplete_pipe_v = 1'h0; + faultRetire_pipe_v = 1'h0; + regLastTarget = 32'h0; + regLastAddr = 32'h0; + regLastIsBranch = 1'h0; + regAfterFlush = 1'h1; + resultBuffer_0_valid = 1'h0; + resultBuffer_0_bits_trap = 1'h0; + resultBuffer_0_bits_cfDone = 1'h0; + resultBuffer_1_valid = 1'h0; + resultBuffer_1_bits_trap = 1'h0; + resultBuffer_1_bits_cfDone = 1'h0; + resultBuffer_2_valid = 1'h0; + resultBuffer_2_bits_trap = 1'h0; + resultBuffer_2_bits_cfDone = 1'h0; + resultBuffer_3_valid = 1'h0; + resultBuffer_3_bits_trap = 1'h0; + resultBuffer_3_bits_cfDone = 1'h0; + resultBuffer_4_valid = 1'h0; + resultBuffer_4_bits_trap = 1'h0; + resultBuffer_4_bits_cfDone = 1'h0; + resultBuffer_5_valid = 1'h0; + resultBuffer_5_bits_trap = 1'h0; + resultBuffer_5_bits_cfDone = 1'h0; + resultBuffer_6_valid = 1'h0; + resultBuffer_6_bits_trap = 1'h0; + resultBuffer_6_bits_cfDone = 1'h0; + resultBuffer_7_valid = 1'h0; + resultBuffer_7_bits_trap = 1'h0; + resultBuffer_7_bits_cfDone = 1'h0; + resultBuffer_8_valid = 1'h0; + resultBuffer_8_bits_trap = 1'h0; + resultBuffer_8_bits_cfDone = 1'h0; + resultBuffer_9_valid = 1'h0; + resultBuffer_9_bits_trap = 1'h0; + resultBuffer_9_bits_cfDone = 1'h0; + resultBuffer_10_valid = 1'h0; + resultBuffer_10_bits_trap = 1'h0; + resultBuffer_10_bits_cfDone = 1'h0; + resultBuffer_11_valid = 1'h0; + resultBuffer_11_bits_trap = 1'h0; + resultBuffer_11_bits_cfDone = 1'h0; + resultBuffer_12_valid = 1'h0; + resultBuffer_12_bits_trap = 1'h0; + resultBuffer_12_bits_cfDone = 1'h0; + resultBuffer_13_valid = 1'h0; + resultBuffer_13_bits_trap = 1'h0; + resultBuffer_13_bits_cfDone = 1'h0; + resultBuffer_14_valid = 1'h0; + resultBuffer_14_bits_trap = 1'h0; + resultBuffer_14_bits_cfDone = 1'h0; + resultBuffer_15_valid = 1'h0; + resultBuffer_15_bits_trap = 1'h0; + resultBuffer_15_bits_cfDone = 1'h0; + deqReady_reg = 4'h0; + instIsEcallMask_reg = 8'h0; + io_trapPending_REG = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_in_ready = io_in_ready_0; - assign io_out_valid = io_out_valid_0; - assign io_out_bits_pc = mem_0_pc; - assign io_out_bits_addr = mem_0_addr; - assign io_out_bits_adrx = mem_0_adrx; - assign io_out_bits_data = mem_0_data; - assign io_out_bits_index = mem_0_index; - assign io_out_bits_size = mem_0_size; - assign io_out_bits_fullsize = mem_0_fullsize; - assign io_out_bits_write = mem_0_write; - assign io_out_bits_sext = mem_0_sext; - assign io_out_bits_iload = mem_0_iload; - assign io_out_bits_fencei = mem_0_fencei; - assign io_out_bits_flushat = mem_0_flushat; - assign io_out_bits_flushall = mem_0_flushall; - assign io_out_bits_sldst = mem_0_sldst; - assign io_out_bits_vldst = mem_0_vldst; - assign io_out_bits_fldst = mem_0_fldst; - assign io_out_bits_regionType = mem_0_regionType; - assign io_out_bits_mask = mem_0_mask; - assign io_out_bits_last = mem_0_last; + CircularBufferMulti_2 instBuffer ( + .clock (clock), + .reset (reset), + .io_enqValid + ({1'h0, + {1'h0, instsWithWriteFired} + + {3'h0, + (decodeFaultValid | noFire0Fault) + & _instBuffer_io_nSpace > {2'h0, instsWithWriteFired}}}), + .io_enqData_0_addr + (noFire0Fault ? io_fault_bits_mepc : io_inst_0_bits_addr), + .io_enqData_0_idx + (io_writeAddrFloat_valid + ? {2'h0, io_writeAddrFloat_addr} + 7'h20 + : noFire0Fault + ? (io_writeAddrScalar_0_valid & (|io_writeAddrScalar_0_addr) + ? _GEN + : {6'h3F, + ~(io_inst_0_bits_inst[6:0] == 7'h23 + | io_inst_0_bits_inst[6:0] == 7'h27 + & (io_inst_0_bits_inst[14:12] == 3'h1 + | io_inst_0_bits_inst[14:12] == 3'h2 + | io_inst_0_bits_inst[14:12] == 3'h3 + | io_inst_0_bits_inst[14:12] == 3'h4))}) + : io_writeAddrScalar_0_valid & (|io_writeAddrScalar_0_addr) + ? _GEN + : {6'h3F, + ~(io_inst_0_bits_inst[6:0] == 7'h23 + | io_inst_0_bits_inst[6:0] == 7'h27 + & (io_inst_0_bits_inst[14:12] == 3'h1 + | io_inst_0_bits_inst[14:12] == 3'h2 + | io_inst_0_bits_inst[14:12] == 3'h3 + | io_inst_0_bits_inst[14:12] == 3'h4))}), + .io_enqData_0_trap + (noFire0Fault | decodeFaultValid & io_fault_bits_mepc == io_inst_0_bits_addr), + .io_enqData_0_isControlFlow (io_jump_0 | io_branch_0), + .io_enqData_0_isBranch (io_branch_0), + .io_enqData_0_isVector (1'h0), + .io_enqData_0_resetsVstart (1'h0), + .io_enqData_0_linkOk + (noFire0Fault + ? io_fault_bits_mepc == regLastTarget | regLastIsBranch + & io_fault_bits_mepc == _lane0LinkOk_T_92 + : regAfterFlush | _lane0LinkOk_T_90 | regLastIsBranch + & io_inst_0_bits_addr == _lane0LinkOk_T_92), + .io_enqData_0_isEcall (io_inst_0_bits_inst == 32'h73), + .io_enqData_0_isMpause (io_inst_0_bits_inst == 32'h8000073), + .io_enqData_0_isTile (1'h0), + .io_enqData_1_addr (io_inst_1_bits_addr), + .io_enqData_1_idx + (io_writeAddrScalar_1_valid & (|io_writeAddrScalar_1_addr) + ? {2'h0, io_writeAddrScalar_1_addr} + : {6'h3F, + ~(io_inst_1_bits_inst[6:0] == 7'h23 | io_inst_1_bits_inst[6:0] == 7'h27 + & (io_inst_1_bits_inst[14:12] == 3'h1 | io_inst_1_bits_inst[14:12] == 3'h2 + | io_inst_1_bits_inst[14:12] == 3'h3 + | io_inst_1_bits_inst[14:12] == 3'h4))}), + .io_enqData_1_trap + (decodeFaultValid & io_fault_bits_mepc == io_inst_1_bits_addr), + .io_enqData_1_isControlFlow (io_jump_1 | io_branch_1), + .io_enqData_1_isBranch (io_branch_1), + .io_enqData_1_isVector (1'h0), + .io_enqData_1_resetsVstart (1'h0), + .io_enqData_1_linkOk + (io_inst_1_bits_addr == (io_inst_0_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_0[31:1], 1'h0} + : io_inst_0_bits_inst[6:0] == 7'h6F | io_branch_0 + ? io_targets_0 + : _targetsList_T_1) | io_branch_0 + & io_inst_1_bits_addr == _targetsList_T_1), + .io_enqData_1_isEcall (io_inst_1_bits_inst == 32'h73), + .io_enqData_1_isMpause (io_inst_1_bits_inst == 32'h8000073), + .io_enqData_1_isTile (1'h0), + .io_enqData_2_addr (io_inst_2_bits_addr), + .io_enqData_2_idx + (io_writeAddrScalar_2_valid & (|io_writeAddrScalar_2_addr) + ? {2'h0, io_writeAddrScalar_2_addr} + : {6'h3F, + ~(io_inst_2_bits_inst[6:0] == 7'h23 | io_inst_2_bits_inst[6:0] == 7'h27 + & (io_inst_2_bits_inst[14:12] == 3'h1 | io_inst_2_bits_inst[14:12] == 3'h2 + | io_inst_2_bits_inst[14:12] == 3'h3 + | io_inst_2_bits_inst[14:12] == 3'h4))}), + .io_enqData_2_trap + (decodeFaultValid & io_fault_bits_mepc == io_inst_2_bits_addr), + .io_enqData_2_isControlFlow (io_jump_2 | io_branch_2), + .io_enqData_2_isBranch (io_branch_2), + .io_enqData_2_isVector (1'h0), + .io_enqData_2_resetsVstart (1'h0), + .io_enqData_2_linkOk + (io_inst_2_bits_addr == (io_inst_1_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_1[31:1], 1'h0} + : io_inst_1_bits_inst[6:0] == 7'h6F | io_branch_1 + ? io_targets_1 + : _targetsList_T_5) | io_branch_1 + & io_inst_2_bits_addr == _targetsList_T_5), + .io_enqData_2_isEcall (io_inst_2_bits_inst == 32'h73), + .io_enqData_2_isMpause (io_inst_2_bits_inst == 32'h8000073), + .io_enqData_2_isTile (1'h0), + .io_enqData_3_addr (io_inst_3_bits_addr), + .io_enqData_3_idx + (io_writeAddrScalar_3_valid & (|io_writeAddrScalar_3_addr) + ? {2'h0, io_writeAddrScalar_3_addr} + : {6'h3F, + ~(io_inst_3_bits_inst[6:0] == 7'h23 | io_inst_3_bits_inst[6:0] == 7'h27 + & (io_inst_3_bits_inst[14:12] == 3'h1 | io_inst_3_bits_inst[14:12] == 3'h2 + | io_inst_3_bits_inst[14:12] == 3'h3 + | io_inst_3_bits_inst[14:12] == 3'h4))}), + .io_enqData_3_trap + (decodeFaultValid & io_fault_bits_mepc == io_inst_3_bits_addr), + .io_enqData_3_isControlFlow (io_jump_3 | io_branch_3), + .io_enqData_3_isBranch (io_branch_3), + .io_enqData_3_isVector (1'h0), + .io_enqData_3_resetsVstart (1'h0), + .io_enqData_3_linkOk + (io_inst_3_bits_addr == (io_inst_2_bits_inst[6:0] == 7'h67 + ? {io_jalrTargets_2[31:1], 1'h0} + : io_inst_2_bits_inst[6:0] == 7'h6F | io_branch_2 + ? io_targets_2 + : _targetsList_T_9) | io_branch_2 + & io_inst_3_bits_addr == _targetsList_T_9), + .io_enqData_3_isEcall (io_inst_3_bits_inst == 32'h73), + .io_enqData_3_isMpause (io_inst_3_bits_inst == 32'h8000073), + .io_enqData_3_isTile (1'h0), + .io_enqData_4_addr (32'h0), + .io_enqData_4_idx (7'h0), + .io_enqData_4_trap (1'h0), + .io_enqData_4_isControlFlow (1'h0), + .io_enqData_4_isBranch (1'h0), + .io_enqData_4_isVector (1'h0), + .io_enqData_4_resetsVstart (1'h0), + .io_enqData_4_linkOk (1'h0), + .io_enqData_4_isEcall (1'h0), + .io_enqData_4_isMpause (1'h0), + .io_enqData_4_isTile (1'h0), + .io_enqData_5_addr (32'h0), + .io_enqData_5_idx (7'h0), + .io_enqData_5_trap (1'h0), + .io_enqData_5_isControlFlow (1'h0), + .io_enqData_5_isBranch (1'h0), + .io_enqData_5_isVector (1'h0), + .io_enqData_5_resetsVstart (1'h0), + .io_enqData_5_linkOk (1'h0), + .io_enqData_5_isEcall (1'h0), + .io_enqData_5_isMpause (1'h0), + .io_enqData_5_isTile (1'h0), + .io_enqData_6_addr (32'h0), + .io_enqData_6_idx (7'h0), + .io_enqData_6_trap (1'h0), + .io_enqData_6_isControlFlow (1'h0), + .io_enqData_6_isBranch (1'h0), + .io_enqData_6_isVector (1'h0), + .io_enqData_6_resetsVstart (1'h0), + .io_enqData_6_linkOk (1'h0), + .io_enqData_6_isEcall (1'h0), + .io_enqData_6_isMpause (1'h0), + .io_enqData_6_isTile (1'h0), + .io_enqData_7_addr (32'h0), + .io_enqData_7_idx (7'h0), + .io_enqData_7_trap (1'h0), + .io_enqData_7_isControlFlow (1'h0), + .io_enqData_7_isBranch (1'h0), + .io_enqData_7_isVector (1'h0), + .io_enqData_7_resetsVstart (1'h0), + .io_enqData_7_linkOk (1'h0), + .io_enqData_7_isEcall (1'h0), + .io_enqData_7_isMpause (1'h0), + .io_enqData_7_isTile (1'h0), + .io_enqData_8_addr (32'h0), + .io_enqData_8_idx (7'h0), + .io_enqData_8_trap (1'h0), + .io_enqData_8_isControlFlow (1'h0), + .io_enqData_8_isBranch (1'h0), + .io_enqData_8_isVector (1'h0), + .io_enqData_8_resetsVstart (1'h0), + .io_enqData_8_linkOk (1'h0), + .io_enqData_8_isEcall (1'h0), + .io_enqData_8_isMpause (1'h0), + .io_enqData_8_isTile (1'h0), + .io_enqData_9_addr (32'h0), + .io_enqData_9_idx (7'h0), + .io_enqData_9_trap (1'h0), + .io_enqData_9_isControlFlow (1'h0), + .io_enqData_9_isBranch (1'h0), + .io_enqData_9_isVector (1'h0), + .io_enqData_9_resetsVstart (1'h0), + .io_enqData_9_linkOk (1'h0), + .io_enqData_9_isEcall (1'h0), + .io_enqData_9_isMpause (1'h0), + .io_enqData_9_isTile (1'h0), + .io_enqData_10_addr (32'h0), + .io_enqData_10_idx (7'h0), + .io_enqData_10_trap (1'h0), + .io_enqData_10_isControlFlow (1'h0), + .io_enqData_10_isBranch (1'h0), + .io_enqData_10_isVector (1'h0), + .io_enqData_10_resetsVstart (1'h0), + .io_enqData_10_linkOk (1'h0), + .io_enqData_10_isEcall (1'h0), + .io_enqData_10_isMpause (1'h0), + .io_enqData_10_isTile (1'h0), + .io_enqData_11_addr (32'h0), + .io_enqData_11_idx (7'h0), + .io_enqData_11_trap (1'h0), + .io_enqData_11_isControlFlow (1'h0), + .io_enqData_11_isBranch (1'h0), + .io_enqData_11_isVector (1'h0), + .io_enqData_11_resetsVstart (1'h0), + .io_enqData_11_linkOk (1'h0), + .io_enqData_11_isEcall (1'h0), + .io_enqData_11_isMpause (1'h0), + .io_enqData_11_isTile (1'h0), + .io_enqData_12_addr (32'h0), + .io_enqData_12_idx (7'h0), + .io_enqData_12_trap (1'h0), + .io_enqData_12_isControlFlow (1'h0), + .io_enqData_12_isBranch (1'h0), + .io_enqData_12_isVector (1'h0), + .io_enqData_12_resetsVstart (1'h0), + .io_enqData_12_linkOk (1'h0), + .io_enqData_12_isEcall (1'h0), + .io_enqData_12_isMpause (1'h0), + .io_enqData_12_isTile (1'h0), + .io_enqData_13_addr (32'h0), + .io_enqData_13_idx (7'h0), + .io_enqData_13_trap (1'h0), + .io_enqData_13_isControlFlow (1'h0), + .io_enqData_13_isBranch (1'h0), + .io_enqData_13_isVector (1'h0), + .io_enqData_13_resetsVstart (1'h0), + .io_enqData_13_linkOk (1'h0), + .io_enqData_13_isEcall (1'h0), + .io_enqData_13_isMpause (1'h0), + .io_enqData_13_isTile (1'h0), + .io_enqData_14_addr (32'h0), + .io_enqData_14_idx (7'h0), + .io_enqData_14_trap (1'h0), + .io_enqData_14_isControlFlow (1'h0), + .io_enqData_14_isBranch (1'h0), + .io_enqData_14_isVector (1'h0), + .io_enqData_14_resetsVstart (1'h0), + .io_enqData_14_linkOk (1'h0), + .io_enqData_14_isEcall (1'h0), + .io_enqData_14_isMpause (1'h0), + .io_enqData_14_isTile (1'h0), + .io_enqData_15_addr (32'h0), + .io_enqData_15_idx (7'h0), + .io_enqData_15_trap (1'h0), + .io_enqData_15_isControlFlow (1'h0), + .io_enqData_15_isBranch (1'h0), + .io_enqData_15_isVector (1'h0), + .io_enqData_15_resetsVstart (1'h0), + .io_enqData_15_linkOk (1'h0), + .io_enqData_15_isEcall (1'h0), + .io_enqData_15_isMpause (1'h0), + .io_enqData_15_isTile (1'h0), + .io_nEnqueued (_instBuffer_io_nEnqueued), + .io_nSpace (_instBuffer_io_nSpace), + .io_dataOut_0_addr (_instBuffer_io_dataOut_0_addr), + .io_dataOut_0_idx (_instBuffer_io_dataOut_0_idx), + .io_dataOut_0_trap (_instBuffer_io_dataOut_0_trap), + .io_dataOut_0_isControlFlow (_instBuffer_io_dataOut_0_isControlFlow), + .io_dataOut_0_isBranch (_instBuffer_io_dataOut_0_isBranch), + .io_dataOut_0_isVector (_instBuffer_io_dataOut_0_isVector), + .io_dataOut_0_resetsVstart (/* unused */), + .io_dataOut_0_linkOk (/* unused */), + .io_dataOut_0_isEcall (_instBuffer_io_dataOut_0_isEcall), + .io_dataOut_0_isMpause (_instBuffer_io_dataOut_0_isMpause), + .io_dataOut_0_isTile (_instBuffer_io_dataOut_0_isTile), + .io_dataOut_1_addr (_instBuffer_io_dataOut_1_addr), + .io_dataOut_1_idx (_instBuffer_io_dataOut_1_idx), + .io_dataOut_1_trap (_instBuffer_io_dataOut_1_trap), + .io_dataOut_1_isControlFlow (_instBuffer_io_dataOut_1_isControlFlow), + .io_dataOut_1_isBranch (_instBuffer_io_dataOut_1_isBranch), + .io_dataOut_1_isVector (_instBuffer_io_dataOut_1_isVector), + .io_dataOut_1_resetsVstart (/* unused */), + .io_dataOut_1_linkOk (_instBuffer_io_dataOut_1_linkOk), + .io_dataOut_1_isEcall (_instBuffer_io_dataOut_1_isEcall), + .io_dataOut_1_isMpause (_instBuffer_io_dataOut_1_isMpause), + .io_dataOut_1_isTile (_instBuffer_io_dataOut_1_isTile), + .io_dataOut_2_addr (_instBuffer_io_dataOut_2_addr), + .io_dataOut_2_idx (_instBuffer_io_dataOut_2_idx), + .io_dataOut_2_trap (_instBuffer_io_dataOut_2_trap), + .io_dataOut_2_isControlFlow (_instBuffer_io_dataOut_2_isControlFlow), + .io_dataOut_2_isBranch (_instBuffer_io_dataOut_2_isBranch), + .io_dataOut_2_isVector (_instBuffer_io_dataOut_2_isVector), + .io_dataOut_2_resetsVstart (/* unused */), + .io_dataOut_2_linkOk (_instBuffer_io_dataOut_2_linkOk), + .io_dataOut_2_isEcall (_instBuffer_io_dataOut_2_isEcall), + .io_dataOut_2_isMpause (_instBuffer_io_dataOut_2_isMpause), + .io_dataOut_2_isTile (_instBuffer_io_dataOut_2_isTile), + .io_dataOut_3_addr (_instBuffer_io_dataOut_3_addr), + .io_dataOut_3_idx (_instBuffer_io_dataOut_3_idx), + .io_dataOut_3_trap (_instBuffer_io_dataOut_3_trap), + .io_dataOut_3_isControlFlow (_instBuffer_io_dataOut_3_isControlFlow), + .io_dataOut_3_isBranch (_instBuffer_io_dataOut_3_isBranch), + .io_dataOut_3_isVector (_instBuffer_io_dataOut_3_isVector), + .io_dataOut_3_resetsVstart (/* unused */), + .io_dataOut_3_linkOk (_instBuffer_io_dataOut_3_linkOk), + .io_dataOut_3_isEcall (_instBuffer_io_dataOut_3_isEcall), + .io_dataOut_3_isMpause (_instBuffer_io_dataOut_3_isMpause), + .io_dataOut_3_isTile (_instBuffer_io_dataOut_3_isTile), + .io_dataOut_4_addr (_instBuffer_io_dataOut_4_addr), + .io_dataOut_4_idx (_instBuffer_io_dataOut_4_idx), + .io_dataOut_4_trap (_instBuffer_io_dataOut_4_trap), + .io_dataOut_4_isControlFlow (_instBuffer_io_dataOut_4_isControlFlow), + .io_dataOut_4_isBranch (_instBuffer_io_dataOut_4_isBranch), + .io_dataOut_4_isVector (_instBuffer_io_dataOut_4_isVector), + .io_dataOut_4_resetsVstart (/* unused */), + .io_dataOut_4_linkOk (_instBuffer_io_dataOut_4_linkOk), + .io_dataOut_4_isEcall (_instBuffer_io_dataOut_4_isEcall), + .io_dataOut_4_isMpause (_instBuffer_io_dataOut_4_isMpause), + .io_dataOut_4_isTile (_instBuffer_io_dataOut_4_isTile), + .io_dataOut_5_addr (_instBuffer_io_dataOut_5_addr), + .io_dataOut_5_idx (_instBuffer_io_dataOut_5_idx), + .io_dataOut_5_trap (_instBuffer_io_dataOut_5_trap), + .io_dataOut_5_isControlFlow (_instBuffer_io_dataOut_5_isControlFlow), + .io_dataOut_5_isBranch (_instBuffer_io_dataOut_5_isBranch), + .io_dataOut_5_isVector (_instBuffer_io_dataOut_5_isVector), + .io_dataOut_5_resetsVstart (/* unused */), + .io_dataOut_5_linkOk (_instBuffer_io_dataOut_5_linkOk), + .io_dataOut_5_isEcall (_instBuffer_io_dataOut_5_isEcall), + .io_dataOut_5_isMpause (_instBuffer_io_dataOut_5_isMpause), + .io_dataOut_5_isTile (_instBuffer_io_dataOut_5_isTile), + .io_dataOut_6_addr (_instBuffer_io_dataOut_6_addr), + .io_dataOut_6_idx (_instBuffer_io_dataOut_6_idx), + .io_dataOut_6_trap (_instBuffer_io_dataOut_6_trap), + .io_dataOut_6_isControlFlow (_instBuffer_io_dataOut_6_isControlFlow), + .io_dataOut_6_isBranch (_instBuffer_io_dataOut_6_isBranch), + .io_dataOut_6_isVector (_instBuffer_io_dataOut_6_isVector), + .io_dataOut_6_resetsVstart (/* unused */), + .io_dataOut_6_linkOk (_instBuffer_io_dataOut_6_linkOk), + .io_dataOut_6_isEcall (_instBuffer_io_dataOut_6_isEcall), + .io_dataOut_6_isMpause (_instBuffer_io_dataOut_6_isMpause), + .io_dataOut_6_isTile (_instBuffer_io_dataOut_6_isTile), + .io_dataOut_7_addr (_instBuffer_io_dataOut_7_addr), + .io_dataOut_7_idx (_instBuffer_io_dataOut_7_idx), + .io_dataOut_7_trap (_instBuffer_io_dataOut_7_trap), + .io_dataOut_7_isControlFlow (_instBuffer_io_dataOut_7_isControlFlow), + .io_dataOut_7_isBranch (_instBuffer_io_dataOut_7_isBranch), + .io_dataOut_7_isVector (_instBuffer_io_dataOut_7_isVector), + .io_dataOut_7_resetsVstart (/* unused */), + .io_dataOut_7_linkOk (_instBuffer_io_dataOut_7_linkOk), + .io_dataOut_7_isEcall (_instBuffer_io_dataOut_7_isEcall), + .io_dataOut_7_isMpause (_instBuffer_io_dataOut_7_isMpause), + .io_dataOut_7_isTile (_instBuffer_io_dataOut_7_isTile), + .io_dataOut_8_addr (_instBuffer_io_dataOut_8_addr), + .io_dataOut_8_idx (_instBuffer_io_dataOut_8_idx), + .io_dataOut_8_trap (_instBuffer_io_dataOut_8_trap), + .io_dataOut_8_isControlFlow (_instBuffer_io_dataOut_8_isControlFlow), + .io_dataOut_8_isBranch (_instBuffer_io_dataOut_8_isBranch), + .io_dataOut_8_isVector (_instBuffer_io_dataOut_8_isVector), + .io_dataOut_8_resetsVstart (/* unused */), + .io_dataOut_8_linkOk (_instBuffer_io_dataOut_8_linkOk), + .io_dataOut_8_isEcall (/* unused */), + .io_dataOut_8_isMpause (_instBuffer_io_dataOut_8_isMpause), + .io_dataOut_8_isTile (_instBuffer_io_dataOut_8_isTile), + .io_dataOut_9_addr (_instBuffer_io_dataOut_9_addr), + .io_dataOut_9_idx (_instBuffer_io_dataOut_9_idx), + .io_dataOut_9_trap (_instBuffer_io_dataOut_9_trap), + .io_dataOut_9_isControlFlow (_instBuffer_io_dataOut_9_isControlFlow), + .io_dataOut_9_isBranch (_instBuffer_io_dataOut_9_isBranch), + .io_dataOut_9_isVector (_instBuffer_io_dataOut_9_isVector), + .io_dataOut_9_resetsVstart (/* unused */), + .io_dataOut_9_linkOk (_instBuffer_io_dataOut_9_linkOk), + .io_dataOut_9_isEcall (/* unused */), + .io_dataOut_9_isMpause (_instBuffer_io_dataOut_9_isMpause), + .io_dataOut_9_isTile (_instBuffer_io_dataOut_9_isTile), + .io_dataOut_10_addr (_instBuffer_io_dataOut_10_addr), + .io_dataOut_10_idx (_instBuffer_io_dataOut_10_idx), + .io_dataOut_10_trap (_instBuffer_io_dataOut_10_trap), + .io_dataOut_10_isControlFlow (_instBuffer_io_dataOut_10_isControlFlow), + .io_dataOut_10_isBranch (_instBuffer_io_dataOut_10_isBranch), + .io_dataOut_10_isVector (_instBuffer_io_dataOut_10_isVector), + .io_dataOut_10_resetsVstart (/* unused */), + .io_dataOut_10_linkOk (_instBuffer_io_dataOut_10_linkOk), + .io_dataOut_10_isEcall (/* unused */), + .io_dataOut_10_isMpause (_instBuffer_io_dataOut_10_isMpause), + .io_dataOut_10_isTile (_instBuffer_io_dataOut_10_isTile), + .io_dataOut_11_addr (_instBuffer_io_dataOut_11_addr), + .io_dataOut_11_idx (_instBuffer_io_dataOut_11_idx), + .io_dataOut_11_trap (_instBuffer_io_dataOut_11_trap), + .io_dataOut_11_isControlFlow (_instBuffer_io_dataOut_11_isControlFlow), + .io_dataOut_11_isBranch (_instBuffer_io_dataOut_11_isBranch), + .io_dataOut_11_isVector (_instBuffer_io_dataOut_11_isVector), + .io_dataOut_11_resetsVstart (/* unused */), + .io_dataOut_11_linkOk (_instBuffer_io_dataOut_11_linkOk), + .io_dataOut_11_isEcall (/* unused */), + .io_dataOut_11_isMpause (_instBuffer_io_dataOut_11_isMpause), + .io_dataOut_11_isTile (_instBuffer_io_dataOut_11_isTile), + .io_dataOut_12_addr (_instBuffer_io_dataOut_12_addr), + .io_dataOut_12_idx (_instBuffer_io_dataOut_12_idx), + .io_dataOut_12_trap (_instBuffer_io_dataOut_12_trap), + .io_dataOut_12_isControlFlow (_instBuffer_io_dataOut_12_isControlFlow), + .io_dataOut_12_isBranch (_instBuffer_io_dataOut_12_isBranch), + .io_dataOut_12_isVector (_instBuffer_io_dataOut_12_isVector), + .io_dataOut_12_resetsVstart (/* unused */), + .io_dataOut_12_linkOk (_instBuffer_io_dataOut_12_linkOk), + .io_dataOut_12_isEcall (/* unused */), + .io_dataOut_12_isMpause (_instBuffer_io_dataOut_12_isMpause), + .io_dataOut_12_isTile (_instBuffer_io_dataOut_12_isTile), + .io_dataOut_13_addr (_instBuffer_io_dataOut_13_addr), + .io_dataOut_13_idx (_instBuffer_io_dataOut_13_idx), + .io_dataOut_13_trap (_instBuffer_io_dataOut_13_trap), + .io_dataOut_13_isControlFlow (_instBuffer_io_dataOut_13_isControlFlow), + .io_dataOut_13_isBranch (_instBuffer_io_dataOut_13_isBranch), + .io_dataOut_13_isVector (_instBuffer_io_dataOut_13_isVector), + .io_dataOut_13_resetsVstart (/* unused */), + .io_dataOut_13_linkOk (_instBuffer_io_dataOut_13_linkOk), + .io_dataOut_13_isEcall (/* unused */), + .io_dataOut_13_isMpause (_instBuffer_io_dataOut_13_isMpause), + .io_dataOut_13_isTile (_instBuffer_io_dataOut_13_isTile), + .io_dataOut_14_addr (_instBuffer_io_dataOut_14_addr), + .io_dataOut_14_idx (_instBuffer_io_dataOut_14_idx), + .io_dataOut_14_trap (_instBuffer_io_dataOut_14_trap), + .io_dataOut_14_isControlFlow (_instBuffer_io_dataOut_14_isControlFlow), + .io_dataOut_14_isBranch (_instBuffer_io_dataOut_14_isBranch), + .io_dataOut_14_isVector (_instBuffer_io_dataOut_14_isVector), + .io_dataOut_14_resetsVstart (/* unused */), + .io_dataOut_14_linkOk (_instBuffer_io_dataOut_14_linkOk), + .io_dataOut_14_isEcall (/* unused */), + .io_dataOut_14_isMpause (_instBuffer_io_dataOut_14_isMpause), + .io_dataOut_14_isTile (_instBuffer_io_dataOut_14_isTile), + .io_dataOut_15_addr (_instBuffer_io_dataOut_15_addr), + .io_dataOut_15_idx (_instBuffer_io_dataOut_15_idx), + .io_dataOut_15_trap (_instBuffer_io_dataOut_15_trap), + .io_dataOut_15_isControlFlow (_instBuffer_io_dataOut_15_isControlFlow), + .io_dataOut_15_isBranch (_instBuffer_io_dataOut_15_isBranch), + .io_dataOut_15_isVector (_instBuffer_io_dataOut_15_isVector), + .io_dataOut_15_resetsVstart (/* unused */), + .io_dataOut_15_linkOk (_instBuffer_io_dataOut_15_linkOk), + .io_dataOut_15_isEcall (/* unused */), + .io_dataOut_15_isMpause (_instBuffer_io_dataOut_15_isMpause), + .io_dataOut_15_isTile (_instBuffer_io_dataOut_15_isTile), + .io_deqReady ({1'h0, deqReady}), + .io_flush (trapRetired) + ); + assign io_nSpace = _instBuffer_io_nSpace; + assign io_nRetired = + deqReady_reg + - ({1'h0, + {1'h0, + {1'h0, (|deqReady_reg) & instIsEcallMask_reg[0]} + + {1'h0, (|(deqReady_reg[3:1])) & instIsEcallMask_reg[1]}} + + {1'h0, + {1'h0, deqReady_reg > 4'h2 & instIsEcallMask_reg[2]} + + {1'h0, (|(deqReady_reg[3:2])) & instIsEcallMask_reg[3]}}} + + {1'h0, + {1'h0, + {1'h0, deqReady_reg > 4'h4 & instIsEcallMask_reg[4]} + + {1'h0, deqReady_reg > 4'h5 & instIsEcallMask_reg[5]}} + + {1'h0, + {1'h0, deqReady_reg > 4'h6 & instIsEcallMask_reg[6]} + + {1'h0, deqReady_reg[3] & instIsEcallMask_reg[7]}}}); + assign io_empty = _instBuffer_io_nEnqueued == 5'h0; + assign io_trapPending = io_trapPending_REG; + assign io_trapRetired = trapRetired; endmodule -module FifoX( +module Alu( input clock, reset, - io_in_valid, - io_in_bits_0_valid, - input [31:0] io_in_bits_0_bits_pc, - io_in_bits_0_bits_addr, - io_in_bits_0_bits_adrx, - io_in_bits_0_bits_data, - input [4:0] io_in_bits_0_bits_index, - io_in_bits_0_bits_size, - io_in_bits_0_bits_fullsize, - input io_in_bits_0_bits_write, - io_in_bits_0_bits_sext, - io_in_bits_0_bits_iload, - io_in_bits_0_bits_fencei, - io_in_bits_0_bits_flushat, - io_in_bits_0_bits_flushall, - io_in_bits_0_bits_sldst, - io_in_bits_0_bits_vldst, - io_in_bits_0_bits_fldst, - input [1:0] io_in_bits_0_bits_regionType, - input [15:0] io_in_bits_0_bits_mask, - input io_in_bits_1_valid, - input [31:0] io_in_bits_1_bits_pc, - io_in_bits_1_bits_addr, - io_in_bits_1_bits_adrx, - io_in_bits_1_bits_data, - input [4:0] io_in_bits_1_bits_index, - io_in_bits_1_bits_size, - io_in_bits_1_bits_fullsize, - input io_in_bits_1_bits_write, - io_in_bits_1_bits_sext, - io_in_bits_1_bits_iload, - io_in_bits_1_bits_fencei, - io_in_bits_1_bits_flushat, - io_in_bits_1_bits_flushall, - io_in_bits_1_bits_sldst, - io_in_bits_1_bits_vldst, - io_in_bits_1_bits_fldst, - input [1:0] io_in_bits_1_bits_regionType, - input [15:0] io_in_bits_1_bits_mask, - input io_in_bits_2_valid, - input [31:0] io_in_bits_2_bits_pc, - io_in_bits_2_bits_addr, - io_in_bits_2_bits_adrx, - io_in_bits_2_bits_data, - input [4:0] io_in_bits_2_bits_index, - io_in_bits_2_bits_size, - io_in_bits_2_bits_fullsize, - input io_in_bits_2_bits_write, - io_in_bits_2_bits_sext, - io_in_bits_2_bits_iload, - io_in_bits_2_bits_fencei, - io_in_bits_2_bits_flushat, - io_in_bits_2_bits_flushall, - io_in_bits_2_bits_sldst, - io_in_bits_2_bits_vldst, - io_in_bits_2_bits_fldst, - input [1:0] io_in_bits_2_bits_regionType, - input [15:0] io_in_bits_2_bits_mask, - input io_in_bits_3_valid, - input [31:0] io_in_bits_3_bits_pc, - io_in_bits_3_bits_addr, - io_in_bits_3_bits_adrx, - io_in_bits_3_bits_data, - input [4:0] io_in_bits_3_bits_index, - io_in_bits_3_bits_size, - io_in_bits_3_bits_fullsize, - input io_in_bits_3_bits_write, - io_in_bits_3_bits_sext, - io_in_bits_3_bits_iload, - io_in_bits_3_bits_fencei, - io_in_bits_3_bits_flushat, - io_in_bits_3_bits_flushall, - io_in_bits_3_bits_sldst, - io_in_bits_3_bits_vldst, - io_in_bits_3_bits_fldst, - input [1:0] io_in_bits_3_bits_regionType, - input [15:0] io_in_bits_3_bits_mask, - input io_in_bits_4_valid, - input [31:0] io_in_bits_4_bits_pc, - io_in_bits_4_bits_addr, - io_in_bits_4_bits_adrx, - io_in_bits_4_bits_data, - input [4:0] io_in_bits_4_bits_index, - io_in_bits_4_bits_size, - io_in_bits_4_bits_fullsize, - input io_in_bits_4_bits_write, - io_in_bits_4_bits_sext, - io_in_bits_4_bits_iload, - io_in_bits_4_bits_fencei, - io_in_bits_4_bits_flushat, - io_in_bits_4_bits_flushall, - io_in_bits_4_bits_sldst, - io_in_bits_4_bits_vldst, - io_in_bits_4_bits_fldst, - input [1:0] io_in_bits_4_bits_regionType, - input [15:0] io_in_bits_4_bits_mask, - input io_in_bits_5_valid, - input [31:0] io_in_bits_5_bits_pc, - io_in_bits_5_bits_addr, - io_in_bits_5_bits_adrx, - io_in_bits_5_bits_data, - input [4:0] io_in_bits_5_bits_index, - io_in_bits_5_bits_size, - io_in_bits_5_bits_fullsize, - input io_in_bits_5_bits_write, - io_in_bits_5_bits_sext, - io_in_bits_5_bits_iload, - io_in_bits_5_bits_fencei, - io_in_bits_5_bits_flushat, - io_in_bits_5_bits_flushall, - io_in_bits_5_bits_sldst, - io_in_bits_5_bits_vldst, - io_in_bits_5_bits_fldst, - input [1:0] io_in_bits_5_bits_regionType, - input [15:0] io_in_bits_5_bits_mask, - input io_in_bits_6_valid, - input [31:0] io_in_bits_6_bits_pc, - io_in_bits_6_bits_addr, - io_in_bits_6_bits_adrx, - io_in_bits_6_bits_data, - input [4:0] io_in_bits_6_bits_index, - io_in_bits_6_bits_size, - io_in_bits_6_bits_fullsize, - input io_in_bits_6_bits_write, - io_in_bits_6_bits_sext, - io_in_bits_6_bits_iload, - io_in_bits_6_bits_fencei, - io_in_bits_6_bits_flushat, - io_in_bits_6_bits_flushall, - io_in_bits_6_bits_sldst, - io_in_bits_6_bits_vldst, - io_in_bits_6_bits_fldst, - input [1:0] io_in_bits_6_bits_regionType, - input [15:0] io_in_bits_6_bits_mask, - input io_in_bits_7_valid, - input [31:0] io_in_bits_7_bits_pc, - io_in_bits_7_bits_addr, - io_in_bits_7_bits_adrx, - io_in_bits_7_bits_data, - input [4:0] io_in_bits_7_bits_index, - io_in_bits_7_bits_size, - io_in_bits_7_bits_fullsize, - input io_in_bits_7_bits_write, - io_in_bits_7_bits_sext, - io_in_bits_7_bits_iload, - io_in_bits_7_bits_fencei, - io_in_bits_7_bits_flushat, - io_in_bits_7_bits_flushall, - io_in_bits_7_bits_sldst, - io_in_bits_7_bits_vldst, - io_in_bits_7_bits_fldst, - input [1:0] io_in_bits_7_bits_regionType, - input [15:0] io_in_bits_7_bits_mask, - input io_out_ready, - output io_out_valid, - output [31:0] io_out_bits_pc, - io_out_bits_addr, - io_out_bits_adrx, - io_out_bits_data, - output [4:0] io_out_bits_index, - io_out_bits_size, - io_out_bits_fullsize, - output io_out_bits_write, - io_out_bits_sext, - io_out_bits_iload, - io_out_bits_fencei, - io_out_bits_flushat, - io_out_bits_flushall, - io_out_bits_sldst, - io_out_bits_vldst, - io_out_bits_fldst, - output [1:0] io_out_bits_regionType, - output [15:0] io_out_bits_mask, - output io_out_bits_last, - output [3:0] io_count + io_req_valid, + input [4:0] io_req_bits_addr, + input [5:0] io_req_bits_op, + input [31:0] io_rs1_data, + io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data ); - wire io_in_ready; - wire _mslice_io_in_ready; - wire _mslice_io_out_valid; - wire [7:0] _GEN = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - reg [31:0] mem_0_pc; - reg [31:0] mem_0_addr; - reg [31:0] mem_0_adrx; - reg [31:0] mem_0_data; - reg [4:0] mem_0_index; - reg [4:0] mem_0_size; - reg [4:0] mem_0_fullsize; - reg mem_0_write; - reg mem_0_sext; - reg mem_0_iload; - reg mem_0_fencei; - reg mem_0_flushat; - reg mem_0_flushall; - reg mem_0_sldst; - reg mem_0_vldst; - reg mem_0_fldst; - reg [1:0] mem_0_regionType; - reg [15:0] mem_0_mask; - reg mem_0_last; - reg [31:0] mem_1_pc; - reg [31:0] mem_1_addr; - reg [31:0] mem_1_adrx; - reg [31:0] mem_1_data; - reg [4:0] mem_1_index; - reg [4:0] mem_1_size; - reg [4:0] mem_1_fullsize; - reg mem_1_write; - reg mem_1_sext; - reg mem_1_iload; - reg mem_1_fencei; - reg mem_1_flushat; - reg mem_1_flushall; - reg mem_1_sldst; - reg mem_1_vldst; - reg mem_1_fldst; - reg [1:0] mem_1_regionType; - reg [15:0] mem_1_mask; - reg mem_1_last; - reg [31:0] mem_2_pc; - reg [31:0] mem_2_addr; - reg [31:0] mem_2_adrx; - reg [31:0] mem_2_data; - reg [4:0] mem_2_index; - reg [4:0] mem_2_size; - reg [4:0] mem_2_fullsize; - reg mem_2_write; - reg mem_2_sext; - reg mem_2_iload; - reg mem_2_fencei; - reg mem_2_flushat; - reg mem_2_flushall; - reg mem_2_sldst; - reg mem_2_vldst; - reg mem_2_fldst; - reg [1:0] mem_2_regionType; - reg [15:0] mem_2_mask; - reg mem_2_last; - reg [31:0] mem_3_pc; - reg [31:0] mem_3_addr; - reg [31:0] mem_3_adrx; - reg [31:0] mem_3_data; - reg [4:0] mem_3_index; - reg [4:0] mem_3_size; - reg [4:0] mem_3_fullsize; - reg mem_3_write; - reg mem_3_sext; - reg mem_3_iload; - reg mem_3_fencei; - reg mem_3_flushat; - reg mem_3_flushall; - reg mem_3_sldst; - reg mem_3_vldst; - reg mem_3_fldst; - reg [1:0] mem_3_regionType; - reg [15:0] mem_3_mask; - reg mem_3_last; - reg [31:0] mem_4_pc; - reg [31:0] mem_4_addr; - reg [31:0] mem_4_adrx; - reg [31:0] mem_4_data; - reg [4:0] mem_4_index; - reg [4:0] mem_4_size; - reg [4:0] mem_4_fullsize; - reg mem_4_write; - reg mem_4_sext; - reg mem_4_iload; - reg mem_4_fencei; - reg mem_4_flushat; - reg mem_4_flushall; - reg mem_4_sldst; - reg mem_4_vldst; - reg mem_4_fldst; - reg [1:0] mem_4_regionType; - reg [15:0] mem_4_mask; - reg mem_4_last; - reg [31:0] mem_5_pc; - reg [31:0] mem_5_addr; - reg [31:0] mem_5_adrx; - reg [31:0] mem_5_data; - reg [4:0] mem_5_index; - reg [4:0] mem_5_size; - reg [4:0] mem_5_fullsize; - reg mem_5_write; - reg mem_5_sext; - reg mem_5_iload; - reg mem_5_fencei; - reg mem_5_flushat; - reg mem_5_flushall; - reg mem_5_sldst; - reg mem_5_vldst; - reg mem_5_fldst; - reg [1:0] mem_5_regionType; - reg [15:0] mem_5_mask; - reg mem_5_last; - reg [31:0] mem_6_pc; - reg [31:0] mem_6_addr; - reg [31:0] mem_6_adrx; - reg [31:0] mem_6_data; - reg [4:0] mem_6_index; - reg [4:0] mem_6_size; - reg [4:0] mem_6_fullsize; - reg mem_6_write; - reg mem_6_sext; - reg mem_6_iload; - reg mem_6_fencei; - reg mem_6_flushat; - reg mem_6_flushall; - reg mem_6_sldst; - reg mem_6_vldst; - reg mem_6_fldst; - reg [1:0] mem_6_regionType; - reg [15:0] mem_6_mask; - reg mem_6_last; - reg [31:0] mem_7_pc; - reg [31:0] mem_7_addr; - reg [31:0] mem_7_adrx; - reg [31:0] mem_7_data; - reg [4:0] mem_7_index; - reg [4:0] mem_7_size; - reg [4:0] mem_7_fullsize; - reg mem_7_write; - reg mem_7_sext; - reg mem_7_iload; - reg mem_7_fencei; - reg mem_7_flushat; - reg mem_7_flushall; - reg mem_7_sldst; - reg mem_7_vldst; - reg mem_7_fldst; - reg [1:0] mem_7_regionType; - reg [15:0] mem_7_mask; - reg mem_7_last; - reg [2:0] inxpos_0; - reg [2:0] inxpos_1; - reg [2:0] inxpos_2; - reg [2:0] inxpos_3; - reg [2:0] inxpos_4; - reg [2:0] inxpos_5; - reg [2:0] inxpos_6; - reg [2:0] inxpos_7; - reg [3:0] outpos; - reg [3:0] mcount; - wire ivalid = io_in_valid & io_in_ready; - wire [1:0] _GEN_0 = {1'h0, io_in_bits_0_valid}; - wire [1:0] _GEN_1 = {1'h0, io_in_bits_1_valid}; - wire [1:0] _GEN_2 = {1'h0, io_in_bits_2_valid}; - wire [1:0] _GEN_3 = {1'h0, io_in_bits_3_valid}; - wire [1:0] _GEN_4 = {1'h0, io_in_bits_4_valid}; - wire [1:0] _GEN_5 = {1'h0, io_in_bits_5_valid}; - wire [1:0] _GEN_6 = {1'h0, io_in_bits_6_valid}; - wire [1:0] _GEN_7 = {1'h0, io_in_bits_7_valid}; - wire [3:0] icount = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}}; - wire [7:0][31:0] _GEN_8 = - {{io_in_bits_7_bits_pc}, - {io_in_bits_6_bits_pc}, - {io_in_bits_5_bits_pc}, - {io_in_bits_4_bits_pc}, - {io_in_bits_3_bits_pc}, - {io_in_bits_2_bits_pc}, - {io_in_bits_1_bits_pc}, - {io_in_bits_0_bits_pc}}; - wire [7:0][31:0] _GEN_9 = - {{io_in_bits_7_bits_addr}, - {io_in_bits_6_bits_addr}, - {io_in_bits_5_bits_addr}, - {io_in_bits_4_bits_addr}, - {io_in_bits_3_bits_addr}, - {io_in_bits_2_bits_addr}, - {io_in_bits_1_bits_addr}, - {io_in_bits_0_bits_addr}}; - wire [7:0][31:0] _GEN_10 = - {{io_in_bits_7_bits_adrx}, - {io_in_bits_6_bits_adrx}, - {io_in_bits_5_bits_adrx}, - {io_in_bits_4_bits_adrx}, - {io_in_bits_3_bits_adrx}, - {io_in_bits_2_bits_adrx}, - {io_in_bits_1_bits_adrx}, - {io_in_bits_0_bits_adrx}}; - wire [7:0][31:0] _GEN_11 = - {{io_in_bits_7_bits_data}, - {io_in_bits_6_bits_data}, - {io_in_bits_5_bits_data}, - {io_in_bits_4_bits_data}, - {io_in_bits_3_bits_data}, - {io_in_bits_2_bits_data}, - {io_in_bits_1_bits_data}, - {io_in_bits_0_bits_data}}; - wire [7:0][4:0] _GEN_12 = - {{io_in_bits_7_bits_index}, - {io_in_bits_6_bits_index}, - {io_in_bits_5_bits_index}, - {io_in_bits_4_bits_index}, - {io_in_bits_3_bits_index}, - {io_in_bits_2_bits_index}, - {io_in_bits_1_bits_index}, - {io_in_bits_0_bits_index}}; - wire [7:0][4:0] _GEN_13 = - {{io_in_bits_7_bits_size}, - {io_in_bits_6_bits_size}, - {io_in_bits_5_bits_size}, - {io_in_bits_4_bits_size}, - {io_in_bits_3_bits_size}, - {io_in_bits_2_bits_size}, - {io_in_bits_1_bits_size}, - {io_in_bits_0_bits_size}}; - wire [7:0][4:0] _GEN_14 = - {{io_in_bits_7_bits_fullsize}, - {io_in_bits_6_bits_fullsize}, - {io_in_bits_5_bits_fullsize}, - {io_in_bits_4_bits_fullsize}, - {io_in_bits_3_bits_fullsize}, - {io_in_bits_2_bits_fullsize}, - {io_in_bits_1_bits_fullsize}, - {io_in_bits_0_bits_fullsize}}; - wire [7:0] _GEN_15 = - {{io_in_bits_7_bits_write}, - {io_in_bits_6_bits_write}, - {io_in_bits_5_bits_write}, - {io_in_bits_4_bits_write}, - {io_in_bits_3_bits_write}, - {io_in_bits_2_bits_write}, - {io_in_bits_1_bits_write}, - {io_in_bits_0_bits_write}}; - wire [7:0] _GEN_16 = - {{io_in_bits_7_bits_sext}, - {io_in_bits_6_bits_sext}, - {io_in_bits_5_bits_sext}, - {io_in_bits_4_bits_sext}, - {io_in_bits_3_bits_sext}, - {io_in_bits_2_bits_sext}, - {io_in_bits_1_bits_sext}, - {io_in_bits_0_bits_sext}}; - wire [7:0] _GEN_17 = - {{io_in_bits_7_bits_iload}, - {io_in_bits_6_bits_iload}, - {io_in_bits_5_bits_iload}, - {io_in_bits_4_bits_iload}, - {io_in_bits_3_bits_iload}, - {io_in_bits_2_bits_iload}, - {io_in_bits_1_bits_iload}, - {io_in_bits_0_bits_iload}}; - wire [7:0] _GEN_18 = - {{io_in_bits_7_bits_fencei}, - {io_in_bits_6_bits_fencei}, - {io_in_bits_5_bits_fencei}, - {io_in_bits_4_bits_fencei}, - {io_in_bits_3_bits_fencei}, - {io_in_bits_2_bits_fencei}, - {io_in_bits_1_bits_fencei}, - {io_in_bits_0_bits_fencei}}; - wire [7:0] _GEN_19 = - {{io_in_bits_7_bits_flushat}, - {io_in_bits_6_bits_flushat}, - {io_in_bits_5_bits_flushat}, - {io_in_bits_4_bits_flushat}, - {io_in_bits_3_bits_flushat}, - {io_in_bits_2_bits_flushat}, - {io_in_bits_1_bits_flushat}, - {io_in_bits_0_bits_flushat}}; - wire [7:0] _GEN_20 = - {{io_in_bits_7_bits_flushall}, - {io_in_bits_6_bits_flushall}, - {io_in_bits_5_bits_flushall}, - {io_in_bits_4_bits_flushall}, - {io_in_bits_3_bits_flushall}, - {io_in_bits_2_bits_flushall}, - {io_in_bits_1_bits_flushall}, - {io_in_bits_0_bits_flushall}}; - wire [7:0] _GEN_21 = - {{io_in_bits_7_bits_sldst}, - {io_in_bits_6_bits_sldst}, - {io_in_bits_5_bits_sldst}, - {io_in_bits_4_bits_sldst}, - {io_in_bits_3_bits_sldst}, - {io_in_bits_2_bits_sldst}, - {io_in_bits_1_bits_sldst}, - {io_in_bits_0_bits_sldst}}; - wire [7:0] _GEN_22 = - {{io_in_bits_7_bits_vldst}, - {io_in_bits_6_bits_vldst}, - {io_in_bits_5_bits_vldst}, - {io_in_bits_4_bits_vldst}, - {io_in_bits_3_bits_vldst}, - {io_in_bits_2_bits_vldst}, - {io_in_bits_1_bits_vldst}, - {io_in_bits_0_bits_vldst}}; - wire [7:0] _GEN_23 = - {{io_in_bits_7_bits_fldst}, - {io_in_bits_6_bits_fldst}, - {io_in_bits_5_bits_fldst}, - {io_in_bits_4_bits_fldst}, - {io_in_bits_3_bits_fldst}, - {io_in_bits_2_bits_fldst}, - {io_in_bits_1_bits_fldst}, - {io_in_bits_0_bits_fldst}}; - wire [7:0][1:0] _GEN_24 = - {{io_in_bits_7_bits_regionType}, - {io_in_bits_6_bits_regionType}, - {io_in_bits_5_bits_regionType}, - {io_in_bits_4_bits_regionType}, - {io_in_bits_3_bits_regionType}, - {io_in_bits_2_bits_regionType}, - {io_in_bits_1_bits_regionType}, - {io_in_bits_0_bits_regionType}}; - wire [7:0][15:0] _GEN_25 = - {{io_in_bits_7_bits_mask}, - {io_in_bits_6_bits_mask}, - {io_in_bits_5_bits_mask}, - {io_in_bits_4_bits_mask}, - {io_in_bits_3_bits_mask}, - {io_in_bits_2_bits_mask}, - {io_in_bits_1_bits_mask}, - {io_in_bits_0_bits_mask}}; - wire _GEN_26 = - ivalid - & (|{io_in_bits_7_valid, - io_in_bits_6_valid, - io_in_bits_5_valid, - io_in_bits_4_valid, - io_in_bits_3_valid, - io_in_bits_2_valid, - io_in_bits_1_valid, - io_in_bits_0_valid}); - wire mslice_io_in_valid = (|mcount) ? io_out_ready : _GEN_26; - wire [15:0][31:0] _GEN_27 = - {{mem_0_pc}, - {mem_0_pc}, - {mem_0_pc}, - {mem_0_pc}, - {mem_0_pc}, - {mem_0_pc}, - {mem_0_pc}, - {32'h0}, - {mem_7_pc}, - {mem_6_pc}, - {mem_5_pc}, - {mem_4_pc}, - {mem_3_pc}, - {mem_2_pc}, - {mem_1_pc}, - {mem_0_pc}}; - wire [15:0][31:0] _GEN_28 = - {{mem_0_addr}, - {mem_0_addr}, - {mem_0_addr}, - {mem_0_addr}, - {mem_0_addr}, - {mem_0_addr}, - {mem_0_addr}, - {32'h0}, - {mem_7_addr}, - {mem_6_addr}, - {mem_5_addr}, - {mem_4_addr}, - {mem_3_addr}, - {mem_2_addr}, - {mem_1_addr}, - {mem_0_addr}}; - wire [15:0][31:0] _GEN_29 = - {{mem_0_adrx}, - {mem_0_adrx}, - {mem_0_adrx}, - {mem_0_adrx}, - {mem_0_adrx}, - {mem_0_adrx}, - {mem_0_adrx}, - {32'h0}, - {mem_7_adrx}, - {mem_6_adrx}, - {mem_5_adrx}, - {mem_4_adrx}, - {mem_3_adrx}, - {mem_2_adrx}, - {mem_1_adrx}, - {mem_0_adrx}}; - wire [15:0][31:0] _GEN_30 = - {{mem_0_data}, - {mem_0_data}, - {mem_0_data}, - {mem_0_data}, - {mem_0_data}, - {mem_0_data}, - {mem_0_data}, - {32'h0}, - {mem_7_data}, - {mem_6_data}, - {mem_5_data}, - {mem_4_data}, - {mem_3_data}, - {mem_2_data}, - {mem_1_data}, - {mem_0_data}}; - wire [15:0][4:0] _GEN_31 = - {{mem_0_index}, - {mem_0_index}, - {mem_0_index}, - {mem_0_index}, - {mem_0_index}, - {mem_0_index}, - {mem_0_index}, - {5'h0}, - {mem_7_index}, - {mem_6_index}, - {mem_5_index}, - {mem_4_index}, - {mem_3_index}, - {mem_2_index}, - {mem_1_index}, - {mem_0_index}}; - wire [15:0][4:0] _GEN_32 = - {{mem_0_size}, - {mem_0_size}, - {mem_0_size}, - {mem_0_size}, - {mem_0_size}, - {mem_0_size}, - {mem_0_size}, - {5'h0}, - {mem_7_size}, - {mem_6_size}, - {mem_5_size}, - {mem_4_size}, - {mem_3_size}, - {mem_2_size}, - {mem_1_size}, - {mem_0_size}}; - wire [15:0][4:0] _GEN_33 = - {{mem_0_fullsize}, - {mem_0_fullsize}, - {mem_0_fullsize}, - {mem_0_fullsize}, - {mem_0_fullsize}, - {mem_0_fullsize}, - {mem_0_fullsize}, - {5'h0}, - {mem_7_fullsize}, - {mem_6_fullsize}, - {mem_5_fullsize}, - {mem_4_fullsize}, - {mem_3_fullsize}, - {mem_2_fullsize}, - {mem_1_fullsize}, - {mem_0_fullsize}}; - wire [15:0] _GEN_34 = - {{mem_0_write}, - {mem_0_write}, - {mem_0_write}, - {mem_0_write}, - {mem_0_write}, - {mem_0_write}, - {mem_0_write}, - {1'h0}, - {mem_7_write}, - {mem_6_write}, - {mem_5_write}, - {mem_4_write}, - {mem_3_write}, - {mem_2_write}, - {mem_1_write}, - {mem_0_write}}; - wire [15:0] _GEN_35 = - {{mem_0_sext}, - {mem_0_sext}, - {mem_0_sext}, - {mem_0_sext}, - {mem_0_sext}, - {mem_0_sext}, - {mem_0_sext}, - {1'h0}, - {mem_7_sext}, - {mem_6_sext}, - {mem_5_sext}, - {mem_4_sext}, - {mem_3_sext}, - {mem_2_sext}, - {mem_1_sext}, - {mem_0_sext}}; - wire [15:0] _GEN_36 = - {{mem_0_iload}, - {mem_0_iload}, - {mem_0_iload}, - {mem_0_iload}, - {mem_0_iload}, - {mem_0_iload}, - {mem_0_iload}, - {1'h0}, - {mem_7_iload}, - {mem_6_iload}, - {mem_5_iload}, - {mem_4_iload}, - {mem_3_iload}, - {mem_2_iload}, - {mem_1_iload}, - {mem_0_iload}}; - wire [15:0] _GEN_37 = - {{mem_0_fencei}, - {mem_0_fencei}, - {mem_0_fencei}, - {mem_0_fencei}, - {mem_0_fencei}, - {mem_0_fencei}, - {mem_0_fencei}, - {1'h0}, - {mem_7_fencei}, - {mem_6_fencei}, - {mem_5_fencei}, - {mem_4_fencei}, - {mem_3_fencei}, - {mem_2_fencei}, - {mem_1_fencei}, - {mem_0_fencei}}; - wire [15:0] _GEN_38 = - {{mem_0_flushat}, - {mem_0_flushat}, - {mem_0_flushat}, - {mem_0_flushat}, - {mem_0_flushat}, - {mem_0_flushat}, - {mem_0_flushat}, - {1'h0}, - {mem_7_flushat}, - {mem_6_flushat}, - {mem_5_flushat}, - {mem_4_flushat}, - {mem_3_flushat}, - {mem_2_flushat}, - {mem_1_flushat}, - {mem_0_flushat}}; - wire [15:0] _GEN_39 = - {{mem_0_flushall}, - {mem_0_flushall}, - {mem_0_flushall}, - {mem_0_flushall}, - {mem_0_flushall}, - {mem_0_flushall}, - {mem_0_flushall}, - {1'h0}, - {mem_7_flushall}, - {mem_6_flushall}, - {mem_5_flushall}, - {mem_4_flushall}, - {mem_3_flushall}, - {mem_2_flushall}, - {mem_1_flushall}, - {mem_0_flushall}}; - wire [15:0] _GEN_40 = - {{mem_0_sldst}, - {mem_0_sldst}, - {mem_0_sldst}, - {mem_0_sldst}, - {mem_0_sldst}, - {mem_0_sldst}, - {mem_0_sldst}, - {1'h0}, - {mem_7_sldst}, - {mem_6_sldst}, - {mem_5_sldst}, - {mem_4_sldst}, - {mem_3_sldst}, - {mem_2_sldst}, - {mem_1_sldst}, - {mem_0_sldst}}; - wire [15:0] _GEN_41 = - {{mem_0_vldst}, - {mem_0_vldst}, - {mem_0_vldst}, - {mem_0_vldst}, - {mem_0_vldst}, - {mem_0_vldst}, - {mem_0_vldst}, - {1'h0}, - {mem_7_vldst}, - {mem_6_vldst}, - {mem_5_vldst}, - {mem_4_vldst}, - {mem_3_vldst}, - {mem_2_vldst}, - {mem_1_vldst}, - {mem_0_vldst}}; - wire [15:0] _GEN_42 = - {{mem_0_fldst}, - {mem_0_fldst}, - {mem_0_fldst}, - {mem_0_fldst}, - {mem_0_fldst}, - {mem_0_fldst}, - {mem_0_fldst}, - {1'h0}, - {mem_7_fldst}, - {mem_6_fldst}, - {mem_5_fldst}, - {mem_4_fldst}, - {mem_3_fldst}, - {mem_2_fldst}, - {mem_1_fldst}, - {mem_0_fldst}}; - wire [15:0][1:0] _GEN_43 = - {{mem_0_regionType}, - {mem_0_regionType}, - {mem_0_regionType}, - {mem_0_regionType}, - {mem_0_regionType}, - {mem_0_regionType}, - {mem_0_regionType}, - {2'h0}, - {mem_7_regionType}, - {mem_6_regionType}, - {mem_5_regionType}, - {mem_4_regionType}, - {mem_3_regionType}, - {mem_2_regionType}, - {mem_1_regionType}, - {mem_0_regionType}}; - wire [15:0][15:0] _GEN_44 = - {{mem_0_mask}, - {mem_0_mask}, - {mem_0_mask}, - {mem_0_mask}, - {mem_0_mask}, - {mem_0_mask}, - {mem_0_mask}, - {16'h0}, - {mem_7_mask}, - {mem_6_mask}, - {mem_5_mask}, - {mem_4_mask}, - {mem_3_mask}, - {mem_2_mask}, - {mem_1_mask}, - {mem_0_mask}}; - wire [15:0] _GEN_45 = - {{mem_0_last}, - {mem_0_last}, - {mem_0_last}, - {mem_0_last}, - {mem_0_last}, - {mem_0_last}, - {mem_0_last}, - {1'h0}, - {mem_7_last}, - {mem_6_last}, - {mem_5_last}, - {mem_4_last}, - {mem_3_last}, - {mem_2_last}, - {mem_1_last}, - {mem_0_last}}; - wire [2:0] idx_8 = - io_in_bits_0_valid - ? 3'h0 - : io_in_bits_1_valid - ? 3'h1 - : io_in_bits_2_valid - ? 3'h2 - : io_in_bits_3_valid - ? 3'h3 - : io_in_bits_4_valid - ? 3'h4 - : io_in_bits_5_valid ? 3'h5 : {2'h3, ~io_in_bits_6_valid}; - assign io_in_ready = mcount <= 4'h8 - icount; - wire [7:0] _GEN_46 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_47 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_48 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_49 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_50 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_51 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_52 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [7:0] _GEN_53 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; - wire [4:0] outpos_c = {1'h0, outpos} + 5'h1; - wire dec = mslice_io_in_valid & _mslice_io_in_ready; - wire _inxvalid_T_25 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h1 - & io_in_bits_7_valid; - wire _inxvalid_T_48 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h1 & io_in_bits_6_valid; - wire _inxvalid_T_68 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h1 - & io_in_bits_5_valid; - wire _inxvalid_T_85 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h1 - & io_in_bits_4_valid; - wire _inxvalid_T_99 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h1 & io_in_bits_3_valid; - wire _inxvalid_T_110 = - _GEN_0 + _GEN_1 + _GEN_2 == 2'h1 & io_in_bits_2_valid; - wire _inxvalid_T_118 = _GEN_0 + _GEN_1 == 2'h1 & io_in_bits_1_valid; - wire _inxvalid_T_149 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h2 - & io_in_bits_7_valid; - wire _inxvalid_T_172 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h2 & io_in_bits_6_valid; - wire _inxvalid_T_192 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h2 - & io_in_bits_5_valid; - wire _inxvalid_T_209 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h2 - & io_in_bits_4_valid; - wire _inxvalid_T_223 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h2 & io_in_bits_3_valid; - wire _inxvalid_T_234 = - _GEN_0 + _GEN_1 + _GEN_2 == 2'h2 & io_in_bits_2_valid; - wire _inxvalid_T_242 = _GEN_0 + _GEN_1 == 2'h2 & io_in_bits_1_valid; - wire _inxvalid_T_268 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h3 - & io_in_bits_7_valid; - wire _inxvalid_T_291 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h3 & io_in_bits_6_valid; - wire _inxvalid_T_311 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h3 - & io_in_bits_5_valid; - wire _inxvalid_T_328 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h3 - & io_in_bits_4_valid; - wire _inxvalid_T_342 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h3 & io_in_bits_3_valid; - wire _inxvalid_T_353 = (&(_GEN_0 + _GEN_1 + _GEN_2)) & io_in_bits_2_valid; - wire _inxvalid_T_379 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h4 - & io_in_bits_7_valid; - wire _inxvalid_T_402 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h4 & io_in_bits_6_valid; - wire _inxvalid_T_422 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h4 - & io_in_bits_5_valid; - wire _inxvalid_T_439 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h4 - & io_in_bits_4_valid; - wire _inxvalid_T_453 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h4 & io_in_bits_3_valid; - wire _inxvalid_T_479 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h5 - & io_in_bits_7_valid; - wire _inxvalid_T_502 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h5 & io_in_bits_6_valid; - wire _inxvalid_T_522 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h5 - & io_in_bits_5_valid; - wire _inxvalid_T_539 = - {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h5 - & io_in_bits_4_valid; - wire _inxvalid_T_565 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h6 - & io_in_bits_7_valid; - wire _inxvalid_T_588 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6} == 3'h6 & io_in_bits_6_valid; - wire _inxvalid_T_608 = - {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h6 - & io_in_bits_5_valid; - wire _inxvalid_T_634 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h7 - & io_in_bits_7_valid; - wire _inxvalid_T_657 = - (&({1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} - + {1'h0, _GEN_5 + _GEN_6})) & io_in_bits_6_valid; - wire _inxvalid_T_683 = - {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} - + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h8 - & io_in_bits_7_valid; - wire _valid_T_133 = inxpos_0 == 3'h0; - wire _valid_T_129 = inxpos_1 == 3'h0; - wire _valid_T_121 = inxpos_2 == 3'h0; - wire _valid_T_109 = inxpos_3 == 3'h0; - wire _valid_T_93 = inxpos_4 == 3'h0; - wire _valid_T_73 = inxpos_5 == 3'h0; - wire _valid_T_49 = inxpos_6 == 3'h0; - wire _valid_T_57 = - _valid_T_133 & _inxvalid_T_48 | _valid_T_129 & _inxvalid_T_172 | _valid_T_121 - & _inxvalid_T_291 | _valid_T_109 & _inxvalid_T_402 | _valid_T_93 & _inxvalid_T_502 - | _valid_T_73 & _inxvalid_T_588 | _valid_T_49 & _inxvalid_T_657; - wire _valid_T_80 = - _valid_T_133 & _inxvalid_T_68 | _valid_T_129 & _inxvalid_T_192 | _valid_T_121 - & _inxvalid_T_311 | _valid_T_109 & _inxvalid_T_422 | _valid_T_93 & _inxvalid_T_522 - | _valid_T_73 & _inxvalid_T_608; - wire _valid_T_99 = - _valid_T_133 & _inxvalid_T_85 | _valid_T_129 & _inxvalid_T_209 | _valid_T_121 - & _inxvalid_T_328 | _valid_T_109 & _inxvalid_T_439 | _valid_T_93 & _inxvalid_T_539; - wire _valid_T_114 = - _valid_T_133 & _inxvalid_T_99 | _valid_T_129 & _inxvalid_T_223 | _valid_T_121 - & _inxvalid_T_342 | _valid_T_109 & _inxvalid_T_453; - wire _valid_T_125 = - _valid_T_133 & _inxvalid_T_110 | _valid_T_129 & _inxvalid_T_234 | _valid_T_121 - & _inxvalid_T_353; - wire _valid_T_132 = - _valid_T_133 & _inxvalid_T_118 | _valid_T_129 & _inxvalid_T_242; - wire _valid_T_135 = _valid_T_133 & io_in_bits_0_valid; - wire _valid_T_269 = inxpos_0 == 3'h1; - wire _valid_T_265 = inxpos_1 == 3'h1; - wire _valid_T_257 = inxpos_2 == 3'h1; - wire _valid_T_245 = inxpos_3 == 3'h1; - wire _valid_T_229 = inxpos_4 == 3'h1; - wire _valid_T_209 = inxpos_5 == 3'h1; - wire _valid_T_185 = inxpos_6 == 3'h1; - wire _valid_T_193 = - _valid_T_269 & _inxvalid_T_48 | _valid_T_265 & _inxvalid_T_172 | _valid_T_257 - & _inxvalid_T_291 | _valid_T_245 & _inxvalid_T_402 | _valid_T_229 & _inxvalid_T_502 - | _valid_T_209 & _inxvalid_T_588 | _valid_T_185 & _inxvalid_T_657; - wire _valid_T_216 = - _valid_T_269 & _inxvalid_T_68 | _valid_T_265 & _inxvalid_T_192 | _valid_T_257 - & _inxvalid_T_311 | _valid_T_245 & _inxvalid_T_422 | _valid_T_229 & _inxvalid_T_522 - | _valid_T_209 & _inxvalid_T_608; - wire _valid_T_235 = - _valid_T_269 & _inxvalid_T_85 | _valid_T_265 & _inxvalid_T_209 | _valid_T_257 - & _inxvalid_T_328 | _valid_T_245 & _inxvalid_T_439 | _valid_T_229 & _inxvalid_T_539; - wire _valid_T_250 = - _valid_T_269 & _inxvalid_T_99 | _valid_T_265 & _inxvalid_T_223 | _valid_T_257 - & _inxvalid_T_342 | _valid_T_245 & _inxvalid_T_453; - wire _valid_T_261 = - _valid_T_269 & _inxvalid_T_110 | _valid_T_265 & _inxvalid_T_234 | _valid_T_257 - & _inxvalid_T_353; - wire _valid_T_268 = - _valid_T_269 & _inxvalid_T_118 | _valid_T_265 & _inxvalid_T_242; - wire _valid_T_271 = _valid_T_269 & io_in_bits_0_valid; - wire _valid_T_405 = inxpos_0 == 3'h2; - wire _valid_T_401 = inxpos_1 == 3'h2; - wire _valid_T_393 = inxpos_2 == 3'h2; - wire _valid_T_381 = inxpos_3 == 3'h2; - wire _valid_T_365 = inxpos_4 == 3'h2; - wire _valid_T_345 = inxpos_5 == 3'h2; - wire _valid_T_321 = inxpos_6 == 3'h2; - wire _valid_T_329 = - _valid_T_405 & _inxvalid_T_48 | _valid_T_401 & _inxvalid_T_172 | _valid_T_393 - & _inxvalid_T_291 | _valid_T_381 & _inxvalid_T_402 | _valid_T_365 & _inxvalid_T_502 - | _valid_T_345 & _inxvalid_T_588 | _valid_T_321 & _inxvalid_T_657; - wire _valid_T_352 = - _valid_T_405 & _inxvalid_T_68 | _valid_T_401 & _inxvalid_T_192 | _valid_T_393 - & _inxvalid_T_311 | _valid_T_381 & _inxvalid_T_422 | _valid_T_365 & _inxvalid_T_522 - | _valid_T_345 & _inxvalid_T_608; - wire _valid_T_371 = - _valid_T_405 & _inxvalid_T_85 | _valid_T_401 & _inxvalid_T_209 | _valid_T_393 - & _inxvalid_T_328 | _valid_T_381 & _inxvalid_T_439 | _valid_T_365 & _inxvalid_T_539; - wire _valid_T_386 = - _valid_T_405 & _inxvalid_T_99 | _valid_T_401 & _inxvalid_T_223 | _valid_T_393 - & _inxvalid_T_342 | _valid_T_381 & _inxvalid_T_453; - wire _valid_T_397 = - _valid_T_405 & _inxvalid_T_110 | _valid_T_401 & _inxvalid_T_234 | _valid_T_393 - & _inxvalid_T_353; - wire _valid_T_404 = - _valid_T_405 & _inxvalid_T_118 | _valid_T_401 & _inxvalid_T_242; - wire _valid_T_407 = _valid_T_405 & io_in_bits_0_valid; - wire _valid_T_541 = inxpos_0 == 3'h3; - wire _valid_T_537 = inxpos_1 == 3'h3; - wire _valid_T_529 = inxpos_2 == 3'h3; - wire _valid_T_517 = inxpos_3 == 3'h3; - wire _valid_T_501 = inxpos_4 == 3'h3; - wire _valid_T_481 = inxpos_5 == 3'h3; - wire _valid_T_457 = inxpos_6 == 3'h3; - wire _valid_T_465 = - _valid_T_541 & _inxvalid_T_48 | _valid_T_537 & _inxvalid_T_172 | _valid_T_529 - & _inxvalid_T_291 | _valid_T_517 & _inxvalid_T_402 | _valid_T_501 & _inxvalid_T_502 - | _valid_T_481 & _inxvalid_T_588 | _valid_T_457 & _inxvalid_T_657; - wire _valid_T_488 = - _valid_T_541 & _inxvalid_T_68 | _valid_T_537 & _inxvalid_T_192 | _valid_T_529 - & _inxvalid_T_311 | _valid_T_517 & _inxvalid_T_422 | _valid_T_501 & _inxvalid_T_522 - | _valid_T_481 & _inxvalid_T_608; - wire _valid_T_507 = - _valid_T_541 & _inxvalid_T_85 | _valid_T_537 & _inxvalid_T_209 | _valid_T_529 - & _inxvalid_T_328 | _valid_T_517 & _inxvalid_T_439 | _valid_T_501 & _inxvalid_T_539; - wire _valid_T_522 = - _valid_T_541 & _inxvalid_T_99 | _valid_T_537 & _inxvalid_T_223 | _valid_T_529 - & _inxvalid_T_342 | _valid_T_517 & _inxvalid_T_453; - wire _valid_T_533 = - _valid_T_541 & _inxvalid_T_110 | _valid_T_537 & _inxvalid_T_234 | _valid_T_529 - & _inxvalid_T_353; - wire _valid_T_540 = - _valid_T_541 & _inxvalid_T_118 | _valid_T_537 & _inxvalid_T_242; - wire _valid_T_543 = _valid_T_541 & io_in_bits_0_valid; - wire _valid_T_677 = inxpos_0 == 3'h4; - wire _valid_T_673 = inxpos_1 == 3'h4; - wire _valid_T_665 = inxpos_2 == 3'h4; - wire _valid_T_653 = inxpos_3 == 3'h4; - wire _valid_T_637 = inxpos_4 == 3'h4; - wire _valid_T_617 = inxpos_5 == 3'h4; - wire _valid_T_593 = inxpos_6 == 3'h4; - wire _valid_T_601 = - _valid_T_677 & _inxvalid_T_48 | _valid_T_673 & _inxvalid_T_172 | _valid_T_665 - & _inxvalid_T_291 | _valid_T_653 & _inxvalid_T_402 | _valid_T_637 & _inxvalid_T_502 - | _valid_T_617 & _inxvalid_T_588 | _valid_T_593 & _inxvalid_T_657; - wire _valid_T_624 = - _valid_T_677 & _inxvalid_T_68 | _valid_T_673 & _inxvalid_T_192 | _valid_T_665 - & _inxvalid_T_311 | _valid_T_653 & _inxvalid_T_422 | _valid_T_637 & _inxvalid_T_522 - | _valid_T_617 & _inxvalid_T_608; - wire _valid_T_643 = - _valid_T_677 & _inxvalid_T_85 | _valid_T_673 & _inxvalid_T_209 | _valid_T_665 - & _inxvalid_T_328 | _valid_T_653 & _inxvalid_T_439 | _valid_T_637 & _inxvalid_T_539; - wire _valid_T_658 = - _valid_T_677 & _inxvalid_T_99 | _valid_T_673 & _inxvalid_T_223 | _valid_T_665 - & _inxvalid_T_342 | _valid_T_653 & _inxvalid_T_453; - wire _valid_T_669 = - _valid_T_677 & _inxvalid_T_110 | _valid_T_673 & _inxvalid_T_234 | _valid_T_665 - & _inxvalid_T_353; - wire _valid_T_676 = - _valid_T_677 & _inxvalid_T_118 | _valid_T_673 & _inxvalid_T_242; - wire _valid_T_679 = _valid_T_677 & io_in_bits_0_valid; - wire _valid_T_813 = inxpos_0 == 3'h5; - wire _valid_T_809 = inxpos_1 == 3'h5; - wire _valid_T_801 = inxpos_2 == 3'h5; - wire _valid_T_789 = inxpos_3 == 3'h5; - wire _valid_T_773 = inxpos_4 == 3'h5; - wire _valid_T_753 = inxpos_5 == 3'h5; - wire _valid_T_729 = inxpos_6 == 3'h5; - wire _valid_T_737 = - _valid_T_813 & _inxvalid_T_48 | _valid_T_809 & _inxvalid_T_172 | _valid_T_801 - & _inxvalid_T_291 | _valid_T_789 & _inxvalid_T_402 | _valid_T_773 & _inxvalid_T_502 - | _valid_T_753 & _inxvalid_T_588 | _valid_T_729 & _inxvalid_T_657; - wire _valid_T_760 = - _valid_T_813 & _inxvalid_T_68 | _valid_T_809 & _inxvalid_T_192 | _valid_T_801 - & _inxvalid_T_311 | _valid_T_789 & _inxvalid_T_422 | _valid_T_773 & _inxvalid_T_522 - | _valid_T_753 & _inxvalid_T_608; - wire _valid_T_779 = - _valid_T_813 & _inxvalid_T_85 | _valid_T_809 & _inxvalid_T_209 | _valid_T_801 - & _inxvalid_T_328 | _valid_T_789 & _inxvalid_T_439 | _valid_T_773 & _inxvalid_T_539; - wire _valid_T_794 = - _valid_T_813 & _inxvalid_T_99 | _valid_T_809 & _inxvalid_T_223 | _valid_T_801 - & _inxvalid_T_342 | _valid_T_789 & _inxvalid_T_453; - wire _valid_T_805 = - _valid_T_813 & _inxvalid_T_110 | _valid_T_809 & _inxvalid_T_234 | _valid_T_801 - & _inxvalid_T_353; - wire _valid_T_812 = - _valid_T_813 & _inxvalid_T_118 | _valid_T_809 & _inxvalid_T_242; - wire _valid_T_815 = _valid_T_813 & io_in_bits_0_valid; - wire _valid_T_949 = inxpos_0 == 3'h6; - wire _valid_T_945 = inxpos_1 == 3'h6; - wire _valid_T_937 = inxpos_2 == 3'h6; - wire _valid_T_925 = inxpos_3 == 3'h6; - wire _valid_T_909 = inxpos_4 == 3'h6; - wire _valid_T_889 = inxpos_5 == 3'h6; - wire _valid_T_865 = inxpos_6 == 3'h6; - wire _valid_T_873 = - _valid_T_949 & _inxvalid_T_48 | _valid_T_945 & _inxvalid_T_172 | _valid_T_937 - & _inxvalid_T_291 | _valid_T_925 & _inxvalid_T_402 | _valid_T_909 & _inxvalid_T_502 - | _valid_T_889 & _inxvalid_T_588 | _valid_T_865 & _inxvalid_T_657; - wire _valid_T_896 = - _valid_T_949 & _inxvalid_T_68 | _valid_T_945 & _inxvalid_T_192 | _valid_T_937 - & _inxvalid_T_311 | _valid_T_925 & _inxvalid_T_422 | _valid_T_909 & _inxvalid_T_522 - | _valid_T_889 & _inxvalid_T_608; - wire _valid_T_915 = - _valid_T_949 & _inxvalid_T_85 | _valid_T_945 & _inxvalid_T_209 | _valid_T_937 - & _inxvalid_T_328 | _valid_T_925 & _inxvalid_T_439 | _valid_T_909 & _inxvalid_T_539; - wire _valid_T_930 = - _valid_T_949 & _inxvalid_T_99 | _valid_T_945 & _inxvalid_T_223 | _valid_T_937 - & _inxvalid_T_342 | _valid_T_925 & _inxvalid_T_453; - wire _valid_T_941 = - _valid_T_949 & _inxvalid_T_110 | _valid_T_945 & _inxvalid_T_234 | _valid_T_937 - & _inxvalid_T_353; - wire _valid_T_948 = - _valid_T_949 & _inxvalid_T_118 | _valid_T_945 & _inxvalid_T_242; - wire _valid_T_951 = _valid_T_949 & io_in_bits_0_valid; - wire _valid_T_1009 = - (&inxpos_0) & _inxvalid_T_48 | (&inxpos_1) & _inxvalid_T_172 | (&inxpos_2) - & _inxvalid_T_291 | (&inxpos_3) & _inxvalid_T_402 | (&inxpos_4) & _inxvalid_T_502 - | (&inxpos_5) & _inxvalid_T_588 | (&inxpos_6) & _inxvalid_T_657; - wire _valid_T_1032 = - (&inxpos_0) & _inxvalid_T_68 | (&inxpos_1) & _inxvalid_T_192 | (&inxpos_2) - & _inxvalid_T_311 | (&inxpos_3) & _inxvalid_T_422 | (&inxpos_4) & _inxvalid_T_522 - | (&inxpos_5) & _inxvalid_T_608; - wire _valid_T_1051 = - (&inxpos_0) & _inxvalid_T_85 | (&inxpos_1) & _inxvalid_T_209 | (&inxpos_2) - & _inxvalid_T_328 | (&inxpos_3) & _inxvalid_T_439 | (&inxpos_4) & _inxvalid_T_539; - wire _valid_T_1066 = - (&inxpos_0) & _inxvalid_T_99 | (&inxpos_1) & _inxvalid_T_223 | (&inxpos_2) - & _inxvalid_T_342 | (&inxpos_3) & _inxvalid_T_453; - wire _valid_T_1077 = - (&inxpos_0) & _inxvalid_T_110 | (&inxpos_1) & _inxvalid_T_234 | (&inxpos_2) - & _inxvalid_T_353; - wire _valid_T_1084 = - (&inxpos_0) & _inxvalid_T_118 | (&inxpos_1) & _inxvalid_T_242; - wire _valid_T_1087 = (&inxpos_0) & io_in_bits_0_valid; - wire [2:0] idx = - _valid_T_135 - ? 3'h0 - : _valid_T_132 - ? 3'h1 - : _valid_T_125 - ? 3'h2 - : _valid_T_114 - ? 3'h3 - : _valid_T_99 ? 3'h4 : _valid_T_80 ? 3'h5 : {2'h3, ~_valid_T_57}; - wire [2:0] idx_1 = - _valid_T_271 - ? 3'h0 - : _valid_T_268 - ? 3'h1 - : _valid_T_261 - ? 3'h2 - : _valid_T_250 - ? 3'h3 - : _valid_T_235 ? 3'h4 : _valid_T_216 ? 3'h5 : {2'h3, ~_valid_T_193}; - wire [2:0] idx_2 = - _valid_T_407 - ? 3'h0 - : _valid_T_404 - ? 3'h1 - : _valid_T_397 - ? 3'h2 - : _valid_T_386 - ? 3'h3 - : _valid_T_371 ? 3'h4 : _valid_T_352 ? 3'h5 : {2'h3, ~_valid_T_329}; - wire [2:0] idx_3 = - _valid_T_543 - ? 3'h0 - : _valid_T_540 - ? 3'h1 - : _valid_T_533 - ? 3'h2 - : _valid_T_522 - ? 3'h3 - : _valid_T_507 ? 3'h4 : _valid_T_488 ? 3'h5 : {2'h3, ~_valid_T_465}; - wire [2:0] idx_4 = - _valid_T_679 - ? 3'h0 - : _valid_T_676 - ? 3'h1 - : _valid_T_669 - ? 3'h2 - : _valid_T_658 - ? 3'h3 - : _valid_T_643 ? 3'h4 : _valid_T_624 ? 3'h5 : {2'h3, ~_valid_T_601}; - wire [2:0] idx_5 = - _valid_T_815 - ? 3'h0 - : _valid_T_812 - ? 3'h1 - : _valid_T_805 - ? 3'h2 - : _valid_T_794 - ? 3'h3 - : _valid_T_779 ? 3'h4 : _valid_T_760 ? 3'h5 : {2'h3, ~_valid_T_737}; - wire [2:0] idx_6 = - _valid_T_951 - ? 3'h0 - : _valid_T_948 - ? 3'h1 - : _valid_T_941 - ? 3'h2 - : _valid_T_930 - ? 3'h3 - : _valid_T_915 ? 3'h4 : _valid_T_896 ? 3'h5 : {2'h3, ~_valid_T_873}; - wire [2:0] idx_7 = - _valid_T_1087 - ? 3'h0 - : _valid_T_1084 - ? 3'h1 - : _valid_T_1077 - ? 3'h2 - : _valid_T_1066 - ? 3'h3 - : _valid_T_1051 ? 3'h4 : _valid_T_1032 ? 3'h5 : {2'h3, ~_valid_T_1009}; + reg valid; + reg [4:0] addr; + reg [5:0] op; + wire r2IsGreater = $signed(io_rs1_data) < $signed(io_rs2_data); + wire r2IsGreaterU = io_rs1_data < io_rs2_data; + wire [31:0] _io_rd_bits_data_T_15 = io_rs1_data + io_rs2_data; + wire [31:0] _io_rd_bits_data_T_20 = io_rs1_data - io_rs2_data; + wire [31:0] _io_rd_bits_data_T_46 = io_rs1_data ^ io_rs2_data; + wire [62:0] _GEN = {31'h0, io_rs1_data}; + wire [62:0] _GEN_0 = {58'h0, io_rs2_data[4:0]}; + wire [62:0] _io_rd_bits_data_T_7 = _GEN << _GEN_0; + wire [31:0] _GEN_1 = {27'h0, io_rs2_data[4:0]}; + wire [62:0] _io_rd_bits_data_T_26 = _GEN << _GEN_0; + wire [31:0] _io_rd_bits_data_T_56 = + {16'h0, io_rs1_data[31:16]} | {io_rs1_data[15:0], 16'h0}; + wire [31:0] _io_rd_bits_data_T_66 = + {8'h0, _io_rd_bits_data_T_56[31:8] & 24'hFF00FF} + | {_io_rd_bits_data_T_56[23:0] & 24'hFF00FF, 8'h0}; + wire [31:0] _io_rd_bits_data_T_76 = + {4'h0, _io_rd_bits_data_T_66[31:4] & 28'hF0F0F0F} + | {_io_rd_bits_data_T_66[27:0] & 28'hF0F0F0F, 4'h0}; + wire [31:0] _io_rd_bits_data_T_86 = + {2'h0, _io_rd_bits_data_T_76[31:2] & 30'h33333333} + | {_io_rd_bits_data_T_76[29:0] & 30'h33333333, 2'h0}; + wire [31:0] _io_rd_bits_data_T_96 = + {1'h0, _io_rd_bits_data_T_86[31:1] & 31'h55555555} + | {_io_rd_bits_data_T_86[30:0] & 31'h55555555, 1'h0}; + wire [31:0] _io_rd_bits_data_T_343 = + io_rs2_data[0] ? {io_rs1_data[30:0], io_rs1_data[31]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_347 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_343[29:0], _io_rd_bits_data_T_343[31:30]} + : _io_rd_bits_data_T_343; + wire [31:0] _io_rd_bits_data_T_351 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_347[27:0], _io_rd_bits_data_T_347[31:28]} + : _io_rd_bits_data_T_347; + wire [31:0] _io_rd_bits_data_T_355 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_351[23:0], _io_rd_bits_data_T_351[31:24]} + : _io_rd_bits_data_T_351; + wire [31:0] _io_rd_bits_data_T_368 = + io_rs2_data[0] ? {io_rs1_data[0], io_rs1_data[31:1]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_372 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_368[1:0], _io_rd_bits_data_T_368[31:2]} + : _io_rd_bits_data_T_368; + wire [31:0] _io_rd_bits_data_T_376 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_372[3:0], _io_rd_bits_data_T_372[31:4]} + : _io_rd_bits_data_T_372; + wire [31:0] _io_rd_bits_data_T_380 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_376[7:0], _io_rd_bits_data_T_376[31:8]} + : _io_rd_bits_data_T_376; + wire [31:0] _io_rd_bits_data_T_400 = + {16'h0, io_rs1_data[31:16]} | {io_rs1_data[15:0], 16'h0}; + wire [31:0] _io_rd_bits_data_T_410 = + {8'h0, _io_rd_bits_data_T_400[31:8] & 24'hFF00FF} + | {_io_rd_bits_data_T_400[23:0] & 24'hFF00FF, 8'h0}; + wire [31:0] _io_rd_bits_data_T_420 = + {4'h0, _io_rd_bits_data_T_410[31:4] & 28'hF0F0F0F} + | {_io_rd_bits_data_T_410[27:0] & 28'hF0F0F0F, 4'h0}; + wire [31:0] _io_rd_bits_data_T_430 = + {2'h0, _io_rd_bits_data_T_420[31:2] & 30'h33333333} + | {_io_rd_bits_data_T_420[29:0] & 30'h33333333, 2'h0}; + wire [31:0] _io_rd_bits_data_T_440 = + {1'h0, _io_rd_bits_data_T_430[31:1] & 31'h55555555} + | {_io_rd_bits_data_T_430[30:0] & 31'h55555555, 1'h0}; + wire [31:0] _io_rd_bits_data_T_687 = + io_rs2_data[0] ? {io_rs1_data[30:0], io_rs1_data[31]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_691 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_687[29:0], _io_rd_bits_data_T_687[31:30]} + : _io_rd_bits_data_T_687; + wire [31:0] _io_rd_bits_data_T_695 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_691[27:0], _io_rd_bits_data_T_691[31:28]} + : _io_rd_bits_data_T_691; + wire [31:0] _io_rd_bits_data_T_699 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_695[23:0], _io_rd_bits_data_T_695[31:24]} + : _io_rd_bits_data_T_695; + wire [31:0] _io_rd_bits_data_T_715 = + io_rs2_data[0] ? {io_rs1_data[0], io_rs1_data[31:1]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_719 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_715[1:0], _io_rd_bits_data_T_715[31:2]} + : _io_rd_bits_data_T_715; + wire [31:0] _io_rd_bits_data_T_723 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_719[3:0], _io_rd_bits_data_T_719[31:4]} + : _io_rd_bits_data_T_719; + wire [31:0] _io_rd_bits_data_T_727 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_723[7:0], _io_rd_bits_data_T_723[31:8]} + : _io_rd_bits_data_T_723; + wire [31:0] _io_rd_bits_data_T_778 = + op == 6'h15 + ? {26'h0, + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[0]} + {1'h0, io_rs1_data[1]}} + + {1'h0, {1'h0, io_rs1_data[2]} + {1'h0, io_rs1_data[3]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[4]} + {1'h0, io_rs1_data[5]}} + + {1'h0, {1'h0, io_rs1_data[6]} + {1'h0, io_rs1_data[7]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[8]} + {1'h0, io_rs1_data[9]}} + + {1'h0, {1'h0, io_rs1_data[10]} + {1'h0, io_rs1_data[11]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[12]} + {1'h0, io_rs1_data[13]}} + + {1'h0, {1'h0, io_rs1_data[14]} + {1'h0, io_rs1_data[15]}}}}} + + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[16]} + {1'h0, io_rs1_data[17]}} + + {1'h0, {1'h0, io_rs1_data[18]} + {1'h0, io_rs1_data[19]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[20]} + {1'h0, io_rs1_data[21]}} + + {1'h0, {1'h0, io_rs1_data[22]} + {1'h0, io_rs1_data[23]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[24]} + {1'h0, io_rs1_data[25]}} + + {1'h0, {1'h0, io_rs1_data[26]} + {1'h0, io_rs1_data[27]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[28]} + {1'h0, io_rs1_data[29]}} + + {1'h0, {1'h0, io_rs1_data[30]} + {1'h0, io_rs1_data[31]}}}}}} + : op == 6'h14 + ? {26'h0, + io_rs1_data[0] + ? 6'h0 + : io_rs1_data[1] + ? 6'h1 + : io_rs1_data[2] + ? 6'h2 + : io_rs1_data[3] + ? 6'h3 + : io_rs1_data[4] + ? 6'h4 + : io_rs1_data[5] + ? 6'h5 + : io_rs1_data[6] + ? 6'h6 + : io_rs1_data[7] + ? 6'h7 + : io_rs1_data[8] + ? 6'h8 + : io_rs1_data[9] + ? 6'h9 + : io_rs1_data[10] + ? 6'hA + : io_rs1_data[11] + ? 6'hB + : io_rs1_data[12] + ? 6'hC + : io_rs1_data[13] + ? 6'hD + : io_rs1_data[14] + ? 6'hE + : io_rs1_data[15] + ? 6'hF + : io_rs1_data[16] + ? 6'h10 + : io_rs1_data[17] + ? 6'h11 + : io_rs1_data[18] + ? 6'h12 + : io_rs1_data[19] + ? 6'h13 + : io_rs1_data[20] + ? 6'h14 + : io_rs1_data[21] + ? 6'h15 + : io_rs1_data[22] + ? 6'h16 + : io_rs1_data[23] + ? 6'h17 + : io_rs1_data[24] + ? 6'h18 + : io_rs1_data[25] + ? 6'h19 + : io_rs1_data[26] + ? 6'h1A + : io_rs1_data[27] + ? 6'h1B + : io_rs1_data[28] + ? 6'h1C + : io_rs1_data[29] + ? 6'h1D + : io_rs1_data[30] + ? 6'h1E + : io_rs1_data[31] + ? 6'h1F + : 6'h20} + : op == 6'h13 + ? {26'h0, + _io_rd_bits_data_T_96[0] + ? 6'h0 + : _io_rd_bits_data_T_96[1] + ? 6'h1 + : _io_rd_bits_data_T_96[2] + ? 6'h2 + : _io_rd_bits_data_T_96[3] + ? 6'h3 + : _io_rd_bits_data_T_96[4] + ? 6'h4 + : _io_rd_bits_data_T_96[5] + ? 6'h5 + : _io_rd_bits_data_T_96[6] + ? 6'h6 + : _io_rd_bits_data_T_96[7] + ? 6'h7 + : _io_rd_bits_data_T_96[8] + ? 6'h8 + : _io_rd_bits_data_T_96[9] + ? 6'h9 + : _io_rd_bits_data_T_96[10] + ? 6'hA + : _io_rd_bits_data_T_96[11] + ? 6'hB + : _io_rd_bits_data_T_96[12] + ? 6'hC + : _io_rd_bits_data_T_96[13] + ? 6'hD + : _io_rd_bits_data_T_96[14] + ? 6'hE + : _io_rd_bits_data_T_96[15] + ? 6'hF + : _io_rd_bits_data_T_96[16] + ? 6'h10 + : _io_rd_bits_data_T_96[17] + ? 6'h11 + : _io_rd_bits_data_T_96[18] + ? 6'h12 + : _io_rd_bits_data_T_96[19] + ? 6'h13 + : _io_rd_bits_data_T_96[20] + ? 6'h14 + : _io_rd_bits_data_T_96[21] + ? 6'h15 + : _io_rd_bits_data_T_96[22] + ? 6'h16 + : _io_rd_bits_data_T_96[23] + ? 6'h17 + : _io_rd_bits_data_T_96[24] + ? 6'h18 + : _io_rd_bits_data_T_96[25] + ? 6'h19 + : _io_rd_bits_data_T_96[26] + ? 6'h1A + : _io_rd_bits_data_T_96[27] + ? 6'h1B + : _io_rd_bits_data_T_96[28] + ? 6'h1C + : _io_rd_bits_data_T_96[29] + ? 6'h1D + : _io_rd_bits_data_T_96[30] + ? 6'h1E + : _io_rd_bits_data_T_96[31] + ? 6'h1F + : 6'h20} + : op == 6'h12 + ? ~_io_rd_bits_data_T_46 + : op == 6'h11 + ? io_rs1_data | ~io_rs2_data + : op == 6'h10 + ? io_rs1_data & ~io_rs2_data + : op == 6'hF + ? $signed($signed(io_rs1_data) >>> _GEN_1) + : op == 6'hE + ? io_rs1_data >> _GEN_1 + : op == 6'hD + ? _io_rd_bits_data_T_26[31:0] + : op == 6'hC + ? _io_rd_bits_data_T_20 + : op == 6'hB + ? _io_rd_bits_data_T_15 + : op == 6'hA + ? io_rs2_data + : op == 6'h9 + ? $signed($signed(io_rs1_data) + >>> _GEN_1) + : op == 6'h8 + ? io_rs1_data >> _GEN_1 + : op == 6'h7 + ? _io_rd_bits_data_T_7[31:0] + : op == 6'h6 + ? io_rs1_data + & io_rs2_data + : op == 6'h5 + ? io_rs1_data + | io_rs2_data + : op == 6'h4 + ? _io_rd_bits_data_T_46 + : op == 6'h3 + ? {31'h0, + r2IsGreaterU} + : op == 6'h2 + ? {31'h0, + r2IsGreater} + : op == 6'h1 + ? _io_rd_bits_data_T_20 + : op == 6'h0 + ? _io_rd_bits_data_T_15 + : 32'h0; + wire [31:0] _io_rd_bits_data_T_806 = + op == 6'h23 + ? {26'h0, + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[0]} + {1'h0, io_rs1_data[1]}} + + {1'h0, {1'h0, io_rs1_data[2]} + {1'h0, io_rs1_data[3]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[4]} + {1'h0, io_rs1_data[5]}} + + {1'h0, {1'h0, io_rs1_data[6]} + {1'h0, io_rs1_data[7]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[8]} + {1'h0, io_rs1_data[9]}} + + {1'h0, {1'h0, io_rs1_data[10]} + {1'h0, io_rs1_data[11]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[12]} + {1'h0, io_rs1_data[13]}} + + {1'h0, {1'h0, io_rs1_data[14]} + {1'h0, io_rs1_data[15]}}}}} + + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[16]} + {1'h0, io_rs1_data[17]}} + + {1'h0, {1'h0, io_rs1_data[18]} + {1'h0, io_rs1_data[19]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[20]} + {1'h0, io_rs1_data[21]}} + + {1'h0, {1'h0, io_rs1_data[22]} + {1'h0, io_rs1_data[23]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[24]} + {1'h0, io_rs1_data[25]}} + + {1'h0, {1'h0, io_rs1_data[26]} + {1'h0, io_rs1_data[27]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[28]} + {1'h0, io_rs1_data[29]}} + + {1'h0, {1'h0, io_rs1_data[30]} + {1'h0, io_rs1_data[31]}}}}}} + : op == 6'h22 + ? {26'h0, + io_rs1_data[0] + ? 6'h0 + : io_rs1_data[1] + ? 6'h1 + : io_rs1_data[2] + ? 6'h2 + : io_rs1_data[3] + ? 6'h3 + : io_rs1_data[4] + ? 6'h4 + : io_rs1_data[5] + ? 6'h5 + : io_rs1_data[6] + ? 6'h6 + : io_rs1_data[7] + ? 6'h7 + : io_rs1_data[8] + ? 6'h8 + : io_rs1_data[9] + ? 6'h9 + : io_rs1_data[10] + ? 6'hA + : io_rs1_data[11] + ? 6'hB + : io_rs1_data[12] + ? 6'hC + : io_rs1_data[13] + ? 6'hD + : io_rs1_data[14] + ? 6'hE + : io_rs1_data[15] + ? 6'hF + : io_rs1_data[16] + ? 6'h10 + : io_rs1_data[17] + ? 6'h11 + : io_rs1_data[18] + ? 6'h12 + : io_rs1_data[19] + ? 6'h13 + : io_rs1_data[20] + ? 6'h14 + : io_rs1_data[21] + ? 6'h15 + : io_rs1_data[22] + ? 6'h16 + : io_rs1_data[23] + ? 6'h17 + : io_rs1_data[24] + ? 6'h18 + : io_rs1_data[25] + ? 6'h19 + : io_rs1_data[26] + ? 6'h1A + : io_rs1_data[27] + ? 6'h1B + : io_rs1_data[28] + ? 6'h1C + : io_rs1_data[29] + ? 6'h1D + : io_rs1_data[30] + ? 6'h1E + : io_rs1_data[31] + ? 6'h1F + : 6'h20} + : op == 6'h21 + ? {26'h0, + _io_rd_bits_data_T_440[0] + ? 6'h0 + : _io_rd_bits_data_T_440[1] + ? 6'h1 + : _io_rd_bits_data_T_440[2] + ? 6'h2 + : _io_rd_bits_data_T_440[3] + ? 6'h3 + : _io_rd_bits_data_T_440[4] + ? 6'h4 + : _io_rd_bits_data_T_440[5] + ? 6'h5 + : _io_rd_bits_data_T_440[6] + ? 6'h6 + : _io_rd_bits_data_T_440[7] + ? 6'h7 + : _io_rd_bits_data_T_440[8] + ? 6'h8 + : _io_rd_bits_data_T_440[9] + ? 6'h9 + : _io_rd_bits_data_T_440[10] + ? 6'hA + : _io_rd_bits_data_T_440[11] + ? 6'hB + : _io_rd_bits_data_T_440[12] + ? 6'hC + : _io_rd_bits_data_T_440[13] + ? 6'hD + : _io_rd_bits_data_T_440[14] + ? 6'hE + : _io_rd_bits_data_T_440[15] + ? 6'hF + : _io_rd_bits_data_T_440[16] + ? 6'h10 + : _io_rd_bits_data_T_440[17] + ? 6'h11 + : _io_rd_bits_data_T_440[18] + ? 6'h12 + : _io_rd_bits_data_T_440[19] + ? 6'h13 + : _io_rd_bits_data_T_440[20] + ? 6'h14 + : _io_rd_bits_data_T_440[21] + ? 6'h15 + : _io_rd_bits_data_T_440[22] + ? 6'h16 + : _io_rd_bits_data_T_440[23] + ? 6'h17 + : _io_rd_bits_data_T_440[24] + ? 6'h18 + : _io_rd_bits_data_T_440[25] + ? 6'h19 + : _io_rd_bits_data_T_440[26] + ? 6'h1A + : _io_rd_bits_data_T_440[27] + ? 6'h1B + : _io_rd_bits_data_T_440[28] + ? 6'h1C + : _io_rd_bits_data_T_440[29] + ? 6'h1D + : _io_rd_bits_data_T_440[30] + ? 6'h1E + : _io_rd_bits_data_T_440[31] + ? 6'h1F + : 6'h20} + : op == 6'h20 + ? {16'h0, io_rs1_data[15:0]} + : op == 6'h1F + ? {io_rs1_data[7:0], + io_rs1_data[15:8], + io_rs1_data[23:16], + io_rs1_data[31:24]} + : op == 6'h1E + ? {io_rs1_data[31:24] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[23:16] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[15:8] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[7:0] == 8'h0 ? 8'h0 : 8'hFF} + : op == 6'h1D + ? (io_rs2_data[4] + ? {_io_rd_bits_data_T_380[15:0], + _io_rd_bits_data_T_380[31:16]} + : _io_rd_bits_data_T_380) + : op == 6'h1C + ? (io_rs2_data[4] + ? {_io_rd_bits_data_T_355[15:0], + _io_rd_bits_data_T_355[31:16]} + : _io_rd_bits_data_T_355) + : op == 6'h1B + ? {{16{io_rs1_data[15]}}, io_rs1_data[15:0]} + : op == 6'h1A + ? {{24{io_rs1_data[7]}}, io_rs1_data[7:0]} + : op == 6'h19 + ? (r2IsGreaterU ? io_rs1_data : io_rs2_data) + : op == 6'h18 + ? (r2IsGreater + ? io_rs1_data + : io_rs2_data) + : op == 6'h17 + ? (r2IsGreaterU + ? io_rs2_data + : io_rs1_data) + : op == 6'h16 + ? (r2IsGreater + ? io_rs2_data + : io_rs1_data) + : _io_rd_bits_data_T_778; always @(posedge clock or posedge reset) begin if (reset) begin - mem_0_pc <= 32'h0; - mem_0_addr <= 32'h0; - mem_0_adrx <= 32'h0; - mem_0_data <= 32'h0; - mem_0_index <= 5'h0; - mem_0_size <= 5'h0; - mem_0_fullsize <= 5'h0; - mem_0_write <= 1'h0; - mem_0_sext <= 1'h0; - mem_0_iload <= 1'h0; - mem_0_fencei <= 1'h0; - mem_0_flushat <= 1'h0; - mem_0_flushall <= 1'h0; - mem_0_sldst <= 1'h0; - mem_0_vldst <= 1'h0; - mem_0_fldst <= 1'h0; - mem_0_regionType <= 2'h0; - mem_0_mask <= 16'h0; - mem_0_last <= 1'h0; - mem_1_pc <= 32'h0; - mem_1_addr <= 32'h0; - mem_1_adrx <= 32'h0; - mem_1_data <= 32'h0; - mem_1_index <= 5'h0; - mem_1_size <= 5'h0; - mem_1_fullsize <= 5'h0; - mem_1_write <= 1'h0; - mem_1_sext <= 1'h0; - mem_1_iload <= 1'h0; - mem_1_fencei <= 1'h0; - mem_1_flushat <= 1'h0; - mem_1_flushall <= 1'h0; - mem_1_sldst <= 1'h0; - mem_1_vldst <= 1'h0; - mem_1_fldst <= 1'h0; - mem_1_regionType <= 2'h0; - mem_1_mask <= 16'h0; - mem_1_last <= 1'h0; - mem_2_pc <= 32'h0; - mem_2_addr <= 32'h0; - mem_2_adrx <= 32'h0; - mem_2_data <= 32'h0; - mem_2_index <= 5'h0; - mem_2_size <= 5'h0; - mem_2_fullsize <= 5'h0; - mem_2_write <= 1'h0; - mem_2_sext <= 1'h0; - mem_2_iload <= 1'h0; - mem_2_fencei <= 1'h0; - mem_2_flushat <= 1'h0; - mem_2_flushall <= 1'h0; - mem_2_sldst <= 1'h0; - mem_2_vldst <= 1'h0; - mem_2_fldst <= 1'h0; - mem_2_regionType <= 2'h0; - mem_2_mask <= 16'h0; - mem_2_last <= 1'h0; - mem_3_pc <= 32'h0; - mem_3_addr <= 32'h0; - mem_3_adrx <= 32'h0; - mem_3_data <= 32'h0; - mem_3_index <= 5'h0; - mem_3_size <= 5'h0; - mem_3_fullsize <= 5'h0; - mem_3_write <= 1'h0; - mem_3_sext <= 1'h0; - mem_3_iload <= 1'h0; - mem_3_fencei <= 1'h0; - mem_3_flushat <= 1'h0; - mem_3_flushall <= 1'h0; - mem_3_sldst <= 1'h0; - mem_3_vldst <= 1'h0; - mem_3_fldst <= 1'h0; - mem_3_regionType <= 2'h0; - mem_3_mask <= 16'h0; - mem_3_last <= 1'h0; - mem_4_pc <= 32'h0; - mem_4_addr <= 32'h0; - mem_4_adrx <= 32'h0; - mem_4_data <= 32'h0; - mem_4_index <= 5'h0; - mem_4_size <= 5'h0; - mem_4_fullsize <= 5'h0; - mem_4_write <= 1'h0; - mem_4_sext <= 1'h0; - mem_4_iload <= 1'h0; - mem_4_fencei <= 1'h0; - mem_4_flushat <= 1'h0; - mem_4_flushall <= 1'h0; - mem_4_sldst <= 1'h0; - mem_4_vldst <= 1'h0; - mem_4_fldst <= 1'h0; - mem_4_regionType <= 2'h0; - mem_4_mask <= 16'h0; - mem_4_last <= 1'h0; - mem_5_pc <= 32'h0; - mem_5_addr <= 32'h0; - mem_5_adrx <= 32'h0; - mem_5_data <= 32'h0; - mem_5_index <= 5'h0; - mem_5_size <= 5'h0; - mem_5_fullsize <= 5'h0; - mem_5_write <= 1'h0; - mem_5_sext <= 1'h0; - mem_5_iload <= 1'h0; - mem_5_fencei <= 1'h0; - mem_5_flushat <= 1'h0; - mem_5_flushall <= 1'h0; - mem_5_sldst <= 1'h0; - mem_5_vldst <= 1'h0; - mem_5_fldst <= 1'h0; - mem_5_regionType <= 2'h0; - mem_5_mask <= 16'h0; - mem_5_last <= 1'h0; - mem_6_pc <= 32'h0; - mem_6_addr <= 32'h0; - mem_6_adrx <= 32'h0; - mem_6_data <= 32'h0; - mem_6_index <= 5'h0; - mem_6_size <= 5'h0; - mem_6_fullsize <= 5'h0; - mem_6_write <= 1'h0; - mem_6_sext <= 1'h0; - mem_6_iload <= 1'h0; - mem_6_fencei <= 1'h0; - mem_6_flushat <= 1'h0; - mem_6_flushall <= 1'h0; - mem_6_sldst <= 1'h0; - mem_6_vldst <= 1'h0; - mem_6_fldst <= 1'h0; - mem_6_regionType <= 2'h0; - mem_6_mask <= 16'h0; - mem_6_last <= 1'h0; - mem_7_pc <= 32'h0; - mem_7_addr <= 32'h0; - mem_7_adrx <= 32'h0; - mem_7_data <= 32'h0; - mem_7_index <= 5'h0; - mem_7_size <= 5'h0; - mem_7_fullsize <= 5'h0; - mem_7_write <= 1'h0; - mem_7_sext <= 1'h0; - mem_7_iload <= 1'h0; - mem_7_fencei <= 1'h0; - mem_7_flushat <= 1'h0; - mem_7_flushall <= 1'h0; - mem_7_sldst <= 1'h0; - mem_7_vldst <= 1'h0; - mem_7_fldst <= 1'h0; - mem_7_regionType <= 2'h0; - mem_7_mask <= 16'h0; - mem_7_last <= 1'h0; - inxpos_0 <= 3'h0; - inxpos_1 <= 3'h1; - inxpos_2 <= 3'h2; - inxpos_3 <= 3'h3; - inxpos_4 <= 3'h4; - inxpos_5 <= 3'h5; - inxpos_6 <= 3'h6; - inxpos_7 <= 3'h7; - outpos <= 4'h0; - mcount <= 4'h0; + valid <= 1'h0; + addr <= 5'h0; + op <= 6'h0; end else begin - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_135} + {1'h0, _valid_T_132}} - + {1'h0, {1'h0, _valid_T_125} + {1'h0, _valid_T_114}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_99} + {1'h0, _valid_T_80}} - + {1'h0, - {1'h0, _valid_T_57} - + {1'h0, - _valid_T_133 & _inxvalid_T_25 | _valid_T_129 & _inxvalid_T_149 - | _valid_T_121 & _inxvalid_T_268 | _valid_T_109 - & _inxvalid_T_379 | _valid_T_93 & _inxvalid_T_479 - | _valid_T_73 & _inxvalid_T_565 | _valid_T_49 - & _inxvalid_T_634 | inxpos_7 == 3'h0 - & _inxvalid_T_683}}}))) begin - mem_0_pc <= _GEN_8[idx]; - mem_0_addr <= _GEN_9[idx]; - mem_0_adrx <= _GEN_10[idx]; - mem_0_data <= _GEN_11[idx]; - mem_0_index <= _GEN_12[idx]; - mem_0_size <= _GEN_13[idx]; - mem_0_fullsize <= _GEN_14[idx]; - mem_0_write <= _GEN_15[idx]; - mem_0_sext <= _GEN_16[idx]; - mem_0_iload <= _GEN_17[idx]; - mem_0_fencei <= _GEN_18[idx]; - mem_0_flushat <= _GEN_19[idx]; - mem_0_flushall <= _GEN_20[idx]; - mem_0_sldst <= _GEN_21[idx]; - mem_0_vldst <= _GEN_22[idx]; - mem_0_fldst <= _GEN_23[idx]; - mem_0_regionType <= _GEN_24[idx]; - mem_0_mask <= _GEN_25[idx]; - mem_0_last <= _GEN_46[idx]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_271} + {1'h0, _valid_T_268}} - + {1'h0, {1'h0, _valid_T_261} + {1'h0, _valid_T_250}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_235} + {1'h0, _valid_T_216}} - + {1'h0, - {1'h0, _valid_T_193} - + {1'h0, - _valid_T_269 & _inxvalid_T_25 | _valid_T_265 & _inxvalid_T_149 - | _valid_T_257 & _inxvalid_T_268 | _valid_T_245 - & _inxvalid_T_379 | _valid_T_229 & _inxvalid_T_479 - | _valid_T_209 & _inxvalid_T_565 | _valid_T_185 - & _inxvalid_T_634 | inxpos_7 == 3'h1 - & _inxvalid_T_683}}}))) begin - mem_1_pc <= _GEN_8[idx_1]; - mem_1_addr <= _GEN_9[idx_1]; - mem_1_adrx <= _GEN_10[idx_1]; - mem_1_data <= _GEN_11[idx_1]; - mem_1_index <= _GEN_12[idx_1]; - mem_1_size <= _GEN_13[idx_1]; - mem_1_fullsize <= _GEN_14[idx_1]; - mem_1_write <= _GEN_15[idx_1]; - mem_1_sext <= _GEN_16[idx_1]; - mem_1_iload <= _GEN_17[idx_1]; - mem_1_fencei <= _GEN_18[idx_1]; - mem_1_flushat <= _GEN_19[idx_1]; - mem_1_flushall <= _GEN_20[idx_1]; - mem_1_sldst <= _GEN_21[idx_1]; - mem_1_vldst <= _GEN_22[idx_1]; - mem_1_fldst <= _GEN_23[idx_1]; - mem_1_regionType <= _GEN_24[idx_1]; - mem_1_mask <= _GEN_25[idx_1]; - mem_1_last <= _GEN_47[idx_1]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_407} + {1'h0, _valid_T_404}} - + {1'h0, {1'h0, _valid_T_397} + {1'h0, _valid_T_386}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_371} + {1'h0, _valid_T_352}} - + {1'h0, - {1'h0, _valid_T_329} - + {1'h0, - _valid_T_405 & _inxvalid_T_25 | _valid_T_401 & _inxvalid_T_149 - | _valid_T_393 & _inxvalid_T_268 | _valid_T_381 - & _inxvalid_T_379 | _valid_T_365 & _inxvalid_T_479 - | _valid_T_345 & _inxvalid_T_565 | _valid_T_321 - & _inxvalid_T_634 | inxpos_7 == 3'h2 - & _inxvalid_T_683}}}))) begin - mem_2_pc <= _GEN_8[idx_2]; - mem_2_addr <= _GEN_9[idx_2]; - mem_2_adrx <= _GEN_10[idx_2]; - mem_2_data <= _GEN_11[idx_2]; - mem_2_index <= _GEN_12[idx_2]; - mem_2_size <= _GEN_13[idx_2]; - mem_2_fullsize <= _GEN_14[idx_2]; - mem_2_write <= _GEN_15[idx_2]; - mem_2_sext <= _GEN_16[idx_2]; - mem_2_iload <= _GEN_17[idx_2]; - mem_2_fencei <= _GEN_18[idx_2]; - mem_2_flushat <= _GEN_19[idx_2]; - mem_2_flushall <= _GEN_20[idx_2]; - mem_2_sldst <= _GEN_21[idx_2]; - mem_2_vldst <= _GEN_22[idx_2]; - mem_2_fldst <= _GEN_23[idx_2]; - mem_2_regionType <= _GEN_24[idx_2]; - mem_2_mask <= _GEN_25[idx_2]; - mem_2_last <= _GEN_48[idx_2]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_543} + {1'h0, _valid_T_540}} - + {1'h0, {1'h0, _valid_T_533} + {1'h0, _valid_T_522}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_507} + {1'h0, _valid_T_488}} - + {1'h0, - {1'h0, _valid_T_465} - + {1'h0, - _valid_T_541 & _inxvalid_T_25 | _valid_T_537 & _inxvalid_T_149 - | _valid_T_529 & _inxvalid_T_268 | _valid_T_517 - & _inxvalid_T_379 | _valid_T_501 & _inxvalid_T_479 - | _valid_T_481 & _inxvalid_T_565 | _valid_T_457 - & _inxvalid_T_634 | inxpos_7 == 3'h3 - & _inxvalid_T_683}}}))) begin - mem_3_pc <= _GEN_8[idx_3]; - mem_3_addr <= _GEN_9[idx_3]; - mem_3_adrx <= _GEN_10[idx_3]; - mem_3_data <= _GEN_11[idx_3]; - mem_3_index <= _GEN_12[idx_3]; - mem_3_size <= _GEN_13[idx_3]; - mem_3_fullsize <= _GEN_14[idx_3]; - mem_3_write <= _GEN_15[idx_3]; - mem_3_sext <= _GEN_16[idx_3]; - mem_3_iload <= _GEN_17[idx_3]; - mem_3_fencei <= _GEN_18[idx_3]; - mem_3_flushat <= _GEN_19[idx_3]; - mem_3_flushall <= _GEN_20[idx_3]; - mem_3_sldst <= _GEN_21[idx_3]; - mem_3_vldst <= _GEN_22[idx_3]; - mem_3_fldst <= _GEN_23[idx_3]; - mem_3_regionType <= _GEN_24[idx_3]; - mem_3_mask <= _GEN_25[idx_3]; - mem_3_last <= _GEN_49[idx_3]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_679} + {1'h0, _valid_T_676}} - + {1'h0, {1'h0, _valid_T_669} + {1'h0, _valid_T_658}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_643} + {1'h0, _valid_T_624}} - + {1'h0, - {1'h0, _valid_T_601} - + {1'h0, - _valid_T_677 & _inxvalid_T_25 | _valid_T_673 & _inxvalid_T_149 - | _valid_T_665 & _inxvalid_T_268 | _valid_T_653 - & _inxvalid_T_379 | _valid_T_637 & _inxvalid_T_479 - | _valid_T_617 & _inxvalid_T_565 | _valid_T_593 - & _inxvalid_T_634 | inxpos_7 == 3'h4 - & _inxvalid_T_683}}}))) begin - mem_4_pc <= _GEN_8[idx_4]; - mem_4_addr <= _GEN_9[idx_4]; - mem_4_adrx <= _GEN_10[idx_4]; - mem_4_data <= _GEN_11[idx_4]; - mem_4_index <= _GEN_12[idx_4]; - mem_4_size <= _GEN_13[idx_4]; - mem_4_fullsize <= _GEN_14[idx_4]; - mem_4_write <= _GEN_15[idx_4]; - mem_4_sext <= _GEN_16[idx_4]; - mem_4_iload <= _GEN_17[idx_4]; - mem_4_fencei <= _GEN_18[idx_4]; - mem_4_flushat <= _GEN_19[idx_4]; - mem_4_flushall <= _GEN_20[idx_4]; - mem_4_sldst <= _GEN_21[idx_4]; - mem_4_vldst <= _GEN_22[idx_4]; - mem_4_fldst <= _GEN_23[idx_4]; - mem_4_regionType <= _GEN_24[idx_4]; - mem_4_mask <= _GEN_25[idx_4]; - mem_4_last <= _GEN_50[idx_4]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_815} + {1'h0, _valid_T_812}} - + {1'h0, {1'h0, _valid_T_805} + {1'h0, _valid_T_794}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_779} + {1'h0, _valid_T_760}} - + {1'h0, - {1'h0, _valid_T_737} - + {1'h0, - _valid_T_813 & _inxvalid_T_25 | _valid_T_809 & _inxvalid_T_149 - | _valid_T_801 & _inxvalid_T_268 | _valid_T_789 - & _inxvalid_T_379 | _valid_T_773 & _inxvalid_T_479 - | _valid_T_753 & _inxvalid_T_565 | _valid_T_729 - & _inxvalid_T_634 | inxpos_7 == 3'h5 - & _inxvalid_T_683}}}))) begin - mem_5_pc <= _GEN_8[idx_5]; - mem_5_addr <= _GEN_9[idx_5]; - mem_5_adrx <= _GEN_10[idx_5]; - mem_5_data <= _GEN_11[idx_5]; - mem_5_index <= _GEN_12[idx_5]; - mem_5_size <= _GEN_13[idx_5]; - mem_5_fullsize <= _GEN_14[idx_5]; - mem_5_write <= _GEN_15[idx_5]; - mem_5_sext <= _GEN_16[idx_5]; - mem_5_iload <= _GEN_17[idx_5]; - mem_5_fencei <= _GEN_18[idx_5]; - mem_5_flushat <= _GEN_19[idx_5]; - mem_5_flushall <= _GEN_20[idx_5]; - mem_5_sldst <= _GEN_21[idx_5]; - mem_5_vldst <= _GEN_22[idx_5]; - mem_5_fldst <= _GEN_23[idx_5]; - mem_5_regionType <= _GEN_24[idx_5]; - mem_5_mask <= _GEN_25[idx_5]; - mem_5_last <= _GEN_51[idx_5]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_951} + {1'h0, _valid_T_948}} - + {1'h0, {1'h0, _valid_T_941} + {1'h0, _valid_T_930}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_915} + {1'h0, _valid_T_896}} - + {1'h0, - {1'h0, _valid_T_873} - + {1'h0, - _valid_T_949 & _inxvalid_T_25 | _valid_T_945 & _inxvalid_T_149 - | _valid_T_937 & _inxvalid_T_268 | _valid_T_925 - & _inxvalid_T_379 | _valid_T_909 & _inxvalid_T_479 - | _valid_T_889 & _inxvalid_T_565 | _valid_T_865 - & _inxvalid_T_634 | inxpos_7 == 3'h6 - & _inxvalid_T_683}}}))) begin - mem_6_pc <= _GEN_8[idx_6]; - mem_6_addr <= _GEN_9[idx_6]; - mem_6_adrx <= _GEN_10[idx_6]; - mem_6_data <= _GEN_11[idx_6]; - mem_6_index <= _GEN_12[idx_6]; - mem_6_size <= _GEN_13[idx_6]; - mem_6_fullsize <= _GEN_14[idx_6]; - mem_6_write <= _GEN_15[idx_6]; - mem_6_sext <= _GEN_16[idx_6]; - mem_6_iload <= _GEN_17[idx_6]; - mem_6_fencei <= _GEN_18[idx_6]; - mem_6_flushat <= _GEN_19[idx_6]; - mem_6_flushall <= _GEN_20[idx_6]; - mem_6_sldst <= _GEN_21[idx_6]; - mem_6_vldst <= _GEN_22[idx_6]; - mem_6_fldst <= _GEN_23[idx_6]; - mem_6_regionType <= _GEN_24[idx_6]; - mem_6_mask <= _GEN_25[idx_6]; - mem_6_last <= _GEN_52[idx_6]; - end - if (ivalid - & (|({1'h0, - {1'h0, {1'h0, _valid_T_1087} + {1'h0, _valid_T_1084}} - + {1'h0, {1'h0, _valid_T_1077} + {1'h0, _valid_T_1066}}} - + {1'h0, - {1'h0, {1'h0, _valid_T_1051} + {1'h0, _valid_T_1032}} - + {1'h0, - {1'h0, _valid_T_1009} - + {1'h0, - (&inxpos_0) & _inxvalid_T_25 | (&inxpos_1) & _inxvalid_T_149 - | (&inxpos_2) & _inxvalid_T_268 | (&inxpos_3) - & _inxvalid_T_379 | (&inxpos_4) & _inxvalid_T_479 - | (&inxpos_5) & _inxvalid_T_565 | (&inxpos_6) - & _inxvalid_T_634 | (&inxpos_7) - & _inxvalid_T_683}}}))) begin - mem_7_pc <= _GEN_8[idx_7]; - mem_7_addr <= _GEN_9[idx_7]; - mem_7_adrx <= _GEN_10[idx_7]; - mem_7_data <= _GEN_11[idx_7]; - mem_7_index <= _GEN_12[idx_7]; - mem_7_size <= _GEN_13[idx_7]; - mem_7_fullsize <= _GEN_14[idx_7]; - mem_7_write <= _GEN_15[idx_7]; - mem_7_sext <= _GEN_16[idx_7]; - mem_7_iload <= _GEN_17[idx_7]; - mem_7_fencei <= _GEN_18[idx_7]; - mem_7_flushat <= _GEN_19[idx_7]; - mem_7_flushall <= _GEN_20[idx_7]; - mem_7_sldst <= _GEN_21[idx_7]; - mem_7_vldst <= _GEN_22[idx_7]; - mem_7_fldst <= _GEN_23[idx_7]; - mem_7_regionType <= _GEN_24[idx_7]; - mem_7_mask <= _GEN_25[idx_7]; - mem_7_last <= _GEN_53[idx_7]; - end - if (ivalid) begin - inxpos_0 <= inxpos_0 + icount[2:0]; - inxpos_1 <= inxpos_1 + icount[2:0]; - inxpos_2 <= inxpos_2 + icount[2:0]; - inxpos_3 <= inxpos_3 + icount[2:0]; - inxpos_4 <= inxpos_4 + icount[2:0]; - inxpos_5 <= inxpos_5 + icount[2:0]; - inxpos_6 <= inxpos_6 + icount[2:0]; - inxpos_7 <= inxpos_7 + icount[2:0]; + valid <= io_req_valid; + if (io_req_valid) begin + addr <= io_req_bits_addr; + op <= io_req_bits_op; end - if (dec) - outpos <= outpos_c < 5'h8 ? outpos_c[3:0] : outpos - 4'h7; - if (ivalid | dec) - mcount <= mcount + (ivalid ? icount : 4'h0) - {3'h0, dec}; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:49]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [5:0] i = 6'h0; i < 6'h32; i += 6'h1) begin - _RANDOM[i] = `RANDOM; - end - mem_0_pc = _RANDOM[6'h0]; - mem_0_addr = _RANDOM[6'h1]; - mem_0_adrx = _RANDOM[6'h2]; - mem_0_data = _RANDOM[6'h3]; - mem_0_index = _RANDOM[6'h4][4:0]; - mem_0_size = _RANDOM[6'h4][9:5]; - mem_0_fullsize = _RANDOM[6'h4][14:10]; - mem_0_write = _RANDOM[6'h4][15]; - mem_0_sext = _RANDOM[6'h4][16]; - mem_0_iload = _RANDOM[6'h4][17]; - mem_0_fencei = _RANDOM[6'h4][18]; - mem_0_flushat = _RANDOM[6'h4][19]; - mem_0_flushall = _RANDOM[6'h4][20]; - mem_0_sldst = _RANDOM[6'h4][21]; - mem_0_vldst = _RANDOM[6'h4][22]; - mem_0_fldst = _RANDOM[6'h4][23]; - mem_0_regionType = _RANDOM[6'h4][25:24]; - mem_0_mask = {_RANDOM[6'h4][31:26], _RANDOM[6'h5][9:0]}; - mem_0_last = _RANDOM[6'h5][10]; - mem_1_pc = {_RANDOM[6'h5][31:11], _RANDOM[6'h6][10:0]}; - mem_1_addr = {_RANDOM[6'h6][31:11], _RANDOM[6'h7][10:0]}; - mem_1_adrx = {_RANDOM[6'h7][31:11], _RANDOM[6'h8][10:0]}; - mem_1_data = {_RANDOM[6'h8][31:11], _RANDOM[6'h9][10:0]}; - mem_1_index = _RANDOM[6'h9][15:11]; - mem_1_size = _RANDOM[6'h9][20:16]; - mem_1_fullsize = _RANDOM[6'h9][25:21]; - mem_1_write = _RANDOM[6'h9][26]; - mem_1_sext = _RANDOM[6'h9][27]; - mem_1_iload = _RANDOM[6'h9][28]; - mem_1_fencei = _RANDOM[6'h9][29]; - mem_1_flushat = _RANDOM[6'h9][30]; - mem_1_flushall = _RANDOM[6'h9][31]; - mem_1_sldst = _RANDOM[6'hA][0]; - mem_1_vldst = _RANDOM[6'hA][1]; - mem_1_fldst = _RANDOM[6'hA][2]; - mem_1_regionType = _RANDOM[6'hA][4:3]; - mem_1_mask = _RANDOM[6'hA][20:5]; - mem_1_last = _RANDOM[6'hA][21]; - mem_2_pc = {_RANDOM[6'hA][31:22], _RANDOM[6'hB][21:0]}; - mem_2_addr = {_RANDOM[6'hB][31:22], _RANDOM[6'hC][21:0]}; - mem_2_adrx = {_RANDOM[6'hC][31:22], _RANDOM[6'hD][21:0]}; - mem_2_data = {_RANDOM[6'hD][31:22], _RANDOM[6'hE][21:0]}; - mem_2_index = _RANDOM[6'hE][26:22]; - mem_2_size = _RANDOM[6'hE][31:27]; - mem_2_fullsize = _RANDOM[6'hF][4:0]; - mem_2_write = _RANDOM[6'hF][5]; - mem_2_sext = _RANDOM[6'hF][6]; - mem_2_iload = _RANDOM[6'hF][7]; - mem_2_fencei = _RANDOM[6'hF][8]; - mem_2_flushat = _RANDOM[6'hF][9]; - mem_2_flushall = _RANDOM[6'hF][10]; - mem_2_sldst = _RANDOM[6'hF][11]; - mem_2_vldst = _RANDOM[6'hF][12]; - mem_2_fldst = _RANDOM[6'hF][13]; - mem_2_regionType = _RANDOM[6'hF][15:14]; - mem_2_mask = _RANDOM[6'hF][31:16]; - mem_2_last = _RANDOM[6'h10][0]; - mem_3_pc = {_RANDOM[6'h10][31:1], _RANDOM[6'h11][0]}; - mem_3_addr = {_RANDOM[6'h11][31:1], _RANDOM[6'h12][0]}; - mem_3_adrx = {_RANDOM[6'h12][31:1], _RANDOM[6'h13][0]}; - mem_3_data = {_RANDOM[6'h13][31:1], _RANDOM[6'h14][0]}; - mem_3_index = _RANDOM[6'h14][5:1]; - mem_3_size = _RANDOM[6'h14][10:6]; - mem_3_fullsize = _RANDOM[6'h14][15:11]; - mem_3_write = _RANDOM[6'h14][16]; - mem_3_sext = _RANDOM[6'h14][17]; - mem_3_iload = _RANDOM[6'h14][18]; - mem_3_fencei = _RANDOM[6'h14][19]; - mem_3_flushat = _RANDOM[6'h14][20]; - mem_3_flushall = _RANDOM[6'h14][21]; - mem_3_sldst = _RANDOM[6'h14][22]; - mem_3_vldst = _RANDOM[6'h14][23]; - mem_3_fldst = _RANDOM[6'h14][24]; - mem_3_regionType = _RANDOM[6'h14][26:25]; - mem_3_mask = {_RANDOM[6'h14][31:27], _RANDOM[6'h15][10:0]}; - mem_3_last = _RANDOM[6'h15][11]; - mem_4_pc = {_RANDOM[6'h15][31:12], _RANDOM[6'h16][11:0]}; - mem_4_addr = {_RANDOM[6'h16][31:12], _RANDOM[6'h17][11:0]}; - mem_4_adrx = {_RANDOM[6'h17][31:12], _RANDOM[6'h18][11:0]}; - mem_4_data = {_RANDOM[6'h18][31:12], _RANDOM[6'h19][11:0]}; - mem_4_index = _RANDOM[6'h19][16:12]; - mem_4_size = _RANDOM[6'h19][21:17]; - mem_4_fullsize = _RANDOM[6'h19][26:22]; - mem_4_write = _RANDOM[6'h19][27]; - mem_4_sext = _RANDOM[6'h19][28]; - mem_4_iload = _RANDOM[6'h19][29]; - mem_4_fencei = _RANDOM[6'h19][30]; - mem_4_flushat = _RANDOM[6'h19][31]; - mem_4_flushall = _RANDOM[6'h1A][0]; - mem_4_sldst = _RANDOM[6'h1A][1]; - mem_4_vldst = _RANDOM[6'h1A][2]; - mem_4_fldst = _RANDOM[6'h1A][3]; - mem_4_regionType = _RANDOM[6'h1A][5:4]; - mem_4_mask = _RANDOM[6'h1A][21:6]; - mem_4_last = _RANDOM[6'h1A][22]; - mem_5_pc = {_RANDOM[6'h1A][31:23], _RANDOM[6'h1B][22:0]}; - mem_5_addr = {_RANDOM[6'h1B][31:23], _RANDOM[6'h1C][22:0]}; - mem_5_adrx = {_RANDOM[6'h1C][31:23], _RANDOM[6'h1D][22:0]}; - mem_5_data = {_RANDOM[6'h1D][31:23], _RANDOM[6'h1E][22:0]}; - mem_5_index = _RANDOM[6'h1E][27:23]; - mem_5_size = {_RANDOM[6'h1E][31:28], _RANDOM[6'h1F][0]}; - mem_5_fullsize = _RANDOM[6'h1F][5:1]; - mem_5_write = _RANDOM[6'h1F][6]; - mem_5_sext = _RANDOM[6'h1F][7]; - mem_5_iload = _RANDOM[6'h1F][8]; - mem_5_fencei = _RANDOM[6'h1F][9]; - mem_5_flushat = _RANDOM[6'h1F][10]; - mem_5_flushall = _RANDOM[6'h1F][11]; - mem_5_sldst = _RANDOM[6'h1F][12]; - mem_5_vldst = _RANDOM[6'h1F][13]; - mem_5_fldst = _RANDOM[6'h1F][14]; - mem_5_regionType = _RANDOM[6'h1F][16:15]; - mem_5_mask = {_RANDOM[6'h1F][31:17], _RANDOM[6'h20][0]}; - mem_5_last = _RANDOM[6'h20][1]; - mem_6_pc = {_RANDOM[6'h20][31:2], _RANDOM[6'h21][1:0]}; - mem_6_addr = {_RANDOM[6'h21][31:2], _RANDOM[6'h22][1:0]}; - mem_6_adrx = {_RANDOM[6'h22][31:2], _RANDOM[6'h23][1:0]}; - mem_6_data = {_RANDOM[6'h23][31:2], _RANDOM[6'h24][1:0]}; - mem_6_index = _RANDOM[6'h24][6:2]; - mem_6_size = _RANDOM[6'h24][11:7]; - mem_6_fullsize = _RANDOM[6'h24][16:12]; - mem_6_write = _RANDOM[6'h24][17]; - mem_6_sext = _RANDOM[6'h24][18]; - mem_6_iload = _RANDOM[6'h24][19]; - mem_6_fencei = _RANDOM[6'h24][20]; - mem_6_flushat = _RANDOM[6'h24][21]; - mem_6_flushall = _RANDOM[6'h24][22]; - mem_6_sldst = _RANDOM[6'h24][23]; - mem_6_vldst = _RANDOM[6'h24][24]; - mem_6_fldst = _RANDOM[6'h24][25]; - mem_6_regionType = _RANDOM[6'h24][27:26]; - mem_6_mask = {_RANDOM[6'h24][31:28], _RANDOM[6'h25][11:0]}; - mem_6_last = _RANDOM[6'h25][12]; - mem_7_pc = {_RANDOM[6'h25][31:13], _RANDOM[6'h26][12:0]}; - mem_7_addr = {_RANDOM[6'h26][31:13], _RANDOM[6'h27][12:0]}; - mem_7_adrx = {_RANDOM[6'h27][31:13], _RANDOM[6'h28][12:0]}; - mem_7_data = {_RANDOM[6'h28][31:13], _RANDOM[6'h29][12:0]}; - mem_7_index = _RANDOM[6'h29][17:13]; - mem_7_size = _RANDOM[6'h29][22:18]; - mem_7_fullsize = _RANDOM[6'h29][27:23]; - mem_7_write = _RANDOM[6'h29][28]; - mem_7_sext = _RANDOM[6'h29][29]; - mem_7_iload = _RANDOM[6'h29][30]; - mem_7_fencei = _RANDOM[6'h29][31]; - mem_7_flushat = _RANDOM[6'h2A][0]; - mem_7_flushall = _RANDOM[6'h2A][1]; - mem_7_sldst = _RANDOM[6'h2A][2]; - mem_7_vldst = _RANDOM[6'h2A][3]; - mem_7_fldst = _RANDOM[6'h2A][4]; - mem_7_regionType = _RANDOM[6'h2A][6:5]; - mem_7_mask = _RANDOM[6'h2A][22:7]; - mem_7_last = _RANDOM[6'h2A][23]; - inxpos_0 = _RANDOM[6'h30][5:3]; - inxpos_1 = _RANDOM[6'h30][8:6]; - inxpos_2 = _RANDOM[6'h30][11:9]; - inxpos_3 = _RANDOM[6'h30][14:12]; - inxpos_4 = _RANDOM[6'h30][17:15]; - inxpos_5 = _RANDOM[6'h30][20:18]; - inxpos_6 = _RANDOM[6'h30][23:21]; - inxpos_7 = _RANDOM[6'h30][26:24]; - outpos = _RANDOM[6'h30][30:27]; - mcount = {_RANDOM[6'h30][31], _RANDOM[6'h31][2:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - mem_0_pc = 32'h0; - mem_0_addr = 32'h0; - mem_0_adrx = 32'h0; - mem_0_data = 32'h0; - mem_0_index = 5'h0; - mem_0_size = 5'h0; - mem_0_fullsize = 5'h0; - mem_0_write = 1'h0; - mem_0_sext = 1'h0; - mem_0_iload = 1'h0; - mem_0_fencei = 1'h0; - mem_0_flushat = 1'h0; - mem_0_flushall = 1'h0; - mem_0_sldst = 1'h0; - mem_0_vldst = 1'h0; - mem_0_fldst = 1'h0; - mem_0_regionType = 2'h0; - mem_0_mask = 16'h0; - mem_0_last = 1'h0; - mem_1_pc = 32'h0; - mem_1_addr = 32'h0; - mem_1_adrx = 32'h0; - mem_1_data = 32'h0; - mem_1_index = 5'h0; - mem_1_size = 5'h0; - mem_1_fullsize = 5'h0; - mem_1_write = 1'h0; - mem_1_sext = 1'h0; - mem_1_iload = 1'h0; - mem_1_fencei = 1'h0; - mem_1_flushat = 1'h0; - mem_1_flushall = 1'h0; - mem_1_sldst = 1'h0; - mem_1_vldst = 1'h0; - mem_1_fldst = 1'h0; - mem_1_regionType = 2'h0; - mem_1_mask = 16'h0; - mem_1_last = 1'h0; - mem_2_pc = 32'h0; - mem_2_addr = 32'h0; - mem_2_adrx = 32'h0; - mem_2_data = 32'h0; - mem_2_index = 5'h0; - mem_2_size = 5'h0; - mem_2_fullsize = 5'h0; - mem_2_write = 1'h0; - mem_2_sext = 1'h0; - mem_2_iload = 1'h0; - mem_2_fencei = 1'h0; - mem_2_flushat = 1'h0; - mem_2_flushall = 1'h0; - mem_2_sldst = 1'h0; - mem_2_vldst = 1'h0; - mem_2_fldst = 1'h0; - mem_2_regionType = 2'h0; - mem_2_mask = 16'h0; - mem_2_last = 1'h0; - mem_3_pc = 32'h0; - mem_3_addr = 32'h0; - mem_3_adrx = 32'h0; - mem_3_data = 32'h0; - mem_3_index = 5'h0; - mem_3_size = 5'h0; - mem_3_fullsize = 5'h0; - mem_3_write = 1'h0; - mem_3_sext = 1'h0; - mem_3_iload = 1'h0; - mem_3_fencei = 1'h0; - mem_3_flushat = 1'h0; - mem_3_flushall = 1'h0; - mem_3_sldst = 1'h0; - mem_3_vldst = 1'h0; - mem_3_fldst = 1'h0; - mem_3_regionType = 2'h0; - mem_3_mask = 16'h0; - mem_3_last = 1'h0; - mem_4_pc = 32'h0; - mem_4_addr = 32'h0; - mem_4_adrx = 32'h0; - mem_4_data = 32'h0; - mem_4_index = 5'h0; - mem_4_size = 5'h0; - mem_4_fullsize = 5'h0; - mem_4_write = 1'h0; - mem_4_sext = 1'h0; - mem_4_iload = 1'h0; - mem_4_fencei = 1'h0; - mem_4_flushat = 1'h0; - mem_4_flushall = 1'h0; - mem_4_sldst = 1'h0; - mem_4_vldst = 1'h0; - mem_4_fldst = 1'h0; - mem_4_regionType = 2'h0; - mem_4_mask = 16'h0; - mem_4_last = 1'h0; - mem_5_pc = 32'h0; - mem_5_addr = 32'h0; - mem_5_adrx = 32'h0; - mem_5_data = 32'h0; - mem_5_index = 5'h0; - mem_5_size = 5'h0; - mem_5_fullsize = 5'h0; - mem_5_write = 1'h0; - mem_5_sext = 1'h0; - mem_5_iload = 1'h0; - mem_5_fencei = 1'h0; - mem_5_flushat = 1'h0; - mem_5_flushall = 1'h0; - mem_5_sldst = 1'h0; - mem_5_vldst = 1'h0; - mem_5_fldst = 1'h0; - mem_5_regionType = 2'h0; - mem_5_mask = 16'h0; - mem_5_last = 1'h0; - mem_6_pc = 32'h0; - mem_6_addr = 32'h0; - mem_6_adrx = 32'h0; - mem_6_data = 32'h0; - mem_6_index = 5'h0; - mem_6_size = 5'h0; - mem_6_fullsize = 5'h0; - mem_6_write = 1'h0; - mem_6_sext = 1'h0; - mem_6_iload = 1'h0; - mem_6_fencei = 1'h0; - mem_6_flushat = 1'h0; - mem_6_flushall = 1'h0; - mem_6_sldst = 1'h0; - mem_6_vldst = 1'h0; - mem_6_fldst = 1'h0; - mem_6_regionType = 2'h0; - mem_6_mask = 16'h0; - mem_6_last = 1'h0; - mem_7_pc = 32'h0; - mem_7_addr = 32'h0; - mem_7_adrx = 32'h0; - mem_7_data = 32'h0; - mem_7_index = 5'h0; - mem_7_size = 5'h0; - mem_7_fullsize = 5'h0; - mem_7_write = 1'h0; - mem_7_sext = 1'h0; - mem_7_iload = 1'h0; - mem_7_fencei = 1'h0; - mem_7_flushat = 1'h0; - mem_7_flushall = 1'h0; - mem_7_sldst = 1'h0; - mem_7_vldst = 1'h0; - mem_7_fldst = 1'h0; - mem_7_regionType = 2'h0; - mem_7_mask = 16'h0; - mem_7_last = 1'h0; - inxpos_0 = 3'h0; - inxpos_1 = 3'h1; - inxpos_2 = 3'h2; - inxpos_3 = 3'h3; - inxpos_4 = 3'h4; - inxpos_5 = 3'h5; - inxpos_6 = 3'h6; - inxpos_7 = 3'h7; - outpos = 4'h0; - mcount = 4'h0; + valid = 1'h0; + addr = 5'h0; + op = 6'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Slice mslice ( - .clock (clock), - .reset (reset), - .io_in_ready (_mslice_io_in_ready), - .io_in_valid (mslice_io_in_valid), - .io_in_bits_pc - ((|mcount) ? _GEN_27[outpos] : _GEN_26 ? _GEN_8[idx_8] : io_in_bits_0_bits_pc), - .io_in_bits_addr - ((|mcount) ? _GEN_28[outpos] : _GEN_26 ? _GEN_9[idx_8] : io_in_bits_0_bits_addr), - .io_in_bits_adrx - ((|mcount) ? _GEN_29[outpos] : _GEN_26 ? _GEN_10[idx_8] : io_in_bits_0_bits_adrx), - .io_in_bits_data - ((|mcount) ? _GEN_30[outpos] : _GEN_26 ? _GEN_11[idx_8] : io_in_bits_0_bits_data), - .io_in_bits_index - ((|mcount) ? _GEN_31[outpos] : _GEN_26 ? _GEN_12[idx_8] : io_in_bits_0_bits_index), - .io_in_bits_size - ((|mcount) ? _GEN_32[outpos] : _GEN_26 ? _GEN_13[idx_8] : io_in_bits_0_bits_size), - .io_in_bits_fullsize - ((|mcount) - ? _GEN_33[outpos] - : _GEN_26 ? _GEN_14[idx_8] : io_in_bits_0_bits_fullsize), - .io_in_bits_write - ((|mcount) ? _GEN_34[outpos] : _GEN_26 ? _GEN_15[idx_8] : io_in_bits_0_bits_write), - .io_in_bits_sext - ((|mcount) ? _GEN_35[outpos] : _GEN_26 ? _GEN_16[idx_8] : io_in_bits_0_bits_sext), - .io_in_bits_iload - ((|mcount) ? _GEN_36[outpos] : _GEN_26 ? _GEN_17[idx_8] : io_in_bits_0_bits_iload), - .io_in_bits_fencei - ((|mcount) ? _GEN_37[outpos] : _GEN_26 ? _GEN_18[idx_8] : io_in_bits_0_bits_fencei), - .io_in_bits_flushat - ((|mcount) - ? _GEN_38[outpos] - : _GEN_26 ? _GEN_19[idx_8] : io_in_bits_0_bits_flushat), - .io_in_bits_flushall - ((|mcount) - ? _GEN_39[outpos] - : _GEN_26 ? _GEN_20[idx_8] : io_in_bits_0_bits_flushall), - .io_in_bits_sldst - ((|mcount) ? _GEN_40[outpos] : _GEN_26 ? _GEN_21[idx_8] : io_in_bits_0_bits_sldst), - .io_in_bits_vldst - ((|mcount) ? _GEN_41[outpos] : _GEN_26 ? _GEN_22[idx_8] : io_in_bits_0_bits_vldst), - .io_in_bits_fldst - ((|mcount) ? _GEN_42[outpos] : _GEN_26 ? _GEN_23[idx_8] : io_in_bits_0_bits_fldst), - .io_in_bits_regionType - ((|mcount) - ? _GEN_43[outpos] - : _GEN_26 ? _GEN_24[idx_8] : io_in_bits_0_bits_regionType), - .io_in_bits_mask - ((|mcount) ? _GEN_44[outpos] : _GEN_26 ? _GEN_25[idx_8] : io_in_bits_0_bits_mask), - .io_in_bits_last ((|mcount) ? _GEN_45[outpos] : _GEN_26 & _GEN[idx_8]), - .io_out_ready (io_out_ready), - .io_out_valid (_mslice_io_out_valid), - .io_out_bits_pc (io_out_bits_pc), - .io_out_bits_addr (io_out_bits_addr), - .io_out_bits_adrx (io_out_bits_adrx), - .io_out_bits_data (io_out_bits_data), - .io_out_bits_index (io_out_bits_index), - .io_out_bits_size (io_out_bits_size), - .io_out_bits_fullsize (io_out_bits_fullsize), - .io_out_bits_write (io_out_bits_write), - .io_out_bits_sext (io_out_bits_sext), - .io_out_bits_iload (io_out_bits_iload), - .io_out_bits_fencei (io_out_bits_fencei), - .io_out_bits_flushat (io_out_bits_flushat), - .io_out_bits_flushall (io_out_bits_flushall), - .io_out_bits_sldst (io_out_bits_sldst), - .io_out_bits_vldst (io_out_bits_vldst), - .io_out_bits_fldst (io_out_bits_fldst), - .io_out_bits_regionType (io_out_bits_regionType), - .io_out_bits_mask (io_out_bits_mask), - .io_out_bits_last (io_out_bits_last) - ); - assign io_out_valid = _mslice_io_out_valid; - assign io_count = mcount + {3'h0, _mslice_io_out_valid}; + assign io_rd_valid = valid; + assign io_rd_bits_addr = addr; + assign io_rd_bits_data = + op == 6'h25 + ? (io_rs2_data[4] + ? {_io_rd_bits_data_T_727[15:0], _io_rd_bits_data_T_727[31:16]} + : _io_rd_bits_data_T_727) + : op == 6'h24 + ? (io_rs2_data[4] + ? {_io_rd_bits_data_T_699[15:0], _io_rd_bits_data_T_699[31:16]} + : _io_rd_bits_data_T_699) + : _io_rd_bits_data_T_806; endmodule -module Slice_1( +module Bru( input clock, reset, - io_in_valid, - input [31:0] io_in_bits_addr, - input [4:0] io_in_bits_index, - io_in_bits_size, - io_in_bits_fullsize, - input io_in_bits_sext, - io_in_bits_iload, - io_in_bits_sldst, - io_in_bits_fldst, - input [1:0] io_in_bits_regionType, - input [15:0] io_in_bits_mask, - input io_in_bits_last, - output io_out_valid, - output [31:0] io_out_bits_addr, - output [4:0] io_out_bits_index, - io_out_bits_size, - io_out_bits_fullsize, - output io_out_bits_sext, - io_out_bits_iload, - io_out_bits_sldst, - io_out_bits_fldst, - output [1:0] io_out_bits_regionType, - output [15:0] io_out_bits_mask, - output io_out_bits_last, - output [1:0] io_count + io_req_valid, + io_req_bits_fwd, + input [3:0] io_req_bits_op, + input [31:0] io_req_bits_pc, + io_req_bits_target, + input [4:0] io_req_bits_link, + output io_csr_in_mode_valid, + io_csr_in_mcause_valid, + output [31:0] io_csr_in_mcause_bits, + output io_csr_in_mepc_valid, + output [31:0] io_csr_in_mepc_bits, + output io_csr_in_mtval_valid, + output [31:0] io_csr_in_mtval_bits, + output io_csr_in_halt, + io_csr_in_fault, + io_csr_in_wfi, + input [31:0] io_csr_out_mepc, + io_csr_out_mtvec, + input io_csr_out_interrupt, + input [31:0] io_csr_out_interrupt_cause, + io_rs1_data, + io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_taken_valid, + output [31:0] io_taken_value, + output io_actually_taken, + output [31:0] io_real_target, + input [31:0] io_target_data, + output io_interlock, + input io_fault_manager_valid, + input [31:0] io_fault_manager_bits_mepc, + io_fault_manager_bits_mtval, + io_fault_manager_bits_mcause ); - reg [1:0] ipos; - reg [1:0] opos; - reg [1:0] count; - reg [31:0] mem_0_addr; - reg [4:0] mem_0_index; - reg [4:0] mem_0_size; - reg [4:0] mem_0_fullsize; - reg mem_0_sext; - reg mem_0_iload; - reg mem_0_sldst; - reg mem_0_fldst; - reg [1:0] mem_0_regionType; - reg [15:0] mem_0_mask; - reg mem_0_last; - reg [31:0] mem_1_addr; - reg [4:0] mem_1_index; - reg [4:0] mem_1_size; - reg [4:0] mem_1_fullsize; - reg mem_1_sext; - reg mem_1_iload; - reg mem_1_sldst; - reg mem_1_fldst; - reg [1:0] mem_1_regionType; - reg [15:0] mem_1_mask; - reg mem_1_last; - wire io_out_valid_0 = ipos != opos; - wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; - wire _GEN = io_in_valid & ~io_out_valid_0; - wire _GEN_0 = io_in_valid & io_out_valid_0; + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg [31:0] stateReg_bits_originalTarget; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + reg [31:0] stateReg_bits_pcEx; + wire [31:0] mtvec = {io_csr_out_mtvec[31:2], 2'h0}; + wire eq = io_rs1_data == io_rs2_data; + wire neq = io_rs1_data != io_rs2_data; + wire lt = $signed(io_rs1_data) < $signed(io_rs2_data); + wire ge = $signed(io_rs1_data) >= $signed(io_rs2_data); + wire ltu = io_rs1_data < io_rs2_data; + wire geu = io_rs1_data >= io_rs2_data; + wire _ignore_WIRE_3 = stateReg_bits_op == 4'h9; + wire _ignore_WIRE_5 = stateReg_bits_op == 4'hB; + wire _ignore_WIRE_2 = stateReg_bits_op == 4'h8; + wire _ignore_WIRE_7 = stateReg_bits_op == 4'hD; + wire interrupt_taken = + stateReg_valid & io_csr_out_interrupt + & {_ignore_WIRE_7, _ignore_WIRE_2, _ignore_WIRE_5, _ignore_WIRE_3} == 4'h0; + wire pipeline0Taken = + stateReg_bits_op == 4'hC | stateReg_bits_op == 4'hB | stateReg_bits_op != 4'hA + & stateReg_bits_op == 4'h9 | interrupt_taken; + wire _ignore_WIRE_4 = stateReg_bits_op == 4'hA; + wire usageFault = stateReg_valid & _ignore_WIRE_2; + wire [31:0] _pc4De_T = io_req_bits_pc + 32'h4; + wire _nextState_linkValid_WIRE_1 = io_req_bits_op == 4'h1; + wire stateRegValid = io_req_valid | io_fault_manager_valid; always @(posedge clock or posedge reset) begin if (reset) begin - ipos <= 2'h0; - opos <= 2'h0; - count <= 2'h0; - mem_0_addr <= 32'h0; - mem_0_index <= 5'h0; - mem_0_size <= 5'h0; - mem_0_fullsize <= 5'h0; - mem_0_sext <= 1'h0; - mem_0_iload <= 1'h0; - mem_0_sldst <= 1'h0; - mem_0_fldst <= 1'h0; - mem_0_regionType <= 2'h0; - mem_0_mask <= 16'h0; - mem_0_last <= 1'h0; - mem_1_addr <= 32'h0; - mem_1_index <= 5'h0; - mem_1_size <= 5'h0; - mem_1_fullsize <= 5'h0; - mem_1_sext <= 1'h0; - mem_1_iload <= 1'h0; - mem_1_sldst <= 1'h0; - mem_1_fldst <= 1'h0; - mem_1_regionType <= 2'h0; - mem_1_mask <= 16'h0; - mem_1_last <= 1'h0; + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h0; + stateReg_bits_originalTarget <= 32'h0; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h0; + stateReg_bits_linkData <= 32'h0; + stateReg_bits_pcEx <= 32'h0; end else begin - if (io_in_valid) - ipos <= ipos + 2'h1; - if (io_out_valid_0) - opos <= opos + 2'h1; - if (~(io_in_valid == io_out_valid_0)) - count <= count + {1'h0, io_in_valid} - {1'h0, io_out_valid_0}; - if (io_out_valid_0 & full) begin - mem_0_addr <= mem_1_addr; - mem_0_index <= mem_1_index; - mem_0_size <= mem_1_size; - mem_0_fullsize <= mem_1_fullsize; - mem_0_sext <= mem_1_sext; - mem_0_iload <= mem_1_iload; - mem_0_sldst <= mem_1_sldst; - mem_0_fldst <= mem_1_fldst; - mem_0_regionType <= mem_1_regionType; - mem_0_mask <= mem_1_mask; - mem_0_last <= mem_1_last; - end - else if (_GEN & ipos == opos | _GEN_0 & ~full) begin - mem_0_addr <= io_in_bits_addr; - mem_0_index <= io_in_bits_index; - mem_0_size <= io_in_bits_size; - mem_0_fullsize <= io_in_bits_fullsize; - mem_0_sext <= io_in_bits_sext; - mem_0_iload <= io_in_bits_iload; - mem_0_sldst <= io_in_bits_sldst; - mem_0_fldst <= io_in_bits_fldst; - mem_0_regionType <= io_in_bits_regionType; - mem_0_mask <= io_in_bits_mask; - mem_0_last <= io_in_bits_last; - end - if (_GEN & io_out_valid_0 | _GEN_0 & full) begin - mem_1_addr <= io_in_bits_addr; - mem_1_index <= io_in_bits_index; - mem_1_size <= io_in_bits_size; - mem_1_fullsize <= io_in_bits_fullsize; - mem_1_sext <= io_in_bits_sext; - mem_1_iload <= io_in_bits_iload; - mem_1_sldst <= io_in_bits_sldst; - mem_1_fldst <= io_in_bits_fldst; - mem_1_regionType <= io_in_bits_regionType; - mem_1_mask <= io_in_bits_mask; - mem_1_last <= io_in_bits_last; + stateReg_valid <= stateRegValid; + if (stateRegValid) begin + stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; + stateReg_bits_op <= io_fault_manager_valid ? 4'hD : io_req_bits_op; + stateReg_bits_target <= + io_fault_manager_valid + ? mtvec + : io_req_bits_fwd + ? _pc4De_T + : _nextState_linkValid_WIRE_1 + ? {io_target_data[31:1], 1'h0} + : io_req_bits_op == 4'h9 + ? mtvec + : io_req_bits_op == 4'hB + ? io_csr_out_mepc + : io_req_bits_op == 4'hC ? _pc4De_T : io_req_bits_target; + stateReg_bits_originalTarget <= io_req_bits_target; + stateReg_bits_linkValid <= + io_req_valid & (|io_req_bits_link) + & (|{_nextState_linkValid_WIRE_1, io_req_bits_op == 4'h0}); + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= _pc4De_T; + stateReg_bits_pcEx <= io_req_bits_pc; end end end // always @(posedge, posedge) @@ -9198,1245 +16671,204 @@ module Slice_1( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:4]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - ipos = _RANDOM[3'h0][1:0]; - opos = _RANDOM[3'h0][3:2]; - count = _RANDOM[3'h0][5:4]; - mem_0_addr = {_RANDOM[3'h0][31:6], _RANDOM[3'h1][5:0]}; - mem_0_index = _RANDOM[3'h1][10:6]; - mem_0_size = _RANDOM[3'h1][15:11]; - mem_0_fullsize = _RANDOM[3'h1][20:16]; - mem_0_sext = _RANDOM[3'h1][21]; - mem_0_iload = _RANDOM[3'h1][22]; - mem_0_sldst = _RANDOM[3'h1][23]; - mem_0_fldst = _RANDOM[3'h1][24]; - mem_0_regionType = _RANDOM[3'h1][26:25]; - mem_0_mask = {_RANDOM[3'h1][31:27], _RANDOM[3'h2][10:0]}; - mem_0_last = _RANDOM[3'h2][11]; - mem_1_addr = {_RANDOM[3'h2][31:12], _RANDOM[3'h3][11:0]}; - mem_1_index = _RANDOM[3'h3][16:12]; - mem_1_size = _RANDOM[3'h3][21:17]; - mem_1_fullsize = _RANDOM[3'h3][26:22]; - mem_1_sext = _RANDOM[3'h3][27]; - mem_1_iload = _RANDOM[3'h3][28]; - mem_1_sldst = _RANDOM[3'h3][29]; - mem_1_fldst = _RANDOM[3'h3][30]; - mem_1_regionType = {_RANDOM[3'h3][31], _RANDOM[3'h4][0]}; - mem_1_mask = _RANDOM[3'h4][16:1]; - mem_1_last = _RANDOM[3'h4][17]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - ipos = 2'h0; - opos = 2'h0; - count = 2'h0; - mem_0_addr = 32'h0; - mem_0_index = 5'h0; - mem_0_size = 5'h0; - mem_0_fullsize = 5'h0; - mem_0_sext = 1'h0; - mem_0_iload = 1'h0; - mem_0_sldst = 1'h0; - mem_0_fldst = 1'h0; - mem_0_regionType = 2'h0; - mem_0_mask = 16'h0; - mem_0_last = 1'h0; - mem_1_addr = 32'h0; - mem_1_index = 5'h0; - mem_1_size = 5'h0; - mem_1_fullsize = 5'h0; - mem_1_sext = 1'h0; - mem_1_iload = 1'h0; - mem_1_sldst = 1'h0; - mem_1_fldst = 1'h0; - mem_1_regionType = 2'h0; - mem_1_mask = 16'h0; - mem_1_last = 1'h0; + stateReg_valid = 1'h0; + stateReg_bits_fwd = 1'h0; + stateReg_bits_op = 4'h0; + stateReg_bits_target = 32'h0; + stateReg_bits_originalTarget = 32'h0; + stateReg_bits_linkValid = 1'h0; + stateReg_bits_linkAddr = 5'h0; + stateReg_bits_linkData = 32'h0; + stateReg_bits_pcEx = 32'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_out_valid = io_out_valid_0; - assign io_out_bits_addr = mem_0_addr; - assign io_out_bits_index = mem_0_index; - assign io_out_bits_size = mem_0_size; - assign io_out_bits_fullsize = mem_0_fullsize; - assign io_out_bits_sext = mem_0_sext; - assign io_out_bits_iload = mem_0_iload; - assign io_out_bits_sldst = mem_0_sldst; - assign io_out_bits_fldst = mem_0_fldst; - assign io_out_bits_regionType = mem_0_regionType; - assign io_out_bits_mask = mem_0_mask; - assign io_out_bits_last = mem_0_last; - assign io_count = count; -endmodule - -module LsuV1( - input clock, - reset, - output io_req_0_ready, - input io_req_0_valid, - io_req_0_bits_store, - input [4:0] io_req_0_bits_addr, - io_req_0_bits_op, - input [31:0] io_req_0_bits_pc, - output io_req_1_ready, - input io_req_1_valid, - io_req_1_bits_store, - input [4:0] io_req_1_bits_addr, - io_req_1_bits_op, - input [31:0] io_req_1_bits_pc, - output io_req_2_ready, - input io_req_2_valid, - io_req_2_bits_store, - input [4:0] io_req_2_bits_addr, - io_req_2_bits_op, - input [31:0] io_req_2_bits_pc, - output io_req_3_ready, - input io_req_3_valid, - io_req_3_bits_store, - input [4:0] io_req_3_bits_addr, - io_req_3_bits_op, - input [31:0] io_req_3_bits_pc, - io_busPort_addr_0, - io_busPort_addr_1, - io_busPort_addr_2, - io_busPort_addr_3, - io_busPort_data_0, - io_busPort_data_1, - io_busPort_data_2, - io_busPort_data_3, - io_busPort_flt_data_0, - output io_rd_valid, - output [4:0] io_rd_bits_addr, - output [31:0] io_rd_bits_data, - output io_rd_flt_valid, - output [4:0] io_rd_flt_bits_addr, - output [31:0] io_rd_flt_bits_data, - output io_ibus_valid, - input io_ibus_ready, - output [31:0] io_ibus_addr, - input [127:0] io_ibus_rdata, - output io_dbus_valid, - io_dbus_write, - output [31:0] io_dbus_addr, - output [127:0] io_dbus_wdata, - output [15:0] io_dbus_wmask, - input [127:0] io_dbus_rdata, - output io_flush_valid, - input io_flush_ready, - output io_flush_fencei, - output [31:0] io_flush_pcNext, - output io_fault_valid, - io_fault_bits_write, - output [31:0] io_fault_bits_addr, - io_fault_bits_epc, - output io_ebus_dbus_valid, - input io_ebus_dbus_ready, - output io_ebus_dbus_write, - output [31:0] io_ebus_dbus_pc, - io_ebus_dbus_addr, - output [4:0] io_ebus_dbus_size, - output [127:0] io_ebus_dbus_wdata, - input [127:0] io_ebus_dbus_rdata, - input io_ebus_fault_valid, - io_ebus_fault_bits_write, - input [31:0] io_ebus_fault_bits_addr, - io_ebus_fault_bits_epc, - output [1:0] io_storeCount, - output io_active + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_csr_in_mode_valid = stateReg_valid & _ignore_WIRE_5; + assign io_csr_in_mcause_valid = + stateReg_valid & (usageFault | _ignore_WIRE_3) | interrupt_taken + | io_fault_manager_valid; + assign io_csr_in_mcause_bits = + io_fault_manager_valid + ? io_fault_manager_bits_mcause + : _ignore_WIRE_3 + ? 32'hB + : usageFault ? 32'h19 : interrupt_taken ? io_csr_out_interrupt_cause : 32'h0; + assign io_csr_in_mepc_valid = + stateReg_valid & _ignore_WIRE_3 | interrupt_taken | io_fault_manager_valid; + assign io_csr_in_mepc_bits = + io_fault_manager_valid ? io_fault_manager_bits_mepc : stateReg_bits_pcEx; + assign io_csr_in_mtval_valid = usageFault | io_fault_manager_valid; + assign io_csr_in_mtval_bits = + io_fault_manager_valid ? io_fault_manager_bits_mtval : stateReg_bits_pcEx; + assign io_csr_in_halt = stateReg_valid & _ignore_WIRE_4 | usageFault; + assign io_csr_in_fault = usageFault; + assign io_csr_in_wfi = stateReg_valid & stateReg_bits_op == 4'hC; + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = + stateReg_valid + & (interrupt_taken | stateReg_bits_op == 4'hD + | (stateReg_bits_op == 4'h7 + ? geu != stateReg_bits_fwd + : stateReg_bits_op == 4'h6 + ? ltu != stateReg_bits_fwd + : stateReg_bits_op == 4'h5 + ? ge != stateReg_bits_fwd + : stateReg_bits_op == 4'h4 + ? lt != stateReg_bits_fwd + : stateReg_bits_op == 4'h3 + ? neq != stateReg_bits_fwd + : stateReg_bits_op == 4'h2 + ? eq != stateReg_bits_fwd + : stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op) + ? ~stateReg_bits_fwd + : pipeline0Taken)); + assign io_taken_value = interrupt_taken ? mtvec : stateReg_bits_target; + assign io_actually_taken = + stateReg_valid + & (stateReg_bits_op == 4'hD + | (stateReg_bits_op == 4'h7 + ? geu + : stateReg_bits_op == 4'h6 + ? ltu + : stateReg_bits_op == 4'h5 + ? ge + : stateReg_bits_op == 4'h4 + ? lt + : stateReg_bits_op == 4'h3 + ? neq + : stateReg_bits_op == 4'h2 + ? eq + : stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op) + | pipeline0Taken)); + assign io_real_target = + stateReg_bits_fwd + ? (stateReg_bits_op == 4'h1 + ? {io_target_data[31:1], 1'h0} + : stateReg_bits_originalTarget) + : stateReg_bits_target; + assign io_interlock = + stateReg_valid + & (|{_ignore_WIRE_7, _ignore_WIRE_5, _ignore_WIRE_4, _ignore_WIRE_3, _ignore_WIRE_2}); +endmodule + +module Bru_1( + input clock, + reset, + io_req_valid, + io_req_bits_fwd, + input [3:0] io_req_bits_op, + input [31:0] io_req_bits_pc, + io_req_bits_target, + input [4:0] io_req_bits_link, + input [31:0] io_rs1_data, + io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_taken_valid, + output [31:0] io_taken_value, + input [31:0] io_target_data ); - wire io_ibus_valid_0; - wire io_ebus_dbus_valid_0; - wire [1:0] _opsext_T_11; - wire opload_3; - wire [4:0] _opiload_T_23; - wire [1:0] _opsext_T_8; - wire opload_2; - wire [4:0] _opiload_T_17; - wire [1:0] _opsext_T_5; - wire opload_1; - wire [4:0] _opiload_T_11; - wire [1:0] _opsext_T_2; - wire opload; - wire [4:0] _opiload_T_5; - wire _data_io_out_valid; - wire [31:0] _data_io_out_bits_addr; - wire [4:0] _data_io_out_bits_index; - wire [4:0] _data_io_out_bits_size; - wire [4:0] _data_io_out_bits_fullsize; - wire _data_io_out_bits_sext; - wire _data_io_out_bits_iload; - wire _data_io_out_bits_sldst; - wire _data_io_out_bits_fldst; - wire [1:0] _data_io_out_bits_regionType; - wire [15:0] _data_io_out_bits_mask; - wire _data_io_out_bits_last; - wire [1:0] _data_io_count; - wire _ctrl_io_out_valid; - wire [31:0] _ctrl_io_out_bits_pc; - wire [31:0] _ctrl_io_out_bits_addr; - wire [31:0] _ctrl_io_out_bits_adrx; - wire [31:0] _ctrl_io_out_bits_data; - wire [4:0] _ctrl_io_out_bits_index; - wire [4:0] _ctrl_io_out_bits_size; - wire [4:0] _ctrl_io_out_bits_fullsize; - wire _ctrl_io_out_bits_write; - wire _ctrl_io_out_bits_sext; - wire _ctrl_io_out_bits_iload; - wire _ctrl_io_out_bits_fencei; - wire _ctrl_io_out_bits_flushat; - wire _ctrl_io_out_bits_flushall; - wire _ctrl_io_out_bits_sldst; - wire _ctrl_io_out_bits_vldst; - wire _ctrl_io_out_bits_fldst; - wire [1:0] _ctrl_io_out_bits_regionType; - wire [15:0] _ctrl_io_out_bits_mask; - wire _ctrl_io_out_bits_last; - wire [3:0] _ctrl_io_count; - wire ctrlready_0 = _ctrl_io_count < 4'h2; - wire ctrlready_1 = _ctrl_io_count < 4'h4; - wire ctrlready_2 = _ctrl_io_count < 4'h6; - wire itcm = io_busPort_addr_0 < 32'h2000; - wire dtcm = (|(io_busPort_addr_0[31:16])) & io_busPort_addr_0 < 32'h18000; - wire _opsize_T_1 = io_req_0_bits_op == 5'h7; - wire _opsize_T_7 = io_req_0_bits_op == 5'h6; - wire _opsize_T_12 = io_req_0_bits_op == 5'h5; - wire _opsize_T = io_req_0_bits_op == 5'h2; - wire _opsize_T_5 = io_req_0_bits_op == 5'h1; - wire _opsize_T_10 = io_req_0_bits_op == 5'h0; - wire _opsize_T_6 = io_req_0_bits_op == 5'h4; - wire _opsize_T_11 = io_req_0_bits_op == 5'h3; - assign _opiload_T_5 = {_opsize_T_11, _opsize_T_6, _opsize_T_10, _opsize_T_5, _opsize_T}; - wire opfldst = io_req_0_bits_op == 5'hC; - assign opload = (|_opiload_T_5) | opfldst & ~io_req_0_bits_store; - wire opfencei = io_req_0_bits_op == 5'h8; - wire opflushat = io_req_0_bits_op == 5'h9; - wire opflushall = io_req_0_bits_op == 5'hA; - wire opsldst = - ((|{_opsize_T_12, _opsize_T_7, _opsize_T_1}) | opload) & io_req_0_bits_op != 5'hC; - wire opvldst = io_req_0_bits_op == 5'hB; - assign _opsext_T_2 = {_opsize_T_5, _opsize_T_10}; - wire [2:0] _opsize_T_3 = {opfldst, _opsize_T_1, _opsize_T}; - wire [2:0] _opsize_T_8 = {_opsize_T_7, _opsize_T_6, _opsize_T_5}; - wire [2:0] _opsize_T_13 = {_opsize_T_12, _opsize_T_11, _opsize_T_10}; - wire [1:0] regionType = - dtcm - ? 2'h1 - : itcm - ? 2'h0 - : {1'h1, ~(io_busPort_addr_0 > 32'h2FFFF & io_busPort_addr_0 < 32'h32000)}; - wire twoLines = - {26'h0, - {2'h0, io_busPort_addr_0[3:0]} - + {3'h0, |_opsize_T_3, |_opsize_T_8, |_opsize_T_13}} > 32'h10 & (itcm | dtcm); - wire [2:0] belowLineBoundary = 3'h0 - io_busPort_addr_0[2:0]; - wire [2:0] txnSizes_0 = - twoLines ? belowLineBoundary : {|_opsize_T_3, |_opsize_T_8, |_opsize_T_13}; - wire [2:0] txnSizes_1 = - twoLines ? {|_opsize_T_3, |_opsize_T_8, |_opsize_T_13} - belowLineBoundary : 3'h0; - wire _mask0_T_2 = txnSizes_0 > 3'h2; - wire _mask0_T_4 = txnSizes_0 > 3'h4; - wire _mask0_T_5 = txnSizes_0 > 3'h5; - wire [15:0] _mask0_T_25 = - io_busPort_addr_0[0] - ? {8'h0, - &txnSizes_0, - _mask0_T_5, - _mask0_T_4, - txnSizes_0[2], - _mask0_T_2, - |(txnSizes_0[2:1]), - |txnSizes_0, - 1'h0} - : {9'h0, - &txnSizes_0, - _mask0_T_5, - _mask0_T_4, - txnSizes_0[2], - _mask0_T_2, - |(txnSizes_0[2:1]), - |txnSizes_0}; - wire [15:0] _mask0_T_29 = - io_busPort_addr_0[1] ? {_mask0_T_25[13:0], _mask0_T_25[15:14]} : _mask0_T_25; - wire [15:0] _mask0_T_33 = - io_busPort_addr_0[2] ? {_mask0_T_29[11:0], _mask0_T_29[15:12]} : _mask0_T_29; - wire _mask1_T_2 = txnSizes_1 > 3'h2; - wire _mask1_T_4 = txnSizes_1 > 3'h4; - wire _mask1_T_5 = txnSizes_1 > 3'h5; - wire [3:0] _mask1_T_17 = io_busPort_addr_0[3:0] + {1'h0, txnSizes_0}; - wire [15:0] _mask1_T_27 = - _mask1_T_17[0] - ? {8'h0, - &txnSizes_1, - _mask1_T_5, - _mask1_T_4, - txnSizes_1[2], - _mask1_T_2, - |(txnSizes_1[2:1]), - |txnSizes_1, - 1'h0} - : {9'h0, - &txnSizes_1, - _mask1_T_5, - _mask1_T_4, - txnSizes_1[2], - _mask1_T_2, - |(txnSizes_1[2:1]), - |txnSizes_1}; - wire [15:0] _mask1_T_31 = - _mask1_T_17[1] ? {_mask1_T_27[13:0], _mask1_T_27[15:14]} : _mask1_T_27; - wire [15:0] _mask1_T_35 = - _mask1_T_17[2] ? {_mask1_T_31[11:0], _mask1_T_31[15:12]} : _mask1_T_31; - wire ctrl_io_in_bits_1_valid = io_req_0_valid & ctrlready_0; - wire [31:0] ctrl_io_in_bits_1_bits_data = - opfldst ? io_busPort_flt_data_0 : io_busPort_data_0; - wire [4:0] ctrl_io_in_bits_1_bits_fullsize = - {2'h0, |_opsize_T_3, |_opsize_T_8, |_opsize_T_13}; - wire [31:0] _ctrl_io_in_bits_0_bits_data_T_24 = - txnSizes_0[0] - ? {ctrl_io_in_bits_1_bits_data[7:0], ctrl_io_in_bits_1_bits_data[31:8]} - : ctrl_io_in_bits_1_bits_data; - wire itcm_1 = io_busPort_addr_1 < 32'h2000; - wire dtcm_1 = (|(io_busPort_addr_1[31:16])) & io_busPort_addr_1 < 32'h18000; - wire _opsize_T_16 = io_req_1_bits_op == 5'h7; - wire _opsize_T_22 = io_req_1_bits_op == 5'h6; - wire _opsize_T_27 = io_req_1_bits_op == 5'h5; - wire _opsize_T_15 = io_req_1_bits_op == 5'h2; - wire _opsize_T_20 = io_req_1_bits_op == 5'h1; - wire _opsize_T_25 = io_req_1_bits_op == 5'h0; - wire _opsize_T_21 = io_req_1_bits_op == 5'h4; - wire _opsize_T_26 = io_req_1_bits_op == 5'h3; - assign _opiload_T_11 = - {_opsize_T_26, _opsize_T_21, _opsize_T_25, _opsize_T_20, _opsize_T_15}; - wire opfldst_1 = io_req_1_bits_op == 5'hC; - assign opload_1 = (|_opiload_T_11) | opfldst_1 & ~io_req_1_bits_store; - wire opfencei_1 = io_req_1_bits_op == 5'h8; - wire opflushat_1 = io_req_1_bits_op == 5'h9; - wire opflushall_1 = io_req_1_bits_op == 5'hA; - wire opsldst_1 = - ((|{_opsize_T_27, _opsize_T_22, _opsize_T_16}) | opload_1) & io_req_1_bits_op != 5'hC; - wire opvldst_1 = io_req_1_bits_op == 5'hB; - assign _opsext_T_5 = {_opsize_T_20, _opsize_T_25}; - wire [2:0] _opsize_T_18 = {opfldst_1, _opsize_T_16, _opsize_T_15}; - wire [2:0] _opsize_T_23 = {_opsize_T_22, _opsize_T_21, _opsize_T_20}; - wire [2:0] _opsize_T_28 = {_opsize_T_27, _opsize_T_26, _opsize_T_25}; - wire [1:0] regionType_1 = - dtcm_1 - ? 2'h1 - : itcm_1 - ? 2'h0 - : {1'h1, ~(io_busPort_addr_1 > 32'h2FFFF & io_busPort_addr_1 < 32'h32000)}; - wire twoLines_1 = - {26'h0, - {2'h0, io_busPort_addr_1[3:0]} - + {3'h0, |_opsize_T_18, |_opsize_T_23, |_opsize_T_28}} > 32'h10 - & (itcm_1 | dtcm_1); - wire [2:0] belowLineBoundary_1 = 3'h0 - io_busPort_addr_1[2:0]; - wire [2:0] txnSizes_1_0 = - twoLines_1 ? belowLineBoundary_1 : {|_opsize_T_18, |_opsize_T_23, |_opsize_T_28}; - wire [2:0] txnSizes_1_1 = - twoLines_1 - ? {|_opsize_T_18, |_opsize_T_23, |_opsize_T_28} - belowLineBoundary_1 - : 3'h0; - wire _mask0_T_40 = txnSizes_1_0 > 3'h2; - wire _mask0_T_42 = txnSizes_1_0 > 3'h4; - wire _mask0_T_43 = txnSizes_1_0 > 3'h5; - wire [15:0] _mask0_T_63 = - io_busPort_addr_1[0] - ? {8'h0, - &txnSizes_1_0, - _mask0_T_43, - _mask0_T_42, - txnSizes_1_0[2], - _mask0_T_40, - |(txnSizes_1_0[2:1]), - |txnSizes_1_0, - 1'h0} - : {9'h0, - &txnSizes_1_0, - _mask0_T_43, - _mask0_T_42, - txnSizes_1_0[2], - _mask0_T_40, - |(txnSizes_1_0[2:1]), - |txnSizes_1_0}; - wire [15:0] _mask0_T_67 = - io_busPort_addr_1[1] ? {_mask0_T_63[13:0], _mask0_T_63[15:14]} : _mask0_T_63; - wire [15:0] _mask0_T_71 = - io_busPort_addr_1[2] ? {_mask0_T_67[11:0], _mask0_T_67[15:12]} : _mask0_T_67; - wire _mask1_T_42 = txnSizes_1_1 > 3'h2; - wire _mask1_T_44 = txnSizes_1_1 > 3'h4; - wire _mask1_T_45 = txnSizes_1_1 > 3'h5; - wire [3:0] _mask1_T_57 = io_busPort_addr_1[3:0] + {1'h0, txnSizes_1_0}; - wire [15:0] _mask1_T_67 = - _mask1_T_57[0] - ? {8'h0, - &txnSizes_1_1, - _mask1_T_45, - _mask1_T_44, - txnSizes_1_1[2], - _mask1_T_42, - |(txnSizes_1_1[2:1]), - |txnSizes_1_1, - 1'h0} - : {9'h0, - &txnSizes_1_1, - _mask1_T_45, - _mask1_T_44, - txnSizes_1_1[2], - _mask1_T_42, - |(txnSizes_1_1[2:1]), - |txnSizes_1_1}; - wire [15:0] _mask1_T_71 = - _mask1_T_57[1] ? {_mask1_T_67[13:0], _mask1_T_67[15:14]} : _mask1_T_67; - wire [15:0] _mask1_T_75 = - _mask1_T_57[2] ? {_mask1_T_71[11:0], _mask1_T_71[15:12]} : _mask1_T_71; - wire ctrl_io_in_bits_3_valid = io_req_1_valid & ctrlready_1; - wire [31:0] ctrl_io_in_bits_3_bits_data = opfldst_1 ? 32'h0 : io_busPort_data_1; - wire [4:0] ctrl_io_in_bits_3_bits_fullsize = - {2'h0, |_opsize_T_18, |_opsize_T_23, |_opsize_T_28}; - wire [31:0] _ctrl_io_in_bits_2_bits_data_T_24 = - txnSizes_1_0[0] - ? {ctrl_io_in_bits_3_bits_data[7:0], ctrl_io_in_bits_3_bits_data[31:8]} - : ctrl_io_in_bits_3_bits_data; - wire itcm_2 = io_busPort_addr_2 < 32'h2000; - wire dtcm_2 = (|(io_busPort_addr_2[31:16])) & io_busPort_addr_2 < 32'h18000; - wire _opsize_T_31 = io_req_2_bits_op == 5'h7; - wire _opsize_T_37 = io_req_2_bits_op == 5'h6; - wire _opsize_T_42 = io_req_2_bits_op == 5'h5; - wire _opsize_T_30 = io_req_2_bits_op == 5'h2; - wire _opsize_T_35 = io_req_2_bits_op == 5'h1; - wire _opsize_T_40 = io_req_2_bits_op == 5'h0; - wire _opsize_T_36 = io_req_2_bits_op == 5'h4; - wire _opsize_T_41 = io_req_2_bits_op == 5'h3; - assign _opiload_T_17 = - {_opsize_T_41, _opsize_T_36, _opsize_T_40, _opsize_T_35, _opsize_T_30}; - wire opfldst_2 = io_req_2_bits_op == 5'hC; - assign opload_2 = (|_opiload_T_17) | opfldst_2 & ~io_req_2_bits_store; - wire opfencei_2 = io_req_2_bits_op == 5'h8; - wire opflushat_2 = io_req_2_bits_op == 5'h9; - wire opflushall_2 = io_req_2_bits_op == 5'hA; - wire opsldst_2 = - ((|{_opsize_T_42, _opsize_T_37, _opsize_T_31}) | opload_2) & io_req_2_bits_op != 5'hC; - wire opvldst_2 = io_req_2_bits_op == 5'hB; - assign _opsext_T_8 = {_opsize_T_35, _opsize_T_40}; - wire [2:0] _opsize_T_33 = {opfldst_2, _opsize_T_31, _opsize_T_30}; - wire [2:0] _opsize_T_38 = {_opsize_T_37, _opsize_T_36, _opsize_T_35}; - wire [2:0] _opsize_T_43 = {_opsize_T_42, _opsize_T_41, _opsize_T_40}; - wire [1:0] regionType_2 = - dtcm_2 - ? 2'h1 - : itcm_2 - ? 2'h0 - : {1'h1, ~(io_busPort_addr_2 > 32'h2FFFF & io_busPort_addr_2 < 32'h32000)}; - wire twoLines_2 = - {26'h0, - {2'h0, io_busPort_addr_2[3:0]} - + {3'h0, |_opsize_T_33, |_opsize_T_38, |_opsize_T_43}} > 32'h10 - & (itcm_2 | dtcm_2); - wire [2:0] belowLineBoundary_2 = 3'h0 - io_busPort_addr_2[2:0]; - wire [2:0] txnSizes_2_0 = - twoLines_2 ? belowLineBoundary_2 : {|_opsize_T_33, |_opsize_T_38, |_opsize_T_43}; - wire [2:0] txnSizes_2_1 = - twoLines_2 - ? {|_opsize_T_33, |_opsize_T_38, |_opsize_T_43} - belowLineBoundary_2 - : 3'h0; - wire _mask0_T_78 = txnSizes_2_0 > 3'h2; - wire _mask0_T_80 = txnSizes_2_0 > 3'h4; - wire _mask0_T_81 = txnSizes_2_0 > 3'h5; - wire [15:0] _mask0_T_101 = - io_busPort_addr_2[0] - ? {8'h0, - &txnSizes_2_0, - _mask0_T_81, - _mask0_T_80, - txnSizes_2_0[2], - _mask0_T_78, - |(txnSizes_2_0[2:1]), - |txnSizes_2_0, - 1'h0} - : {9'h0, - &txnSizes_2_0, - _mask0_T_81, - _mask0_T_80, - txnSizes_2_0[2], - _mask0_T_78, - |(txnSizes_2_0[2:1]), - |txnSizes_2_0}; - wire [15:0] _mask0_T_105 = - io_busPort_addr_2[1] ? {_mask0_T_101[13:0], _mask0_T_101[15:14]} : _mask0_T_101; - wire [15:0] _mask0_T_109 = - io_busPort_addr_2[2] ? {_mask0_T_105[11:0], _mask0_T_105[15:12]} : _mask0_T_105; - wire _mask1_T_82 = txnSizes_2_1 > 3'h2; - wire _mask1_T_84 = txnSizes_2_1 > 3'h4; - wire _mask1_T_85 = txnSizes_2_1 > 3'h5; - wire [3:0] _mask1_T_97 = io_busPort_addr_2[3:0] + {1'h0, txnSizes_2_0}; - wire [15:0] _mask1_T_107 = - _mask1_T_97[0] - ? {8'h0, - &txnSizes_2_1, - _mask1_T_85, - _mask1_T_84, - txnSizes_2_1[2], - _mask1_T_82, - |(txnSizes_2_1[2:1]), - |txnSizes_2_1, - 1'h0} - : {9'h0, - &txnSizes_2_1, - _mask1_T_85, - _mask1_T_84, - txnSizes_2_1[2], - _mask1_T_82, - |(txnSizes_2_1[2:1]), - |txnSizes_2_1}; - wire [15:0] _mask1_T_111 = - _mask1_T_97[1] ? {_mask1_T_107[13:0], _mask1_T_107[15:14]} : _mask1_T_107; - wire [15:0] _mask1_T_115 = - _mask1_T_97[2] ? {_mask1_T_111[11:0], _mask1_T_111[15:12]} : _mask1_T_111; - wire ctrl_io_in_bits_5_valid = io_req_2_valid & ctrlready_2; - wire [31:0] ctrl_io_in_bits_5_bits_data = opfldst_2 ? 32'h0 : io_busPort_data_2; - wire [4:0] ctrl_io_in_bits_5_bits_fullsize = - {2'h0, |_opsize_T_33, |_opsize_T_38, |_opsize_T_43}; - wire [31:0] _ctrl_io_in_bits_4_bits_data_T_24 = - txnSizes_2_0[0] - ? {ctrl_io_in_bits_5_bits_data[7:0], ctrl_io_in_bits_5_bits_data[31:8]} - : ctrl_io_in_bits_5_bits_data; - wire itcm_3 = io_busPort_addr_3 < 32'h2000; - wire dtcm_3 = (|(io_busPort_addr_3[31:16])) & io_busPort_addr_3 < 32'h18000; - wire _opsize_T_46 = io_req_3_bits_op == 5'h7; - wire _opsize_T_52 = io_req_3_bits_op == 5'h6; - wire _opsize_T_57 = io_req_3_bits_op == 5'h5; - wire _opsize_T_45 = io_req_3_bits_op == 5'h2; - wire _opsize_T_50 = io_req_3_bits_op == 5'h1; - wire _opsize_T_55 = io_req_3_bits_op == 5'h0; - wire _opsize_T_51 = io_req_3_bits_op == 5'h4; - wire _opsize_T_56 = io_req_3_bits_op == 5'h3; - assign _opiload_T_23 = - {_opsize_T_56, _opsize_T_51, _opsize_T_55, _opsize_T_50, _opsize_T_45}; - wire opfldst_3 = io_req_3_bits_op == 5'hC; - assign opload_3 = (|_opiload_T_23) | opfldst_3 & ~io_req_3_bits_store; - wire opfencei_3 = io_req_3_bits_op == 5'h8; - wire opflushat_3 = io_req_3_bits_op == 5'h9; - wire opflushall_3 = io_req_3_bits_op == 5'hA; - wire opsldst_3 = - ((|{_opsize_T_57, _opsize_T_52, _opsize_T_46}) | opload_3) & io_req_3_bits_op != 5'hC; - wire opvldst_3 = io_req_3_bits_op == 5'hB; - assign _opsext_T_11 = {_opsize_T_50, _opsize_T_55}; - wire [2:0] _opsize_T_48 = {opfldst_3, _opsize_T_46, _opsize_T_45}; - wire [2:0] _opsize_T_53 = {_opsize_T_52, _opsize_T_51, _opsize_T_50}; - wire [2:0] _opsize_T_58 = {_opsize_T_57, _opsize_T_56, _opsize_T_55}; - wire [1:0] regionType_3 = - dtcm_3 - ? 2'h1 - : itcm_3 - ? 2'h0 - : {1'h1, ~(io_busPort_addr_3 > 32'h2FFFF & io_busPort_addr_3 < 32'h32000)}; - wire twoLines_3 = - {26'h0, - {2'h0, io_busPort_addr_3[3:0]} - + {3'h0, |_opsize_T_48, |_opsize_T_53, |_opsize_T_58}} > 32'h10 - & (itcm_3 | dtcm_3); - wire [2:0] belowLineBoundary_3 = 3'h0 - io_busPort_addr_3[2:0]; - wire [2:0] txnSizes_3_0 = - twoLines_3 ? belowLineBoundary_3 : {|_opsize_T_48, |_opsize_T_53, |_opsize_T_58}; - wire [2:0] txnSizes_3_1 = - twoLines_3 - ? {|_opsize_T_48, |_opsize_T_53, |_opsize_T_58} - belowLineBoundary_3 - : 3'h0; - wire _mask0_T_116 = txnSizes_3_0 > 3'h2; - wire _mask0_T_118 = txnSizes_3_0 > 3'h4; - wire _mask0_T_119 = txnSizes_3_0 > 3'h5; - wire [15:0] _mask0_T_139 = - io_busPort_addr_3[0] - ? {8'h0, - &txnSizes_3_0, - _mask0_T_119, - _mask0_T_118, - txnSizes_3_0[2], - _mask0_T_116, - |(txnSizes_3_0[2:1]), - |txnSizes_3_0, - 1'h0} - : {9'h0, - &txnSizes_3_0, - _mask0_T_119, - _mask0_T_118, - txnSizes_3_0[2], - _mask0_T_116, - |(txnSizes_3_0[2:1]), - |txnSizes_3_0}; - wire [15:0] _mask0_T_143 = - io_busPort_addr_3[1] ? {_mask0_T_139[13:0], _mask0_T_139[15:14]} : _mask0_T_139; - wire [15:0] _mask0_T_147 = - io_busPort_addr_3[2] ? {_mask0_T_143[11:0], _mask0_T_143[15:12]} : _mask0_T_143; - wire _mask1_T_122 = txnSizes_3_1 > 3'h2; - wire _mask1_T_124 = txnSizes_3_1 > 3'h4; - wire _mask1_T_125 = txnSizes_3_1 > 3'h5; - wire [3:0] _mask1_T_137 = io_busPort_addr_3[3:0] + {1'h0, txnSizes_3_0}; - wire [15:0] _mask1_T_147 = - _mask1_T_137[0] - ? {8'h0, - &txnSizes_3_1, - _mask1_T_125, - _mask1_T_124, - txnSizes_3_1[2], - _mask1_T_122, - |(txnSizes_3_1[2:1]), - |txnSizes_3_1, - 1'h0} - : {9'h0, - &txnSizes_3_1, - _mask1_T_125, - _mask1_T_124, - txnSizes_3_1[2], - _mask1_T_122, - |(txnSizes_3_1[2:1]), - |txnSizes_3_1}; - wire [15:0] _mask1_T_151 = - _mask1_T_137[1] ? {_mask1_T_147[13:0], _mask1_T_147[15:14]} : _mask1_T_147; - wire [15:0] _mask1_T_155 = - _mask1_T_137[2] ? {_mask1_T_151[11:0], _mask1_T_151[15:12]} : _mask1_T_151; - wire ctrl_io_in_bits_7_valid = io_req_3_valid & ~(_ctrl_io_count[3]); - wire [31:0] ctrl_io_in_bits_7_bits_data = opfldst_3 ? 32'h0 : io_busPort_data_3; - wire [4:0] ctrl_io_in_bits_7_bits_fullsize = - {2'h0, |_opsize_T_48, |_opsize_T_53, |_opsize_T_58}; - wire [31:0] _ctrl_io_in_bits_6_bits_data_T_24 = - txnSizes_3_0[0] - ? {ctrl_io_in_bits_7_bits_data[7:0], ctrl_io_in_bits_7_bits_data[31:8]} - : ctrl_io_in_bits_7_bits_data; - wire [15:0] wmaskT = 16'hFFFF >> 5'h10 - _ctrl_io_out_bits_size; - wire [30:0] _wmaskS_T_1 = {15'h0, wmaskT} << _ctrl_io_out_bits_addr[3:0]; - wire [127:0] wdata = - {2{{2{(_ctrl_io_out_bits_addr[1:0] == 2'h0 ? _ctrl_io_out_bits_data : 32'h0) - | (_ctrl_io_out_bits_addr[1:0] == 2'h1 - ? {_ctrl_io_out_bits_data[23:0], _ctrl_io_out_bits_data[31:24]} - : 32'h0) - | (_ctrl_io_out_bits_addr[1:0] == 2'h2 - ? {_ctrl_io_out_bits_data[15:0], _ctrl_io_out_bits_data[31:16]} - : 32'h0) - | ((&(_ctrl_io_out_bits_addr[1:0])) - ? {_ctrl_io_out_bits_data[7:0], _ctrl_io_out_bits_data[31:8]} - : 32'h0)}}}}; - wire _dataFired_T_3 = io_ebus_dbus_valid_0 & io_ebus_dbus_ready; - wire _dataFired_T_7 = io_ibus_valid_0 & io_ibus_ready; - wire _imem_store_fault_T = _ctrl_io_out_bits_sldst | _ctrl_io_out_bits_fldst; - wire io_dbus_valid_0 = - _ctrl_io_out_valid & _imem_store_fault_T & _ctrl_io_out_bits_regionType == 2'h1; - wire [31:0] io_dbus_addr_0 = {1'h0, _ctrl_io_out_bits_addr[30:0]}; - assign io_ebus_dbus_valid_0 = - _ctrl_io_out_valid & _imem_store_fault_T - & ((&_ctrl_io_out_bits_regionType) | _ctrl_io_out_bits_regionType == 2'h2); - wire _imem_store_fault_T_2 = _ctrl_io_out_bits_regionType == 2'h0; - assign io_ibus_valid_0 = - _ctrl_io_out_valid & _imem_store_fault_T & _imem_store_fault_T_2 - & ~_ctrl_io_out_bits_write; - wire imem_store_fault = - _ctrl_io_out_valid & _imem_store_fault_T & _imem_store_fault_T_2 - & _ctrl_io_out_bits_write; - wire io_flush_valid_0 = - _ctrl_io_out_valid - & (_ctrl_io_out_bits_fencei | _ctrl_io_out_bits_flushat | _ctrl_io_out_bits_flushall); - wire rvalid = _data_io_out_valid & _data_io_out_bits_last; - wire [127:0] srdataMasked = - (_data_io_out_bits_regionType == 2'h2 | (&_data_io_out_bits_regionType) - ? io_ebus_dbus_rdata - : _data_io_out_bits_regionType == 2'h0 ? io_ibus_rdata : io_dbus_rdata) - & {{8{_data_io_out_bits_mask[15]}}, - {8{_data_io_out_bits_mask[14]}}, - {8{_data_io_out_bits_mask[13]}}, - {8{_data_io_out_bits_mask[12]}}, - {8{_data_io_out_bits_mask[11]}}, - {8{_data_io_out_bits_mask[10]}}, - {8{_data_io_out_bits_mask[9]}}, - {8{_data_io_out_bits_mask[8]}}, - {8{_data_io_out_bits_mask[7]}}, - {8{_data_io_out_bits_mask[6]}}, - {8{_data_io_out_bits_mask[5]}}, - {8{_data_io_out_bits_mask[4]}}, - {8{_data_io_out_bits_mask[3]}}, - {8{_data_io_out_bits_mask[2]}}, - {8{_data_io_out_bits_mask[1]}}, - {8{_data_io_out_bits_mask[0]}}}; - reg [127:0] prevSrdataReg; - wire io_rd_pre_pipe_valid = rvalid & _data_io_out_bits_iload; - reg io_rd_pipe_pipe_v; - reg [4:0] io_rd_pipe_pipe_b_addr; - reg [31:0] io_rd_pipe_pipe_b_data; - wire io_rd_flt_pre_pipe_valid = rvalid & _data_io_out_bits_fldst; - reg io_rd_flt_pipe_pipe_v; - reg [4:0] io_rd_flt_pipe_pipe_b_addr; - reg [31:0] io_rd_flt_pipe_pipe_b_data; + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + wire [31:0] _pc4De_T = io_req_bits_pc + 32'h4; + wire _nextState_linkValid_WIRE_1 = io_req_bits_op == 4'h1; always @(posedge clock or posedge reset) begin if (reset) begin - prevSrdataReg <= 128'h0; - io_rd_pipe_pipe_v <= 1'h0; - io_rd_flt_pipe_pipe_v <= 1'h0; + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h0; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h0; + stateReg_bits_linkData <= 32'h0; end else begin - prevSrdataReg <= srdataMasked; - io_rd_pipe_pipe_v <= io_rd_pre_pipe_valid; - io_rd_flt_pipe_pipe_v <= io_rd_flt_pre_pipe_valid; + stateReg_valid <= io_req_valid; + if (io_req_valid) begin + stateReg_bits_fwd <= io_req_bits_fwd; + stateReg_bits_op <= io_req_bits_op; + stateReg_bits_target <= + io_req_bits_fwd + ? _pc4De_T + : _nextState_linkValid_WIRE_1 + ? {io_target_data[31:1], 1'h0} + : io_req_bits_target; + stateReg_bits_linkValid <= + (|io_req_bits_link) & (|{_nextState_linkValid_WIRE_1, io_req_bits_op == 4'h0}); + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= _pc4De_T; + end end end // always @(posedge, posedge) - wire [127:0] _combinedSrdata_T = - srdataMasked - | (_data_io_out_bits_fullsize == _data_io_out_bits_size ? 128'h0 : prevSrdataReg); - wire _combinedSrdata_sizeMask_T_75 = _data_io_out_bits_fullsize == 5'h4; - wire _combinedSrdata_sizeMask_T_76 = _data_io_out_bits_fullsize == 5'h3; - wire _combinedSrdata_signExtend_T_90 = _data_io_out_bits_fullsize == 5'h2; - wire [31:0] _GEN = - (_data_io_out_bits_addr[3:0] == 4'h0 - ? _combinedSrdata_T[31:0] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[15] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[7] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h1 - ? _combinedSrdata_T[39:8] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[23] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[15] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h2 - ? _combinedSrdata_T[47:16] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[31] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[23] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h3 - ? _combinedSrdata_T[55:24] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[39] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[31] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h4 - ? _combinedSrdata_T[63:32] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[47] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[39] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h5 - ? _combinedSrdata_T[71:40] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[55] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[47] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h6 - ? _combinedSrdata_T[79:48] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[63] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[55] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h7 - ? _combinedSrdata_T[87:56] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[71] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[63] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h8 - ? _combinedSrdata_T[95:64] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[79] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[71] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'h9 - ? _combinedSrdata_T[103:72] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[87] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[79] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'hA - ? _combinedSrdata_T[111:80] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[95] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[87] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'hB - ? _combinedSrdata_T[119:88] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[103] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[95] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'hC - ? _combinedSrdata_T[127:96] - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[111] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[103] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'hD - ? {_combinedSrdata_T[7:0], _combinedSrdata_T[127:104]} - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[119] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[111] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | (_data_io_out_bits_addr[3:0] == 4'hE - ? {_combinedSrdata_T[15:0], _combinedSrdata_T[127:112]} - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[127] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[119] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0) - | ((&(_data_io_out_bits_addr[3:0])) - ? {_combinedSrdata_T[23:0], _combinedSrdata_T[127:120]} - & (_combinedSrdata_sizeMask_T_75 - ? 32'hFFFFFFFF - : _combinedSrdata_sizeMask_T_76 - ? 32'hFFFFFF - : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) - | (_data_io_out_bits_sext - ? (_combinedSrdata_signExtend_T_90 - ? (_combinedSrdata_T[7] ? 32'hFFFF0000 : 32'h0) - : _combinedSrdata_T[127] ? 32'hFFFFFF00 : 32'h0) - : 32'h0) - : 32'h0); - always @(posedge clock) begin - if (io_rd_pre_pipe_valid) begin - io_rd_pipe_pipe_b_addr <= _data_io_out_bits_index; - io_rd_pipe_pipe_b_data <= _data_io_out_bits_sldst ? _GEN : 32'h0; - end - if (io_rd_flt_pre_pipe_valid) begin - io_rd_flt_pipe_pipe_b_addr <= _data_io_out_bits_index; - io_rd_flt_pipe_pipe_b_data <= _data_io_out_bits_fldst ? _GEN : 32'h0; - end - end // always @(posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:6]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - prevSrdataReg = {_RANDOM[3'h0], _RANDOM[3'h1], _RANDOM[3'h2], _RANDOM[3'h3]}; - io_rd_pipe_pipe_v = _RANDOM[3'h4][0]; - io_rd_pipe_pipe_b_addr = _RANDOM[3'h4][5:1]; - io_rd_pipe_pipe_b_data = {_RANDOM[3'h4][31:6], _RANDOM[3'h5][5:0]}; - io_rd_flt_pipe_pipe_v = _RANDOM[3'h5][6]; - io_rd_flt_pipe_pipe_b_addr = _RANDOM[3'h5][11:7]; - io_rd_flt_pipe_pipe_b_data = {_RANDOM[3'h5][31:12], _RANDOM[3'h6][11:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - prevSrdataReg = 128'h0; - io_rd_pipe_pipe_v = 1'h0; - io_rd_flt_pipe_pipe_v = 1'h0; + stateReg_valid = 1'h0; + stateReg_bits_fwd = 1'h0; + stateReg_bits_op = 4'h0; + stateReg_bits_target = 32'h0; + stateReg_bits_linkValid = 1'h0; + stateReg_bits_linkAddr = 5'h0; + stateReg_bits_linkData = 32'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FifoX ctrl ( - .clock (clock), - .reset (reset), - .io_in_valid - (io_req_0_valid | io_req_1_valid | io_req_2_valid | io_req_3_valid), - .io_in_bits_0_valid (ctrl_io_in_bits_1_valid & twoLines), - .io_in_bits_0_bits_pc (io_req_0_bits_pc), - .io_in_bits_0_bits_addr ({io_busPort_addr_0[31:4] + 28'h1, 4'h0}), - .io_in_bits_0_bits_adrx ({io_busPort_addr_0[31:4] + 28'h1, 4'h0} + 32'h10), - .io_in_bits_0_bits_data - (txnSizes_0[1] - ? {_ctrl_io_in_bits_0_bits_data_T_24[15:0], - _ctrl_io_in_bits_0_bits_data_T_24[31:16]} - : _ctrl_io_in_bits_0_bits_data_T_24), - .io_in_bits_0_bits_index (io_req_0_bits_addr), - .io_in_bits_0_bits_size ({2'h0, txnSizes_1}), - .io_in_bits_0_bits_fullsize (ctrl_io_in_bits_1_bits_fullsize), - .io_in_bits_0_bits_write (~opload), - .io_in_bits_0_bits_sext (|_opsext_T_2), - .io_in_bits_0_bits_iload (|_opiload_T_5), - .io_in_bits_0_bits_fencei (opfencei), - .io_in_bits_0_bits_flushat (opflushat), - .io_in_bits_0_bits_flushall (opflushall), - .io_in_bits_0_bits_sldst (opsldst), - .io_in_bits_0_bits_vldst (opvldst), - .io_in_bits_0_bits_fldst (opfldst), - .io_in_bits_0_bits_regionType (regionType), - .io_in_bits_0_bits_mask - (_mask1_T_17[3] ? {_mask1_T_35[7:0], _mask1_T_35[15:8]} : _mask1_T_35), - .io_in_bits_1_valid (ctrl_io_in_bits_1_valid), - .io_in_bits_1_bits_pc (io_req_0_bits_pc), - .io_in_bits_1_bits_addr (io_busPort_addr_0), - .io_in_bits_1_bits_adrx (io_busPort_addr_0 + 32'h10), - .io_in_bits_1_bits_data (ctrl_io_in_bits_1_bits_data), - .io_in_bits_1_bits_index (io_req_0_bits_addr), - .io_in_bits_1_bits_size ({2'h0, txnSizes_0}), - .io_in_bits_1_bits_fullsize (ctrl_io_in_bits_1_bits_fullsize), - .io_in_bits_1_bits_write (~opload), - .io_in_bits_1_bits_sext (|_opsext_T_2), - .io_in_bits_1_bits_iload (|_opiload_T_5), - .io_in_bits_1_bits_fencei (opfencei), - .io_in_bits_1_bits_flushat (opflushat), - .io_in_bits_1_bits_flushall (opflushall), - .io_in_bits_1_bits_sldst (opsldst), - .io_in_bits_1_bits_vldst (opvldst), - .io_in_bits_1_bits_fldst (opfldst), - .io_in_bits_1_bits_regionType (regionType), - .io_in_bits_1_bits_mask - (io_busPort_addr_0[3] ? {_mask0_T_33[7:0], _mask0_T_33[15:8]} : _mask0_T_33), - .io_in_bits_2_valid (ctrl_io_in_bits_3_valid & twoLines_1), - .io_in_bits_2_bits_pc (io_req_1_bits_pc), - .io_in_bits_2_bits_addr ({io_busPort_addr_1[31:4] + 28'h1, 4'h0}), - .io_in_bits_2_bits_adrx ({io_busPort_addr_1[31:4] + 28'h1, 4'h0} + 32'h10), - .io_in_bits_2_bits_data - (txnSizes_1_0[1] - ? {_ctrl_io_in_bits_2_bits_data_T_24[15:0], - _ctrl_io_in_bits_2_bits_data_T_24[31:16]} - : _ctrl_io_in_bits_2_bits_data_T_24), - .io_in_bits_2_bits_index (io_req_1_bits_addr), - .io_in_bits_2_bits_size ({2'h0, txnSizes_1_1}), - .io_in_bits_2_bits_fullsize (ctrl_io_in_bits_3_bits_fullsize), - .io_in_bits_2_bits_write (~opload_1), - .io_in_bits_2_bits_sext (|_opsext_T_5), - .io_in_bits_2_bits_iload (|_opiload_T_11), - .io_in_bits_2_bits_fencei (opfencei_1), - .io_in_bits_2_bits_flushat (opflushat_1), - .io_in_bits_2_bits_flushall (opflushall_1), - .io_in_bits_2_bits_sldst (opsldst_1), - .io_in_bits_2_bits_vldst (opvldst_1), - .io_in_bits_2_bits_fldst (opfldst_1), - .io_in_bits_2_bits_regionType (regionType_1), - .io_in_bits_2_bits_mask - (_mask1_T_57[3] ? {_mask1_T_75[7:0], _mask1_T_75[15:8]} : _mask1_T_75), - .io_in_bits_3_valid (ctrl_io_in_bits_3_valid), - .io_in_bits_3_bits_pc (io_req_1_bits_pc), - .io_in_bits_3_bits_addr (io_busPort_addr_1), - .io_in_bits_3_bits_adrx (io_busPort_addr_1 + 32'h10), - .io_in_bits_3_bits_data (ctrl_io_in_bits_3_bits_data), - .io_in_bits_3_bits_index (io_req_1_bits_addr), - .io_in_bits_3_bits_size ({2'h0, txnSizes_1_0}), - .io_in_bits_3_bits_fullsize (ctrl_io_in_bits_3_bits_fullsize), - .io_in_bits_3_bits_write (~opload_1), - .io_in_bits_3_bits_sext (|_opsext_T_5), - .io_in_bits_3_bits_iload (|_opiload_T_11), - .io_in_bits_3_bits_fencei (opfencei_1), - .io_in_bits_3_bits_flushat (opflushat_1), - .io_in_bits_3_bits_flushall (opflushall_1), - .io_in_bits_3_bits_sldst (opsldst_1), - .io_in_bits_3_bits_vldst (opvldst_1), - .io_in_bits_3_bits_fldst (opfldst_1), - .io_in_bits_3_bits_regionType (regionType_1), - .io_in_bits_3_bits_mask - (io_busPort_addr_1[3] ? {_mask0_T_71[7:0], _mask0_T_71[15:8]} : _mask0_T_71), - .io_in_bits_4_valid (ctrl_io_in_bits_5_valid & twoLines_2), - .io_in_bits_4_bits_pc (io_req_2_bits_pc), - .io_in_bits_4_bits_addr ({io_busPort_addr_2[31:4] + 28'h1, 4'h0}), - .io_in_bits_4_bits_adrx ({io_busPort_addr_2[31:4] + 28'h1, 4'h0} + 32'h10), - .io_in_bits_4_bits_data - (txnSizes_2_0[1] - ? {_ctrl_io_in_bits_4_bits_data_T_24[15:0], - _ctrl_io_in_bits_4_bits_data_T_24[31:16]} - : _ctrl_io_in_bits_4_bits_data_T_24), - .io_in_bits_4_bits_index (io_req_2_bits_addr), - .io_in_bits_4_bits_size ({2'h0, txnSizes_2_1}), - .io_in_bits_4_bits_fullsize (ctrl_io_in_bits_5_bits_fullsize), - .io_in_bits_4_bits_write (~opload_2), - .io_in_bits_4_bits_sext (|_opsext_T_8), - .io_in_bits_4_bits_iload (|_opiload_T_17), - .io_in_bits_4_bits_fencei (opfencei_2), - .io_in_bits_4_bits_flushat (opflushat_2), - .io_in_bits_4_bits_flushall (opflushall_2), - .io_in_bits_4_bits_sldst (opsldst_2), - .io_in_bits_4_bits_vldst (opvldst_2), - .io_in_bits_4_bits_fldst (opfldst_2), - .io_in_bits_4_bits_regionType (regionType_2), - .io_in_bits_4_bits_mask - (_mask1_T_97[3] ? {_mask1_T_115[7:0], _mask1_T_115[15:8]} : _mask1_T_115), - .io_in_bits_5_valid (ctrl_io_in_bits_5_valid), - .io_in_bits_5_bits_pc (io_req_2_bits_pc), - .io_in_bits_5_bits_addr (io_busPort_addr_2), - .io_in_bits_5_bits_adrx (io_busPort_addr_2 + 32'h10), - .io_in_bits_5_bits_data (ctrl_io_in_bits_5_bits_data), - .io_in_bits_5_bits_index (io_req_2_bits_addr), - .io_in_bits_5_bits_size ({2'h0, txnSizes_2_0}), - .io_in_bits_5_bits_fullsize (ctrl_io_in_bits_5_bits_fullsize), - .io_in_bits_5_bits_write (~opload_2), - .io_in_bits_5_bits_sext (|_opsext_T_8), - .io_in_bits_5_bits_iload (|_opiload_T_17), - .io_in_bits_5_bits_fencei (opfencei_2), - .io_in_bits_5_bits_flushat (opflushat_2), - .io_in_bits_5_bits_flushall (opflushall_2), - .io_in_bits_5_bits_sldst (opsldst_2), - .io_in_bits_5_bits_vldst (opvldst_2), - .io_in_bits_5_bits_fldst (opfldst_2), - .io_in_bits_5_bits_regionType (regionType_2), - .io_in_bits_5_bits_mask - (io_busPort_addr_2[3] ? {_mask0_T_109[7:0], _mask0_T_109[15:8]} : _mask0_T_109), - .io_in_bits_6_valid (ctrl_io_in_bits_7_valid & twoLines_3), - .io_in_bits_6_bits_pc (io_req_3_bits_pc), - .io_in_bits_6_bits_addr ({io_busPort_addr_3[31:4] + 28'h1, 4'h0}), - .io_in_bits_6_bits_adrx ({io_busPort_addr_3[31:4] + 28'h1, 4'h0} + 32'h10), - .io_in_bits_6_bits_data - (txnSizes_3_0[1] - ? {_ctrl_io_in_bits_6_bits_data_T_24[15:0], - _ctrl_io_in_bits_6_bits_data_T_24[31:16]} - : _ctrl_io_in_bits_6_bits_data_T_24), - .io_in_bits_6_bits_index (io_req_3_bits_addr), - .io_in_bits_6_bits_size ({2'h0, txnSizes_3_1}), - .io_in_bits_6_bits_fullsize (ctrl_io_in_bits_7_bits_fullsize), - .io_in_bits_6_bits_write (~opload_3), - .io_in_bits_6_bits_sext (|_opsext_T_11), - .io_in_bits_6_bits_iload (|_opiload_T_23), - .io_in_bits_6_bits_fencei (opfencei_3), - .io_in_bits_6_bits_flushat (opflushat_3), - .io_in_bits_6_bits_flushall (opflushall_3), - .io_in_bits_6_bits_sldst (opsldst_3), - .io_in_bits_6_bits_vldst (opvldst_3), - .io_in_bits_6_bits_fldst (opfldst_3), - .io_in_bits_6_bits_regionType (regionType_3), - .io_in_bits_6_bits_mask - (_mask1_T_137[3] ? {_mask1_T_155[7:0], _mask1_T_155[15:8]} : _mask1_T_155), - .io_in_bits_7_valid (ctrl_io_in_bits_7_valid), - .io_in_bits_7_bits_pc (io_req_3_bits_pc), - .io_in_bits_7_bits_addr (io_busPort_addr_3), - .io_in_bits_7_bits_adrx (io_busPort_addr_3 + 32'h10), - .io_in_bits_7_bits_data (ctrl_io_in_bits_7_bits_data), - .io_in_bits_7_bits_index (io_req_3_bits_addr), - .io_in_bits_7_bits_size ({2'h0, txnSizes_3_0}), - .io_in_bits_7_bits_fullsize (ctrl_io_in_bits_7_bits_fullsize), - .io_in_bits_7_bits_write (~opload_3), - .io_in_bits_7_bits_sext (|_opsext_T_11), - .io_in_bits_7_bits_iload (|_opiload_T_23), - .io_in_bits_7_bits_fencei (opfencei_3), - .io_in_bits_7_bits_flushat (opflushat_3), - .io_in_bits_7_bits_flushall (opflushall_3), - .io_in_bits_7_bits_sldst (opsldst_3), - .io_in_bits_7_bits_vldst (opvldst_3), - .io_in_bits_7_bits_fldst (opfldst_3), - .io_in_bits_7_bits_regionType (regionType_3), - .io_in_bits_7_bits_mask - (io_busPort_addr_3[3] ? {_mask0_T_147[7:0], _mask0_T_147[15:8]} : _mask0_T_147), - .io_out_ready - (io_flush_valid_0 & io_flush_ready | imem_store_fault | _ctrl_io_out_bits_vldst - | io_dbus_valid_0 | _dataFired_T_3 | _dataFired_T_7), - .io_out_valid (_ctrl_io_out_valid), - .io_out_bits_pc (_ctrl_io_out_bits_pc), - .io_out_bits_addr (_ctrl_io_out_bits_addr), - .io_out_bits_adrx (_ctrl_io_out_bits_adrx), - .io_out_bits_data (_ctrl_io_out_bits_data), - .io_out_bits_index (_ctrl_io_out_bits_index), - .io_out_bits_size (_ctrl_io_out_bits_size), - .io_out_bits_fullsize (_ctrl_io_out_bits_fullsize), - .io_out_bits_write (_ctrl_io_out_bits_write), - .io_out_bits_sext (_ctrl_io_out_bits_sext), - .io_out_bits_iload (_ctrl_io_out_bits_iload), - .io_out_bits_fencei (_ctrl_io_out_bits_fencei), - .io_out_bits_flushat (_ctrl_io_out_bits_flushat), - .io_out_bits_flushall (_ctrl_io_out_bits_flushall), - .io_out_bits_sldst (_ctrl_io_out_bits_sldst), - .io_out_bits_vldst (_ctrl_io_out_bits_vldst), - .io_out_bits_fldst (_ctrl_io_out_bits_fldst), - .io_out_bits_regionType (_ctrl_io_out_bits_regionType), - .io_out_bits_mask (_ctrl_io_out_bits_mask), - .io_out_bits_last (_ctrl_io_out_bits_last), - .io_count (_ctrl_io_count) - ); - Slice_1 data ( - .clock (clock), - .reset (reset), - .io_in_valid - (io_dbus_valid_0 & ~_ctrl_io_out_bits_write | _dataFired_T_3 - & ~_ctrl_io_out_bits_write | _dataFired_T_7), - .io_in_bits_addr (_ctrl_io_out_bits_addr), - .io_in_bits_index (_ctrl_io_out_bits_index), - .io_in_bits_size (_ctrl_io_out_bits_size), - .io_in_bits_fullsize (_ctrl_io_out_bits_fullsize), - .io_in_bits_sext (_ctrl_io_out_bits_sext), - .io_in_bits_iload (_ctrl_io_out_bits_iload), - .io_in_bits_sldst (_ctrl_io_out_bits_sldst), - .io_in_bits_fldst (_ctrl_io_out_bits_fldst), - .io_in_bits_regionType (_ctrl_io_out_bits_regionType), - .io_in_bits_mask (_ctrl_io_out_bits_mask), - .io_in_bits_last (_ctrl_io_out_bits_last), - .io_out_valid (_data_io_out_valid), - .io_out_bits_addr (_data_io_out_bits_addr), - .io_out_bits_index (_data_io_out_bits_index), - .io_out_bits_size (_data_io_out_bits_size), - .io_out_bits_fullsize (_data_io_out_bits_fullsize), - .io_out_bits_sext (_data_io_out_bits_sext), - .io_out_bits_iload (_data_io_out_bits_iload), - .io_out_bits_sldst (_data_io_out_bits_sldst), - .io_out_bits_fldst (_data_io_out_bits_fldst), - .io_out_bits_regionType (_data_io_out_bits_regionType), - .io_out_bits_mask (_data_io_out_bits_mask), - .io_out_bits_last (_data_io_out_bits_last), - .io_count (_data_io_count) - ); - assign io_req_0_ready = ctrlready_0; - assign io_req_1_ready = ctrlready_1; - assign io_req_2_ready = ctrlready_2; - assign io_req_3_ready = ~(_ctrl_io_count[3]); - assign io_rd_valid = io_rd_pipe_pipe_v; - assign io_rd_bits_addr = io_rd_pipe_pipe_b_addr; - assign io_rd_bits_data = io_rd_pipe_pipe_b_data; - assign io_rd_flt_valid = io_rd_flt_pipe_pipe_v; - assign io_rd_flt_bits_addr = io_rd_flt_pipe_pipe_b_addr; - assign io_rd_flt_bits_data = io_rd_flt_pipe_pipe_b_data; - assign io_ibus_valid = io_ibus_valid_0; - assign io_ibus_addr = _ctrl_io_out_bits_addr; - assign io_dbus_valid = io_dbus_valid_0; - assign io_dbus_write = _ctrl_io_out_bits_write; - assign io_dbus_addr = io_dbus_addr_0; - assign io_dbus_wdata = wdata; - assign io_dbus_wmask = - _wmaskS_T_1[15:0] | wmaskT >> 5'h10 - {1'h0, _ctrl_io_out_bits_addr[3:0]}; - assign io_flush_valid = io_flush_valid_0; - assign io_flush_fencei = _ctrl_io_out_bits_fencei; - assign io_flush_pcNext = _ctrl_io_out_bits_pc + 32'h4; - assign io_fault_valid = imem_store_fault | io_ebus_fault_valid; - assign io_fault_bits_write = - imem_store_fault | io_ebus_fault_valid & io_ebus_fault_bits_write; - assign io_fault_bits_addr = - imem_store_fault - ? _ctrl_io_out_bits_addr - : io_ebus_fault_valid ? io_ebus_fault_bits_addr : 32'h0; - assign io_fault_bits_epc = - imem_store_fault - ? _ctrl_io_out_bits_pc - : io_ebus_fault_valid ? io_ebus_fault_bits_epc : 32'h0; - assign io_ebus_dbus_valid = io_ebus_dbus_valid_0; - assign io_ebus_dbus_write = _ctrl_io_out_bits_write; - assign io_ebus_dbus_pc = _ctrl_io_out_bits_pc; - assign io_ebus_dbus_addr = _ctrl_io_out_bits_addr; - assign io_ebus_dbus_size = _ctrl_io_out_bits_size; - assign io_ebus_dbus_wdata = wdata; - assign io_storeCount = - {1'h0, io_ebus_dbus_valid_0 & _ctrl_io_out_bits_write} - + {1'h0, io_dbus_valid_0 & _ctrl_io_out_bits_write}; - assign io_active = |{_ctrl_io_count, _data_io_count}; + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = + stateReg_valid + & (stateReg_bits_op == 4'hD + | (stateReg_bits_op == 4'h7 + ? io_rs1_data >= io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h6 + ? io_rs1_data < io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h5 + ? $signed(io_rs1_data) >= $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h4 + ? $signed(io_rs1_data) < $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h3 + ? io_rs1_data != io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h2 + ? io_rs1_data == io_rs2_data != stateReg_bits_fwd + : (stateReg_bits_op == 4'h1 | stateReg_bits_op == 4'h0) + & ~stateReg_bits_fwd)); + assign io_taken_value = stateReg_bits_target; endmodule module Arbiter4_MluCmd( input io_in_0_valid, input [4:0] io_in_0_bits_addr, input [2:0] io_in_0_bits_op, + output io_in_1_ready, input io_in_1_valid, input [4:0] io_in_1_bits_addr, input [2:0] io_in_1_bits_op, + output io_in_2_ready, input io_in_2_valid, input [4:0] io_in_2_bits_addr, input [2:0] io_in_2_bits_op, + output io_in_3_ready, input io_in_3_valid, input [4:0] io_in_3_bits_addr, input [2:0] io_in_3_bits_op, @@ -10446,7 +16878,12 @@ module Arbiter4_MluCmd( output [1:0] io_chosen ); - assign io_out_valid = io_in_0_valid | io_in_1_valid | io_in_2_valid | io_in_3_valid; + wire _grant_T = io_in_0_valid | io_in_1_valid; + wire _io_out_valid_T = _grant_T | io_in_2_valid; + assign io_in_1_ready = ~io_in_0_valid; + assign io_in_2_ready = ~_grant_T; + assign io_in_3_ready = ~_io_out_valid_T; + assign io_out_valid = _io_out_valid_T | io_in_3_valid; assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr @@ -10476,12 +16913,12 @@ module Queue1_MluStage1( ); reg [11:0] ram; - reg full; + reg maybe_full; always @(posedge clock or posedge reset) begin if (reset) - full <= 1'h0; - else if (~(io_enq_valid == full)) - full <= io_enq_valid; + maybe_full <= 1'h0; + else if (io_enq_valid != maybe_full) + maybe_full <= io_enq_valid; end // always @(posedge, posedge) always @(posedge clock) begin if (io_enq_valid) @@ -10491,24 +16928,15 @@ module Queue1_MluStage1( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - full = _RANDOM[/*Zero width*/ 1'b0][0]; - ram = _RANDOM[/*Zero width*/ 1'b0][12:1]; - `endif // RANDOMIZE_REG_INIT if (reset) - full = 1'h0; + maybe_full = 1'h0; end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_deq_valid = full; + assign io_deq_valid = maybe_full; assign io_deq_bits_rd = ram[11:7]; assign io_deq_bits_op = ram[6:4]; assign io_deq_bits_sel = ram[3:0]; @@ -10528,12 +16956,12 @@ module Queue1_MluStage2( ); reg [73:0] ram; - reg full; + reg maybe_full; always @(posedge clock or posedge reset) begin if (reset) - full <= 1'h0; - else if (~(io_enq_valid == full)) - full <= io_enq_valid; + maybe_full <= 1'h0; + else if (io_enq_valid != maybe_full) + maybe_full <= io_enq_valid; end // always @(posedge, posedge) always @(posedge clock) begin if (io_enq_valid) @@ -10543,26 +16971,15 @@ module Queue1_MluStage2( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; - end - full = _RANDOM[2'h0][0]; - ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2][10:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) - full = 1'h0; + maybe_full = 1'h0; end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_deq_valid = full; + assign io_deq_valid = maybe_full; assign io_deq_bits_rd = ram[73:69]; assign io_deq_bits_op = ram[68:66]; assign io_deq_bits_prod = ram[65:0]; @@ -10574,31 +16991,26 @@ module Mlu( io_req_0_valid, input [4:0] io_req_0_bits_addr, input [2:0] io_req_0_bits_op, + output io_req_1_ready, input io_req_1_valid, input [4:0] io_req_1_bits_addr, input [2:0] io_req_1_bits_op, + output io_req_2_ready, input io_req_2_valid, input [4:0] io_req_2_bits_addr, input [2:0] io_req_2_bits_op, + output io_req_3_ready, input io_req_3_valid, input [4:0] io_req_3_bits_addr, input [2:0] io_req_3_bits_op, - input io_rs1_0_valid, input [31:0] io_rs1_0_data, - input io_rs1_1_valid, - input [31:0] io_rs1_1_data, - input io_rs1_2_valid, - input [31:0] io_rs1_2_data, - input io_rs1_3_valid, - input [31:0] io_rs1_3_data, - input io_rs2_0_valid, - input [31:0] io_rs2_0_data, - input io_rs2_1_valid, - input [31:0] io_rs2_1_data, - input io_rs2_2_valid, - input [31:0] io_rs2_2_data, - input io_rs2_3_valid, - input [31:0] io_rs2_3_data, + io_rs1_1_data, + io_rs1_2_data, + io_rs1_3_data, + io_rs2_0_data, + io_rs2_1_data, + io_rs2_2_data, + io_rs2_3_data, output io_rd_valid, output [4:0] io_rd_bits_addr, output [31:0] io_rd_bits_data @@ -10645,12 +17057,15 @@ module Mlu( .io_in_0_valid (io_req_0_valid), .io_in_0_bits_addr (io_req_0_bits_addr), .io_in_0_bits_op (io_req_0_bits_op), + .io_in_1_ready (io_req_1_ready), .io_in_1_valid (io_req_1_valid), .io_in_1_bits_addr (io_req_1_bits_addr), .io_in_1_bits_op (io_req_1_bits_op), + .io_in_2_ready (io_req_2_ready), .io_in_2_valid (io_req_2_valid), .io_in_2_bits_addr (io_req_2_bits_addr), .io_in_2_bits_op (io_req_2_bits_op), + .io_in_3_ready (io_req_3_ready), .io_in_3_valid (io_req_3_valid), .io_in_3_bits_addr (io_req_3_bits_addr), .io_in_3_bits_op (io_req_3_bits_op), @@ -10686,13 +17101,9 @@ module Mlu( .io_deq_bits_prod (_stage3Input_q_io_deq_bits_prod) ); assign io_rd_bits_data = - _stage3Input_q_io_deq_bits_op == 3'h0 + _stage3Input_q_io_deq_bits_op == 3'h4 | _stage3Input_q_io_deq_bits_op == 3'h0 ? _stage3Input_q_io_deq_bits_prod[31:0] - : (|{_stage3Input_q_io_deq_bits_op == 3'h3, - _stage3Input_q_io_deq_bits_op == 3'h2, - _stage3Input_q_io_deq_bits_op == 3'h1}) - ? _stage3Input_q_io_deq_bits_prod[63:32] - : 32'h0; + : _stage3Input_q_io_deq_bits_prod[63:32]; endmodule module Dvu( @@ -10701,7 +17112,7 @@ module Dvu( output io_req_ready, input io_req_valid, input [4:0] io_req_bits_addr, - input [1:0] io_req_bits_op, + input [2:0] io_req_bits_op, input [31:0] io_rs1_data, io_rs2_data, input io_rd_ready, @@ -10724,18 +17135,19 @@ module Dvu( reg [31:0] remain; reg [31:0] denom; wire io_req_ready_0 = ~active & ~compute & ~(count[5]); - wire _divide1_T_1 = io_req_bits_op == 2'h0; + wire _divide1_WIRE_0 = io_req_bits_op == 3'h0; + wire _isWord1_WIRE_0 = io_req_bits_op == 3'h4; wire [31:0] inp = signed1 & io_rs1_data[31] ? ~io_rs1_data + 32'h1 : io_rs1_data; - wire [15:0] _clz_T_12 = {8'h0, inp[15:8]} | {inp[7:0], 8'h0}; - wire [15:0] _clz_T_22 = - {4'h0, _clz_T_12[15:4] & 12'hF0F} | {_clz_T_12[11:0] & 12'hF0F, 4'h0}; - wire [15:0] _clz_T_32 = - {2'h0, _clz_T_22[15:2] & 14'h3333} | {_clz_T_22[13:0] & 14'h3333, 2'h0}; - wire [14:0] _clz_T_42 = - _clz_T_32[15:1] & 15'h5555 | {1'h0, _clz_T_32[12:0] & 13'h1555, 1'h0}; - wire [7:0] _clz_T_53 = {4'h0, inp[23:20]} | {inp[19:16], 4'h0}; - wire [7:0] _clz_T_63 = {2'h0, _clz_T_53[7:2] & 6'h33} | {_clz_T_53[5:0] & 6'h33, 2'h0}; - wire [7:0] _clz_T_73 = {1'h0, _clz_T_63[7:1] & 7'h55} | {_clz_T_63[6:0] & 7'h55, 1'h0}; + wire [15:0] _clz_T_11 = {8'h0, inp[15:8]} | {inp[7:0], 8'h0}; + wire [15:0] _clz_T_21 = + {4'h0, _clz_T_11[15:4] & 12'hF0F} | {_clz_T_11[11:0] & 12'hF0F, 4'h0}; + wire [15:0] _clz_T_31 = + {2'h0, _clz_T_21[15:2] & 14'h3333} | {_clz_T_21[13:0] & 14'h3333, 2'h0}; + wire [14:0] _clz_T_41 = + _clz_T_31[15:1] & 15'h5555 | {1'h0, _clz_T_31[12:0] & 13'h1555, 1'h0}; + wire [7:0] _clz_T_52 = {4'h0, inp[23:20]} | {inp[19:16], 4'h0}; + wire [7:0] _clz_T_62 = {2'h0, _clz_T_52[7:2] & 6'h33} | {_clz_T_52[5:0] & 6'h33, 2'h0}; + wire [7:0] _clz_T_72 = {1'h0, _clz_T_62[7:1] & 7'h55} | {_clz_T_62[6:0] & 7'h55, 1'h0}; wire [4:0] clz = ~(|io_rs2_data) | inp[31] | inp[30] ? 5'h0 @@ -10751,56 +17163,56 @@ module Dvu( ? 5'h5 : inp[24] ? 5'h6 - : _clz_T_73[0] + : _clz_T_72[0] ? 5'h7 - : _clz_T_73[1] + : _clz_T_72[1] ? 5'h8 - : _clz_T_73[2] + : _clz_T_72[2] ? 5'h9 - : _clz_T_73[3] + : _clz_T_72[3] ? 5'hA - : _clz_T_73[4] + : _clz_T_72[4] ? 5'hB - : _clz_T_73[5] + : _clz_T_72[5] ? 5'hC - : _clz_T_73[6] + : _clz_T_72[6] ? 5'hD - : _clz_T_73[7] + : _clz_T_72[7] ? 5'hE - : _clz_T_42[0] + : _clz_T_41[0] ? 5'hF - : _clz_T_42[1] + : _clz_T_41[1] ? 5'h10 - : _clz_T_42[2] + : _clz_T_41[2] ? 5'h11 - : _clz_T_42[3] + : _clz_T_41[3] ? 5'h12 - : _clz_T_42[4] + : _clz_T_41[4] ? 5'h13 - : _clz_T_42[5] + : _clz_T_41[5] ? 5'h14 - : _clz_T_42[6] + : _clz_T_41[6] ? 5'h15 - : _clz_T_42[7] + : _clz_T_41[7] ? 5'h16 - : _clz_T_42[8] + : _clz_T_41[8] ? 5'h17 - : _clz_T_42[9] + : _clz_T_41[9] ? 5'h18 - : _clz_T_42[10] + : _clz_T_41[10] ? 5'h19 - : _clz_T_42[11] + : _clz_T_41[11] ? 5'h1A - : _clz_T_42[12] + : _clz_T_41[12] ? 5'h1B - : _clz_T_42[13] + : _clz_T_41[13] ? 5'h1C - : _clz_T_42[14] + : _clz_T_41[14] ? 5'h1D : 5'h1E; wire [62:0] _divide_T = {31'h0, inp} << clz; wire [32:0] subtract = {1'h0, remain[30:0], divide[31]} - {1'h0, denom}; - wire _divide1_T = io_req_valid & io_req_ready_0; + wire _isWord1_T = io_req_valid & io_req_ready_0; always @(posedge clock or posedge reset) begin if (reset) begin active <= 1'h0; @@ -10818,12 +17230,20 @@ module Dvu( denom <= 32'h0; end else begin - active <= _divide1_T | count != 6'h1E & active; + active <= _isWord1_T | count != 6'h1E & active; compute <= active; - if (_divide1_T) begin + if (_isWord1_T) begin addr1 <= io_req_bits_addr; - signed1 <= |{io_req_bits_op == 2'h2, _divide1_T_1}; - divide1 <= |{io_req_bits_op == 2'h1, _divide1_T_1}; + signed1 <= + |{io_req_bits_op == 3'h6, + _isWord1_WIRE_0, + io_req_bits_op == 3'h2, + _divide1_WIRE_0}; + divide1 <= + |{io_req_bits_op == 3'h5, + _isWord1_WIRE_0, + io_req_bits_op == 3'h1, + _divide1_WIRE_0}; end if (active & ~compute) begin addr2 <= addr1; @@ -10848,29 +17268,7 @@ module Dvu( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; - end - active = _RANDOM[2'h0][0]; - compute = _RANDOM[2'h0][1]; - addr1 = _RANDOM[2'h0][6:2]; - signed1 = _RANDOM[2'h0][7]; - divide1 = _RANDOM[2'h0][8]; - addr2 = _RANDOM[2'h0][13:9]; - signed2d = _RANDOM[2'h0][14]; - signed2r = _RANDOM[2'h0][15]; - divide2 = _RANDOM[2'h0][16]; - count = _RANDOM[2'h0][22:17]; - divide = {_RANDOM[2'h0][31:23], _RANDOM[2'h1][22:0]}; - remain = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][22:0]}; - denom = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][22:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin active = 1'h0; compute = 1'h0; @@ -10886,142 +17284,41 @@ module Dvu( remain = 32'h0; denom = 32'h0; end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_req_ready = io_req_ready_0; - assign io_rd_valid = count[5]; - assign io_rd_bits_addr = addr2; - assign io_rd_bits_data = - divide2 ? (signed2d ? ~divide + 32'h1 : divide) : signed2r ? ~remain + 32'h1 : remain; -endmodule - -module FaultManager( - input io_in_fault_0_csr, - io_in_fault_0_jal, - io_in_fault_0_jalr, - io_in_fault_0_bxx, - io_in_fault_0_undef, - io_in_fault_1_jal, - io_in_fault_1_jalr, - io_in_fault_1_bxx, - io_in_fault_2_jal, - io_in_fault_2_jalr, - io_in_fault_2_bxx, - io_in_fault_3_jal, - io_in_fault_3_jalr, - io_in_fault_3_bxx, - input [31:0] io_in_pc_0_pc, - io_in_pc_1_pc, - io_in_pc_2_pc, - io_in_pc_3_pc, - input io_in_memory_fault_valid, - io_in_memory_fault_bits_write, - input [31:0] io_in_memory_fault_bits_addr, - io_in_memory_fault_bits_epc, - input io_in_ibus_fault, - input [31:0] io_in_undef_0_inst, - io_in_undef_1_inst, - io_in_undef_2_inst, - io_in_undef_3_inst, - io_in_jal_0_target, - io_in_jal_1_target, - io_in_jal_2_target, - io_in_jal_3_target, - io_in_jalr_0_target, - io_in_jalr_1_target, - io_in_jalr_2_target, - io_in_jalr_3_target, - output io_out_valid, - output [31:0] io_out_bits_mepc, - io_out_bits_mtval, - io_out_bits_mcause -); - - wire faults_0 = - io_in_fault_0_csr | io_in_fault_0_jal | io_in_fault_0_jalr | io_in_fault_0_bxx - | io_in_fault_0_undef; - wire faults_1 = io_in_fault_1_jal | io_in_fault_1_jalr | io_in_fault_1_bxx; - wire faults_2 = io_in_fault_2_jal | io_in_fault_2_jalr | io_in_fault_2_bxx; - wire fault = - faults_0 | faults_1 | faults_2 | io_in_fault_3_jal | io_in_fault_3_jalr - | io_in_fault_3_bxx; - wire [1:0] first_fault = faults_0 ? 2'h0 : faults_1 ? 2'h1 : {1'h1, ~faults_2}; - wire [1:0] undef_fault_idx = io_in_fault_0_undef ? 2'h0 : 2'h3; - wire jal_fault = - io_in_fault_0_jal | io_in_fault_1_jal | io_in_fault_2_jal | io_in_fault_3_jal; - wire [1:0] jal_fault_idx = - io_in_fault_0_jal ? 2'h0 : io_in_fault_1_jal ? 2'h1 : {1'h1, ~io_in_fault_2_jal}; - wire jalr_fault = - io_in_fault_0_jalr | io_in_fault_1_jalr | io_in_fault_2_jalr | io_in_fault_3_jalr; - wire [1:0] jalr_fault_idx = - io_in_fault_0_jalr ? 2'h0 : io_in_fault_1_jalr ? 2'h1 : {1'h1, ~io_in_fault_2_jalr}; - wire bxx_fault = - io_in_fault_0_bxx | io_in_fault_1_bxx | io_in_fault_2_bxx | io_in_fault_3_bxx; - wire instr_access_fault = io_in_memory_fault_valid & io_in_ibus_fault; - wire load_fault = - io_in_memory_fault_valid & ~io_in_memory_fault_bits_write & ~io_in_ibus_fault; - wire store_fault = - io_in_memory_fault_valid & io_in_memory_fault_bits_write & ~io_in_ibus_fault; - wire [3:0][31:0] _GEN = - {{io_in_pc_3_pc}, {io_in_pc_2_pc}, {io_in_pc_1_pc}, {io_in_pc_0_pc}}; - wire _io_out_bits_mtval_T = - (io_in_fault_0_csr ? 2'h0 : 2'h3) == first_fault; - wire _io_out_bits_mtval_T_2 = jal_fault_idx == first_fault; - wire _io_out_bits_mtval_T_4 = jalr_fault_idx == first_fault; - wire _io_out_bits_mtval_T_7 = - (io_in_fault_0_bxx - ? 2'h0 - : io_in_fault_1_bxx ? 2'h1 : {1'h1, ~io_in_fault_2_bxx}) == first_fault; - wire _io_out_bits_mtval_T_9 = undef_fault_idx == first_fault; - wire [3:0][31:0] _GEN_0 = - {{io_in_jalr_3_target}, - {io_in_jalr_2_target}, - {io_in_jalr_1_target}, - {io_in_jalr_0_target}}; - wire [3:0][31:0] _GEN_1 = - {{io_in_undef_3_inst}, - {io_in_undef_2_inst}, - {io_in_undef_1_inst}, - {io_in_undef_0_inst}}; - wire [3:0][31:0] _GEN_2 = - {{io_in_jal_3_target}, - {io_in_jal_2_target}, - {io_in_jal_1_target}, - {io_in_jal_0_target}}; - assign io_out_valid = fault | io_in_memory_fault_valid; - assign io_out_bits_mepc = - load_fault | store_fault | instr_access_fault - ? io_in_memory_fault_bits_epc - : fault ? _GEN[first_fault] : 32'h0; - assign io_out_bits_mtval = - load_fault | store_fault - ? io_in_memory_fault_bits_addr - : instr_access_fault | io_in_fault_0_csr & _io_out_bits_mtval_T - ? 32'h0 - : jal_fault & _io_out_bits_mtval_T_2 - ? _GEN_2[jal_fault_idx] - : jalr_fault & _io_out_bits_mtval_T_4 - ? _GEN_0[jalr_fault_idx] & 32'hFFFFFFFE - : bxx_fault & _io_out_bits_mtval_T_7 - | ~(io_in_fault_0_undef & _io_out_bits_mtval_T_9) - ? 32'h0 - : _GEN_1[undef_fault_idx]; - assign io_out_bits_mcause = - load_fault - ? 32'h5 - : store_fault - ? 32'h7 - : instr_access_fault - ? 32'h1 - : io_in_fault_0_csr & _io_out_bits_mtval_T - ? 32'h2 - : jal_fault & _io_out_bits_mtval_T_2 | jalr_fault - & _io_out_bits_mtval_T_4 | bxx_fault & _io_out_bits_mtval_T_7 - ? 32'h0 - : {30'h0, io_in_fault_0_undef & _io_out_bits_mtval_T_9, 1'h0}; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_req_ready = io_req_ready_0; + assign io_rd_valid = count[5]; + assign io_rd_bits_addr = addr2; + assign io_rd_bits_data = + divide2 ? (signed2d ? ~divide + 32'h1 : divide) : signed2r ? ~remain + 32'h1 : remain; +endmodule + +module Arbiter2_CsrCmd( + input io_in_0_valid, + input [4:0] io_in_0_bits_addr, + input [11:0] io_in_0_bits_index, + input [4:0] io_in_0_bits_rs1, + input [1:0] io_in_0_bits_op, + input io_in_1_valid, + input [4:0] io_in_1_bits_addr, + input [11:0] io_in_1_bits_index, + input [4:0] io_in_1_bits_rs1, + input [1:0] io_in_1_bits_op, + output io_out_valid, + output [4:0] io_out_bits_addr, + output [11:0] io_out_bits_index, + output [4:0] io_out_bits_rs1, + output [1:0] io_out_bits_op +); + + assign io_out_valid = io_in_0_valid | io_in_1_valid; + assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : io_in_1_bits_addr; + assign io_out_bits_index = io_in_0_valid ? io_in_0_bits_index : io_in_1_bits_index; + assign io_out_bits_rs1 = io_in_0_valid ? io_in_0_bits_rs1 : io_in_1_bits_rs1; + assign io_out_bits_op = io_in_0_valid ? io_in_0_bits_op : io_in_1_bits_op; endmodule module Queue1_FloatInstruction( @@ -11030,7 +17327,9 @@ module Queue1_FloatInstruction( io_enq_valid, input [2:0] io_enq_bits_opcode, input [4:0] io_enq_bits_funct5, - io_enq_bits_rs3, + input [2:0] io_enq_bits_src_fmt, + io_enq_bits_dst_fmt, + input [4:0] io_enq_bits_rs3, io_enq_bits_rs2, io_enq_bits_rs1, input [2:0] io_enq_bits_rm, @@ -11038,6 +17337,7 @@ module Queue1_FloatInstruction( io_enq_bits_pc, input io_enq_bits_scalar_rd, io_enq_bits_scalar_rs1, + io_enq_bits_float_rs1, input [4:0] io_enq_bits_rd, input io_enq_bits_uses_rs3, io_enq_bits_uses_rs2, @@ -11045,31 +17345,36 @@ module Queue1_FloatInstruction( output io_deq_valid, output [2:0] io_deq_bits_opcode, output [4:0] io_deq_bits_funct5, - io_deq_bits_rs3, + output [2:0] io_deq_bits_src_fmt, + io_deq_bits_dst_fmt, + output [4:0] io_deq_bits_rs3, io_deq_bits_rs2, io_deq_bits_rs1, output [2:0] io_deq_bits_rm, + output [31:0] io_deq_bits_inst, output io_deq_bits_scalar_rd, output [4:0] io_deq_bits_rd, output io_count ); - reg [98:0] ram; - wire io_enq_ready; - reg full; - wire do_enq = io_enq_ready & io_enq_valid; - assign io_enq_ready = ~full; + reg [105:0] ram; + wire io_enq_ready; + reg maybe_full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~maybe_full; always @(posedge clock or posedge reset) begin if (reset) - full <= 1'h0; - else if (~(do_enq == (io_deq_ready & full))) - full <= do_enq; + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; end // always @(posedge, posedge) always @(posedge clock) begin if (do_enq) ram <= {io_enq_bits_opcode, io_enq_bits_funct5, + io_enq_bits_src_fmt, + io_enq_bits_dst_fmt, io_enq_bits_rs3, io_enq_bits_rs2, io_enq_bits_rs1, @@ -11078,6 +17383,7 @@ module Queue1_FloatInstruction( io_enq_bits_pc, io_enq_bits_scalar_rd, io_enq_bits_scalar_rs1, + io_enq_bits_float_rs1, io_enq_bits_rd, io_enq_bits_uses_rs3, io_enq_bits_uses_rs2}; @@ -11086,51 +17392,30 @@ module Queue1_FloatInstruction( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:3]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin - _RANDOM[i[1:0]] = `RANDOM; - end - full = _RANDOM[2'h0][0]; - ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2], _RANDOM[2'h3][3:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) - full = 1'h0; + maybe_full = 1'h0; end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_deq_valid = full; - assign io_deq_bits_opcode = ram[98:96]; - assign io_deq_bits_funct5 = ram[95:91]; - assign io_deq_bits_rs3 = ram[90:86]; - assign io_deq_bits_rs2 = ram[85:81]; - assign io_deq_bits_rs1 = ram[80:76]; - assign io_deq_bits_rm = ram[75:73]; - assign io_deq_bits_scalar_rd = ram[8]; + assign io_deq_valid = maybe_full; + assign io_deq_bits_opcode = ram[105:103]; + assign io_deq_bits_funct5 = ram[102:98]; + assign io_deq_bits_src_fmt = ram[97:95]; + assign io_deq_bits_dst_fmt = ram[94:92]; + assign io_deq_bits_rs3 = ram[91:87]; + assign io_deq_bits_rs2 = ram[86:82]; + assign io_deq_bits_rs1 = ram[81:77]; + assign io_deq_bits_rm = ram[76:74]; + assign io_deq_bits_inst = ram[73:42]; + assign io_deq_bits_scalar_rd = ram[9]; assign io_deq_bits_rd = ram[6:2]; - assign io_count = full; + assign io_count = maybe_full; endmodule - -// Include rmemory initializers in init blocks unless synthesis is set -`ifndef RANDOMIZE - `ifdef RANDOMIZE_MEM_INIT - `define RANDOMIZE - `endif // RANDOMIZE_MEM_INIT -`endif // not def RANDOMIZE -`ifndef SYNTHESIS - `ifndef ENABLE_INITIAL_MEM_ - `define ENABLE_INITIAL_MEM_ - `endif // not def ENABLE_INITIAL_MEM_ -`endif // not def SYNTHESIS - -// VCS coverage exclude_module +// VCS coverage exclude_file module ram_2x37( input R0_addr, R0_en, @@ -11144,23 +17429,9 @@ module ram_2x37( reg [36:0] Memory[0:1]; always @(posedge W0_clk) begin - if (W0_en & 1'h1) + if (W0_en) Memory[W0_addr] <= W0_data; end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ - reg [63:0] _RANDOM_MEM; - initial begin - `INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_MEM_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - for (logic [6:0] j = 7'h0; j < 7'h40; j += 7'h20) begin - _RANDOM_MEM[j[5:0] +: 32] = `RANDOM; - end - Memory[i[0]] = _RANDOM_MEM[36:0]; - end - `endif // RANDOMIZE_MEM_INIT - end // initial - `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 37'bx; endmodule @@ -11178,26 +17449,26 @@ module Queue2_RegfileWriteDataIO( ); wire [36:0] _ram_ext_R0_data; - reg wrap; - reg wrap_1; + reg enq_ptr_value; + reg deq_ptr_value; reg maybe_full; - wire ptr_match = wrap == wrap_1; + wire ptr_match = enq_ptr_value == deq_ptr_value; wire empty = ptr_match & ~maybe_full; wire full = ptr_match & maybe_full; wire do_enq = ~full & io_enq_valid; wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - wrap <= 1'h0; - wrap_1 <= 1'h0; + enq_ptr_value <= 1'h0; + deq_ptr_value <= 1'h0; maybe_full <= 1'h0; end else begin if (do_enq) - wrap <= wrap - 1'h1; + enq_ptr_value <= enq_ptr_value - 1'h1; if (do_deq) - wrap_1 <= wrap_1 - 1'h1; - if (~(do_enq == do_deq)) + deq_ptr_value <= deq_ptr_value - 1'h1; + if (do_enq != do_deq) maybe_full <= do_enq; end end // always @(posedge, posedge) @@ -11205,20 +17476,10 @@ module Queue2_RegfileWriteDataIO( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - wrap = _RANDOM[/*Zero width*/ 1'b0][0]; - wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; - maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - wrap = 1'h0; - wrap_1 = 1'h0; + enq_ptr_value = 1'h0; + deq_ptr_value = 1'h0; maybe_full = 1'h0; end end // initial @@ -11227,11 +17488,11 @@ module Queue2_RegfileWriteDataIO( `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ ram_2x37 ram_ext ( - .R0_addr (wrap_1), + .R0_addr (deq_ptr_value), .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), - .W0_addr (wrap), + .W0_addr (enq_ptr_value), .W0_en (do_enq), .W0_clk (clock), .W0_data ({io_enq_bits_addr, io_enq_bits_data}) @@ -11249,7 +17510,9 @@ module FloatCore( input io_inst_valid, input [2:0] io_inst_bits_opcode, input [4:0] io_inst_bits_funct5, - io_inst_bits_rs3, + input [2:0] io_inst_bits_src_fmt, + io_inst_bits_dst_fmt, + input [4:0] io_inst_bits_rs3, io_inst_bits_rs2, io_inst_bits_rs1, input [2:0] io_inst_bits_rm, @@ -11257,6 +17520,7 @@ module FloatCore( io_inst_bits_pc, input io_inst_bits_scalar_rd, io_inst_bits_scalar_rs1, + io_inst_bits_float_rs1, input [4:0] io_inst_bits_rd, input io_inst_bits_uses_rs3, io_inst_bits_uses_rs2, @@ -11300,68 +17564,94 @@ module FloatCore( wire instQueue_io_deq_ready; wire _floatCoreWrapper_io_out_ready_i_T_4; - wire _floatCoreWrapper_io_in_valid_i_T_3; + wire _floatCoreWrapper_io_in_valid_i_T_4; wire _scalar_rd_pipe_q_io_enq_ready; wire _floatCoreWrapper_in_ready_o; wire _floatCoreWrapper_out_valid_o; wire [31:0] _floatCoreWrapper_result_o; + wire _floatCoreWrapper_status_o_0; + wire _floatCoreWrapper_status_o_1; + wire _floatCoreWrapper_status_o_2; + wire _floatCoreWrapper_status_o_3; + wire _floatCoreWrapper_status_o_4; wire _instQueue_io_deq_valid; wire [2:0] _instQueue_io_deq_bits_opcode; wire [4:0] _instQueue_io_deq_bits_funct5; + wire [2:0] _instQueue_io_deq_bits_src_fmt; + wire [2:0] _instQueue_io_deq_bits_dst_fmt; wire [4:0] _instQueue_io_deq_bits_rs3; wire [4:0] _instQueue_io_deq_bits_rs2; wire [4:0] _instQueue_io_deq_bits_rs1; wire [2:0] _instQueue_io_deq_bits_rm; + wire [31:0] _instQueue_io_deq_bits_inst; wire _instQueue_io_deq_bits_scalar_rd; wire [4:0] _instQueue_io_deq_bits_rd; wire _instQueue_io_count; wire _opfp_mod_T_6 = _instQueue_io_deq_bits_funct5 == 5'h4; wire _opfp_mod_T_8 = _instQueue_io_deq_bits_funct5 == 5'h18; - wire _fmv_x_w_T_2 = _instQueue_io_deq_bits_funct5 == 5'h1C; + wire _fmv_to_gpr_T = _instQueue_io_deq_bits_funct5 == 5'h1C; wire _opfp_mod_T_10 = _instQueue_io_deq_bits_funct5 == 5'h1A; wire [3:0] opfp_operation = - _opfp_mod_T_10 - ? 4'hC - : _fmv_x_w_T_2 - ? 4'h9 - : _instQueue_io_deq_bits_funct5 == 5'h14 - ? 4'h8 - : _opfp_mod_T_8 - ? 4'hB - : {1'h0, - _instQueue_io_deq_bits_funct5 == 5'h5 - ? 3'h7 - : _opfp_mod_T_6 - ? 3'h6 - : _instQueue_io_deq_bits_funct5 == 5'hB - ? 3'h5 - : _instQueue_io_deq_bits_funct5 == 5'h3 - ? 3'h4 - : {2'h1, _instQueue_io_deq_bits_funct5 == 5'h2}}; + _instQueue_io_deq_bits_funct5 == 5'h8 + ? 4'hA + : _opfp_mod_T_10 + ? 4'hC + : _fmv_to_gpr_T + ? 4'h9 + : _instQueue_io_deq_bits_funct5 == 5'h14 + ? 4'h8 + : _opfp_mod_T_8 + ? 4'hB + : {1'h0, + _instQueue_io_deq_bits_funct5 == 5'h5 + ? 3'h7 + : _opfp_mod_T_6 + ? 3'h6 + : _instQueue_io_deq_bits_funct5 == 5'hB + ? 3'h5 + : _instQueue_io_deq_bits_funct5 == 5'h3 + ? 3'h4 + : {2'h1, _instQueue_io_deq_bits_funct5 == 5'h2}}; wire [7:0][3:0] _GEN = {{4'h2}, {4'h1}, {4'h1}, {4'h0}, {4'h0}, {opfp_operation}, {4'hF}, {4'h2}}; wire [3:0] op_i = _GEN[_instQueue_io_deq_bits_opcode]; - wire _read_port_2_valid_T = op_i == 4'h0; - wire _read_port_2_valid_T_1 = op_i == 4'h1; - wire _fmv_w_x_T = _instQueue_io_deq_bits_opcode == 3'h2; - wire _floatCoreWrapper_io_operands_i_0_T_1 = opfp_operation == 4'hC; - wire _fmv_w_x_T_4 = _instQueue_io_deq_bits_rm == 3'h0; - wire fmv_x_w = - _instQueue_io_deq_valid & _fmv_w_x_T & _fmv_x_w_T_2 & _fmv_w_x_T_4; - wire fmv_w_x = - _instQueue_io_deq_valid & _fmv_w_x_T & _instQueue_io_deq_bits_funct5 == 5'h1E - & _fmv_w_x_T_4; - wire fmv = fmv_x_w | fmv_w_x; + wire _read_port_2_valid_WIRE_0 = op_i == 4'h0; + wire _read_port_2_valid_WIRE_1 = op_i == 4'h1; + wire _is_32b_int_conv_T = _instQueue_io_deq_bits_opcode == 3'h2; + wire _read_port_1_valid_WIRE_1_3 = opfp_operation == 4'hC; + wire is_fmt_bf16 = _instQueue_io_deq_bits_inst[26:25] == 2'h2; + wire _fmv_to_fpr_T = _instQueue_io_deq_bits_funct5 == 5'h1E; + wire fmv = + _instQueue_io_deq_valid & _is_32b_int_conv_T & (_fmv_to_gpr_T | _fmv_to_fpr_T) + & ~(|_instQueue_io_deq_bits_rm) + & (_instQueue_io_deq_bits_inst[26:25] == 2'h0 | is_fmt_bf16); + wire fmv_to_gpr = fmv & _fmv_to_gpr_T; + wire fmv_to_fpr = fmv & _fmv_to_fpr_T; wire _op2_addr_T = op_i == 4'h2; + wire inst_rm_valid = + ~(|_instQueue_io_deq_bits_rm) | _instQueue_io_deq_bits_rm == 3'h1 + | _instQueue_io_deq_bits_rm == 3'h2 | _instQueue_io_deq_bits_rm == 3'h3 + | _instQueue_io_deq_bits_rm == 3'h4 | (&_instQueue_io_deq_bits_rm); + wire csr_rm_valid = + io_csr_out_frm == 3'h0 | io_csr_out_frm == 3'h1 | io_csr_out_frm == 3'h2 + | io_csr_out_frm == 3'h3 | io_csr_out_frm == 3'h4 | (&io_csr_out_frm); reg fpuActive; wire _io_csr_in_fflags_valid_T = instQueue_io_deq_ready & _instQueue_io_deq_valid; wire _instQueue_io_deq_ready_T = - _floatCoreWrapper_io_in_valid_i_T_3 & _floatCoreWrapper_in_ready_o; - assign _floatCoreWrapper_io_in_valid_i_T_3 = - _instQueue_io_deq_valid & ~fmv & ~fpuActive; - wire [31:0] _io_write_ports_0_data_T = - fmv_w_x ? io_rs1_data : _floatCoreWrapper_result_o; + _floatCoreWrapper_io_in_valid_i_T_4 & _floatCoreWrapper_in_ready_o; + assign _floatCoreWrapper_io_in_valid_i_T_4 = + _instQueue_io_deq_valid & ~fmv & ~fpuActive & inst_rm_valid + & (~(&_instQueue_io_deq_bits_rm) | ~(~csr_rm_valid | csr_rm_valid & (&io_csr_out_frm)) + & csr_rm_valid); + wire [31:0] _fmv_gpr_data_T_7 = + {io_read_ports_0_data_sign, + io_read_ports_0_data_exponent, + io_read_ports_0_data_mantissa}; + wire [31:0] _io_write_ports_0_data_T_1 = + fmv_to_fpr + ? (is_fmt_bf16 ? {16'hFFFF, io_rs1_data[15:0]} : io_rs1_data) + : _floatCoreWrapper_result_o; assign _floatCoreWrapper_io_out_ready_i_T_4 = _instQueue_io_deq_valid & _instQueue_io_deq_bits_scalar_rd & _scalar_rd_pipe_q_io_enq_ready | _instQueue_io_deq_valid @@ -11379,15 +17669,7 @@ module FloatCore( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - fpuActive = _RANDOM[/*Zero width*/ 1'b0][0]; - `endif // RANDOMIZE_REG_INIT if (reset) fpuActive = 1'h0; end // initial @@ -11401,6 +17683,8 @@ module FloatCore( .io_enq_valid (io_inst_valid), .io_enq_bits_opcode (io_inst_bits_opcode), .io_enq_bits_funct5 (io_inst_bits_funct5), + .io_enq_bits_src_fmt (io_inst_bits_src_fmt), + .io_enq_bits_dst_fmt (io_inst_bits_dst_fmt), .io_enq_bits_rs3 (io_inst_bits_rs3), .io_enq_bits_rs2 (io_inst_bits_rs2), .io_enq_bits_rs1 (io_inst_bits_rs1), @@ -11409,6 +17693,7 @@ module FloatCore( .io_enq_bits_pc (io_inst_bits_pc), .io_enq_bits_scalar_rd (io_inst_bits_scalar_rd), .io_enq_bits_scalar_rs1 (io_inst_bits_scalar_rs1), + .io_enq_bits_float_rs1 (io_inst_bits_float_rs1), .io_enq_bits_rd (io_inst_bits_rd), .io_enq_bits_uses_rs3 (io_inst_bits_uses_rs3), .io_enq_bits_uses_rs2 (io_inst_bits_uses_rs2), @@ -11416,25 +17701,26 @@ module FloatCore( .io_deq_valid (_instQueue_io_deq_valid), .io_deq_bits_opcode (_instQueue_io_deq_bits_opcode), .io_deq_bits_funct5 (_instQueue_io_deq_bits_funct5), + .io_deq_bits_src_fmt (_instQueue_io_deq_bits_src_fmt), + .io_deq_bits_dst_fmt (_instQueue_io_deq_bits_dst_fmt), .io_deq_bits_rs3 (_instQueue_io_deq_bits_rs3), .io_deq_bits_rs2 (_instQueue_io_deq_bits_rs2), .io_deq_bits_rs1 (_instQueue_io_deq_bits_rs1), .io_deq_bits_rm (_instQueue_io_deq_bits_rm), + .io_deq_bits_inst (_instQueue_io_deq_bits_inst), .io_deq_bits_scalar_rd (_instQueue_io_deq_bits_scalar_rd), .io_deq_bits_rd (_instQueue_io_deq_bits_rd), .io_count (_instQueue_io_count) ); FloatCoreWrapper floatCoreWrapper ( - .clk_i (clock), - .rst_ni (~reset), - .in_valid_i (_floatCoreWrapper_io_in_valid_i_T_3), - .in_ready_o (_floatCoreWrapper_in_ready_o), + .clk_i (clock), + .rst_ni (~reset), + .in_valid_i (_floatCoreWrapper_io_in_valid_i_T_4), + .in_ready_o (_floatCoreWrapper_in_ready_o), .operands_i_0 - (_fmv_w_x_T & _floatCoreWrapper_io_operands_i_0_T_1 + (_is_32b_int_conv_T & _read_port_1_valid_WIRE_1_3 ? io_rs1_data - : {io_read_ports_0_data_sign, - io_read_ports_0_data_exponent, - io_read_ports_0_data_mantissa}), + : _fmv_gpr_data_T_7), .operands_i_1 ({io_read_ports_1_data_sign, io_read_ports_1_data_exponent, @@ -11443,7 +17729,7 @@ module FloatCore( ({io_read_ports_2_data_sign, io_read_ports_2_data_exponent, io_read_ports_2_data_mantissa}), - .op_i (op_i), + .op_i (op_i), .op_mod_i (_instQueue_io_deq_bits_opcode != 3'h6 & (_instQueue_io_deq_bits_opcode == 3'h5 | _instQueue_io_deq_bits_opcode == 3'h4 @@ -11452,13 +17738,23 @@ module FloatCore( ? _instQueue_io_deq_bits_rs2[0] : _opfp_mod_T_6 | _instQueue_io_deq_bits_funct5 == 5'h1))), .rnd_mode_i - ((&_instQueue_io_deq_bits_rm) ? io_csr_out_frm : _instQueue_io_deq_bits_rm), - .flush_i (1'h0), - .out_valid_o (_floatCoreWrapper_out_valid_o), - .out_ready_i (_floatCoreWrapper_io_out_ready_i_T_4), - .result_o (_floatCoreWrapper_result_o), - .status_o (io_csr_in_fflags_bits), - .busy_o (/* unused */) + (inst_rm_valid & (&_instQueue_io_deq_bits_rm) + ? io_csr_out_frm + : _instQueue_io_deq_bits_rm), + .src_fmt_i (_instQueue_io_deq_bits_src_fmt), + .dst_fmt_i (_instQueue_io_deq_bits_dst_fmt), + .int_fmt_i ({1'h1, _instQueue_io_deq_bits_rs2[1]}), + .flush_i (1'h0), + .out_valid_o (_floatCoreWrapper_out_valid_o), + .out_ready_i (_floatCoreWrapper_io_out_ready_i_T_4), + .result_o (_floatCoreWrapper_result_o), + .status_o_0 (_floatCoreWrapper_status_o_0), + .status_o_1 (_floatCoreWrapper_status_o_1), + .status_o_2 (_floatCoreWrapper_status_o_2), + .status_o_3 (_floatCoreWrapper_status_o_3), + .status_o_4 (_floatCoreWrapper_status_o_4), + .busy_o (/* unused */), + .early_valid_o (/* unused */) ); Queue2_RegfileWriteDataIO scalar_rd_pipe_q ( .clock (clock), @@ -11467,13 +17763,14 @@ module FloatCore( .io_enq_valid ((_instQueue_io_deq_ready_T | fpuActive) & _floatCoreWrapper_out_valid_o & _floatCoreWrapper_io_out_ready_i_T_4 & _instQueue_io_deq_bits_scalar_rd - | fmv_x_w), + | fmv_to_gpr), .io_enq_bits_addr (_instQueue_io_deq_bits_rd), .io_enq_bits_data - (fmv_x_w - ? {io_read_ports_0_data_sign, - io_read_ports_0_data_exponent, - io_read_ports_0_data_mantissa} + (fmv_to_gpr + ? (is_fmt_bf16 + ? {{16{io_read_ports_0_data_mantissa[15]}}, + io_read_ports_0_data_mantissa[15:0]} + : _fmv_gpr_data_T_7) : _floatCoreWrapper_result_o), .io_deq_ready (io_scalar_rd_ready), .io_deq_valid (io_scalar_rd_valid), @@ -11481,29 +17778,31 @@ module FloatCore( .io_deq_bits_data (io_scalar_rd_bits_data) ); assign io_inst_ready = ~_instQueue_io_count; - assign io_read_ports_0_valid = op_i != 4'h2 & _instQueue_io_deq_valid; + assign io_read_ports_0_valid = + op_i != 4'h2 & _instQueue_io_deq_valid & (~fpuActive | fmv); assign io_read_ports_0_addr = _instQueue_io_deq_bits_rs1; assign io_read_ports_1_valid = - ((|{_read_port_2_valid_T_1, _read_port_2_valid_T}) | _fmv_w_x_T - & {_floatCoreWrapper_io_operands_i_0_T_1, + ((|{_read_port_2_valid_WIRE_1, _read_port_2_valid_WIRE_0}) | _is_32b_int_conv_T + & {opfp_operation == 4'hA, + _read_port_1_valid_WIRE_1_3, opfp_operation == 4'hB, opfp_operation == 4'h9, - opfp_operation == 4'h5} == 4'h0) & _instQueue_io_deq_valid; + opfp_operation == 4'h5} == 5'h0) & _instQueue_io_deq_valid & (~fpuActive | fmv); assign io_read_ports_1_addr = _op2_addr_T ? _instQueue_io_deq_bits_rs1 : _instQueue_io_deq_bits_rs2; assign io_read_ports_2_valid = - ((|{_read_port_2_valid_T_1, _read_port_2_valid_T}) | _fmv_w_x_T - & opfp_operation == 4'h2) & _instQueue_io_deq_valid; + ((|{_read_port_2_valid_WIRE_1, _read_port_2_valid_WIRE_0}) | _is_32b_int_conv_T + & opfp_operation == 4'h2) & _instQueue_io_deq_valid & (~fpuActive | fmv); assign io_read_ports_2_addr = _op2_addr_T ? _instQueue_io_deq_bits_rs2 : _instQueue_io_deq_bits_rs3; assign io_write_ports_0_valid = (_floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T - & ~_instQueue_io_deq_bits_scalar_rd | fmv_w_x) + & ~_instQueue_io_deq_bits_scalar_rd | fmv_to_fpr) & ~(_instQueue_io_deq_valid & _instQueue_io_deq_bits_opcode == 3'h1); assign io_write_ports_0_addr = _instQueue_io_deq_bits_rd; - assign io_write_ports_0_data_mantissa = _io_write_ports_0_data_T[22:0]; - assign io_write_ports_0_data_exponent = _io_write_ports_0_data_T[30:23]; - assign io_write_ports_0_data_sign = _io_write_ports_0_data_T[31]; + assign io_write_ports_0_data_mantissa = _io_write_ports_0_data_T_1[22:0]; + assign io_write_ports_0_data_exponent = _io_write_ports_0_data_T_1[30:23]; + assign io_write_ports_0_data_sign = _io_write_ports_0_data_T_1[31]; assign io_write_ports_1_valid = io_lsu_rd_valid; assign io_write_ports_1_addr = io_lsu_rd_bits_addr; assign io_write_ports_1_data_mantissa = io_lsu_rd_bits_data[22:0]; @@ -11511,6 +17810,12 @@ module FloatCore( assign io_write_ports_1_data_sign = io_lsu_rd_bits_data[31]; assign io_csr_in_fflags_valid = _floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T & ~fmv; + assign io_csr_in_fflags_bits = + {_floatCoreWrapper_status_o_4, + _floatCoreWrapper_status_o_3, + _floatCoreWrapper_status_o_2, + _floatCoreWrapper_status_o_1, + _floatCoreWrapper_status_o_0}; endmodule module FRegfile( @@ -11541,6 +17846,7 @@ module FRegfile( input [22:0] io_write_ports_1_data_mantissa, input [7:0] io_write_ports_1_data_exponent, input io_write_ports_1_data_sign, + io_pipelineFlush, input [31:0] io_scoreboard_set, output [31:0] io_scoreboard, io_busPort_data_0, @@ -11644,7 +17950,6 @@ module FRegfile( reg [7:0] fregfile_31_exponent; reg fregfile_31_sign; reg [31:0] scoreboard; - reg scoreboard_error; wire [31:0][22:0] _GEN = {{fregfile_31_mantissa}, {fregfile_30_mantissa}, @@ -11744,11 +18049,6 @@ module FRegfile( {fregfile_2_sign}, {fregfile_1_sign}, {fregfile_0_sign}}; - wire _io_busPort_data_0_T_1 = - io_write_ports_0_valid & io_write_ports_0_addr == io_read_ports_1_addr; - wire [31:0] scoreboard_clr = - (io_write_ports_0_valid ? 32'h1 << io_write_ports_0_addr : 32'h0) - | (io_write_ports_1_valid ? 32'h1 << io_write_ports_1_addr : 32'h0); wire valid_0 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h0; wire valid_0_1 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1; wire valid_0_2 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h2; @@ -11880,7 +18180,6 @@ module FRegfile( fregfile_31_exponent <= 8'h0; fregfile_31_sign <= 1'h0; scoreboard <= 32'h0; - scoreboard_error <= 1'h0; end else begin if (valid_0 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h0) begin @@ -12139,122 +18438,18 @@ module FRegfile( fregfile_31_sign <= valid_0_31 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; end - scoreboard <= scoreboard & ~scoreboard_clr | io_scoreboard_set; - scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + scoreboard <= + {32{~io_pipelineFlush}} & scoreboard + & ~((io_write_ports_0_valid ? 32'h1 << io_write_ports_0_addr : 32'h0) + | (io_write_ports_1_valid ? 32'h1 << io_write_ports_1_addr : 32'h0)) + | io_scoreboard_set; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:33]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin - _RANDOM[i] = `RANDOM; - end - fregfile_0_mantissa = _RANDOM[6'h0][22:0]; - fregfile_0_exponent = _RANDOM[6'h0][30:23]; - fregfile_0_sign = _RANDOM[6'h0][31]; - fregfile_1_mantissa = _RANDOM[6'h1][22:0]; - fregfile_1_exponent = _RANDOM[6'h1][30:23]; - fregfile_1_sign = _RANDOM[6'h1][31]; - fregfile_2_mantissa = _RANDOM[6'h2][22:0]; - fregfile_2_exponent = _RANDOM[6'h2][30:23]; - fregfile_2_sign = _RANDOM[6'h2][31]; - fregfile_3_mantissa = _RANDOM[6'h3][22:0]; - fregfile_3_exponent = _RANDOM[6'h3][30:23]; - fregfile_3_sign = _RANDOM[6'h3][31]; - fregfile_4_mantissa = _RANDOM[6'h4][22:0]; - fregfile_4_exponent = _RANDOM[6'h4][30:23]; - fregfile_4_sign = _RANDOM[6'h4][31]; - fregfile_5_mantissa = _RANDOM[6'h5][22:0]; - fregfile_5_exponent = _RANDOM[6'h5][30:23]; - fregfile_5_sign = _RANDOM[6'h5][31]; - fregfile_6_mantissa = _RANDOM[6'h6][22:0]; - fregfile_6_exponent = _RANDOM[6'h6][30:23]; - fregfile_6_sign = _RANDOM[6'h6][31]; - fregfile_7_mantissa = _RANDOM[6'h7][22:0]; - fregfile_7_exponent = _RANDOM[6'h7][30:23]; - fregfile_7_sign = _RANDOM[6'h7][31]; - fregfile_8_mantissa = _RANDOM[6'h8][22:0]; - fregfile_8_exponent = _RANDOM[6'h8][30:23]; - fregfile_8_sign = _RANDOM[6'h8][31]; - fregfile_9_mantissa = _RANDOM[6'h9][22:0]; - fregfile_9_exponent = _RANDOM[6'h9][30:23]; - fregfile_9_sign = _RANDOM[6'h9][31]; - fregfile_10_mantissa = _RANDOM[6'hA][22:0]; - fregfile_10_exponent = _RANDOM[6'hA][30:23]; - fregfile_10_sign = _RANDOM[6'hA][31]; - fregfile_11_mantissa = _RANDOM[6'hB][22:0]; - fregfile_11_exponent = _RANDOM[6'hB][30:23]; - fregfile_11_sign = _RANDOM[6'hB][31]; - fregfile_12_mantissa = _RANDOM[6'hC][22:0]; - fregfile_12_exponent = _RANDOM[6'hC][30:23]; - fregfile_12_sign = _RANDOM[6'hC][31]; - fregfile_13_mantissa = _RANDOM[6'hD][22:0]; - fregfile_13_exponent = _RANDOM[6'hD][30:23]; - fregfile_13_sign = _RANDOM[6'hD][31]; - fregfile_14_mantissa = _RANDOM[6'hE][22:0]; - fregfile_14_exponent = _RANDOM[6'hE][30:23]; - fregfile_14_sign = _RANDOM[6'hE][31]; - fregfile_15_mantissa = _RANDOM[6'hF][22:0]; - fregfile_15_exponent = _RANDOM[6'hF][30:23]; - fregfile_15_sign = _RANDOM[6'hF][31]; - fregfile_16_mantissa = _RANDOM[6'h10][22:0]; - fregfile_16_exponent = _RANDOM[6'h10][30:23]; - fregfile_16_sign = _RANDOM[6'h10][31]; - fregfile_17_mantissa = _RANDOM[6'h11][22:0]; - fregfile_17_exponent = _RANDOM[6'h11][30:23]; - fregfile_17_sign = _RANDOM[6'h11][31]; - fregfile_18_mantissa = _RANDOM[6'h12][22:0]; - fregfile_18_exponent = _RANDOM[6'h12][30:23]; - fregfile_18_sign = _RANDOM[6'h12][31]; - fregfile_19_mantissa = _RANDOM[6'h13][22:0]; - fregfile_19_exponent = _RANDOM[6'h13][30:23]; - fregfile_19_sign = _RANDOM[6'h13][31]; - fregfile_20_mantissa = _RANDOM[6'h14][22:0]; - fregfile_20_exponent = _RANDOM[6'h14][30:23]; - fregfile_20_sign = _RANDOM[6'h14][31]; - fregfile_21_mantissa = _RANDOM[6'h15][22:0]; - fregfile_21_exponent = _RANDOM[6'h15][30:23]; - fregfile_21_sign = _RANDOM[6'h15][31]; - fregfile_22_mantissa = _RANDOM[6'h16][22:0]; - fregfile_22_exponent = _RANDOM[6'h16][30:23]; - fregfile_22_sign = _RANDOM[6'h16][31]; - fregfile_23_mantissa = _RANDOM[6'h17][22:0]; - fregfile_23_exponent = _RANDOM[6'h17][30:23]; - fregfile_23_sign = _RANDOM[6'h17][31]; - fregfile_24_mantissa = _RANDOM[6'h18][22:0]; - fregfile_24_exponent = _RANDOM[6'h18][30:23]; - fregfile_24_sign = _RANDOM[6'h18][31]; - fregfile_25_mantissa = _RANDOM[6'h19][22:0]; - fregfile_25_exponent = _RANDOM[6'h19][30:23]; - fregfile_25_sign = _RANDOM[6'h19][31]; - fregfile_26_mantissa = _RANDOM[6'h1A][22:0]; - fregfile_26_exponent = _RANDOM[6'h1A][30:23]; - fregfile_26_sign = _RANDOM[6'h1A][31]; - fregfile_27_mantissa = _RANDOM[6'h1B][22:0]; - fregfile_27_exponent = _RANDOM[6'h1B][30:23]; - fregfile_27_sign = _RANDOM[6'h1B][31]; - fregfile_28_mantissa = _RANDOM[6'h1C][22:0]; - fregfile_28_exponent = _RANDOM[6'h1C][30:23]; - fregfile_28_sign = _RANDOM[6'h1C][31]; - fregfile_29_mantissa = _RANDOM[6'h1D][22:0]; - fregfile_29_exponent = _RANDOM[6'h1D][30:23]; - fregfile_29_sign = _RANDOM[6'h1D][31]; - fregfile_30_mantissa = _RANDOM[6'h1E][22:0]; - fregfile_30_exponent = _RANDOM[6'h1E][30:23]; - fregfile_30_sign = _RANDOM[6'h1E][31]; - fregfile_31_mantissa = _RANDOM[6'h1F][22:0]; - fregfile_31_exponent = _RANDOM[6'h1F][30:23]; - fregfile_31_sign = _RANDOM[6'h1F][31]; - scoreboard = _RANDOM[6'h20]; - scoreboard_error = _RANDOM[6'h21][0]; - `endif // RANDOMIZE_REG_INIT if (reset) begin fregfile_0_mantissa = 23'h0; fregfile_0_exponent = 8'h0; @@ -12353,7 +18548,6 @@ module FRegfile( fregfile_31_exponent = 8'h0; fregfile_31_sign = 1'h0; scoreboard = 32'h0; - scoreboard_error = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -12377,12 +18571,10 @@ module FRegfile( assign io_read_ports_2_data_sign = io_read_ports_2_valid & _GEN_1[io_read_ports_2_addr]; assign io_scoreboard = scoreboard; assign io_busPort_data_0 = - {_io_busPort_data_0_T_1 ? io_write_ports_0_data_sign : _GEN_1[io_busPortAddr], - _io_busPort_data_0_T_1 ? io_write_ports_0_data_exponent : _GEN_0[io_busPortAddr], - _io_busPort_data_0_T_1 ? io_write_ports_0_data_mantissa : _GEN[io_busPortAddr]}; + {_GEN_1[io_busPortAddr], _GEN_0[io_busPortAddr], _GEN[io_busPortAddr]}; endmodule -module Arbiter3_RegfileWriteDataIO( +module Arbiter4_RegfileWriteDataIO( input io_in_0_valid, input [4:0] io_in_0_bits_addr, input [31:0] io_in_0_bits_data, @@ -12394,23 +18586,33 @@ module Arbiter3_RegfileWriteDataIO( input io_in_2_valid, input [4:0] io_in_2_bits_addr, input [31:0] io_in_2_bits_data, + output io_in_3_ready, + input io_in_3_valid, + input [4:0] io_in_3_bits_addr, + input [31:0] io_in_3_bits_data, output io_out_valid, output [4:0] io_out_bits_addr, output [31:0] io_out_bits_data ); - wire _io_out_valid_T = io_in_0_valid | io_in_1_valid; + wire _grant_T = io_in_0_valid | io_in_1_valid; + wire _io_out_valid_T = _grant_T | io_in_2_valid; assign io_in_1_ready = ~io_in_0_valid; - assign io_in_2_ready = ~_io_out_valid_T; - assign io_out_valid = _io_out_valid_T | io_in_2_valid; + assign io_in_2_ready = ~_grant_T; + assign io_in_3_ready = ~_io_out_valid_T; + assign io_out_valid = _io_out_valid_T | io_in_3_valid; assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr - : io_in_1_valid ? io_in_1_bits_addr : io_in_2_bits_addr; + : io_in_1_valid + ? io_in_1_bits_addr + : io_in_2_valid ? io_in_2_bits_addr : io_in_3_bits_addr; assign io_out_bits_data = io_in_0_valid ? io_in_0_bits_data - : io_in_1_valid ? io_in_1_bits_data : io_in_2_bits_data; + : io_in_1_valid + ? io_in_1_bits_data + : io_in_2_valid ? io_in_2_bits_data : io_in_3_bits_data; endmodule module SCore( @@ -12425,15 +18627,45 @@ module SCore( io_csr_out_value_5, io_csr_out_value_6, io_csr_out_value_7, + io_csr_out_value_8, output io_halted, io_fault, io_wfi, input io_irq, + io_dm_debug_req, + io_dm_resume_req, + io_dm_csr_valid, + input [4:0] io_dm_csr_bits_addr, + input [11:0] io_dm_csr_bits_index, + input [4:0] io_dm_csr_bits_rs1, + input [1:0] io_dm_csr_bits_op, + input [31:0] io_dm_csr_rs1, + output io_dm_csr_rd_valid, + output [31:0] io_dm_csr_rd_bits, + output io_dm_scalar_rd_ready, + input io_dm_scalar_rd_valid, + input [4:0] io_dm_scalar_rd_bits_addr, + input [31:0] io_dm_scalar_rd_bits_data, + input [4:0] io_dm_scalar_rs_idx, + output [31:0] io_dm_scalar_rs_data, + input io_dm_float_rd_valid, + input [4:0] io_dm_float_rd_addr, + input [22:0] io_dm_float_rd_data_mantissa, + input [7:0] io_dm_float_rd_data_exponent, + input io_dm_float_rd_data_sign, + io_dm_float_rs_valid, + input [4:0] io_dm_float_rs_addr, + output [22:0] io_dm_float_rs_data_mantissa, + output [7:0] io_dm_float_rs_data_exponent, + output io_dm_float_rs_data_sign, + io_dm_debug_mode, + input io_timer_irq, + io_software_irq, output io_ibus_valid, + input io_ibus_ready, output [31:0] io_ibus_addr, input [127:0] io_ibus_rdata, input io_ibus_fault_valid, - input [31:0] io_ibus_fault_bits_epc, output io_dbus_valid, io_dbus_write, output [31:0] io_dbus_addr, @@ -12443,547 +18675,423 @@ module SCore( output io_ebus_dbus_valid, input io_ebus_dbus_ready, output io_ebus_dbus_write, - output [31:0] io_ebus_dbus_pc, - io_ebus_dbus_addr, + output [31:0] io_ebus_dbus_addr, output [4:0] io_ebus_dbus_size, output [127:0] io_ebus_dbus_wdata, + output [15:0] io_ebus_dbus_wmask, input [127:0] io_ebus_dbus_rdata, - input io_ebus_fault_valid, - io_ebus_fault_bits_write, - input [31:0] io_ebus_fault_bits_addr, - io_ebus_fault_bits_epc, - output io_slog_valid, - output [4:0] io_slog_addr, - output [31:0] io_slog_data, - output [3:0] io_debug_en, - output [31:0] io_debug_addr_0, - io_debug_addr_1, - io_debug_addr_2, - io_debug_addr_3, - io_debug_inst_0, - io_debug_inst_1, - io_debug_inst_2, - io_debug_inst_3, - io_debug_cycles, - output io_debug_dbus_valid, - output [31:0] io_debug_dbus_bits_addr, - output [127:0] io_debug_dbus_bits_wdata, - output io_debug_dbus_bits_write, - io_debug_dispatch_0_instFire, - output [31:0] io_debug_dispatch_0_instAddr, - io_debug_dispatch_0_instInst, - output io_debug_dispatch_1_instFire, - output [31:0] io_debug_dispatch_1_instAddr, - io_debug_dispatch_1_instInst, - output io_debug_dispatch_2_instFire, - output [31:0] io_debug_dispatch_2_instAddr, - io_debug_dispatch_2_instInst, - output io_debug_dispatch_3_instFire, - output [31:0] io_debug_dispatch_3_instAddr, - io_debug_dispatch_3_instInst, - output io_debug_regfile_writeAddr_0_valid, - output [4:0] io_debug_regfile_writeAddr_0_bits, - output io_debug_regfile_writeAddr_1_valid, - output [4:0] io_debug_regfile_writeAddr_1_bits, - output io_debug_regfile_writeAddr_2_valid, - output [4:0] io_debug_regfile_writeAddr_2_bits, - output io_debug_regfile_writeAddr_3_valid, - output [4:0] io_debug_regfile_writeAddr_3_bits, - output io_debug_regfile_writeData_0_valid, - output [4:0] io_debug_regfile_writeData_0_bits_addr, - output [31:0] io_debug_regfile_writeData_0_bits_data, - output io_debug_regfile_writeData_1_valid, - output [4:0] io_debug_regfile_writeData_1_bits_addr, - output [31:0] io_debug_regfile_writeData_1_bits_data, - output io_debug_regfile_writeData_2_valid, - output [4:0] io_debug_regfile_writeData_2_bits_addr, - output [31:0] io_debug_regfile_writeData_2_bits_data, - output io_debug_regfile_writeData_3_valid, - output [4:0] io_debug_regfile_writeData_3_bits_addr, - output [31:0] io_debug_regfile_writeData_3_bits_data, - output io_debug_regfile_writeData_4_valid, - output [4:0] io_debug_regfile_writeData_4_bits_addr, - output [31:0] io_debug_regfile_writeData_4_bits_data, - output io_debug_regfile_writeData_5_valid, - output [4:0] io_debug_regfile_writeData_5_bits_addr, - output [31:0] io_debug_regfile_writeData_5_bits_data, - output io_debug_float_writeAddr_valid, - output [4:0] io_debug_float_writeAddr_bits, - output io_debug_float_writeData_0_valid, - output [31:0] io_debug_float_writeData_0_bits_addr, - io_debug_float_writeData_0_bits_data, - output io_debug_float_writeData_1_valid, - output [31:0] io_debug_float_writeData_1_bits_addr, - io_debug_float_writeData_1_bits_data + input io_ebus_fault_valid ); - wire _arb_io_in_1_ready; - wire _arb_io_in_2_ready; - wire _arb_io_out_valid; - wire [4:0] _arb_io_out_bits_addr; - wire [31:0] _arb_io_out_bits_data; - wire [22:0] _fRegfile_io_read_ports_0_data_mantissa; - wire [7:0] _fRegfile_io_read_ports_0_data_exponent; - wire _fRegfile_io_read_ports_0_data_sign; - wire [22:0] _fRegfile_io_read_ports_1_data_mantissa; - wire [7:0] _fRegfile_io_read_ports_1_data_exponent; - wire _fRegfile_io_read_ports_1_data_sign; - wire [22:0] _fRegfile_io_read_ports_2_data_mantissa; - wire [7:0] _fRegfile_io_read_ports_2_data_exponent; - wire _fRegfile_io_read_ports_2_data_sign; - wire [31:0] _fRegfile_io_scoreboard; - wire [31:0] _fRegfile_io_busPort_data_0; - wire _floatCore_io_inst_ready; - wire _floatCore_io_read_ports_0_valid; - wire [4:0] _floatCore_io_read_ports_0_addr; - wire _floatCore_io_read_ports_1_valid; - wire [4:0] _floatCore_io_read_ports_1_addr; - wire _floatCore_io_read_ports_2_valid; - wire [4:0] _floatCore_io_read_ports_2_addr; - wire _floatCore_io_write_ports_0_valid; - wire [4:0] _floatCore_io_write_ports_0_addr; - wire [22:0] _floatCore_io_write_ports_0_data_mantissa; - wire [7:0] _floatCore_io_write_ports_0_data_exponent; - wire _floatCore_io_write_ports_0_data_sign; - wire _floatCore_io_write_ports_1_valid; - wire [4:0] _floatCore_io_write_ports_1_addr; - wire [22:0] _floatCore_io_write_ports_1_data_mantissa; - wire [7:0] _floatCore_io_write_ports_1_data_exponent; - wire _floatCore_io_write_ports_1_data_sign; - wire _floatCore_io_scalar_rd_valid; - wire [4:0] _floatCore_io_scalar_rd_bits_addr; - wire [31:0] _floatCore_io_scalar_rd_bits_data; - wire _floatCore_io_csr_in_fflags_valid; - wire [4:0] _floatCore_io_csr_in_fflags_bits; - wire _fault_manager_io_out_valid; - wire [31:0] _fault_manager_io_out_bits_mepc; - wire [31:0] _fault_manager_io_out_bits_mtval; - wire [31:0] _fault_manager_io_out_bits_mcause; - wire _dvu_io_req_ready; - wire _dvu_io_rd_valid; - wire [4:0] _dvu_io_rd_bits_addr; - wire [31:0] _dvu_io_rd_bits_data; - wire _mlu_io_rd_valid; - wire [4:0] _mlu_io_rd_bits_addr; - wire [31:0] _mlu_io_rd_bits_data; - wire _lsu_io_req_0_ready; - wire _lsu_io_req_1_ready; - wire _lsu_io_req_2_ready; - wire _lsu_io_req_3_ready; - wire _lsu_io_rd_valid; - wire [4:0] _lsu_io_rd_bits_addr; - wire [31:0] _lsu_io_rd_bits_data; - wire _lsu_io_rd_flt_valid; - wire [4:0] _lsu_io_rd_flt_bits_addr; - wire [31:0] _lsu_io_rd_flt_bits_data; - wire _lsu_io_ibus_valid; - wire [31:0] _lsu_io_ibus_addr; - wire _lsu_io_dbus_valid; - wire _lsu_io_dbus_write; - wire [31:0] _lsu_io_dbus_addr; - wire [127:0] _lsu_io_dbus_wdata; - wire _lsu_io_flush_valid; - wire _lsu_io_flush_fencei; - wire [31:0] _lsu_io_flush_pcNext; - wire _lsu_io_fault_valid; - wire _lsu_io_fault_bits_write; - wire [31:0] _lsu_io_fault_bits_addr; - wire [31:0] _lsu_io_fault_bits_epc; - wire [1:0] _lsu_io_storeCount; - wire _lsu_io_active; - wire _bru_3_io_rd_valid; - wire [4:0] _bru_3_io_rd_bits_addr; - wire [31:0] _bru_3_io_rd_bits_data; - wire _bru_3_io_taken_valid; - wire [31:0] _bru_3_io_taken_value; - wire _bru_2_io_rd_valid; - wire [4:0] _bru_2_io_rd_bits_addr; - wire [31:0] _bru_2_io_rd_bits_data; - wire _bru_2_io_taken_valid; - wire [31:0] _bru_2_io_taken_value; - wire _bru_1_io_rd_valid; - wire [4:0] _bru_1_io_rd_bits_addr; - wire [31:0] _bru_1_io_rd_bits_data; - wire _bru_1_io_taken_valid; - wire [31:0] _bru_1_io_taken_value; - wire _bru_0_io_csr_in_mode_valid; - wire [1:0] _bru_0_io_csr_in_mode_bits; - wire _bru_0_io_csr_in_mcause_valid; - wire [31:0] _bru_0_io_csr_in_mcause_bits; - wire _bru_0_io_csr_in_mepc_valid; - wire [31:0] _bru_0_io_csr_in_mepc_bits; - wire _bru_0_io_csr_in_mtval_valid; - wire [31:0] _bru_0_io_csr_in_mtval_bits; - wire _bru_0_io_csr_in_halt; - wire _bru_0_io_csr_in_fault; - wire _bru_0_io_csr_in_wfi; - wire _bru_0_io_rd_valid; - wire [4:0] _bru_0_io_rd_bits_addr; - wire [31:0] _bru_0_io_rd_bits_data; - wire _bru_0_io_taken_valid; - wire [31:0] _bru_0_io_taken_value; - wire _bru_0_io_interlock; - wire _alu_3_io_rd_valid; - wire [4:0] _alu_3_io_rd_bits_addr; - wire [31:0] _alu_3_io_rd_bits_data; - wire _alu_2_io_rd_valid; - wire [4:0] _alu_2_io_rd_bits_addr; - wire [31:0] _alu_2_io_rd_bits_data; - wire _alu_1_io_rd_valid; - wire [4:0] _alu_1_io_rd_bits_addr; - wire [31:0] _alu_1_io_rd_bits_data; - wire _alu_0_io_rd_valid; - wire [4:0] _alu_0_io_rd_bits_addr; - wire [31:0] _alu_0_io_rd_bits_data; - wire _dispatch_io_csrFault_0; - wire _dispatch_io_jalFault_0; - wire _dispatch_io_jalFault_1; - wire _dispatch_io_jalFault_2; - wire _dispatch_io_jalFault_3; - wire _dispatch_io_jalrFault_0; - wire _dispatch_io_jalrFault_1; - wire _dispatch_io_jalrFault_2; - wire _dispatch_io_jalrFault_3; - wire _dispatch_io_bxxFault_0; - wire _dispatch_io_bxxFault_1; - wire _dispatch_io_bxxFault_2; - wire _dispatch_io_bxxFault_3; - wire _dispatch_io_undefFault_0; - wire [31:0] _dispatch_io_bruTarget_0; - wire [31:0] _dispatch_io_bruTarget_1; - wire [31:0] _dispatch_io_bruTarget_2; - wire [31:0] _dispatch_io_bruTarget_3; - wire _dispatch_io_inst_0_ready; - wire _dispatch_io_inst_1_ready; - wire _dispatch_io_inst_2_ready; - wire _dispatch_io_inst_3_ready; - wire _dispatch_io_rs1Read_0_valid; - wire [4:0] _dispatch_io_rs1Read_0_addr; - wire _dispatch_io_rs1Read_1_valid; - wire [4:0] _dispatch_io_rs1Read_1_addr; - wire _dispatch_io_rs1Read_2_valid; - wire [4:0] _dispatch_io_rs1Read_2_addr; - wire _dispatch_io_rs1Read_3_valid; - wire [4:0] _dispatch_io_rs1Read_3_addr; - wire _dispatch_io_rs1Set_0_valid; - wire [31:0] _dispatch_io_rs1Set_0_value; - wire _dispatch_io_rs1Set_1_valid; - wire [31:0] _dispatch_io_rs1Set_1_value; - wire _dispatch_io_rs1Set_2_valid; - wire [31:0] _dispatch_io_rs1Set_2_value; - wire _dispatch_io_rs1Set_3_valid; - wire [31:0] _dispatch_io_rs1Set_3_value; - wire _dispatch_io_rs2Read_0_valid; - wire [4:0] _dispatch_io_rs2Read_0_addr; - wire _dispatch_io_rs2Read_1_valid; - wire [4:0] _dispatch_io_rs2Read_1_addr; - wire _dispatch_io_rs2Read_2_valid; - wire [4:0] _dispatch_io_rs2Read_2_addr; - wire _dispatch_io_rs2Read_3_valid; - wire [4:0] _dispatch_io_rs2Read_3_addr; - wire _dispatch_io_rs2Set_0_valid; - wire [31:0] _dispatch_io_rs2Set_0_value; - wire _dispatch_io_rs2Set_1_valid; - wire [31:0] _dispatch_io_rs2Set_1_value; - wire _dispatch_io_rs2Set_2_valid; - wire [31:0] _dispatch_io_rs2Set_2_value; - wire _dispatch_io_rs2Set_3_valid; - wire [31:0] _dispatch_io_rs2Set_3_value; - wire _dispatch_io_rdMark_0_valid; - wire [4:0] _dispatch_io_rdMark_0_addr; - wire _dispatch_io_rdMark_1_valid; - wire [4:0] _dispatch_io_rdMark_1_addr; - wire _dispatch_io_rdMark_2_valid; - wire [4:0] _dispatch_io_rdMark_2_addr; - wire _dispatch_io_rdMark_3_valid; - wire [4:0] _dispatch_io_rdMark_3_addr; - wire _dispatch_io_busRead_0_bypass; - wire _dispatch_io_busRead_0_immen; - wire [31:0] _dispatch_io_busRead_0_immed; - wire _dispatch_io_busRead_1_bypass; - wire [31:0] _dispatch_io_busRead_1_immed; - wire _dispatch_io_busRead_2_bypass; - wire [31:0] _dispatch_io_busRead_2_immed; - wire _dispatch_io_busRead_3_bypass; - wire [31:0] _dispatch_io_busRead_3_immed; - wire _dispatch_io_rdMark_flt_valid; - wire [4:0] _dispatch_io_rdMark_flt_addr; - wire _dispatch_io_alu_0_valid; - wire [4:0] _dispatch_io_alu_0_bits_addr; - wire [4:0] _dispatch_io_alu_0_bits_op; - wire _dispatch_io_alu_1_valid; - wire [4:0] _dispatch_io_alu_1_bits_addr; - wire [4:0] _dispatch_io_alu_1_bits_op; - wire _dispatch_io_alu_2_valid; - wire [4:0] _dispatch_io_alu_2_bits_addr; - wire [4:0] _dispatch_io_alu_2_bits_op; - wire _dispatch_io_alu_3_valid; - wire [4:0] _dispatch_io_alu_3_bits_addr; - wire [4:0] _dispatch_io_alu_3_bits_op; - wire _dispatch_io_bru_0_valid; - wire _dispatch_io_bru_0_bits_fwd; - wire [3:0] _dispatch_io_bru_0_bits_op; - wire [31:0] _dispatch_io_bru_0_bits_pc; - wire [31:0] _dispatch_io_bru_0_bits_target; - wire [4:0] _dispatch_io_bru_0_bits_link; - wire _dispatch_io_bru_1_valid; - wire _dispatch_io_bru_1_bits_fwd; - wire [3:0] _dispatch_io_bru_1_bits_op; - wire [31:0] _dispatch_io_bru_1_bits_pc; - wire [31:0] _dispatch_io_bru_1_bits_target; - wire [4:0] _dispatch_io_bru_1_bits_link; - wire _dispatch_io_bru_2_valid; - wire _dispatch_io_bru_2_bits_fwd; - wire [3:0] _dispatch_io_bru_2_bits_op; - wire [31:0] _dispatch_io_bru_2_bits_pc; - wire [31:0] _dispatch_io_bru_2_bits_target; - wire [4:0] _dispatch_io_bru_2_bits_link; - wire _dispatch_io_bru_3_valid; - wire _dispatch_io_bru_3_bits_fwd; - wire [3:0] _dispatch_io_bru_3_bits_op; - wire [31:0] _dispatch_io_bru_3_bits_pc; - wire [31:0] _dispatch_io_bru_3_bits_target; - wire [4:0] _dispatch_io_bru_3_bits_link; - wire _dispatch_io_csr_valid; - wire [4:0] _dispatch_io_csr_bits_addr; - wire [11:0] _dispatch_io_csr_bits_index; - wire [1:0] _dispatch_io_csr_bits_op; - wire _dispatch_io_lsu_0_valid; - wire _dispatch_io_lsu_0_bits_store; - wire [4:0] _dispatch_io_lsu_0_bits_addr; - wire [4:0] _dispatch_io_lsu_0_bits_op; - wire [31:0] _dispatch_io_lsu_0_bits_pc; - wire _dispatch_io_lsu_1_valid; - wire _dispatch_io_lsu_1_bits_store; - wire [4:0] _dispatch_io_lsu_1_bits_addr; - wire [4:0] _dispatch_io_lsu_1_bits_op; - wire [31:0] _dispatch_io_lsu_1_bits_pc; - wire _dispatch_io_lsu_2_valid; - wire _dispatch_io_lsu_2_bits_store; - wire [4:0] _dispatch_io_lsu_2_bits_addr; - wire [4:0] _dispatch_io_lsu_2_bits_op; - wire [31:0] _dispatch_io_lsu_2_bits_pc; - wire _dispatch_io_lsu_3_valid; - wire _dispatch_io_lsu_3_bits_store; - wire [4:0] _dispatch_io_lsu_3_bits_addr; - wire [4:0] _dispatch_io_lsu_3_bits_op; - wire [31:0] _dispatch_io_lsu_3_bits_pc; - wire _dispatch_io_mlu_0_valid; - wire [4:0] _dispatch_io_mlu_0_bits_addr; - wire [2:0] _dispatch_io_mlu_0_bits_op; - wire _dispatch_io_mlu_1_valid; - wire [4:0] _dispatch_io_mlu_1_bits_addr; - wire [2:0] _dispatch_io_mlu_1_bits_op; - wire _dispatch_io_mlu_2_valid; - wire [4:0] _dispatch_io_mlu_2_bits_addr; - wire [2:0] _dispatch_io_mlu_2_bits_op; - wire _dispatch_io_mlu_3_valid; - wire [4:0] _dispatch_io_mlu_3_bits_addr; - wire [2:0] _dispatch_io_mlu_3_bits_op; - wire _dispatch_io_dvu_0_valid; - wire [4:0] _dispatch_io_dvu_0_bits_addr; - wire [1:0] _dispatch_io_dvu_0_bits_op; - wire _dispatch_io_float_valid; - wire [2:0] _dispatch_io_float_bits_opcode; - wire [4:0] _dispatch_io_float_bits_funct5; - wire [4:0] _dispatch_io_float_bits_rs3; - wire [4:0] _dispatch_io_float_bits_rs2; - wire [4:0] _dispatch_io_float_bits_rs1; - wire [2:0] _dispatch_io_float_bits_rm; - wire [31:0] _dispatch_io_float_bits_inst; - wire [31:0] _dispatch_io_float_bits_pc; - wire _dispatch_io_float_bits_scalar_rd; - wire _dispatch_io_float_bits_scalar_rs1; - wire [4:0] _dispatch_io_float_bits_rd; - wire _dispatch_io_float_bits_uses_rs3; - wire _dispatch_io_float_bits_uses_rs2; - wire [4:0] _dispatch_io_fbusPortAddr; - wire _dispatch_io_slog; - wire [31:0] _csr_io_csr_out_value_4; - wire _csr_io_rd_valid; - wire [4:0] _csr_io_rd_bits_addr; - wire [31:0] _csr_io_rd_bits_data; - wire [1:0] _csr_io_bru_out_mode; - wire [31:0] _csr_io_bru_out_mepc; - wire [31:0] _csr_io_bru_out_mtvec; - wire [2:0] _csr_io_float_out_frm; - wire _csr_io_halted; - wire _csr_io_wfi; - wire _fetch_io_ibus_valid; - wire [31:0] _fetch_io_ibus_addr; - wire _fetch_io_inst_lanes_0_valid; - wire [31:0] _fetch_io_inst_lanes_0_bits_addr; - wire [31:0] _fetch_io_inst_lanes_0_bits_inst; - wire _fetch_io_inst_lanes_0_bits_brchFwd; - wire _fetch_io_inst_lanes_1_valid; - wire [31:0] _fetch_io_inst_lanes_1_bits_addr; - wire [31:0] _fetch_io_inst_lanes_1_bits_inst; - wire _fetch_io_inst_lanes_1_bits_brchFwd; - wire _fetch_io_inst_lanes_2_valid; - wire [31:0] _fetch_io_inst_lanes_2_bits_addr; - wire [31:0] _fetch_io_inst_lanes_2_bits_inst; - wire _fetch_io_inst_lanes_2_bits_brchFwd; - wire _fetch_io_inst_lanes_3_valid; - wire [31:0] _fetch_io_inst_lanes_3_bits_addr; - wire [31:0] _fetch_io_inst_lanes_3_bits_inst; - wire _fetch_io_inst_lanes_3_bits_brchFwd; - wire [31:0] _fetch_io_pc; - wire [31:0] _regfile_io_target_0_data; - wire [31:0] _regfile_io_target_1_data; - wire [31:0] _regfile_io_target_2_data; - wire [31:0] _regfile_io_target_3_data; - wire [31:0] _regfile_io_busPort_addr_0; - wire [31:0] _regfile_io_busPort_addr_1; - wire [31:0] _regfile_io_busPort_addr_2; - wire [31:0] _regfile_io_busPort_addr_3; - wire [31:0] _regfile_io_busPort_data_0; - wire [31:0] _regfile_io_busPort_data_1; - wire [31:0] _regfile_io_busPort_data_2; - wire [31:0] _regfile_io_busPort_data_3; - wire _regfile_io_readData_0_valid; - wire [31:0] _regfile_io_readData_0_data; - wire _regfile_io_readData_1_valid; - wire [31:0] _regfile_io_readData_1_data; - wire _regfile_io_readData_2_valid; - wire [31:0] _regfile_io_readData_2_data; - wire _regfile_io_readData_3_valid; - wire [31:0] _regfile_io_readData_3_data; - wire _regfile_io_readData_4_valid; - wire [31:0] _regfile_io_readData_4_data; - wire _regfile_io_readData_5_valid; - wire [31:0] _regfile_io_readData_5_data; - wire _regfile_io_readData_6_valid; - wire [31:0] _regfile_io_readData_6_data; - wire _regfile_io_readData_7_valid; - wire [31:0] _regfile_io_readData_7_data; - wire [31:0] _regfile_io_scoreboard_regd; - wire [31:0] _regfile_io_scoreboard_comb; - wire [5:0] _regfile_io_rfwriteCount; - wire branchTaken = + wire _arb_io_in_1_ready; + wire _arb_io_in_2_ready; + wire _arb_io_out_valid; + wire [4:0] _arb_io_out_bits_addr; + wire [31:0] _arb_io_out_bits_data; + wire [22:0] _fRegfile_io_read_ports_0_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_0_data_exponent; + wire _fRegfile_io_read_ports_0_data_sign; + wire [22:0] _fRegfile_io_read_ports_1_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_1_data_exponent; + wire _fRegfile_io_read_ports_1_data_sign; + wire [22:0] _fRegfile_io_read_ports_2_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_2_data_exponent; + wire _fRegfile_io_read_ports_2_data_sign; + wire [31:0] _fRegfile_io_scoreboard; + wire [31:0] _fRegfile_io_busPort_data_0; + wire _floatCore_io_inst_ready; + wire _floatCore_io_read_ports_0_valid; + wire [4:0] _floatCore_io_read_ports_0_addr; + wire _floatCore_io_read_ports_1_valid; + wire [4:0] _floatCore_io_read_ports_1_addr; + wire _floatCore_io_read_ports_2_valid; + wire [4:0] _floatCore_io_read_ports_2_addr; + wire _floatCore_io_write_ports_0_valid; + wire [4:0] _floatCore_io_write_ports_0_addr; + wire [22:0] _floatCore_io_write_ports_0_data_mantissa; + wire [7:0] _floatCore_io_write_ports_0_data_exponent; + wire _floatCore_io_write_ports_0_data_sign; + wire _floatCore_io_write_ports_1_valid; + wire [4:0] _floatCore_io_write_ports_1_addr; + wire [22:0] _floatCore_io_write_ports_1_data_mantissa; + wire [7:0] _floatCore_io_write_ports_1_data_exponent; + wire _floatCore_io_write_ports_1_data_sign; + wire _floatCore_io_scalar_rd_valid; + wire [4:0] _floatCore_io_scalar_rd_bits_addr; + wire [31:0] _floatCore_io_scalar_rd_bits_data; + wire _floatCore_io_csr_in_fflags_valid; + wire [4:0] _floatCore_io_csr_in_fflags_bits; + wire _csrReqArbiter_io_out_valid; + wire [4:0] _csrReqArbiter_io_out_bits_addr; + wire [11:0] _csrReqArbiter_io_out_bits_index; + wire [4:0] _csrReqArbiter_io_out_bits_rs1; + wire [1:0] _csrReqArbiter_io_out_bits_op; + wire _dvu_io_req_ready; + wire _dvu_io_rd_valid; + wire [4:0] _dvu_io_rd_bits_addr; + wire [31:0] _dvu_io_rd_bits_data; + wire _mlu_io_req_1_ready; + wire _mlu_io_req_2_ready; + wire _mlu_io_req_3_ready; + wire _mlu_io_rd_valid; + wire [4:0] _mlu_io_rd_bits_addr; + wire [31:0] _mlu_io_rd_bits_data; + wire _bru_3_io_rd_valid; + wire [4:0] _bru_3_io_rd_bits_addr; + wire [31:0] _bru_3_io_rd_bits_data; + wire _bru_3_io_taken_valid; + wire [31:0] _bru_3_io_taken_value; + wire _bru_2_io_rd_valid; + wire [4:0] _bru_2_io_rd_bits_addr; + wire [31:0] _bru_2_io_rd_bits_data; + wire _bru_2_io_taken_valid; + wire [31:0] _bru_2_io_taken_value; + wire _bru_1_io_rd_valid; + wire [4:0] _bru_1_io_rd_bits_addr; + wire [31:0] _bru_1_io_rd_bits_data; + wire _bru_1_io_taken_valid; + wire [31:0] _bru_1_io_taken_value; + wire _bru_0_io_csr_in_mode_valid; + wire _bru_0_io_csr_in_mcause_valid; + wire [31:0] _bru_0_io_csr_in_mcause_bits; + wire _bru_0_io_csr_in_mepc_valid; + wire [31:0] _bru_0_io_csr_in_mepc_bits; + wire _bru_0_io_csr_in_mtval_valid; + wire [31:0] _bru_0_io_csr_in_mtval_bits; + wire _bru_0_io_csr_in_halt; + wire _bru_0_io_csr_in_fault; + wire _bru_0_io_csr_in_wfi; + wire _bru_0_io_rd_valid; + wire [4:0] _bru_0_io_rd_bits_addr; + wire [31:0] _bru_0_io_rd_bits_data; + wire _bru_0_io_taken_valid; + wire [31:0] _bru_0_io_taken_value; + wire _bru_0_io_actually_taken; + wire [31:0] _bru_0_io_real_target; + wire _bru_0_io_interlock; + wire _alu_3_io_rd_valid; + wire [4:0] _alu_3_io_rd_bits_addr; + wire [31:0] _alu_3_io_rd_bits_data; + wire _alu_2_io_rd_valid; + wire [4:0] _alu_2_io_rd_bits_addr; + wire [31:0] _alu_2_io_rd_bits_data; + wire _alu_1_io_rd_valid; + wire [4:0] _alu_1_io_rd_bits_addr; + wire [31:0] _alu_1_io_rd_bits_data; + wire _alu_0_io_rd_valid; + wire [4:0] _alu_0_io_rd_bits_addr; + wire [31:0] _alu_0_io_rd_bits_data; + wire [4:0] _retirement_buffer_io_nSpace; + wire [3:0] _retirement_buffer_io_nRetired; + wire _retirement_buffer_io_empty; + wire _retirement_buffer_io_trapPending; + wire _retirement_buffer_io_trapRetired; + wire _fault_manager_io_out_valid; + wire [31:0] _fault_manager_io_out_bits_mepc; + wire [31:0] _fault_manager_io_out_bits_mtval; + wire [31:0] _fault_manager_io_out_bits_mcause; + wire _fault_manager_io_out_bits_decode; + wire _lsu_io_req_0_ready; + wire _lsu_io_req_1_ready; + wire _lsu_io_req_2_ready; + wire _lsu_io_req_3_ready; + wire _lsu_io_rd_valid; + wire [4:0] _lsu_io_rd_bits_addr; + wire [31:0] _lsu_io_rd_bits_data; + wire _lsu_io_rd_flt_valid; + wire [4:0] _lsu_io_rd_flt_bits_addr; + wire [31:0] _lsu_io_rd_flt_bits_data; + wire _lsu_io_ibus_valid; + wire [31:0] _lsu_io_ibus_addr; + wire _lsu_io_flush_valid; + wire [31:0] _lsu_io_flush_pcNext; + wire _lsu_io_fault_valid; + wire _lsu_io_fault_bits_write; + wire [31:0] _lsu_io_fault_bits_addr; + wire [31:0] _lsu_io_fault_bits_epc; + wire [2:0] _lsu_io_queueCapacity; + wire _lsu_io_active; + wire _lsu_io_storeComplete_valid; + wire [31:0] _lsu_io_storeComplete_bits; + wire _dispatch_io_csrFault_0; + wire _dispatch_io_jalFault_0; + wire _dispatch_io_jalFault_1; + wire _dispatch_io_jalFault_2; + wire _dispatch_io_jalFault_3; + wire _dispatch_io_jalrFault_0; + wire _dispatch_io_jalrFault_1; + wire _dispatch_io_jalrFault_2; + wire _dispatch_io_jalrFault_3; + wire _dispatch_io_bxxFault_0; + wire _dispatch_io_bxxFault_1; + wire _dispatch_io_bxxFault_2; + wire _dispatch_io_bxxFault_3; + wire _dispatch_io_undefFault_0; + wire [31:0] _dispatch_io_bruTarget_0; + wire [31:0] _dispatch_io_bruTarget_1; + wire [31:0] _dispatch_io_bruTarget_2; + wire [31:0] _dispatch_io_bruTarget_3; + wire _dispatch_io_inst_0_ready; + wire _dispatch_io_inst_1_ready; + wire _dispatch_io_inst_2_ready; + wire _dispatch_io_inst_3_ready; + wire _dispatch_io_rs1Read_0_valid; + wire [4:0] _dispatch_io_rs1Read_0_addr; + wire _dispatch_io_rs1Read_1_valid; + wire [4:0] _dispatch_io_rs1Read_1_addr; + wire _dispatch_io_rs1Read_2_valid; + wire [4:0] _dispatch_io_rs1Read_2_addr; + wire _dispatch_io_rs1Read_3_valid; + wire [4:0] _dispatch_io_rs1Read_3_addr; + wire _dispatch_io_rs1Set_0_valid; + wire [31:0] _dispatch_io_rs1Set_0_value; + wire _dispatch_io_rs1Set_1_valid; + wire [31:0] _dispatch_io_rs1Set_1_value; + wire _dispatch_io_rs1Set_2_valid; + wire [31:0] _dispatch_io_rs1Set_2_value; + wire _dispatch_io_rs1Set_3_valid; + wire [31:0] _dispatch_io_rs1Set_3_value; + wire _dispatch_io_rs2Read_0_valid; + wire [4:0] _dispatch_io_rs2Read_0_addr; + wire _dispatch_io_rs2Read_1_valid; + wire [4:0] _dispatch_io_rs2Read_1_addr; + wire _dispatch_io_rs2Read_2_valid; + wire [4:0] _dispatch_io_rs2Read_2_addr; + wire _dispatch_io_rs2Read_3_valid; + wire [4:0] _dispatch_io_rs2Read_3_addr; + wire _dispatch_io_rs2Set_0_valid; + wire [31:0] _dispatch_io_rs2Set_0_value; + wire _dispatch_io_rs2Set_1_valid; + wire [31:0] _dispatch_io_rs2Set_1_value; + wire _dispatch_io_rs2Set_2_valid; + wire [31:0] _dispatch_io_rs2Set_2_value; + wire _dispatch_io_rs2Set_3_valid; + wire [31:0] _dispatch_io_rs2Set_3_value; + wire _dispatch_io_rdMark_0_valid; + wire [4:0] _dispatch_io_rdMark_0_addr; + wire _dispatch_io_rdMark_1_valid; + wire [4:0] _dispatch_io_rdMark_1_addr; + wire _dispatch_io_rdMark_2_valid; + wire [4:0] _dispatch_io_rdMark_2_addr; + wire _dispatch_io_rdMark_3_valid; + wire [4:0] _dispatch_io_rdMark_3_addr; + wire [31:0] _dispatch_io_busRead_0_immed; + wire [31:0] _dispatch_io_busRead_1_immed; + wire [31:0] _dispatch_io_busRead_2_immed; + wire [31:0] _dispatch_io_busRead_3_immed; + wire _dispatch_io_rdMark_flt_valid; + wire [4:0] _dispatch_io_rdMark_flt_addr; + wire _dispatch_io_alu_0_valid; + wire [4:0] _dispatch_io_alu_0_bits_addr; + wire [5:0] _dispatch_io_alu_0_bits_op; + wire _dispatch_io_alu_1_valid; + wire [4:0] _dispatch_io_alu_1_bits_addr; + wire [5:0] _dispatch_io_alu_1_bits_op; + wire _dispatch_io_alu_2_valid; + wire [4:0] _dispatch_io_alu_2_bits_addr; + wire [5:0] _dispatch_io_alu_2_bits_op; + wire _dispatch_io_alu_3_valid; + wire [4:0] _dispatch_io_alu_3_bits_addr; + wire [5:0] _dispatch_io_alu_3_bits_op; + wire _dispatch_io_bru_0_valid; + wire _dispatch_io_bru_0_bits_fwd; + wire [3:0] _dispatch_io_bru_0_bits_op; + wire [31:0] _dispatch_io_bru_0_bits_pc; + wire [31:0] _dispatch_io_bru_0_bits_target; + wire [4:0] _dispatch_io_bru_0_bits_link; + wire _dispatch_io_bru_1_valid; + wire _dispatch_io_bru_1_bits_fwd; + wire [3:0] _dispatch_io_bru_1_bits_op; + wire [31:0] _dispatch_io_bru_1_bits_pc; + wire [31:0] _dispatch_io_bru_1_bits_target; + wire [4:0] _dispatch_io_bru_1_bits_link; + wire _dispatch_io_bru_2_valid; + wire _dispatch_io_bru_2_bits_fwd; + wire [3:0] _dispatch_io_bru_2_bits_op; + wire [31:0] _dispatch_io_bru_2_bits_pc; + wire [31:0] _dispatch_io_bru_2_bits_target; + wire [4:0] _dispatch_io_bru_2_bits_link; + wire _dispatch_io_bru_3_valid; + wire _dispatch_io_bru_3_bits_fwd; + wire [3:0] _dispatch_io_bru_3_bits_op; + wire [31:0] _dispatch_io_bru_3_bits_pc; + wire [31:0] _dispatch_io_bru_3_bits_target; + wire [4:0] _dispatch_io_bru_3_bits_link; + wire _dispatch_io_csr_valid; + wire [4:0] _dispatch_io_csr_bits_addr; + wire [11:0] _dispatch_io_csr_bits_index; + wire [4:0] _dispatch_io_csr_bits_rs1; + wire [1:0] _dispatch_io_csr_bits_op; + wire _dispatch_io_lsu_0_valid; + wire _dispatch_io_lsu_0_bits_store; + wire [4:0] _dispatch_io_lsu_0_bits_addr; + wire [4:0] _dispatch_io_lsu_0_bits_op; + wire [31:0] _dispatch_io_lsu_0_bits_pc; + wire _dispatch_io_lsu_1_valid; + wire _dispatch_io_lsu_1_bits_store; + wire [4:0] _dispatch_io_lsu_1_bits_addr; + wire [4:0] _dispatch_io_lsu_1_bits_op; + wire [31:0] _dispatch_io_lsu_1_bits_pc; + wire _dispatch_io_lsu_2_valid; + wire _dispatch_io_lsu_2_bits_store; + wire [4:0] _dispatch_io_lsu_2_bits_addr; + wire [4:0] _dispatch_io_lsu_2_bits_op; + wire [31:0] _dispatch_io_lsu_2_bits_pc; + wire _dispatch_io_lsu_3_valid; + wire _dispatch_io_lsu_3_bits_store; + wire [4:0] _dispatch_io_lsu_3_bits_addr; + wire [4:0] _dispatch_io_lsu_3_bits_op; + wire [31:0] _dispatch_io_lsu_3_bits_pc; + wire _dispatch_io_mlu_0_valid; + wire [4:0] _dispatch_io_mlu_0_bits_addr; + wire [2:0] _dispatch_io_mlu_0_bits_op; + wire _dispatch_io_mlu_1_valid; + wire [4:0] _dispatch_io_mlu_1_bits_addr; + wire [2:0] _dispatch_io_mlu_1_bits_op; + wire _dispatch_io_mlu_2_valid; + wire [4:0] _dispatch_io_mlu_2_bits_addr; + wire [2:0] _dispatch_io_mlu_2_bits_op; + wire _dispatch_io_mlu_3_valid; + wire [4:0] _dispatch_io_mlu_3_bits_addr; + wire [2:0] _dispatch_io_mlu_3_bits_op; + wire _dispatch_io_dvu_0_valid; + wire [4:0] _dispatch_io_dvu_0_bits_addr; + wire [2:0] _dispatch_io_dvu_0_bits_op; + wire _dispatch_io_float_valid; + wire [2:0] _dispatch_io_float_bits_opcode; + wire [4:0] _dispatch_io_float_bits_funct5; + wire [2:0] _dispatch_io_float_bits_src_fmt; + wire [2:0] _dispatch_io_float_bits_dst_fmt; + wire [4:0] _dispatch_io_float_bits_rs3; + wire [4:0] _dispatch_io_float_bits_rs2; + wire [4:0] _dispatch_io_float_bits_rs1; + wire [2:0] _dispatch_io_float_bits_rm; + wire [31:0] _dispatch_io_float_bits_inst; + wire [31:0] _dispatch_io_float_bits_pc; + wire _dispatch_io_float_bits_scalar_rd; + wire _dispatch_io_float_bits_scalar_rs1; + wire _dispatch_io_float_bits_float_rs1; + wire [4:0] _dispatch_io_float_bits_rd; + wire _dispatch_io_float_bits_uses_rs3; + wire _dispatch_io_float_bits_uses_rs2; + wire [4:0] _dispatch_io_fbusPortAddr; + wire _dispatch_io_branch_0; + wire _dispatch_io_branch_1; + wire _dispatch_io_branch_2; + wire _dispatch_io_branch_3; + wire _dispatch_io_jump_0; + wire _dispatch_io_jump_1; + wire _dispatch_io_jump_2; + wire _dispatch_io_jump_3; + wire _csr_io_rd_valid; + wire [4:0] _csr_io_rd_bits_addr; + wire [31:0] _csr_io_rd_bits_data; + wire [31:0] _csr_io_bru_out_mepc; + wire [31:0] _csr_io_bru_out_mtvec; + wire _csr_io_bru_out_interrupt; + wire [31:0] _csr_io_bru_out_interrupt_cause; + wire [2:0] _csr_io_float_out_frm; + wire _csr_io_halted; + wire _csr_io_wfi; + wire _csr_io_dm_debug_mode; + wire _csr_io_dm_entering_debug_mode; + wire _csr_io_dm_single_step; + wire _csr_io_dm_dcsr_step; + wire _csr_io_dm_debug_pc_valid; + wire [31:0] _csr_io_dm_debug_pc_bits; + wire _fetch_io_ibus_valid; + wire [31:0] _fetch_io_ibus_addr; + wire _fetch_io_inst_lanes_0_valid; + wire [31:0] _fetch_io_inst_lanes_0_bits_addr; + wire [31:0] _fetch_io_inst_lanes_0_bits_inst; + wire _fetch_io_inst_lanes_0_bits_brchFwd; + wire _fetch_io_inst_lanes_1_valid; + wire [31:0] _fetch_io_inst_lanes_1_bits_addr; + wire [31:0] _fetch_io_inst_lanes_1_bits_inst; + wire _fetch_io_inst_lanes_1_bits_brchFwd; + wire _fetch_io_inst_lanes_2_valid; + wire [31:0] _fetch_io_inst_lanes_2_bits_addr; + wire [31:0] _fetch_io_inst_lanes_2_bits_inst; + wire _fetch_io_inst_lanes_2_bits_brchFwd; + wire _fetch_io_inst_lanes_3_valid; + wire [31:0] _fetch_io_inst_lanes_3_bits_addr; + wire [31:0] _fetch_io_inst_lanes_3_bits_inst; + wire _fetch_io_inst_lanes_3_bits_brchFwd; + wire [31:0] _fetch_io_pc; + wire _fetch_io_fault_valid; + wire [31:0] _fetch_io_fault_bits; + wire [31:0] _regfile_io_target_0_data; + wire [31:0] _regfile_io_target_1_data; + wire [31:0] _regfile_io_target_2_data; + wire [31:0] _regfile_io_target_3_data; + wire [31:0] _regfile_io_busPort_addr_0; + wire [31:0] _regfile_io_busPort_addr_1; + wire [31:0] _regfile_io_busPort_addr_2; + wire [31:0] _regfile_io_busPort_addr_3; + wire [31:0] _regfile_io_busPort_data_0; + wire [31:0] _regfile_io_busPort_data_1; + wire [31:0] _regfile_io_busPort_data_2; + wire [31:0] _regfile_io_busPort_data_3; + wire [31:0] _regfile_io_readData_0_data; + wire [31:0] _regfile_io_readData_1_data; + wire [31:0] _regfile_io_readData_2_data; + wire [31:0] _regfile_io_readData_3_data; + wire [31:0] _regfile_io_readData_4_data; + wire [31:0] _regfile_io_readData_5_data; + wire [31:0] _regfile_io_readData_6_data; + wire [31:0] _regfile_io_readData_7_data; + wire [31:0] _regfile_io_scoreboard_regd; + wire [31:0] _regfile_io_scoreboard_comb; + wire branchTaken = _bru_0_io_taken_valid | _bru_1_io_taken_valid | _bru_2_io_taken_valid | _bru_3_io_taken_valid; - wire regfile_io_writeData_0_valid = + reg csr_io_rs1_REG; + reg stepTriggeredReg; + wire regfile_io_writeData_0_valid = _csr_io_rd_valid | _alu_0_io_rd_valid | _bru_0_io_rd_valid; - wire [4:0] regfile_io_writeData_0_bits_addr = + wire [4:0] regfile_io_writeData_0_bits_addr = (_csr_io_rd_valid ? _csr_io_rd_bits_addr : 5'h0) | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_addr : 5'h0) | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_addr : 5'h0); - wire [31:0] regfile_io_writeData_0_bits_data = - (_csr_io_rd_valid ? _csr_io_rd_bits_data : 32'h0) - | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_data : 32'h0) - | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_data : 32'h0); - wire regfile_io_writeData_1_valid = _alu_1_io_rd_valid | _bru_1_io_rd_valid; - wire [4:0] regfile_io_writeData_1_bits_addr = + wire regfile_io_writeData_1_valid = _alu_1_io_rd_valid | _bru_1_io_rd_valid; + wire [4:0] regfile_io_writeData_1_bits_addr = (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_addr : 5'h0) | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_addr : 5'h0); - wire [31:0] regfile_io_writeData_1_bits_data = - (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_data : 32'h0) - | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_data : 32'h0); - wire regfile_io_writeData_2_valid = _alu_2_io_rd_valid | _bru_2_io_rd_valid; - wire [4:0] regfile_io_writeData_2_bits_addr = + wire regfile_io_writeData_2_valid = _alu_2_io_rd_valid | _bru_2_io_rd_valid; + wire [4:0] regfile_io_writeData_2_bits_addr = (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_addr : 5'h0) | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_addr : 5'h0); - wire [31:0] regfile_io_writeData_2_bits_data = - (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_data : 32'h0) - | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_data : 32'h0); - wire regfile_io_writeData_3_valid = _alu_3_io_rd_valid | _bru_3_io_rd_valid; - wire [4:0] regfile_io_writeData_3_bits_addr = + wire regfile_io_writeData_3_valid = _alu_3_io_rd_valid | _bru_3_io_rd_valid; + wire [4:0] regfile_io_writeData_3_bits_addr = (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_addr : 5'h0) | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_addr : 5'h0); - wire [31:0] regfile_io_writeData_3_bits_data = - (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_data : 32'h0) - | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_data : 32'h0); - wire writeMask_2 = _bru_0_io_taken_valid | _bru_1_io_taken_valid; - reg slogValid; - reg [1:0] slogAddr; - reg [3:0] debugEn; - reg [31:0] debugAddr_0; - reg [31:0] debugAddr_1; - reg [31:0] debugAddr_2; - reg [31:0] debugAddr_3; - reg [31:0] debugInst_0; - reg [31:0] debugInst_1; - reg [31:0] debugInst_2; - reg [31:0] debugInst_3; - wire _debugBrch_T_1 = _bru_2_io_taken_valid | _bru_3_io_taken_valid; + wire fRegfile_io_write_ports_0_valid = + io_dm_float_rd_valid | _floatCore_io_write_ports_0_valid; + wire [4:0] fRegfile_io_write_ports_0_addr = + io_dm_float_rd_valid + ? io_dm_float_rd_addr + : _floatCore_io_write_ports_0_valid ? _floatCore_io_write_ports_0_addr : 5'h0; + wire writeMask_2 = _bru_0_io_taken_valid | _bru_1_io_taken_valid; always @(posedge clock or posedge reset) begin if (reset) begin - slogValid <= 1'h0; - slogAddr <= 2'h0; - debugEn <= 4'h0; - debugAddr_0 <= 32'h0; - debugAddr_1 <= 32'h0; - debugAddr_2 <= 32'h0; - debugAddr_3 <= 32'h0; - debugInst_0 <= 32'h0; - debugInst_1 <= 32'h0; - debugInst_2 <= 32'h0; - debugInst_3 <= 32'h0; + csr_io_rs1_REG <= 1'h0; + stepTriggeredReg <= 1'h0; end else begin - slogValid <= _dispatch_io_slog; - if (_dispatch_io_slog) - slogAddr <= _fetch_io_inst_lanes_0_bits_inst[13:12]; - debugEn <= - {_fetch_io_inst_lanes_0_valid & _dispatch_io_inst_0_ready & ~branchTaken, - _fetch_io_inst_lanes_1_valid & _dispatch_io_inst_1_ready & ~branchTaken, - _fetch_io_inst_lanes_2_valid & _dispatch_io_inst_2_ready & ~branchTaken, - _fetch_io_inst_lanes_3_valid & _dispatch_io_inst_3_ready & ~branchTaken}; - if (debugEn[0]) begin - debugAddr_0 <= _fetch_io_inst_lanes_0_bits_addr; - debugInst_0 <= _fetch_io_inst_lanes_0_bits_inst; - end - if (debugEn[1]) begin - debugAddr_1 <= _fetch_io_inst_lanes_1_bits_addr; - debugInst_1 <= _fetch_io_inst_lanes_1_bits_inst; - end - if (debugEn[2]) begin - debugAddr_2 <= _fetch_io_inst_lanes_2_bits_addr; - debugInst_2 <= _fetch_io_inst_lanes_2_bits_inst; - end - if (debugEn[3]) begin - debugAddr_3 <= _fetch_io_inst_lanes_3_bits_addr; - debugInst_3 <= _fetch_io_inst_lanes_3_bits_inst; - end + csr_io_rs1_REG <= _dispatch_io_csr_valid; + stepTriggeredReg <= + ~_csr_io_dm_debug_mode & _csr_io_dm_dcsr_step & _dispatch_io_inst_0_ready + & _fetch_io_inst_lanes_0_valid; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:8]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin - _RANDOM[i] = `RANDOM; - end - slogValid = _RANDOM[4'h0][0]; - slogAddr = _RANDOM[4'h0][2:1]; - debugEn = _RANDOM[4'h0][6:3]; - debugAddr_0 = {_RANDOM[4'h0][31:7], _RANDOM[4'h1][6:0]}; - debugAddr_1 = {_RANDOM[4'h1][31:7], _RANDOM[4'h2][6:0]}; - debugAddr_2 = {_RANDOM[4'h2][31:7], _RANDOM[4'h3][6:0]}; - debugAddr_3 = {_RANDOM[4'h3][31:7], _RANDOM[4'h4][6:0]}; - debugInst_0 = {_RANDOM[4'h4][31:7], _RANDOM[4'h5][6:0]}; - debugInst_1 = {_RANDOM[4'h5][31:7], _RANDOM[4'h6][6:0]}; - debugInst_2 = {_RANDOM[4'h6][31:7], _RANDOM[4'h7][6:0]}; - debugInst_3 = {_RANDOM[4'h7][31:7], _RANDOM[4'h8][6:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) begin - slogValid = 1'h0; - slogAddr = 2'h0; - debugEn = 4'h0; - debugAddr_0 = 32'h0; - debugAddr_1 = 32'h0; - debugAddr_2 = 32'h0; - debugAddr_3 = 32'h0; - debugInst_0 = 32'h0; - debugInst_1 = 32'h0; - debugInst_2 = 32'h0; - debugInst_3 = 32'h0; + csr_io_rs1_REG = 1'h0; + stepTriggeredReg = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -13033,14 +19141,9 @@ module SCore( .io_writeAddr_2_addr (_dispatch_io_rdMark_2_addr), .io_writeAddr_3_valid (_dispatch_io_rdMark_3_valid), .io_writeAddr_3_addr (_dispatch_io_rdMark_3_addr), - .io_busAddr_0_bypass (_dispatch_io_busRead_0_bypass), - .io_busAddr_0_immen (_dispatch_io_busRead_0_immen), .io_busAddr_0_immed (_dispatch_io_busRead_0_immed), - .io_busAddr_1_bypass (_dispatch_io_busRead_1_bypass), .io_busAddr_1_immed (_dispatch_io_busRead_1_immed), - .io_busAddr_2_bypass (_dispatch_io_busRead_2_bypass), .io_busAddr_2_immed (_dispatch_io_busRead_2_immed), - .io_busAddr_3_bypass (_dispatch_io_busRead_3_bypass), .io_busAddr_3_immed (_dispatch_io_busRead_3_immed), .io_target_0_data (_regfile_io_target_0_data), .io_target_1_data (_regfile_io_target_1_data), @@ -13054,34 +19157,37 @@ module SCore( .io_busPort_data_1 (_regfile_io_busPort_data_1), .io_busPort_data_2 (_regfile_io_busPort_data_2), .io_busPort_data_3 (_regfile_io_busPort_data_3), - .io_readData_0_valid (_regfile_io_readData_0_valid), + .io_debugBusPort_idx (io_dm_scalar_rs_idx), + .io_debugBusPort_data (io_dm_scalar_rs_data), .io_readData_0_data (_regfile_io_readData_0_data), - .io_readData_1_valid (_regfile_io_readData_1_valid), .io_readData_1_data (_regfile_io_readData_1_data), - .io_readData_2_valid (_regfile_io_readData_2_valid), .io_readData_2_data (_regfile_io_readData_2_data), - .io_readData_3_valid (_regfile_io_readData_3_valid), .io_readData_3_data (_regfile_io_readData_3_data), - .io_readData_4_valid (_regfile_io_readData_4_valid), .io_readData_4_data (_regfile_io_readData_4_data), - .io_readData_5_valid (_regfile_io_readData_5_valid), .io_readData_5_data (_regfile_io_readData_5_data), - .io_readData_6_valid (_regfile_io_readData_6_valid), .io_readData_6_data (_regfile_io_readData_6_data), - .io_readData_7_valid (_regfile_io_readData_7_valid), .io_readData_7_data (_regfile_io_readData_7_data), .io_writeData_0_valid (regfile_io_writeData_0_valid), .io_writeData_0_bits_addr (regfile_io_writeData_0_bits_addr), - .io_writeData_0_bits_data (regfile_io_writeData_0_bits_data), + .io_writeData_0_bits_data + ((_csr_io_rd_valid ? _csr_io_rd_bits_data : 32'h0) + | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_data : 32'h0) + | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_data : 32'h0)), .io_writeData_1_valid (regfile_io_writeData_1_valid), .io_writeData_1_bits_addr (regfile_io_writeData_1_bits_addr), - .io_writeData_1_bits_data (regfile_io_writeData_1_bits_data), + .io_writeData_1_bits_data + ((_alu_1_io_rd_valid ? _alu_1_io_rd_bits_data : 32'h0) + | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_data : 32'h0)), .io_writeData_2_valid (regfile_io_writeData_2_valid), .io_writeData_2_bits_addr (regfile_io_writeData_2_bits_addr), - .io_writeData_2_bits_data (regfile_io_writeData_2_bits_data), + .io_writeData_2_bits_data + ((_alu_2_io_rd_valid ? _alu_2_io_rd_bits_data : 32'h0) + | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_data : 32'h0)), .io_writeData_3_valid (regfile_io_writeData_3_valid), .io_writeData_3_bits_addr (regfile_io_writeData_3_bits_addr), - .io_writeData_3_bits_data (regfile_io_writeData_3_bits_data), + .io_writeData_3_bits_data + ((_alu_3_io_rd_valid ? _alu_3_io_rd_bits_data : 32'h0) + | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_data : 32'h0)), .io_writeData_4_valid (_arb_io_out_valid), .io_writeData_4_bits_addr (_arb_io_out_bits_addr), .io_writeData_4_bits_data (_arb_io_out_bits_data), @@ -13091,18 +19197,22 @@ module SCore( .io_writeMask_1_valid (_bru_0_io_taken_valid), .io_writeMask_2_valid (writeMask_2), .io_writeMask_3_valid (writeMask_2 | _bru_2_io_taken_valid), + .io_writeMask_5_valid (_lsu_io_fault_valid), + .io_pipelineFlush (_retirement_buffer_io_trapRetired), .io_scoreboard_regd (_regfile_io_scoreboard_regd), - .io_scoreboard_comb (_regfile_io_scoreboard_comb), - .io_rfwriteCount (_regfile_io_rfwriteCount) + .io_scoreboard_comb (_regfile_io_scoreboard_comb) ); UncachedFetch fetch ( .clock (clock), .reset (reset), .io_csr_value_0 (io_csr_in_value_0), + .io_debug_pc_valid (_csr_io_dm_debug_pc_valid), + .io_debug_pc_bits (_csr_io_dm_debug_pc_bits), .io_ibus_valid (_fetch_io_ibus_valid), - .io_ibus_ready (~_lsu_io_ibus_valid), + .io_ibus_ready (~_lsu_io_ibus_valid & io_ibus_ready), .io_ibus_addr (_fetch_io_ibus_addr), .io_ibus_rdata (io_ibus_rdata), + .io_ibus_fault_valid (~_lsu_io_ibus_valid & io_ibus_fault_valid), .io_inst_lanes_0_ready (_dispatch_io_inst_0_ready), .io_inst_lanes_0_valid (_fetch_io_inst_lanes_0_valid), .io_inst_lanes_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), @@ -13131,254 +19241,484 @@ module SCore( .io_branch_2_value (_bru_2_io_taken_value), .io_branch_3_valid (_bru_3_io_taken_valid), .io_branch_3_value (_bru_3_io_taken_value), - .io_iflush_valid (_lsu_io_flush_valid & _lsu_io_flush_fencei), + .io_iflush_valid (_lsu_io_flush_valid), .io_iflush_pcNext (_lsu_io_flush_pcNext), - .io_pc (_fetch_io_pc) + .io_pc (_fetch_io_pc), + .io_fault_valid (_fetch_io_fault_valid), + .io_fault_bits (_fetch_io_fault_bits) ); Csr csr ( - .clock (clock), - .reset (reset), - .io_csr_in_value_12 (_fetch_io_pc), - .io_csr_out_value_0 (io_csr_out_value_0), - .io_csr_out_value_1 (io_csr_out_value_1), - .io_csr_out_value_2 (io_csr_out_value_2), - .io_csr_out_value_3 (io_csr_out_value_3), - .io_csr_out_value_4 (_csr_io_csr_out_value_4), - .io_csr_out_value_5 (io_csr_out_value_5), - .io_csr_out_value_6 (io_csr_out_value_6), - .io_csr_out_value_7 (io_csr_out_value_7), - .io_req_valid (_dispatch_io_csr_valid), - .io_req_bits_addr (_dispatch_io_csr_bits_addr), - .io_req_bits_index (_dispatch_io_csr_bits_index), - .io_req_bits_op (_dispatch_io_csr_bits_op), - .io_rs1_valid (_regfile_io_readData_0_valid), - .io_rs1_data (_regfile_io_readData_0_data), - .io_rd_valid (_csr_io_rd_valid), - .io_rd_bits_addr (_csr_io_rd_bits_addr), - .io_rd_bits_data (_csr_io_rd_bits_data), - .io_bru_in_mode_valid (_bru_0_io_csr_in_mode_valid), - .io_bru_in_mode_bits (_bru_0_io_csr_in_mode_bits), - .io_bru_in_mcause_valid (_bru_0_io_csr_in_mcause_valid), - .io_bru_in_mcause_bits (_bru_0_io_csr_in_mcause_bits), - .io_bru_in_mepc_valid (_bru_0_io_csr_in_mepc_valid), - .io_bru_in_mepc_bits (_bru_0_io_csr_in_mepc_bits), - .io_bru_in_mtval_valid (_bru_0_io_csr_in_mtval_valid), - .io_bru_in_mtval_bits (_bru_0_io_csr_in_mtval_bits), - .io_bru_in_halt (_bru_0_io_csr_in_halt), - .io_bru_in_fault (_bru_0_io_csr_in_fault), - .io_bru_in_wfi (_bru_0_io_csr_in_wfi), - .io_bru_out_mode (_csr_io_bru_out_mode), - .io_bru_out_mepc (_csr_io_bru_out_mepc), - .io_bru_out_mtvec (_csr_io_bru_out_mtvec), - .io_float_in_fflags_valid (_floatCore_io_csr_in_fflags_valid), - .io_float_in_fflags_bits (_floatCore_io_csr_in_fflags_bits), - .io_float_out_frm (_csr_io_float_out_frm), - .io_counters_rfwriteCount (_regfile_io_rfwriteCount[2:0]), - .io_counters_storeCount (_lsu_io_storeCount), - .io_counters_branchCount (_bru_0_io_taken_valid), - .io_halted (_csr_io_halted), - .io_fault (io_fault), - .io_wfi (_csr_io_wfi), - .io_irq (io_irq) + .clock (clock), + .reset (reset), + .io_csr_in_value_12 (_fetch_io_pc), + .io_csr_out_value_0 (io_csr_out_value_0), + .io_csr_out_value_1 (io_csr_out_value_1), + .io_csr_out_value_2 (io_csr_out_value_2), + .io_csr_out_value_3 (io_csr_out_value_3), + .io_csr_out_value_4 (io_csr_out_value_4), + .io_csr_out_value_5 (io_csr_out_value_5), + .io_csr_out_value_6 (io_csr_out_value_6), + .io_csr_out_value_7 (io_csr_out_value_7), + .io_csr_out_value_8 (io_csr_out_value_8), + .io_req_valid (_csrReqArbiter_io_out_valid), + .io_req_bits_addr (_csrReqArbiter_io_out_bits_addr), + .io_req_bits_index (_csrReqArbiter_io_out_bits_index), + .io_req_bits_rs1 (_csrReqArbiter_io_out_bits_rs1), + .io_req_bits_op (_csrReqArbiter_io_out_bits_op), + .io_rs1_data + (csr_io_rs1_REG ? _regfile_io_readData_0_data : io_dm_csr_rs1), + .io_rd_valid (_csr_io_rd_valid), + .io_rd_bits_addr (_csr_io_rd_bits_addr), + .io_rd_bits_data (_csr_io_rd_bits_data), + .io_bru_in_mode_valid (_bru_0_io_csr_in_mode_valid), + .io_bru_in_mcause_valid (_bru_0_io_csr_in_mcause_valid), + .io_bru_in_mcause_bits (_bru_0_io_csr_in_mcause_bits), + .io_bru_in_mepc_valid (_bru_0_io_csr_in_mepc_valid), + .io_bru_in_mepc_bits (_bru_0_io_csr_in_mepc_bits), + .io_bru_in_mtval_valid (_bru_0_io_csr_in_mtval_valid), + .io_bru_in_mtval_bits (_bru_0_io_csr_in_mtval_bits), + .io_bru_in_halt (_bru_0_io_csr_in_halt), + .io_bru_in_fault (_bru_0_io_csr_in_fault), + .io_bru_in_wfi (_bru_0_io_csr_in_wfi), + .io_bru_out_mepc (_csr_io_bru_out_mepc), + .io_bru_out_mtvec (_csr_io_bru_out_mtvec), + .io_bru_out_interrupt (_csr_io_bru_out_interrupt), + .io_bru_out_interrupt_cause (_csr_io_bru_out_interrupt_cause), + .io_float_in_fflags_valid (_floatCore_io_csr_in_fflags_valid), + .io_float_in_fflags_bits (_floatCore_io_csr_in_fflags_bits), + .io_float_out_frm (_csr_io_float_out_frm), + .io_float_dirty + (fRegfile_io_write_ports_0_valid | _floatCore_io_write_ports_1_valid), + .io_counters_nRetired (_retirement_buffer_io_nRetired), + .io_halted (_csr_io_halted), + .io_fault (io_fault), + .io_wfi (_csr_io_wfi), + .io_irq (io_irq), + .io_dm_debug_req (io_dm_debug_req | stepTriggeredReg), + .io_dm_resume_req (io_dm_resume_req), + .io_dm_debug_mode (_csr_io_dm_debug_mode), + .io_dm_entering_debug_mode (_csr_io_dm_entering_debug_mode), + .io_dm_single_step (_csr_io_dm_single_step), + .io_dm_dcsr_step (_csr_io_dm_dcsr_step), + .io_dm_current_pc (_fetch_io_inst_lanes_0_bits_addr), + .io_dm_next_pc + (_bru_0_io_actually_taken + ? _bru_0_io_real_target + : _fetch_io_inst_lanes_0_bits_addr), + .io_dm_debug_pc_valid (_csr_io_dm_debug_pc_valid), + .io_dm_debug_pc_bits (_csr_io_dm_debug_pc_bits), + .io_timer_irq (io_timer_irq), + .io_software_irq (io_software_irq) ); - DispatchV1 dispatch ( - .io_halted (_csr_io_halted | _csr_io_wfi), - .io_lsuActive (_lsu_io_active), - .io_scoreboard_regd (_regfile_io_scoreboard_regd), - .io_scoreboard_comb (_regfile_io_scoreboard_comb), - .io_fscoreboard (_fRegfile_io_scoreboard), - .io_branchTaken (branchTaken), - .io_csrFault_0 (_dispatch_io_csrFault_0), - .io_jalFault_0 (_dispatch_io_jalFault_0), - .io_jalFault_1 (_dispatch_io_jalFault_1), - .io_jalFault_2 (_dispatch_io_jalFault_2), - .io_jalFault_3 (_dispatch_io_jalFault_3), - .io_jalrFault_0 (_dispatch_io_jalrFault_0), - .io_jalrFault_1 (_dispatch_io_jalrFault_1), - .io_jalrFault_2 (_dispatch_io_jalrFault_2), - .io_jalrFault_3 (_dispatch_io_jalrFault_3), - .io_bxxFault_0 (_dispatch_io_bxxFault_0), - .io_bxxFault_1 (_dispatch_io_bxxFault_1), - .io_bxxFault_2 (_dispatch_io_bxxFault_2), - .io_bxxFault_3 (_dispatch_io_bxxFault_3), - .io_undefFault_0 (_dispatch_io_undefFault_0), - .io_bruTarget_0 (_dispatch_io_bruTarget_0), - .io_bruTarget_1 (_dispatch_io_bruTarget_1), - .io_bruTarget_2 (_dispatch_io_bruTarget_2), - .io_bruTarget_3 (_dispatch_io_bruTarget_3), - .io_jalrTarget_0_data (_regfile_io_target_0_data), - .io_jalrTarget_1_data (_regfile_io_target_1_data), - .io_jalrTarget_2_data (_regfile_io_target_2_data), - .io_jalrTarget_3_data (_regfile_io_target_3_data), - .io_interlock (_bru_0_io_interlock | _lsu_io_flush_valid), - .io_inst_0_ready (_dispatch_io_inst_0_ready), - .io_inst_0_valid (_fetch_io_inst_lanes_0_valid), - .io_inst_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), - .io_inst_0_bits_inst (_fetch_io_inst_lanes_0_bits_inst), - .io_inst_0_bits_brchFwd (_fetch_io_inst_lanes_0_bits_brchFwd), - .io_inst_1_ready (_dispatch_io_inst_1_ready), - .io_inst_1_valid (_fetch_io_inst_lanes_1_valid), - .io_inst_1_bits_addr (_fetch_io_inst_lanes_1_bits_addr), - .io_inst_1_bits_inst (_fetch_io_inst_lanes_1_bits_inst), - .io_inst_1_bits_brchFwd (_fetch_io_inst_lanes_1_bits_brchFwd), - .io_inst_2_ready (_dispatch_io_inst_2_ready), - .io_inst_2_valid (_fetch_io_inst_lanes_2_valid), - .io_inst_2_bits_addr (_fetch_io_inst_lanes_2_bits_addr), - .io_inst_2_bits_inst (_fetch_io_inst_lanes_2_bits_inst), - .io_inst_2_bits_brchFwd (_fetch_io_inst_lanes_2_bits_brchFwd), - .io_inst_3_ready (_dispatch_io_inst_3_ready), - .io_inst_3_valid (_fetch_io_inst_lanes_3_valid), - .io_inst_3_bits_addr (_fetch_io_inst_lanes_3_bits_addr), - .io_inst_3_bits_inst (_fetch_io_inst_lanes_3_bits_inst), - .io_inst_3_bits_brchFwd (_fetch_io_inst_lanes_3_bits_brchFwd), - .io_rs1Read_0_valid (_dispatch_io_rs1Read_0_valid), - .io_rs1Read_0_addr (_dispatch_io_rs1Read_0_addr), - .io_rs1Read_1_valid (_dispatch_io_rs1Read_1_valid), - .io_rs1Read_1_addr (_dispatch_io_rs1Read_1_addr), - .io_rs1Read_2_valid (_dispatch_io_rs1Read_2_valid), - .io_rs1Read_2_addr (_dispatch_io_rs1Read_2_addr), - .io_rs1Read_3_valid (_dispatch_io_rs1Read_3_valid), - .io_rs1Read_3_addr (_dispatch_io_rs1Read_3_addr), - .io_rs1Set_0_valid (_dispatch_io_rs1Set_0_valid), - .io_rs1Set_0_value (_dispatch_io_rs1Set_0_value), - .io_rs1Set_1_valid (_dispatch_io_rs1Set_1_valid), - .io_rs1Set_1_value (_dispatch_io_rs1Set_1_value), - .io_rs1Set_2_valid (_dispatch_io_rs1Set_2_valid), - .io_rs1Set_2_value (_dispatch_io_rs1Set_2_value), - .io_rs1Set_3_valid (_dispatch_io_rs1Set_3_valid), - .io_rs1Set_3_value (_dispatch_io_rs1Set_3_value), - .io_rs2Read_0_valid (_dispatch_io_rs2Read_0_valid), - .io_rs2Read_0_addr (_dispatch_io_rs2Read_0_addr), - .io_rs2Read_1_valid (_dispatch_io_rs2Read_1_valid), - .io_rs2Read_1_addr (_dispatch_io_rs2Read_1_addr), - .io_rs2Read_2_valid (_dispatch_io_rs2Read_2_valid), - .io_rs2Read_2_addr (_dispatch_io_rs2Read_2_addr), - .io_rs2Read_3_valid (_dispatch_io_rs2Read_3_valid), - .io_rs2Read_3_addr (_dispatch_io_rs2Read_3_addr), - .io_rs2Set_0_valid (_dispatch_io_rs2Set_0_valid), - .io_rs2Set_0_value (_dispatch_io_rs2Set_0_value), - .io_rs2Set_1_valid (_dispatch_io_rs2Set_1_valid), - .io_rs2Set_1_value (_dispatch_io_rs2Set_1_value), - .io_rs2Set_2_valid (_dispatch_io_rs2Set_2_valid), - .io_rs2Set_2_value (_dispatch_io_rs2Set_2_value), - .io_rs2Set_3_valid (_dispatch_io_rs2Set_3_valid), - .io_rs2Set_3_value (_dispatch_io_rs2Set_3_value), - .io_rdMark_0_valid (_dispatch_io_rdMark_0_valid), - .io_rdMark_0_addr (_dispatch_io_rdMark_0_addr), - .io_rdMark_1_valid (_dispatch_io_rdMark_1_valid), - .io_rdMark_1_addr (_dispatch_io_rdMark_1_addr), - .io_rdMark_2_valid (_dispatch_io_rdMark_2_valid), - .io_rdMark_2_addr (_dispatch_io_rdMark_2_addr), - .io_rdMark_3_valid (_dispatch_io_rdMark_3_valid), - .io_rdMark_3_addr (_dispatch_io_rdMark_3_addr), - .io_busRead_0_bypass (_dispatch_io_busRead_0_bypass), - .io_busRead_0_immen (_dispatch_io_busRead_0_immen), - .io_busRead_0_immed (_dispatch_io_busRead_0_immed), - .io_busRead_1_bypass (_dispatch_io_busRead_1_bypass), - .io_busRead_1_immed (_dispatch_io_busRead_1_immed), - .io_busRead_2_bypass (_dispatch_io_busRead_2_bypass), - .io_busRead_2_immed (_dispatch_io_busRead_2_immed), - .io_busRead_3_bypass (_dispatch_io_busRead_3_bypass), - .io_busRead_3_immed (_dispatch_io_busRead_3_immed), - .io_rdMark_flt_valid (_dispatch_io_rdMark_flt_valid), - .io_rdMark_flt_addr (_dispatch_io_rdMark_flt_addr), - .io_alu_0_valid (_dispatch_io_alu_0_valid), - .io_alu_0_bits_addr (_dispatch_io_alu_0_bits_addr), - .io_alu_0_bits_op (_dispatch_io_alu_0_bits_op), - .io_alu_1_valid (_dispatch_io_alu_1_valid), - .io_alu_1_bits_addr (_dispatch_io_alu_1_bits_addr), - .io_alu_1_bits_op (_dispatch_io_alu_1_bits_op), - .io_alu_2_valid (_dispatch_io_alu_2_valid), - .io_alu_2_bits_addr (_dispatch_io_alu_2_bits_addr), - .io_alu_2_bits_op (_dispatch_io_alu_2_bits_op), - .io_alu_3_valid (_dispatch_io_alu_3_valid), - .io_alu_3_bits_addr (_dispatch_io_alu_3_bits_addr), - .io_alu_3_bits_op (_dispatch_io_alu_3_bits_op), - .io_bru_0_valid (_dispatch_io_bru_0_valid), - .io_bru_0_bits_fwd (_dispatch_io_bru_0_bits_fwd), - .io_bru_0_bits_op (_dispatch_io_bru_0_bits_op), - .io_bru_0_bits_pc (_dispatch_io_bru_0_bits_pc), - .io_bru_0_bits_target (_dispatch_io_bru_0_bits_target), - .io_bru_0_bits_link (_dispatch_io_bru_0_bits_link), - .io_bru_1_valid (_dispatch_io_bru_1_valid), - .io_bru_1_bits_fwd (_dispatch_io_bru_1_bits_fwd), - .io_bru_1_bits_op (_dispatch_io_bru_1_bits_op), - .io_bru_1_bits_pc (_dispatch_io_bru_1_bits_pc), - .io_bru_1_bits_target (_dispatch_io_bru_1_bits_target), - .io_bru_1_bits_link (_dispatch_io_bru_1_bits_link), - .io_bru_2_valid (_dispatch_io_bru_2_valid), - .io_bru_2_bits_fwd (_dispatch_io_bru_2_bits_fwd), - .io_bru_2_bits_op (_dispatch_io_bru_2_bits_op), - .io_bru_2_bits_pc (_dispatch_io_bru_2_bits_pc), - .io_bru_2_bits_target (_dispatch_io_bru_2_bits_target), - .io_bru_2_bits_link (_dispatch_io_bru_2_bits_link), - .io_bru_3_valid (_dispatch_io_bru_3_valid), - .io_bru_3_bits_fwd (_dispatch_io_bru_3_bits_fwd), - .io_bru_3_bits_op (_dispatch_io_bru_3_bits_op), - .io_bru_3_bits_pc (_dispatch_io_bru_3_bits_pc), - .io_bru_3_bits_target (_dispatch_io_bru_3_bits_target), - .io_bru_3_bits_link (_dispatch_io_bru_3_bits_link), - .io_csr_valid (_dispatch_io_csr_valid), - .io_csr_bits_addr (_dispatch_io_csr_bits_addr), - .io_csr_bits_index (_dispatch_io_csr_bits_index), - .io_csr_bits_op (_dispatch_io_csr_bits_op), - .io_lsu_0_ready (_lsu_io_req_0_ready), - .io_lsu_0_valid (_dispatch_io_lsu_0_valid), - .io_lsu_0_bits_store (_dispatch_io_lsu_0_bits_store), - .io_lsu_0_bits_addr (_dispatch_io_lsu_0_bits_addr), - .io_lsu_0_bits_op (_dispatch_io_lsu_0_bits_op), - .io_lsu_0_bits_pc (_dispatch_io_lsu_0_bits_pc), - .io_lsu_1_ready (_lsu_io_req_1_ready), - .io_lsu_1_valid (_dispatch_io_lsu_1_valid), - .io_lsu_1_bits_store (_dispatch_io_lsu_1_bits_store), - .io_lsu_1_bits_addr (_dispatch_io_lsu_1_bits_addr), - .io_lsu_1_bits_op (_dispatch_io_lsu_1_bits_op), - .io_lsu_1_bits_pc (_dispatch_io_lsu_1_bits_pc), - .io_lsu_2_ready (_lsu_io_req_2_ready), - .io_lsu_2_valid (_dispatch_io_lsu_2_valid), - .io_lsu_2_bits_store (_dispatch_io_lsu_2_bits_store), - .io_lsu_2_bits_addr (_dispatch_io_lsu_2_bits_addr), - .io_lsu_2_bits_op (_dispatch_io_lsu_2_bits_op), - .io_lsu_2_bits_pc (_dispatch_io_lsu_2_bits_pc), - .io_lsu_3_ready (_lsu_io_req_3_ready), - .io_lsu_3_valid (_dispatch_io_lsu_3_valid), - .io_lsu_3_bits_store (_dispatch_io_lsu_3_bits_store), - .io_lsu_3_bits_addr (_dispatch_io_lsu_3_bits_addr), - .io_lsu_3_bits_op (_dispatch_io_lsu_3_bits_op), - .io_lsu_3_bits_pc (_dispatch_io_lsu_3_bits_pc), - .io_mlu_0_valid (_dispatch_io_mlu_0_valid), - .io_mlu_0_bits_addr (_dispatch_io_mlu_0_bits_addr), - .io_mlu_0_bits_op (_dispatch_io_mlu_0_bits_op), - .io_mlu_1_valid (_dispatch_io_mlu_1_valid), - .io_mlu_1_bits_addr (_dispatch_io_mlu_1_bits_addr), - .io_mlu_1_bits_op (_dispatch_io_mlu_1_bits_op), - .io_mlu_2_valid (_dispatch_io_mlu_2_valid), - .io_mlu_2_bits_addr (_dispatch_io_mlu_2_bits_addr), - .io_mlu_2_bits_op (_dispatch_io_mlu_2_bits_op), - .io_mlu_3_valid (_dispatch_io_mlu_3_valid), - .io_mlu_3_bits_addr (_dispatch_io_mlu_3_bits_addr), - .io_mlu_3_bits_op (_dispatch_io_mlu_3_bits_op), - .io_dvu_0_ready (_dvu_io_req_ready), - .io_dvu_0_valid (_dispatch_io_dvu_0_valid), - .io_dvu_0_bits_addr (_dispatch_io_dvu_0_bits_addr), - .io_dvu_0_bits_op (_dispatch_io_dvu_0_bits_op), - .io_float_ready (_floatCore_io_inst_ready), - .io_float_valid (_dispatch_io_float_valid), - .io_float_bits_opcode (_dispatch_io_float_bits_opcode), - .io_float_bits_funct5 (_dispatch_io_float_bits_funct5), - .io_float_bits_rs3 (_dispatch_io_float_bits_rs3), - .io_float_bits_rs2 (_dispatch_io_float_bits_rs2), - .io_float_bits_rs1 (_dispatch_io_float_bits_rs1), - .io_float_bits_rm (_dispatch_io_float_bits_rm), - .io_float_bits_inst (_dispatch_io_float_bits_inst), - .io_float_bits_pc (_dispatch_io_float_bits_pc), - .io_float_bits_scalar_rd (_dispatch_io_float_bits_scalar_rd), - .io_float_bits_scalar_rs1 (_dispatch_io_float_bits_scalar_rs1), - .io_float_bits_rd (_dispatch_io_float_bits_rd), - .io_float_bits_uses_rs3 (_dispatch_io_float_bits_uses_rs3), - .io_float_bits_uses_rs2 (_dispatch_io_float_bits_uses_rs2), - .io_fbusPortAddr (_dispatch_io_fbusPortAddr), - .io_slog (_dispatch_io_slog) + DispatchV2 dispatch ( + .io_halted + (_csr_io_halted | _csr_io_wfi | _csr_io_dm_debug_mode + | _csr_io_dm_entering_debug_mode), + .io_lsuActive (_lsu_io_active), + .io_scoreboard_regd (_regfile_io_scoreboard_regd), + .io_scoreboard_comb (_regfile_io_scoreboard_comb), + .io_fscoreboard (_fRegfile_io_scoreboard), + .io_branchTaken (branchTaken), + .io_csrFault_0 (_dispatch_io_csrFault_0), + .io_jalFault_0 (_dispatch_io_jalFault_0), + .io_jalFault_1 (_dispatch_io_jalFault_1), + .io_jalFault_2 (_dispatch_io_jalFault_2), + .io_jalFault_3 (_dispatch_io_jalFault_3), + .io_jalrFault_0 (_dispatch_io_jalrFault_0), + .io_jalrFault_1 (_dispatch_io_jalrFault_1), + .io_jalrFault_2 (_dispatch_io_jalrFault_2), + .io_jalrFault_3 (_dispatch_io_jalrFault_3), + .io_bxxFault_0 (_dispatch_io_bxxFault_0), + .io_bxxFault_1 (_dispatch_io_bxxFault_1), + .io_bxxFault_2 (_dispatch_io_bxxFault_2), + .io_bxxFault_3 (_dispatch_io_bxxFault_3), + .io_undefFault_0 (_dispatch_io_undefFault_0), + .io_bruTarget_0 (_dispatch_io_bruTarget_0), + .io_bruTarget_1 (_dispatch_io_bruTarget_1), + .io_bruTarget_2 (_dispatch_io_bruTarget_2), + .io_bruTarget_3 (_dispatch_io_bruTarget_3), + .io_jalrTarget_0_data (_regfile_io_target_0_data), + .io_jalrTarget_1_data (_regfile_io_target_1_data), + .io_jalrTarget_2_data (_regfile_io_target_2_data), + .io_jalrTarget_3_data (_regfile_io_target_3_data), + .io_interlock (_bru_0_io_interlock | _lsu_io_flush_valid), + .io_inst_0_ready (_dispatch_io_inst_0_ready), + .io_inst_0_valid (_fetch_io_inst_lanes_0_valid), + .io_inst_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), + .io_inst_0_bits_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_inst_0_bits_brchFwd (_fetch_io_inst_lanes_0_bits_brchFwd), + .io_inst_1_ready (_dispatch_io_inst_1_ready), + .io_inst_1_valid (_fetch_io_inst_lanes_1_valid), + .io_inst_1_bits_addr (_fetch_io_inst_lanes_1_bits_addr), + .io_inst_1_bits_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_inst_1_bits_brchFwd (_fetch_io_inst_lanes_1_bits_brchFwd), + .io_inst_2_ready (_dispatch_io_inst_2_ready), + .io_inst_2_valid (_fetch_io_inst_lanes_2_valid), + .io_inst_2_bits_addr (_fetch_io_inst_lanes_2_bits_addr), + .io_inst_2_bits_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_inst_2_bits_brchFwd (_fetch_io_inst_lanes_2_bits_brchFwd), + .io_inst_3_ready (_dispatch_io_inst_3_ready), + .io_inst_3_valid (_fetch_io_inst_lanes_3_valid), + .io_inst_3_bits_addr (_fetch_io_inst_lanes_3_bits_addr), + .io_inst_3_bits_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_inst_3_bits_brchFwd (_fetch_io_inst_lanes_3_bits_brchFwd), + .io_rs1Read_0_valid (_dispatch_io_rs1Read_0_valid), + .io_rs1Read_0_addr (_dispatch_io_rs1Read_0_addr), + .io_rs1Read_1_valid (_dispatch_io_rs1Read_1_valid), + .io_rs1Read_1_addr (_dispatch_io_rs1Read_1_addr), + .io_rs1Read_2_valid (_dispatch_io_rs1Read_2_valid), + .io_rs1Read_2_addr (_dispatch_io_rs1Read_2_addr), + .io_rs1Read_3_valid (_dispatch_io_rs1Read_3_valid), + .io_rs1Read_3_addr (_dispatch_io_rs1Read_3_addr), + .io_rs1Set_0_valid (_dispatch_io_rs1Set_0_valid), + .io_rs1Set_0_value (_dispatch_io_rs1Set_0_value), + .io_rs1Set_1_valid (_dispatch_io_rs1Set_1_valid), + .io_rs1Set_1_value (_dispatch_io_rs1Set_1_value), + .io_rs1Set_2_valid (_dispatch_io_rs1Set_2_valid), + .io_rs1Set_2_value (_dispatch_io_rs1Set_2_value), + .io_rs1Set_3_valid (_dispatch_io_rs1Set_3_valid), + .io_rs1Set_3_value (_dispatch_io_rs1Set_3_value), + .io_rs2Read_0_valid (_dispatch_io_rs2Read_0_valid), + .io_rs2Read_0_addr (_dispatch_io_rs2Read_0_addr), + .io_rs2Read_1_valid (_dispatch_io_rs2Read_1_valid), + .io_rs2Read_1_addr (_dispatch_io_rs2Read_1_addr), + .io_rs2Read_2_valid (_dispatch_io_rs2Read_2_valid), + .io_rs2Read_2_addr (_dispatch_io_rs2Read_2_addr), + .io_rs2Read_3_valid (_dispatch_io_rs2Read_3_valid), + .io_rs2Read_3_addr (_dispatch_io_rs2Read_3_addr), + .io_rs2Set_0_valid (_dispatch_io_rs2Set_0_valid), + .io_rs2Set_0_value (_dispatch_io_rs2Set_0_value), + .io_rs2Set_1_valid (_dispatch_io_rs2Set_1_valid), + .io_rs2Set_1_value (_dispatch_io_rs2Set_1_value), + .io_rs2Set_2_valid (_dispatch_io_rs2Set_2_valid), + .io_rs2Set_2_value (_dispatch_io_rs2Set_2_value), + .io_rs2Set_3_valid (_dispatch_io_rs2Set_3_valid), + .io_rs2Set_3_value (_dispatch_io_rs2Set_3_value), + .io_rdMark_0_valid (_dispatch_io_rdMark_0_valid), + .io_rdMark_0_addr (_dispatch_io_rdMark_0_addr), + .io_rdMark_1_valid (_dispatch_io_rdMark_1_valid), + .io_rdMark_1_addr (_dispatch_io_rdMark_1_addr), + .io_rdMark_2_valid (_dispatch_io_rdMark_2_valid), + .io_rdMark_2_addr (_dispatch_io_rdMark_2_addr), + .io_rdMark_3_valid (_dispatch_io_rdMark_3_valid), + .io_rdMark_3_addr (_dispatch_io_rdMark_3_addr), + .io_busRead_0_immed (_dispatch_io_busRead_0_immed), + .io_busRead_1_immed (_dispatch_io_busRead_1_immed), + .io_busRead_2_immed (_dispatch_io_busRead_2_immed), + .io_busRead_3_immed (_dispatch_io_busRead_3_immed), + .io_rdMark_flt_valid (_dispatch_io_rdMark_flt_valid), + .io_rdMark_flt_addr (_dispatch_io_rdMark_flt_addr), + .io_alu_0_valid (_dispatch_io_alu_0_valid), + .io_alu_0_bits_addr (_dispatch_io_alu_0_bits_addr), + .io_alu_0_bits_op (_dispatch_io_alu_0_bits_op), + .io_alu_1_valid (_dispatch_io_alu_1_valid), + .io_alu_1_bits_addr (_dispatch_io_alu_1_bits_addr), + .io_alu_1_bits_op (_dispatch_io_alu_1_bits_op), + .io_alu_2_valid (_dispatch_io_alu_2_valid), + .io_alu_2_bits_addr (_dispatch_io_alu_2_bits_addr), + .io_alu_2_bits_op (_dispatch_io_alu_2_bits_op), + .io_alu_3_valid (_dispatch_io_alu_3_valid), + .io_alu_3_bits_addr (_dispatch_io_alu_3_bits_addr), + .io_alu_3_bits_op (_dispatch_io_alu_3_bits_op), + .io_bru_0_valid (_dispatch_io_bru_0_valid), + .io_bru_0_bits_fwd (_dispatch_io_bru_0_bits_fwd), + .io_bru_0_bits_op (_dispatch_io_bru_0_bits_op), + .io_bru_0_bits_pc (_dispatch_io_bru_0_bits_pc), + .io_bru_0_bits_target (_dispatch_io_bru_0_bits_target), + .io_bru_0_bits_link (_dispatch_io_bru_0_bits_link), + .io_bru_1_valid (_dispatch_io_bru_1_valid), + .io_bru_1_bits_fwd (_dispatch_io_bru_1_bits_fwd), + .io_bru_1_bits_op (_dispatch_io_bru_1_bits_op), + .io_bru_1_bits_pc (_dispatch_io_bru_1_bits_pc), + .io_bru_1_bits_target (_dispatch_io_bru_1_bits_target), + .io_bru_1_bits_link (_dispatch_io_bru_1_bits_link), + .io_bru_2_valid (_dispatch_io_bru_2_valid), + .io_bru_2_bits_fwd (_dispatch_io_bru_2_bits_fwd), + .io_bru_2_bits_op (_dispatch_io_bru_2_bits_op), + .io_bru_2_bits_pc (_dispatch_io_bru_2_bits_pc), + .io_bru_2_bits_target (_dispatch_io_bru_2_bits_target), + .io_bru_2_bits_link (_dispatch_io_bru_2_bits_link), + .io_bru_3_valid (_dispatch_io_bru_3_valid), + .io_bru_3_bits_fwd (_dispatch_io_bru_3_bits_fwd), + .io_bru_3_bits_op (_dispatch_io_bru_3_bits_op), + .io_bru_3_bits_pc (_dispatch_io_bru_3_bits_pc), + .io_bru_3_bits_target (_dispatch_io_bru_3_bits_target), + .io_bru_3_bits_link (_dispatch_io_bru_3_bits_link), + .io_csr_valid (_dispatch_io_csr_valid), + .io_csr_bits_addr (_dispatch_io_csr_bits_addr), + .io_csr_bits_index (_dispatch_io_csr_bits_index), + .io_csr_bits_rs1 (_dispatch_io_csr_bits_rs1), + .io_csr_bits_op (_dispatch_io_csr_bits_op), + .io_lsu_0_ready (_lsu_io_req_0_ready), + .io_lsu_0_valid (_dispatch_io_lsu_0_valid), + .io_lsu_0_bits_store (_dispatch_io_lsu_0_bits_store), + .io_lsu_0_bits_addr (_dispatch_io_lsu_0_bits_addr), + .io_lsu_0_bits_op (_dispatch_io_lsu_0_bits_op), + .io_lsu_0_bits_pc (_dispatch_io_lsu_0_bits_pc), + .io_lsu_1_ready (_lsu_io_req_1_ready), + .io_lsu_1_valid (_dispatch_io_lsu_1_valid), + .io_lsu_1_bits_store (_dispatch_io_lsu_1_bits_store), + .io_lsu_1_bits_addr (_dispatch_io_lsu_1_bits_addr), + .io_lsu_1_bits_op (_dispatch_io_lsu_1_bits_op), + .io_lsu_1_bits_pc (_dispatch_io_lsu_1_bits_pc), + .io_lsu_2_ready (_lsu_io_req_2_ready), + .io_lsu_2_valid (_dispatch_io_lsu_2_valid), + .io_lsu_2_bits_store (_dispatch_io_lsu_2_bits_store), + .io_lsu_2_bits_addr (_dispatch_io_lsu_2_bits_addr), + .io_lsu_2_bits_op (_dispatch_io_lsu_2_bits_op), + .io_lsu_2_bits_pc (_dispatch_io_lsu_2_bits_pc), + .io_lsu_3_ready (_lsu_io_req_3_ready), + .io_lsu_3_valid (_dispatch_io_lsu_3_valid), + .io_lsu_3_bits_store (_dispatch_io_lsu_3_bits_store), + .io_lsu_3_bits_addr (_dispatch_io_lsu_3_bits_addr), + .io_lsu_3_bits_op (_dispatch_io_lsu_3_bits_op), + .io_lsu_3_bits_pc (_dispatch_io_lsu_3_bits_pc), + .io_lsuQueueCapacity (_lsu_io_queueCapacity), + .io_mlu_0_valid (_dispatch_io_mlu_0_valid), + .io_mlu_0_bits_addr (_dispatch_io_mlu_0_bits_addr), + .io_mlu_0_bits_op (_dispatch_io_mlu_0_bits_op), + .io_mlu_1_ready (_mlu_io_req_1_ready), + .io_mlu_1_valid (_dispatch_io_mlu_1_valid), + .io_mlu_1_bits_addr (_dispatch_io_mlu_1_bits_addr), + .io_mlu_1_bits_op (_dispatch_io_mlu_1_bits_op), + .io_mlu_2_ready (_mlu_io_req_2_ready), + .io_mlu_2_valid (_dispatch_io_mlu_2_valid), + .io_mlu_2_bits_addr (_dispatch_io_mlu_2_bits_addr), + .io_mlu_2_bits_op (_dispatch_io_mlu_2_bits_op), + .io_mlu_3_ready (_mlu_io_req_3_ready), + .io_mlu_3_valid (_dispatch_io_mlu_3_valid), + .io_mlu_3_bits_addr (_dispatch_io_mlu_3_bits_addr), + .io_mlu_3_bits_op (_dispatch_io_mlu_3_bits_op), + .io_dvu_0_ready (_dvu_io_req_ready), + .io_dvu_0_valid (_dispatch_io_dvu_0_valid), + .io_dvu_0_bits_addr (_dispatch_io_dvu_0_bits_addr), + .io_dvu_0_bits_op (_dispatch_io_dvu_0_bits_op), + .io_float_ready (_floatCore_io_inst_ready), + .io_float_valid (_dispatch_io_float_valid), + .io_float_bits_opcode (_dispatch_io_float_bits_opcode), + .io_float_bits_funct5 (_dispatch_io_float_bits_funct5), + .io_float_bits_src_fmt (_dispatch_io_float_bits_src_fmt), + .io_float_bits_dst_fmt (_dispatch_io_float_bits_dst_fmt), + .io_float_bits_rs3 (_dispatch_io_float_bits_rs3), + .io_float_bits_rs2 (_dispatch_io_float_bits_rs2), + .io_float_bits_rs1 (_dispatch_io_float_bits_rs1), + .io_float_bits_rm (_dispatch_io_float_bits_rm), + .io_float_bits_inst (_dispatch_io_float_bits_inst), + .io_float_bits_pc (_dispatch_io_float_bits_pc), + .io_float_bits_scalar_rd (_dispatch_io_float_bits_scalar_rd), + .io_float_bits_scalar_rs1 (_dispatch_io_float_bits_scalar_rs1), + .io_float_bits_float_rs1 (_dispatch_io_float_bits_float_rs1), + .io_float_bits_rd (_dispatch_io_float_bits_rd), + .io_float_bits_uses_rs3 (_dispatch_io_float_bits_uses_rs3), + .io_float_bits_uses_rs2 (_dispatch_io_float_bits_uses_rs2), + .io_csrFrm (_csr_io_float_out_frm), + .io_fbusPortAddr (_dispatch_io_fbusPortAddr), + .io_retirement_buffer_nSpace (_retirement_buffer_io_nSpace), + .io_retirement_buffer_empty (_retirement_buffer_io_empty), + .io_retirement_buffer_trap_pending (_retirement_buffer_io_trapPending), + .io_single_step (_csr_io_dm_single_step | _csr_io_dm_dcsr_step), + .io_branch_0 (_dispatch_io_branch_0), + .io_branch_1 (_dispatch_io_branch_1), + .io_branch_2 (_dispatch_io_branch_2), + .io_branch_3 (_dispatch_io_branch_3), + .io_jump_0 (_dispatch_io_jump_0), + .io_jump_1 (_dispatch_io_jump_1), + .io_jump_2 (_dispatch_io_jump_2), + .io_jump_3 (_dispatch_io_jump_3) + ); + LsuV3 lsu ( + .clock (clock), + .reset (reset), + .io_req_0_ready (_lsu_io_req_0_ready), + .io_req_0_valid (_dispatch_io_lsu_0_valid), + .io_req_0_bits_store (_dispatch_io_lsu_0_bits_store), + .io_req_0_bits_addr (_dispatch_io_lsu_0_bits_addr), + .io_req_0_bits_op (_dispatch_io_lsu_0_bits_op), + .io_req_0_bits_pc (_dispatch_io_lsu_0_bits_pc), + .io_req_1_ready (_lsu_io_req_1_ready), + .io_req_1_valid (_dispatch_io_lsu_1_valid), + .io_req_1_bits_store (_dispatch_io_lsu_1_bits_store), + .io_req_1_bits_addr (_dispatch_io_lsu_1_bits_addr), + .io_req_1_bits_op (_dispatch_io_lsu_1_bits_op), + .io_req_1_bits_pc (_dispatch_io_lsu_1_bits_pc), + .io_req_2_ready (_lsu_io_req_2_ready), + .io_req_2_valid (_dispatch_io_lsu_2_valid), + .io_req_2_bits_store (_dispatch_io_lsu_2_bits_store), + .io_req_2_bits_addr (_dispatch_io_lsu_2_bits_addr), + .io_req_2_bits_op (_dispatch_io_lsu_2_bits_op), + .io_req_2_bits_pc (_dispatch_io_lsu_2_bits_pc), + .io_req_3_ready (_lsu_io_req_3_ready), + .io_req_3_valid (_dispatch_io_lsu_3_valid), + .io_req_3_bits_store (_dispatch_io_lsu_3_bits_store), + .io_req_3_bits_addr (_dispatch_io_lsu_3_bits_addr), + .io_req_3_bits_op (_dispatch_io_lsu_3_bits_op), + .io_req_3_bits_pc (_dispatch_io_lsu_3_bits_pc), + .io_busPort_addr_0 (_regfile_io_busPort_addr_0), + .io_busPort_addr_1 (_regfile_io_busPort_addr_1), + .io_busPort_addr_2 (_regfile_io_busPort_addr_2), + .io_busPort_addr_3 (_regfile_io_busPort_addr_3), + .io_busPort_data_0 (_regfile_io_busPort_data_0), + .io_busPort_data_1 (_regfile_io_busPort_data_1), + .io_busPort_data_2 (_regfile_io_busPort_data_2), + .io_busPort_data_3 (_regfile_io_busPort_data_3), + .io_busPort_flt_data_0 (_fRegfile_io_busPort_data_0), + .io_rd_valid (_lsu_io_rd_valid), + .io_rd_bits_addr (_lsu_io_rd_bits_addr), + .io_rd_bits_data (_lsu_io_rd_bits_data), + .io_rd_flt_valid (_lsu_io_rd_flt_valid), + .io_rd_flt_bits_addr (_lsu_io_rd_flt_bits_addr), + .io_rd_flt_bits_data (_lsu_io_rd_flt_bits_data), + .io_ibus_valid (_lsu_io_ibus_valid), + .io_ibus_ready (_lsu_io_ibus_valid & io_ibus_ready), + .io_ibus_addr (_lsu_io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_dbus_valid (io_dbus_valid), + .io_dbus_write (io_dbus_write), + .io_dbus_addr (io_dbus_addr), + .io_dbus_wdata (io_dbus_wdata), + .io_dbus_wmask (io_dbus_wmask), + .io_dbus_rdata (io_dbus_rdata), + .io_flush_valid (_lsu_io_flush_valid), + .io_flush_pcNext (_lsu_io_flush_pcNext), + .io_flush_ready (_lsu_io_flush_valid), + .io_fault_valid (_lsu_io_fault_valid), + .io_fault_bits_write (_lsu_io_fault_bits_write), + .io_fault_bits_addr (_lsu_io_fault_bits_addr), + .io_fault_bits_epc (_lsu_io_fault_bits_epc), + .io_ebus_dbus_valid (io_ebus_dbus_valid), + .io_ebus_dbus_ready (io_ebus_dbus_ready), + .io_ebus_dbus_write (io_ebus_dbus_write), + .io_ebus_dbus_addr (io_ebus_dbus_addr), + .io_ebus_dbus_size (io_ebus_dbus_size), + .io_ebus_dbus_wdata (io_ebus_dbus_wdata), + .io_ebus_dbus_wmask (io_ebus_dbus_wmask), + .io_ebus_dbus_rdata (io_ebus_dbus_rdata), + .io_ebus_fault_valid (io_ebus_fault_valid), + .io_queueCapacity (_lsu_io_queueCapacity), + .io_active (_lsu_io_active), + .io_storeComplete_valid (_lsu_io_storeComplete_valid), + .io_storeComplete_bits (_lsu_io_storeComplete_bits), + .io_pipelineFlush (_retirement_buffer_io_trapRetired) + ); + FaultManager fault_manager ( + .io_in_fault_0_csr (_dispatch_io_csrFault_0), + .io_in_fault_0_jal (_dispatch_io_jalFault_0), + .io_in_fault_0_jalr (_dispatch_io_jalrFault_0), + .io_in_fault_0_bxx (_dispatch_io_bxxFault_0), + .io_in_fault_0_undef (_dispatch_io_undefFault_0), + .io_in_fault_1_jal (_dispatch_io_jalFault_1), + .io_in_fault_1_jalr (_dispatch_io_jalrFault_1), + .io_in_fault_1_bxx (_dispatch_io_bxxFault_1), + .io_in_fault_2_jal (_dispatch_io_jalFault_2), + .io_in_fault_2_jalr (_dispatch_io_jalrFault_2), + .io_in_fault_2_bxx (_dispatch_io_bxxFault_2), + .io_in_fault_3_jal (_dispatch_io_jalFault_3), + .io_in_fault_3_jalr (_dispatch_io_jalrFault_3), + .io_in_fault_3_bxx (_dispatch_io_bxxFault_3), + .io_in_pc_0_pc (_fetch_io_inst_lanes_0_bits_addr), + .io_in_pc_1_pc (_fetch_io_inst_lanes_1_bits_addr), + .io_in_pc_2_pc (_fetch_io_inst_lanes_2_bits_addr), + .io_in_pc_3_pc (_fetch_io_inst_lanes_3_bits_addr), + .io_in_memory_fault_valid (_lsu_io_fault_valid), + .io_in_memory_fault_bits_write (_lsu_io_fault_bits_write), + .io_in_memory_fault_bits_addr (_lsu_io_fault_bits_addr), + .io_in_memory_fault_bits_epc (_lsu_io_fault_bits_epc), + .io_in_undef_0_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_in_undef_1_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_in_undef_2_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_in_undef_3_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_in_jal_0_target (_dispatch_io_bruTarget_0), + .io_in_jal_1_target (_dispatch_io_bruTarget_1), + .io_in_jal_2_target (_dispatch_io_bruTarget_2), + .io_in_jal_3_target (_dispatch_io_bruTarget_3), + .io_in_jalr_0_target (_regfile_io_target_0_data), + .io_in_jalr_1_target (_regfile_io_target_1_data), + .io_in_jalr_2_target (_regfile_io_target_2_data), + .io_in_jalr_3_target (_regfile_io_target_3_data), + .io_in_fetchFault_valid + (_fetch_io_fault_valid & ~branchTaken & _regfile_io_scoreboard_regd == 32'h0 + & _fRegfile_io_scoreboard == 32'h0 & ~_lsu_io_active + & ~(_fetch_io_inst_lanes_0_valid | _fetch_io_inst_lanes_1_valid + | _fetch_io_inst_lanes_2_valid | _fetch_io_inst_lanes_3_valid)), + .io_in_fetchFault_bits (_fetch_io_fault_bits), + .io_out_valid (_fault_manager_io_out_valid), + .io_out_bits_mepc (_fault_manager_io_out_bits_mepc), + .io_out_bits_mtval (_fault_manager_io_out_bits_mtval), + .io_out_bits_mcause (_fault_manager_io_out_bits_mcause), + .io_out_bits_decode (_fault_manager_io_out_bits_decode) + ); + RetirementBuffer retirement_buffer ( + .clock (clock), + .reset (reset), + .io_inst_0_ready (_dispatch_io_inst_0_ready), + .io_inst_0_valid (_fetch_io_inst_lanes_0_valid), + .io_inst_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), + .io_inst_0_bits_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_inst_1_ready (_dispatch_io_inst_1_ready), + .io_inst_1_valid (_fetch_io_inst_lanes_1_valid), + .io_inst_1_bits_addr (_fetch_io_inst_lanes_1_bits_addr), + .io_inst_1_bits_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_inst_2_ready (_dispatch_io_inst_2_ready), + .io_inst_2_valid (_fetch_io_inst_lanes_2_valid), + .io_inst_2_bits_addr (_fetch_io_inst_lanes_2_bits_addr), + .io_inst_2_bits_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_inst_3_ready (_dispatch_io_inst_3_ready), + .io_inst_3_valid (_fetch_io_inst_lanes_3_valid), + .io_inst_3_bits_addr (_fetch_io_inst_lanes_3_bits_addr), + .io_inst_3_bits_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_targets_0 (_dispatch_io_bruTarget_0), + .io_targets_1 (_dispatch_io_bruTarget_1), + .io_targets_2 (_dispatch_io_bruTarget_2), + .io_targets_3 (_dispatch_io_bruTarget_3), + .io_jalrTargets_0 ({_regfile_io_target_0_data[31:1], 1'h0}), + .io_jalrTargets_1 ({_regfile_io_target_1_data[31:1], 1'h0}), + .io_jalrTargets_2 ({_regfile_io_target_2_data[31:1], 1'h0}), + .io_jalrTargets_3 ({_regfile_io_target_3_data[31:1], 1'h0}), + .io_jump_0 (_dispatch_io_jump_0), + .io_jump_1 (_dispatch_io_jump_1), + .io_jump_2 (_dispatch_io_jump_2), + .io_jump_3 (_dispatch_io_jump_3), + .io_branch_0 (_dispatch_io_branch_0), + .io_branch_1 (_dispatch_io_branch_1), + .io_branch_2 (_dispatch_io_branch_2), + .io_branch_3 (_dispatch_io_branch_3), + .io_storeComplete_valid (_lsu_io_storeComplete_valid), + .io_storeComplete_bits (_lsu_io_storeComplete_bits), + .io_writeAddrScalar_0_valid (_dispatch_io_rdMark_0_valid), + .io_writeAddrScalar_0_addr (_dispatch_io_rdMark_0_addr), + .io_writeAddrScalar_1_valid (_dispatch_io_rdMark_1_valid), + .io_writeAddrScalar_1_addr (_dispatch_io_rdMark_1_addr), + .io_writeAddrScalar_2_valid (_dispatch_io_rdMark_2_valid), + .io_writeAddrScalar_2_addr (_dispatch_io_rdMark_2_addr), + .io_writeAddrScalar_3_valid (_dispatch_io_rdMark_3_valid), + .io_writeAddrScalar_3_addr (_dispatch_io_rdMark_3_addr), + .io_writeDataScalar_0_valid (regfile_io_writeData_0_valid), + .io_writeDataScalar_0_bits_addr (regfile_io_writeData_0_bits_addr), + .io_writeDataScalar_1_valid (regfile_io_writeData_1_valid), + .io_writeDataScalar_1_bits_addr (regfile_io_writeData_1_bits_addr), + .io_writeDataScalar_2_valid (regfile_io_writeData_2_valid), + .io_writeDataScalar_2_bits_addr (regfile_io_writeData_2_bits_addr), + .io_writeDataScalar_3_valid (regfile_io_writeData_3_valid), + .io_writeDataScalar_3_bits_addr (regfile_io_writeData_3_bits_addr), + .io_writeDataScalar_4_valid (_arb_io_out_valid), + .io_writeDataScalar_4_bits_addr (_arb_io_out_bits_addr), + .io_writeDataScalar_5_valid (_lsu_io_rd_valid), + .io_writeDataScalar_5_bits_addr (_lsu_io_rd_bits_addr), + .io_writeAddrFloat_valid (_dispatch_io_rdMark_flt_valid), + .io_writeAddrFloat_addr (_dispatch_io_rdMark_flt_addr), + .io_writeDataFloat_0_valid (fRegfile_io_write_ports_0_valid), + .io_writeDataFloat_0_bits_addr (fRegfile_io_write_ports_0_addr), + .io_writeDataFloat_1_valid (_floatCore_io_write_ports_1_valid), + .io_writeDataFloat_1_bits_addr (_floatCore_io_write_ports_1_addr), + .io_fault_valid (_fault_manager_io_out_valid), + .io_fault_bits_mepc (_fault_manager_io_out_bits_mepc), + .io_fault_bits_mcause (_fault_manager_io_out_bits_mcause), + .io_fault_bits_decode (_fault_manager_io_out_bits_decode), + .io_nSpace (_retirement_buffer_io_nSpace), + .io_nRetired (_retirement_buffer_io_nRetired), + .io_empty (_retirement_buffer_io_empty), + .io_trapPending (_retirement_buffer_io_trapPending), + .io_trapRetired (_retirement_buffer_io_trapRetired) ); Alu alu_0 ( .clock (clock), @@ -13386,9 +19726,7 @@ module SCore( .io_req_valid (_dispatch_io_alu_0_valid), .io_req_bits_addr (_dispatch_io_alu_0_bits_addr), .io_req_bits_op (_dispatch_io_alu_0_bits_op), - .io_rs1_valid (_regfile_io_readData_0_valid), .io_rs1_data (_regfile_io_readData_0_data), - .io_rs2_valid (_regfile_io_readData_1_valid), .io_rs2_data (_regfile_io_readData_1_data), .io_rd_valid (_alu_0_io_rd_valid), .io_rd_bits_addr (_alu_0_io_rd_bits_addr), @@ -13400,9 +19738,7 @@ module SCore( .io_req_valid (_dispatch_io_alu_1_valid), .io_req_bits_addr (_dispatch_io_alu_1_bits_addr), .io_req_bits_op (_dispatch_io_alu_1_bits_op), - .io_rs1_valid (_regfile_io_readData_2_valid), .io_rs1_data (_regfile_io_readData_2_data), - .io_rs2_valid (_regfile_io_readData_3_valid), .io_rs2_data (_regfile_io_readData_3_data), .io_rd_valid (_alu_1_io_rd_valid), .io_rd_bits_addr (_alu_1_io_rd_bits_addr), @@ -13414,9 +19750,7 @@ module SCore( .io_req_valid (_dispatch_io_alu_2_valid), .io_req_bits_addr (_dispatch_io_alu_2_bits_addr), .io_req_bits_op (_dispatch_io_alu_2_bits_op), - .io_rs1_valid (_regfile_io_readData_4_valid), .io_rs1_data (_regfile_io_readData_4_data), - .io_rs2_valid (_regfile_io_readData_5_valid), .io_rs2_data (_regfile_io_readData_5_data), .io_rd_valid (_alu_2_io_rd_valid), .io_rd_bits_addr (_alu_2_io_rd_bits_addr), @@ -13428,9 +19762,7 @@ module SCore( .io_req_valid (_dispatch_io_alu_3_valid), .io_req_bits_addr (_dispatch_io_alu_3_bits_addr), .io_req_bits_op (_dispatch_io_alu_3_bits_op), - .io_rs1_valid (_regfile_io_readData_6_valid), .io_rs1_data (_regfile_io_readData_6_data), - .io_rs2_valid (_regfile_io_readData_7_valid), .io_rs2_data (_regfile_io_readData_7_data), .io_rd_valid (_alu_3_io_rd_valid), .io_rd_bits_addr (_alu_3_io_rd_bits_addr), @@ -13446,7 +19778,6 @@ module SCore( .io_req_bits_target (_dispatch_io_bru_0_bits_target), .io_req_bits_link (_dispatch_io_bru_0_bits_link), .io_csr_in_mode_valid (_bru_0_io_csr_in_mode_valid), - .io_csr_in_mode_bits (_bru_0_io_csr_in_mode_bits), .io_csr_in_mcause_valid (_bru_0_io_csr_in_mcause_valid), .io_csr_in_mcause_bits (_bru_0_io_csr_in_mcause_bits), .io_csr_in_mepc_valid (_bru_0_io_csr_in_mepc_valid), @@ -13456,18 +19787,19 @@ module SCore( .io_csr_in_halt (_bru_0_io_csr_in_halt), .io_csr_in_fault (_bru_0_io_csr_in_fault), .io_csr_in_wfi (_bru_0_io_csr_in_wfi), - .io_csr_out_mode (_csr_io_bru_out_mode), .io_csr_out_mepc (_csr_io_bru_out_mepc), .io_csr_out_mtvec (_csr_io_bru_out_mtvec), - .io_rs1_valid (_regfile_io_readData_0_valid), + .io_csr_out_interrupt (_csr_io_bru_out_interrupt), + .io_csr_out_interrupt_cause (_csr_io_bru_out_interrupt_cause), .io_rs1_data (_regfile_io_readData_0_data), - .io_rs2_valid (_regfile_io_readData_1_valid), .io_rs2_data (_regfile_io_readData_1_data), .io_rd_valid (_bru_0_io_rd_valid), .io_rd_bits_addr (_bru_0_io_rd_bits_addr), .io_rd_bits_data (_bru_0_io_rd_bits_data), .io_taken_valid (_bru_0_io_taken_valid), .io_taken_value (_bru_0_io_taken_value), + .io_actually_taken (_bru_0_io_actually_taken), + .io_real_target (_bru_0_io_real_target), .io_target_data (_regfile_io_target_0_data), .io_interlock (_bru_0_io_interlock), .io_fault_manager_valid (_fault_manager_io_out_valid), @@ -13484,9 +19816,7 @@ module SCore( .io_req_bits_pc (_dispatch_io_bru_1_bits_pc), .io_req_bits_target (_dispatch_io_bru_1_bits_target), .io_req_bits_link (_dispatch_io_bru_1_bits_link), - .io_rs1_valid (_regfile_io_readData_2_valid), .io_rs1_data (_regfile_io_readData_2_data), - .io_rs2_valid (_regfile_io_readData_3_valid), .io_rs2_data (_regfile_io_readData_3_data), .io_rd_valid (_bru_1_io_rd_valid), .io_rd_bits_addr (_bru_1_io_rd_bits_addr), @@ -13504,9 +19834,7 @@ module SCore( .io_req_bits_pc (_dispatch_io_bru_2_bits_pc), .io_req_bits_target (_dispatch_io_bru_2_bits_target), .io_req_bits_link (_dispatch_io_bru_2_bits_link), - .io_rs1_valid (_regfile_io_readData_4_valid), .io_rs1_data (_regfile_io_readData_4_data), - .io_rs2_valid (_regfile_io_readData_5_valid), .io_rs2_data (_regfile_io_readData_5_data), .io_rd_valid (_bru_2_io_rd_valid), .io_rd_bits_addr (_bru_2_io_rd_bits_addr), @@ -13524,9 +19852,7 @@ module SCore( .io_req_bits_pc (_dispatch_io_bru_3_bits_pc), .io_req_bits_target (_dispatch_io_bru_3_bits_target), .io_req_bits_link (_dispatch_io_bru_3_bits_link), - .io_rs1_valid (_regfile_io_readData_6_valid), .io_rs1_data (_regfile_io_readData_6_data), - .io_rs2_valid (_regfile_io_readData_7_valid), .io_rs2_data (_regfile_io_readData_7_data), .io_rd_valid (_bru_3_io_rd_valid), .io_rd_bits_addr (_bru_3_io_rd_bits_addr), @@ -13535,111 +19861,31 @@ module SCore( .io_taken_value (_bru_3_io_taken_value), .io_target_data (_regfile_io_target_3_data) ); - LsuV1 lsu ( - .clock (clock), - .reset (reset), - .io_req_0_ready (_lsu_io_req_0_ready), - .io_req_0_valid (_dispatch_io_lsu_0_valid), - .io_req_0_bits_store (_dispatch_io_lsu_0_bits_store), - .io_req_0_bits_addr (_dispatch_io_lsu_0_bits_addr), - .io_req_0_bits_op (_dispatch_io_lsu_0_bits_op), - .io_req_0_bits_pc (_dispatch_io_lsu_0_bits_pc), - .io_req_1_ready (_lsu_io_req_1_ready), - .io_req_1_valid (_dispatch_io_lsu_1_valid), - .io_req_1_bits_store (_dispatch_io_lsu_1_bits_store), - .io_req_1_bits_addr (_dispatch_io_lsu_1_bits_addr), - .io_req_1_bits_op (_dispatch_io_lsu_1_bits_op), - .io_req_1_bits_pc (_dispatch_io_lsu_1_bits_pc), - .io_req_2_ready (_lsu_io_req_2_ready), - .io_req_2_valid (_dispatch_io_lsu_2_valid), - .io_req_2_bits_store (_dispatch_io_lsu_2_bits_store), - .io_req_2_bits_addr (_dispatch_io_lsu_2_bits_addr), - .io_req_2_bits_op (_dispatch_io_lsu_2_bits_op), - .io_req_2_bits_pc (_dispatch_io_lsu_2_bits_pc), - .io_req_3_ready (_lsu_io_req_3_ready), - .io_req_3_valid (_dispatch_io_lsu_3_valid), - .io_req_3_bits_store (_dispatch_io_lsu_3_bits_store), - .io_req_3_bits_addr (_dispatch_io_lsu_3_bits_addr), - .io_req_3_bits_op (_dispatch_io_lsu_3_bits_op), - .io_req_3_bits_pc (_dispatch_io_lsu_3_bits_pc), - .io_busPort_addr_0 (_regfile_io_busPort_addr_0), - .io_busPort_addr_1 (_regfile_io_busPort_addr_1), - .io_busPort_addr_2 (_regfile_io_busPort_addr_2), - .io_busPort_addr_3 (_regfile_io_busPort_addr_3), - .io_busPort_data_0 (_regfile_io_busPort_data_0), - .io_busPort_data_1 (_regfile_io_busPort_data_1), - .io_busPort_data_2 (_regfile_io_busPort_data_2), - .io_busPort_data_3 (_regfile_io_busPort_data_3), - .io_busPort_flt_data_0 (_fRegfile_io_busPort_data_0), - .io_rd_valid (_lsu_io_rd_valid), - .io_rd_bits_addr (_lsu_io_rd_bits_addr), - .io_rd_bits_data (_lsu_io_rd_bits_data), - .io_rd_flt_valid (_lsu_io_rd_flt_valid), - .io_rd_flt_bits_addr (_lsu_io_rd_flt_bits_addr), - .io_rd_flt_bits_data (_lsu_io_rd_flt_bits_data), - .io_ibus_valid (_lsu_io_ibus_valid), - .io_ibus_ready (_lsu_io_ibus_valid), - .io_ibus_addr (_lsu_io_ibus_addr), - .io_ibus_rdata (io_ibus_rdata), - .io_dbus_valid (_lsu_io_dbus_valid), - .io_dbus_write (_lsu_io_dbus_write), - .io_dbus_addr (_lsu_io_dbus_addr), - .io_dbus_wdata (_lsu_io_dbus_wdata), - .io_dbus_wmask (io_dbus_wmask), - .io_dbus_rdata (io_dbus_rdata), - .io_flush_valid (_lsu_io_flush_valid), - .io_flush_ready (_lsu_io_flush_valid), - .io_flush_fencei (_lsu_io_flush_fencei), - .io_flush_pcNext (_lsu_io_flush_pcNext), - .io_fault_valid (_lsu_io_fault_valid), - .io_fault_bits_write (_lsu_io_fault_bits_write), - .io_fault_bits_addr (_lsu_io_fault_bits_addr), - .io_fault_bits_epc (_lsu_io_fault_bits_epc), - .io_ebus_dbus_valid (io_ebus_dbus_valid), - .io_ebus_dbus_ready (io_ebus_dbus_ready), - .io_ebus_dbus_write (io_ebus_dbus_write), - .io_ebus_dbus_pc (io_ebus_dbus_pc), - .io_ebus_dbus_addr (io_ebus_dbus_addr), - .io_ebus_dbus_size (io_ebus_dbus_size), - .io_ebus_dbus_wdata (io_ebus_dbus_wdata), - .io_ebus_dbus_rdata (io_ebus_dbus_rdata), - .io_ebus_fault_valid (io_ebus_fault_valid), - .io_ebus_fault_bits_write (io_ebus_fault_bits_write), - .io_ebus_fault_bits_addr (io_ebus_fault_bits_addr), - .io_ebus_fault_bits_epc (io_ebus_fault_bits_epc), - .io_storeCount (_lsu_io_storeCount), - .io_active (_lsu_io_active) - ); Mlu mlu ( .clock (clock), .reset (reset), .io_req_0_valid (_dispatch_io_mlu_0_valid), .io_req_0_bits_addr (_dispatch_io_mlu_0_bits_addr), .io_req_0_bits_op (_dispatch_io_mlu_0_bits_op), + .io_req_1_ready (_mlu_io_req_1_ready), .io_req_1_valid (_dispatch_io_mlu_1_valid), .io_req_1_bits_addr (_dispatch_io_mlu_1_bits_addr), .io_req_1_bits_op (_dispatch_io_mlu_1_bits_op), + .io_req_2_ready (_mlu_io_req_2_ready), .io_req_2_valid (_dispatch_io_mlu_2_valid), .io_req_2_bits_addr (_dispatch_io_mlu_2_bits_addr), .io_req_2_bits_op (_dispatch_io_mlu_2_bits_op), + .io_req_3_ready (_mlu_io_req_3_ready), .io_req_3_valid (_dispatch_io_mlu_3_valid), .io_req_3_bits_addr (_dispatch_io_mlu_3_bits_addr), .io_req_3_bits_op (_dispatch_io_mlu_3_bits_op), - .io_rs1_0_valid (_regfile_io_readData_0_valid), .io_rs1_0_data (_regfile_io_readData_0_data), - .io_rs1_1_valid (_regfile_io_readData_2_valid), .io_rs1_1_data (_regfile_io_readData_2_data), - .io_rs1_2_valid (_regfile_io_readData_4_valid), .io_rs1_2_data (_regfile_io_readData_4_data), - .io_rs1_3_valid (_regfile_io_readData_6_valid), .io_rs1_3_data (_regfile_io_readData_6_data), - .io_rs2_0_valid (_regfile_io_readData_1_valid), .io_rs2_0_data (_regfile_io_readData_1_data), - .io_rs2_1_valid (_regfile_io_readData_3_valid), .io_rs2_1_data (_regfile_io_readData_3_data), - .io_rs2_2_valid (_regfile_io_readData_5_valid), .io_rs2_2_data (_regfile_io_readData_5_data), - .io_rs2_3_valid (_regfile_io_readData_7_valid), .io_rs2_3_data (_regfile_io_readData_7_data), .io_rd_valid (_mlu_io_rd_valid), .io_rd_bits_addr (_mlu_io_rd_bits_addr), @@ -13659,52 +19905,22 @@ module SCore( .io_rd_bits_addr (_dvu_io_rd_bits_addr), .io_rd_bits_data (_dvu_io_rd_bits_data) ); - FaultManager fault_manager ( - .io_in_fault_0_csr (_dispatch_io_csrFault_0), - .io_in_fault_0_jal (_dispatch_io_jalFault_0), - .io_in_fault_0_jalr (_dispatch_io_jalrFault_0), - .io_in_fault_0_bxx (_dispatch_io_bxxFault_0), - .io_in_fault_0_undef (_dispatch_io_undefFault_0), - .io_in_fault_1_jal (_dispatch_io_jalFault_1), - .io_in_fault_1_jalr (_dispatch_io_jalrFault_1), - .io_in_fault_1_bxx (_dispatch_io_bxxFault_1), - .io_in_fault_2_jal (_dispatch_io_jalFault_2), - .io_in_fault_2_jalr (_dispatch_io_jalrFault_2), - .io_in_fault_2_bxx (_dispatch_io_bxxFault_2), - .io_in_fault_3_jal (_dispatch_io_jalFault_3), - .io_in_fault_3_jalr (_dispatch_io_jalrFault_3), - .io_in_fault_3_bxx (_dispatch_io_bxxFault_3), - .io_in_pc_0_pc (_fetch_io_inst_lanes_0_bits_addr), - .io_in_pc_1_pc (_fetch_io_inst_lanes_1_bits_addr), - .io_in_pc_2_pc (_fetch_io_inst_lanes_2_bits_addr), - .io_in_pc_3_pc (_fetch_io_inst_lanes_3_bits_addr), - .io_in_memory_fault_valid - (io_ibus_fault_valid ? io_ibus_fault_valid : _lsu_io_fault_valid), - .io_in_memory_fault_bits_write - (~io_ibus_fault_valid & _lsu_io_fault_valid & _lsu_io_fault_bits_write), - .io_in_memory_fault_bits_addr - (io_ibus_fault_valid | ~_lsu_io_fault_valid ? 32'h0 : _lsu_io_fault_bits_addr), - .io_in_memory_fault_bits_epc - (io_ibus_fault_valid - ? io_ibus_fault_bits_epc - : _lsu_io_fault_valid ? _lsu_io_fault_bits_epc : 32'h0), - .io_in_ibus_fault (io_ibus_fault_valid), - .io_in_undef_0_inst (_fetch_io_inst_lanes_0_bits_inst), - .io_in_undef_1_inst (_fetch_io_inst_lanes_1_bits_inst), - .io_in_undef_2_inst (_fetch_io_inst_lanes_2_bits_inst), - .io_in_undef_3_inst (_fetch_io_inst_lanes_3_bits_inst), - .io_in_jal_0_target (_dispatch_io_bruTarget_0), - .io_in_jal_1_target (_dispatch_io_bruTarget_1), - .io_in_jal_2_target (_dispatch_io_bruTarget_2), - .io_in_jal_3_target (_dispatch_io_bruTarget_3), - .io_in_jalr_0_target (_regfile_io_target_0_data), - .io_in_jalr_1_target (_regfile_io_target_1_data), - .io_in_jalr_2_target (_regfile_io_target_2_data), - .io_in_jalr_3_target (_regfile_io_target_3_data), - .io_out_valid (_fault_manager_io_out_valid), - .io_out_bits_mepc (_fault_manager_io_out_bits_mepc), - .io_out_bits_mtval (_fault_manager_io_out_bits_mtval), - .io_out_bits_mcause (_fault_manager_io_out_bits_mcause) + Arbiter2_CsrCmd csrReqArbiter ( + .io_in_0_valid (_dispatch_io_csr_valid), + .io_in_0_bits_addr (_dispatch_io_csr_bits_addr), + .io_in_0_bits_index (_dispatch_io_csr_bits_index), + .io_in_0_bits_rs1 (_dispatch_io_csr_bits_rs1), + .io_in_0_bits_op (_dispatch_io_csr_bits_op), + .io_in_1_valid (io_dm_csr_valid), + .io_in_1_bits_addr (io_dm_csr_bits_addr), + .io_in_1_bits_index (io_dm_csr_bits_index), + .io_in_1_bits_rs1 (io_dm_csr_bits_rs1), + .io_in_1_bits_op (io_dm_csr_bits_op), + .io_out_valid (_csrReqArbiter_io_out_valid), + .io_out_bits_addr (_csrReqArbiter_io_out_bits_addr), + .io_out_bits_index (_csrReqArbiter_io_out_bits_index), + .io_out_bits_rs1 (_csrReqArbiter_io_out_bits_rs1), + .io_out_bits_op (_csrReqArbiter_io_out_bits_op) ); FloatCore floatCore ( .clock (clock), @@ -13713,6 +19929,8 @@ module SCore( .io_inst_valid (_dispatch_io_float_valid), .io_inst_bits_opcode (_dispatch_io_float_bits_opcode), .io_inst_bits_funct5 (_dispatch_io_float_bits_funct5), + .io_inst_bits_src_fmt (_dispatch_io_float_bits_src_fmt), + .io_inst_bits_dst_fmt (_dispatch_io_float_bits_dst_fmt), .io_inst_bits_rs3 (_dispatch_io_float_bits_rs3), .io_inst_bits_rs2 (_dispatch_io_float_bits_rs2), .io_inst_bits_rs1 (_dispatch_io_float_bits_rs1), @@ -13721,6 +19939,7 @@ module SCore( .io_inst_bits_pc (_dispatch_io_float_bits_pc), .io_inst_bits_scalar_rd (_dispatch_io_float_bits_scalar_rd), .io_inst_bits_scalar_rs1 (_dispatch_io_float_bits_scalar_rs1), + .io_inst_bits_float_rs1 (_dispatch_io_float_bits_float_rs1), .io_inst_bits_rd (_dispatch_io_float_bits_rd), .io_inst_bits_uses_rs3 (_dispatch_io_float_bits_uses_rs3), .io_inst_bits_uses_rs2 (_dispatch_io_float_bits_uses_rs2), @@ -13764,8 +19983,12 @@ module SCore( FRegfile fRegfile ( .clock (clock), .reset (reset), - .io_read_ports_0_valid (_floatCore_io_read_ports_0_valid), - .io_read_ports_0_addr (_floatCore_io_read_ports_0_addr), + .io_read_ports_0_valid + (io_dm_float_rs_valid | _floatCore_io_read_ports_0_valid), + .io_read_ports_0_addr + (io_dm_float_rs_valid + ? io_dm_float_rs_addr + : _floatCore_io_read_ports_0_valid ? _floatCore_io_read_ports_0_addr : 5'h0), .io_read_ports_0_data_mantissa (_fRegfile_io_read_ports_0_data_mantissa), .io_read_ports_0_data_exponent (_fRegfile_io_read_ports_0_data_exponent), .io_read_ports_0_data_sign (_fRegfile_io_read_ports_0_data_sign), @@ -13779,23 +20002,37 @@ module SCore( .io_read_ports_2_data_mantissa (_fRegfile_io_read_ports_2_data_mantissa), .io_read_ports_2_data_exponent (_fRegfile_io_read_ports_2_data_exponent), .io_read_ports_2_data_sign (_fRegfile_io_read_ports_2_data_sign), - .io_write_ports_0_valid (_floatCore_io_write_ports_0_valid), - .io_write_ports_0_addr (_floatCore_io_write_ports_0_addr), - .io_write_ports_0_data_mantissa (_floatCore_io_write_ports_0_data_mantissa), - .io_write_ports_0_data_exponent (_floatCore_io_write_ports_0_data_exponent), - .io_write_ports_0_data_sign (_floatCore_io_write_ports_0_data_sign), + .io_write_ports_0_valid (fRegfile_io_write_ports_0_valid), + .io_write_ports_0_addr (fRegfile_io_write_ports_0_addr), + .io_write_ports_0_data_mantissa + (io_dm_float_rd_valid + ? io_dm_float_rd_data_mantissa + : _floatCore_io_write_ports_0_valid + ? _floatCore_io_write_ports_0_data_mantissa + : 23'h0), + .io_write_ports_0_data_exponent + (io_dm_float_rd_valid + ? io_dm_float_rd_data_exponent + : _floatCore_io_write_ports_0_valid + ? _floatCore_io_write_ports_0_data_exponent + : 8'h0), + .io_write_ports_0_data_sign + (io_dm_float_rd_valid + ? io_dm_float_rd_data_sign + : _floatCore_io_write_ports_0_valid & _floatCore_io_write_ports_0_data_sign), .io_write_ports_1_valid (_floatCore_io_write_ports_1_valid), .io_write_ports_1_addr (_floatCore_io_write_ports_1_addr), .io_write_ports_1_data_mantissa (_floatCore_io_write_ports_1_data_mantissa), .io_write_ports_1_data_exponent (_floatCore_io_write_ports_1_data_exponent), .io_write_ports_1_data_sign (_floatCore_io_write_ports_1_data_sign), + .io_pipelineFlush (_retirement_buffer_io_trapRetired), .io_scoreboard_set (_dispatch_io_rdMark_flt_valid ? 32'h1 << _dispatch_io_rdMark_flt_addr : 32'h0), .io_scoreboard (_fRegfile_io_scoreboard), .io_busPort_data_0 (_fRegfile_io_busPort_data_0), .io_busPortAddr (_dispatch_io_fbusPortAddr) ); - Arbiter3_RegfileWriteDataIO arb ( + Arbiter4_RegfileWriteDataIO arb ( .io_in_0_valid (_mlu_io_rd_valid), .io_in_0_bits_addr (_mlu_io_rd_bits_addr), .io_in_0_bits_data (_mlu_io_rd_bits_data), @@ -13807,99 +20044,27 @@ module SCore( .io_in_2_valid (_floatCore_io_scalar_rd_valid), .io_in_2_bits_addr (_floatCore_io_scalar_rd_bits_addr), .io_in_2_bits_data (_floatCore_io_scalar_rd_bits_data), + .io_in_3_ready (io_dm_scalar_rd_ready), + .io_in_3_valid (io_dm_scalar_rd_valid), + .io_in_3_bits_addr (io_dm_scalar_rd_bits_addr), + .io_in_3_bits_data (io_dm_scalar_rd_bits_data), .io_out_valid (_arb_io_out_valid), .io_out_bits_addr (_arb_io_out_bits_addr), .io_out_bits_data (_arb_io_out_bits_data) ); - assign io_csr_out_value_4 = _csr_io_csr_out_value_4; assign io_halted = _csr_io_halted; assign io_wfi = _csr_io_wfi; + assign io_dm_csr_rd_valid = _csr_io_rd_valid; + assign io_dm_csr_rd_bits = _csr_io_rd_bits_data; + assign io_dm_float_rs_data_mantissa = _fRegfile_io_read_ports_0_data_mantissa; + assign io_dm_float_rs_data_exponent = _fRegfile_io_read_ports_0_data_exponent; + assign io_dm_float_rs_data_sign = _fRegfile_io_read_ports_0_data_sign; + assign io_dm_debug_mode = _csr_io_dm_debug_mode; assign io_ibus_valid = _lsu_io_ibus_valid ? _lsu_io_ibus_valid : _fetch_io_ibus_valid; assign io_ibus_addr = _lsu_io_ibus_valid ? _lsu_io_ibus_addr : _fetch_io_ibus_addr; - assign io_dbus_valid = _lsu_io_dbus_valid; - assign io_dbus_write = _lsu_io_dbus_write; - assign io_dbus_addr = _lsu_io_dbus_addr; - assign io_dbus_wdata = _lsu_io_dbus_wdata; - assign io_slog_valid = slogValid; - assign io_slog_addr = {3'h0, slogValid ? slogAddr : 2'h0}; - assign io_slog_data = slogValid ? _regfile_io_readData_0_data : 32'h0; - assign io_debug_en = - {~(_bru_1_io_taken_valid | _debugBrch_T_1), - ~_debugBrch_T_1, - ~_bru_3_io_taken_valid, - 1'h1} & debugEn; - assign io_debug_addr_0 = debugAddr_0; - assign io_debug_addr_1 = debugAddr_1; - assign io_debug_addr_2 = debugAddr_2; - assign io_debug_addr_3 = debugAddr_3; - assign io_debug_inst_0 = debugInst_0; - assign io_debug_inst_1 = debugInst_1; - assign io_debug_inst_2 = debugInst_2; - assign io_debug_inst_3 = debugInst_3; - assign io_debug_cycles = _csr_io_csr_out_value_4; - assign io_debug_dbus_valid = _lsu_io_dbus_valid; - assign io_debug_dbus_bits_addr = _lsu_io_dbus_addr; - assign io_debug_dbus_bits_wdata = _lsu_io_dbus_wdata; - assign io_debug_dbus_bits_write = _lsu_io_dbus_write; - assign io_debug_dispatch_0_instFire = - _dispatch_io_inst_0_ready & _fetch_io_inst_lanes_0_valid; - assign io_debug_dispatch_0_instAddr = _fetch_io_inst_lanes_0_bits_addr; - assign io_debug_dispatch_0_instInst = _fetch_io_inst_lanes_0_bits_inst; - assign io_debug_dispatch_1_instFire = - _dispatch_io_inst_1_ready & _fetch_io_inst_lanes_1_valid; - assign io_debug_dispatch_1_instAddr = _fetch_io_inst_lanes_1_bits_addr; - assign io_debug_dispatch_1_instInst = _fetch_io_inst_lanes_1_bits_inst; - assign io_debug_dispatch_2_instFire = - _dispatch_io_inst_2_ready & _fetch_io_inst_lanes_2_valid; - assign io_debug_dispatch_2_instAddr = _fetch_io_inst_lanes_2_bits_addr; - assign io_debug_dispatch_2_instInst = _fetch_io_inst_lanes_2_bits_inst; - assign io_debug_dispatch_3_instFire = - _dispatch_io_inst_3_ready & _fetch_io_inst_lanes_3_valid; - assign io_debug_dispatch_3_instAddr = _fetch_io_inst_lanes_3_bits_addr; - assign io_debug_dispatch_3_instInst = _fetch_io_inst_lanes_3_bits_inst; - assign io_debug_regfile_writeAddr_0_valid = _dispatch_io_rdMark_0_valid; - assign io_debug_regfile_writeAddr_0_bits = _dispatch_io_rdMark_0_addr; - assign io_debug_regfile_writeAddr_1_valid = _dispatch_io_rdMark_1_valid; - assign io_debug_regfile_writeAddr_1_bits = _dispatch_io_rdMark_1_addr; - assign io_debug_regfile_writeAddr_2_valid = _dispatch_io_rdMark_2_valid; - assign io_debug_regfile_writeAddr_2_bits = _dispatch_io_rdMark_2_addr; - assign io_debug_regfile_writeAddr_3_valid = _dispatch_io_rdMark_3_valid; - assign io_debug_regfile_writeAddr_3_bits = _dispatch_io_rdMark_3_addr; - assign io_debug_regfile_writeData_0_valid = regfile_io_writeData_0_valid; - assign io_debug_regfile_writeData_0_bits_addr = regfile_io_writeData_0_bits_addr; - assign io_debug_regfile_writeData_0_bits_data = regfile_io_writeData_0_bits_data; - assign io_debug_regfile_writeData_1_valid = regfile_io_writeData_1_valid; - assign io_debug_regfile_writeData_1_bits_addr = regfile_io_writeData_1_bits_addr; - assign io_debug_regfile_writeData_1_bits_data = regfile_io_writeData_1_bits_data; - assign io_debug_regfile_writeData_2_valid = regfile_io_writeData_2_valid; - assign io_debug_regfile_writeData_2_bits_addr = regfile_io_writeData_2_bits_addr; - assign io_debug_regfile_writeData_2_bits_data = regfile_io_writeData_2_bits_data; - assign io_debug_regfile_writeData_3_valid = regfile_io_writeData_3_valid; - assign io_debug_regfile_writeData_3_bits_addr = regfile_io_writeData_3_bits_addr; - assign io_debug_regfile_writeData_3_bits_data = regfile_io_writeData_3_bits_data; - assign io_debug_regfile_writeData_4_valid = _arb_io_out_valid; - assign io_debug_regfile_writeData_4_bits_addr = _arb_io_out_bits_addr; - assign io_debug_regfile_writeData_4_bits_data = _arb_io_out_bits_data; - assign io_debug_regfile_writeData_5_valid = _lsu_io_rd_valid; - assign io_debug_regfile_writeData_5_bits_addr = _lsu_io_rd_bits_addr; - assign io_debug_regfile_writeData_5_bits_data = _lsu_io_rd_bits_data; - assign io_debug_float_writeAddr_valid = _dispatch_io_rdMark_flt_valid; - assign io_debug_float_writeAddr_bits = _dispatch_io_rdMark_flt_addr; - assign io_debug_float_writeData_0_valid = _floatCore_io_write_ports_0_valid; - assign io_debug_float_writeData_0_bits_addr = {27'h0, _floatCore_io_write_ports_0_addr}; - assign io_debug_float_writeData_0_bits_data = - {_floatCore_io_write_ports_0_data_sign, - _floatCore_io_write_ports_0_data_exponent, - _floatCore_io_write_ports_0_data_mantissa}; - assign io_debug_float_writeData_1_valid = _floatCore_io_write_ports_1_valid; - assign io_debug_float_writeData_1_bits_addr = {27'h0, _floatCore_io_write_ports_1_addr}; - assign io_debug_float_writeData_1_bits_data = - {_floatCore_io_write_ports_1_data_sign, - _floatCore_io_write_ports_1_data_exponent, - _floatCore_io_write_ports_1_data_mantissa}; endmodule -module CoreMini( +module CoreMiniCore( input clock, reset, input [31:0] io_csr_in_value_0, @@ -13911,15 +20076,45 @@ module CoreMini( io_csr_out_value_5, io_csr_out_value_6, io_csr_out_value_7, + io_csr_out_value_8, output io_halted, io_fault, io_wfi, input io_irq, - output io_ibus_valid, + io_timer_irq, + io_software_irq, + io_dm_debug_req, + io_dm_resume_req, + io_dm_csr_valid, + input [4:0] io_dm_csr_bits_addr, + input [11:0] io_dm_csr_bits_index, + input [4:0] io_dm_csr_bits_rs1, + input [1:0] io_dm_csr_bits_op, + input [31:0] io_dm_csr_rs1, + output io_dm_csr_rd_valid, + output [31:0] io_dm_csr_rd_bits, + output io_dm_scalar_rd_ready, + input io_dm_scalar_rd_valid, + input [4:0] io_dm_scalar_rd_bits_addr, + input [31:0] io_dm_scalar_rd_bits_data, + input [4:0] io_dm_scalar_rs_idx, + output [31:0] io_dm_scalar_rs_data, + input io_dm_float_rd_valid, + input [4:0] io_dm_float_rd_addr, + input [22:0] io_dm_float_rd_data_mantissa, + input [7:0] io_dm_float_rd_data_exponent, + input io_dm_float_rd_data_sign, + io_dm_float_rs_valid, + input [4:0] io_dm_float_rs_addr, + output [22:0] io_dm_float_rs_data_mantissa, + output [7:0] io_dm_float_rs_data_exponent, + output io_dm_float_rs_data_sign, + io_dm_debug_mode, + io_ibus_valid, + input io_ibus_ready, output [31:0] io_ibus_addr, input [127:0] io_ibus_rdata, input io_ibus_fault_valid, - input [31:0] io_ibus_fault_bits_epc, output io_dbus_valid, io_dbus_write, output [31:0] io_dbus_addr, @@ -13929,182 +20124,80 @@ module CoreMini( output io_ebus_dbus_valid, input io_ebus_dbus_ready, output io_ebus_dbus_write, - output [31:0] io_ebus_dbus_pc, - io_ebus_dbus_addr, + output [31:0] io_ebus_dbus_addr, output [4:0] io_ebus_dbus_size, output [127:0] io_ebus_dbus_wdata, + output [15:0] io_ebus_dbus_wmask, input [127:0] io_ebus_dbus_rdata, - input io_ebus_fault_valid, - io_ebus_fault_bits_write, - input [31:0] io_ebus_fault_bits_addr, - io_ebus_fault_bits_epc, - output io_slog_valid, - output [4:0] io_slog_addr, - output [31:0] io_slog_data, - output [3:0] io_debug_en, - output [31:0] io_debug_addr_0, - io_debug_addr_1, - io_debug_addr_2, - io_debug_addr_3, - io_debug_inst_0, - io_debug_inst_1, - io_debug_inst_2, - io_debug_inst_3, - io_debug_cycles, - output io_debug_dbus_valid, - output [31:0] io_debug_dbus_bits_addr, - output [127:0] io_debug_dbus_bits_wdata, - output io_debug_dbus_bits_write, - io_debug_dispatch_0_instFire, - output [31:0] io_debug_dispatch_0_instAddr, - io_debug_dispatch_0_instInst, - output io_debug_dispatch_1_instFire, - output [31:0] io_debug_dispatch_1_instAddr, - io_debug_dispatch_1_instInst, - output io_debug_dispatch_2_instFire, - output [31:0] io_debug_dispatch_2_instAddr, - io_debug_dispatch_2_instInst, - output io_debug_dispatch_3_instFire, - output [31:0] io_debug_dispatch_3_instAddr, - io_debug_dispatch_3_instInst, - output io_debug_regfile_writeAddr_0_valid, - output [4:0] io_debug_regfile_writeAddr_0_bits, - output io_debug_regfile_writeAddr_1_valid, - output [4:0] io_debug_regfile_writeAddr_1_bits, - output io_debug_regfile_writeAddr_2_valid, - output [4:0] io_debug_regfile_writeAddr_2_bits, - output io_debug_regfile_writeAddr_3_valid, - output [4:0] io_debug_regfile_writeAddr_3_bits, - output io_debug_regfile_writeData_0_valid, - output [4:0] io_debug_regfile_writeData_0_bits_addr, - output [31:0] io_debug_regfile_writeData_0_bits_data, - output io_debug_regfile_writeData_1_valid, - output [4:0] io_debug_regfile_writeData_1_bits_addr, - output [31:0] io_debug_regfile_writeData_1_bits_data, - output io_debug_regfile_writeData_2_valid, - output [4:0] io_debug_regfile_writeData_2_bits_addr, - output [31:0] io_debug_regfile_writeData_2_bits_data, - output io_debug_regfile_writeData_3_valid, - output [4:0] io_debug_regfile_writeData_3_bits_addr, - output [31:0] io_debug_regfile_writeData_3_bits_data, - output io_debug_regfile_writeData_4_valid, - output [4:0] io_debug_regfile_writeData_4_bits_addr, - output [31:0] io_debug_regfile_writeData_4_bits_data, - output io_debug_regfile_writeData_5_valid, - output [4:0] io_debug_regfile_writeData_5_bits_addr, - output [31:0] io_debug_regfile_writeData_5_bits_data, - output io_debug_float_writeAddr_valid, - output [4:0] io_debug_float_writeAddr_bits, - output io_debug_float_writeData_0_valid, - output [31:0] io_debug_float_writeData_0_bits_addr, - io_debug_float_writeData_0_bits_data, - output io_debug_float_writeData_1_valid, - output [31:0] io_debug_float_writeData_1_bits_addr, - io_debug_float_writeData_1_bits_data + input io_ebus_fault_valid ); SCore score ( - .clock (clock), - .reset (reset), - .io_csr_in_value_0 (io_csr_in_value_0), - .io_csr_out_value_0 (io_csr_out_value_0), - .io_csr_out_value_1 (io_csr_out_value_1), - .io_csr_out_value_2 (io_csr_out_value_2), - .io_csr_out_value_3 (io_csr_out_value_3), - .io_csr_out_value_4 (io_csr_out_value_4), - .io_csr_out_value_5 (io_csr_out_value_5), - .io_csr_out_value_6 (io_csr_out_value_6), - .io_csr_out_value_7 (io_csr_out_value_7), - .io_halted (io_halted), - .io_fault (io_fault), - .io_wfi (io_wfi), - .io_irq (io_irq), - .io_ibus_valid (io_ibus_valid), - .io_ibus_addr (io_ibus_addr), - .io_ibus_rdata (io_ibus_rdata), - .io_ibus_fault_valid (io_ibus_fault_valid), - .io_ibus_fault_bits_epc (io_ibus_fault_bits_epc), - .io_dbus_valid (io_dbus_valid), - .io_dbus_write (io_dbus_write), - .io_dbus_addr (io_dbus_addr), - .io_dbus_wdata (io_dbus_wdata), - .io_dbus_wmask (io_dbus_wmask), - .io_dbus_rdata (io_dbus_rdata), - .io_ebus_dbus_valid (io_ebus_dbus_valid), - .io_ebus_dbus_ready (io_ebus_dbus_ready), - .io_ebus_dbus_write (io_ebus_dbus_write), - .io_ebus_dbus_pc (io_ebus_dbus_pc), - .io_ebus_dbus_addr (io_ebus_dbus_addr), - .io_ebus_dbus_size (io_ebus_dbus_size), - .io_ebus_dbus_wdata (io_ebus_dbus_wdata), - .io_ebus_dbus_rdata (io_ebus_dbus_rdata), - .io_ebus_fault_valid (io_ebus_fault_valid), - .io_ebus_fault_bits_write (io_ebus_fault_bits_write), - .io_ebus_fault_bits_addr (io_ebus_fault_bits_addr), - .io_ebus_fault_bits_epc (io_ebus_fault_bits_epc), - .io_slog_valid (io_slog_valid), - .io_slog_addr (io_slog_addr), - .io_slog_data (io_slog_data), - .io_debug_en (io_debug_en), - .io_debug_addr_0 (io_debug_addr_0), - .io_debug_addr_1 (io_debug_addr_1), - .io_debug_addr_2 (io_debug_addr_2), - .io_debug_addr_3 (io_debug_addr_3), - .io_debug_inst_0 (io_debug_inst_0), - .io_debug_inst_1 (io_debug_inst_1), - .io_debug_inst_2 (io_debug_inst_2), - .io_debug_inst_3 (io_debug_inst_3), - .io_debug_cycles (io_debug_cycles), - .io_debug_dbus_valid (io_debug_dbus_valid), - .io_debug_dbus_bits_addr (io_debug_dbus_bits_addr), - .io_debug_dbus_bits_wdata (io_debug_dbus_bits_wdata), - .io_debug_dbus_bits_write (io_debug_dbus_bits_write), - .io_debug_dispatch_0_instFire (io_debug_dispatch_0_instFire), - .io_debug_dispatch_0_instAddr (io_debug_dispatch_0_instAddr), - .io_debug_dispatch_0_instInst (io_debug_dispatch_0_instInst), - .io_debug_dispatch_1_instFire (io_debug_dispatch_1_instFire), - .io_debug_dispatch_1_instAddr (io_debug_dispatch_1_instAddr), - .io_debug_dispatch_1_instInst (io_debug_dispatch_1_instInst), - .io_debug_dispatch_2_instFire (io_debug_dispatch_2_instFire), - .io_debug_dispatch_2_instAddr (io_debug_dispatch_2_instAddr), - .io_debug_dispatch_2_instInst (io_debug_dispatch_2_instInst), - .io_debug_dispatch_3_instFire (io_debug_dispatch_3_instFire), - .io_debug_dispatch_3_instAddr (io_debug_dispatch_3_instAddr), - .io_debug_dispatch_3_instInst (io_debug_dispatch_3_instInst), - .io_debug_regfile_writeAddr_0_valid (io_debug_regfile_writeAddr_0_valid), - .io_debug_regfile_writeAddr_0_bits (io_debug_regfile_writeAddr_0_bits), - .io_debug_regfile_writeAddr_1_valid (io_debug_regfile_writeAddr_1_valid), - .io_debug_regfile_writeAddr_1_bits (io_debug_regfile_writeAddr_1_bits), - .io_debug_regfile_writeAddr_2_valid (io_debug_regfile_writeAddr_2_valid), - .io_debug_regfile_writeAddr_2_bits (io_debug_regfile_writeAddr_2_bits), - .io_debug_regfile_writeAddr_3_valid (io_debug_regfile_writeAddr_3_valid), - .io_debug_regfile_writeAddr_3_bits (io_debug_regfile_writeAddr_3_bits), - .io_debug_regfile_writeData_0_valid (io_debug_regfile_writeData_0_valid), - .io_debug_regfile_writeData_0_bits_addr (io_debug_regfile_writeData_0_bits_addr), - .io_debug_regfile_writeData_0_bits_data (io_debug_regfile_writeData_0_bits_data), - .io_debug_regfile_writeData_1_valid (io_debug_regfile_writeData_1_valid), - .io_debug_regfile_writeData_1_bits_addr (io_debug_regfile_writeData_1_bits_addr), - .io_debug_regfile_writeData_1_bits_data (io_debug_regfile_writeData_1_bits_data), - .io_debug_regfile_writeData_2_valid (io_debug_regfile_writeData_2_valid), - .io_debug_regfile_writeData_2_bits_addr (io_debug_regfile_writeData_2_bits_addr), - .io_debug_regfile_writeData_2_bits_data (io_debug_regfile_writeData_2_bits_data), - .io_debug_regfile_writeData_3_valid (io_debug_regfile_writeData_3_valid), - .io_debug_regfile_writeData_3_bits_addr (io_debug_regfile_writeData_3_bits_addr), - .io_debug_regfile_writeData_3_bits_data (io_debug_regfile_writeData_3_bits_data), - .io_debug_regfile_writeData_4_valid (io_debug_regfile_writeData_4_valid), - .io_debug_regfile_writeData_4_bits_addr (io_debug_regfile_writeData_4_bits_addr), - .io_debug_regfile_writeData_4_bits_data (io_debug_regfile_writeData_4_bits_data), - .io_debug_regfile_writeData_5_valid (io_debug_regfile_writeData_5_valid), - .io_debug_regfile_writeData_5_bits_addr (io_debug_regfile_writeData_5_bits_addr), - .io_debug_regfile_writeData_5_bits_data (io_debug_regfile_writeData_5_bits_data), - .io_debug_float_writeAddr_valid (io_debug_float_writeAddr_valid), - .io_debug_float_writeAddr_bits (io_debug_float_writeAddr_bits), - .io_debug_float_writeData_0_valid (io_debug_float_writeData_0_valid), - .io_debug_float_writeData_0_bits_addr (io_debug_float_writeData_0_bits_addr), - .io_debug_float_writeData_0_bits_data (io_debug_float_writeData_0_bits_data), - .io_debug_float_writeData_1_valid (io_debug_float_writeData_1_valid), - .io_debug_float_writeData_1_bits_addr (io_debug_float_writeData_1_bits_addr), - .io_debug_float_writeData_1_bits_data (io_debug_float_writeData_1_bits_data) + .clock (clock), + .reset (reset), + .io_csr_in_value_0 (io_csr_in_value_0), + .io_csr_out_value_0 (io_csr_out_value_0), + .io_csr_out_value_1 (io_csr_out_value_1), + .io_csr_out_value_2 (io_csr_out_value_2), + .io_csr_out_value_3 (io_csr_out_value_3), + .io_csr_out_value_4 (io_csr_out_value_4), + .io_csr_out_value_5 (io_csr_out_value_5), + .io_csr_out_value_6 (io_csr_out_value_6), + .io_csr_out_value_7 (io_csr_out_value_7), + .io_csr_out_value_8 (io_csr_out_value_8), + .io_halted (io_halted), + .io_fault (io_fault), + .io_wfi (io_wfi), + .io_irq (io_irq), + .io_dm_debug_req (io_dm_debug_req), + .io_dm_resume_req (io_dm_resume_req), + .io_dm_csr_valid (io_dm_csr_valid), + .io_dm_csr_bits_addr (io_dm_csr_bits_addr), + .io_dm_csr_bits_index (io_dm_csr_bits_index), + .io_dm_csr_bits_rs1 (io_dm_csr_bits_rs1), + .io_dm_csr_bits_op (io_dm_csr_bits_op), + .io_dm_csr_rs1 (io_dm_csr_rs1), + .io_dm_csr_rd_valid (io_dm_csr_rd_valid), + .io_dm_csr_rd_bits (io_dm_csr_rd_bits), + .io_dm_scalar_rd_ready (io_dm_scalar_rd_ready), + .io_dm_scalar_rd_valid (io_dm_scalar_rd_valid), + .io_dm_scalar_rd_bits_addr (io_dm_scalar_rd_bits_addr), + .io_dm_scalar_rd_bits_data (io_dm_scalar_rd_bits_data), + .io_dm_scalar_rs_idx (io_dm_scalar_rs_idx), + .io_dm_scalar_rs_data (io_dm_scalar_rs_data), + .io_dm_float_rd_valid (io_dm_float_rd_valid), + .io_dm_float_rd_addr (io_dm_float_rd_addr), + .io_dm_float_rd_data_mantissa (io_dm_float_rd_data_mantissa), + .io_dm_float_rd_data_exponent (io_dm_float_rd_data_exponent), + .io_dm_float_rd_data_sign (io_dm_float_rd_data_sign), + .io_dm_float_rs_valid (io_dm_float_rs_valid), + .io_dm_float_rs_addr (io_dm_float_rs_addr), + .io_dm_float_rs_data_mantissa (io_dm_float_rs_data_mantissa), + .io_dm_float_rs_data_exponent (io_dm_float_rs_data_exponent), + .io_dm_float_rs_data_sign (io_dm_float_rs_data_sign), + .io_dm_debug_mode (io_dm_debug_mode), + .io_timer_irq (io_timer_irq), + .io_software_irq (io_software_irq), + .io_ibus_valid (io_ibus_valid), + .io_ibus_ready (io_ibus_ready), + .io_ibus_addr (io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_ibus_fault_valid (io_ibus_fault_valid), + .io_dbus_valid (io_dbus_valid), + .io_dbus_write (io_dbus_write), + .io_dbus_addr (io_dbus_addr), + .io_dbus_wdata (io_dbus_wdata), + .io_dbus_wmask (io_dbus_wmask), + .io_dbus_rdata (io_dbus_rdata), + .io_ebus_dbus_valid (io_ebus_dbus_valid), + .io_ebus_dbus_ready (io_ebus_dbus_ready), + .io_ebus_dbus_write (io_ebus_dbus_write), + .io_ebus_dbus_addr (io_ebus_dbus_addr), + .io_ebus_dbus_size (io_ebus_dbus_size), + .io_ebus_dbus_wdata (io_ebus_dbus_wdata), + .io_ebus_dbus_wmask (io_ebus_dbus_wmask), + .io_ebus_dbus_rdata (io_ebus_dbus_rdata), + .io_ebus_fault_valid (io_ebus_fault_valid) ); endmodule @@ -14118,14 +20211,18 @@ module SRAM_512x128( output [127:0] io_rdata ); - Sram_512x128 sramModules_0 ( + Sram #( + .GLOBAL_BASE_ADDR(0), + .NUM_ENTRIES(512) + ) sramModules_0 ( .clock (clock), .enable (io_enable), .write (io_write), .addr (io_addr), .wdata (io_wdata), .wmask (io_wmask), - .rdata (io_rdata) + .rdata (io_rdata), + .rvalid (/* unused */) ); endmodule @@ -14319,15 +20416,7 @@ module SRAM( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - readIssued = _RANDOM[/*Zero width*/ 1'b0][0]; - `endif // RANDOMIZE_REG_INIT if (reset) readIssued = 1'h0; end // initial @@ -14356,10 +20445,9 @@ module SRAM( io_sram_readData_15} : 128'h0; assign io_sram_address = - io_fabric_writeDataAddr_valid - ? io_fabric_writeDataAddr_bits[12:4] - : io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[12:4] : 9'h0; - assign io_sram_enable = io_fabric_readDataAddr_valid | io_fabric_writeDataAddr_valid; + (io_fabric_writeDataAddr_valid ? io_fabric_writeDataAddr_bits[12:4] : 9'h0) + | (io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[12:4] : 9'h0); + assign io_sram_enable = io_fabric_writeDataAddr_valid | io_fabric_readDataAddr_valid; assign io_sram_isWrite = io_fabric_writeDataAddr_valid; assign io_sram_writeData_0 = io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h0; @@ -14412,9 +20500,7 @@ module SRAM( endmodule module FabricArbiter( - input clock, - reset, - io_source_0_readDataAddr_valid, + input io_source_0_readDataAddr_valid, input [31:0] io_source_0_readDataAddr_bits, output [127:0] io_source_0_readData_bits, input io_source_0_writeDataAddr_valid, @@ -14429,7 +20515,15 @@ module FabricArbiter( input [31:0] io_source_1_writeDataAddr_bits, input [127:0] io_source_1_writeDataBits, input [15:0] io_source_1_writeDataStrb, - output io_fabricBusy, + input io_source_2_readDataAddr_valid, + input [31:0] io_source_2_readDataAddr_bits, + output io_source_2_readData_valid, + output [127:0] io_source_2_readData_bits, + input io_source_2_writeDataAddr_valid, + input [31:0] io_source_2_writeDataAddr_bits, + input [127:0] io_source_2_writeDataBits, + input [15:0] io_source_2_writeDataStrb, + output io_fabricBusy_1, io_port_readDataAddr_valid, output [31:0] io_port_readDataAddr_bits, input io_port_readData_valid, @@ -14440,27 +20534,130 @@ module FabricArbiter( output [15:0] io_port_writeDataStrb ); - wire source0Valid = io_source_0_readDataAddr_valid | io_source_0_writeDataAddr_valid; + wire sourceValid_0 = io_source_0_readDataAddr_valid | io_source_0_writeDataAddr_valid; + wire sourceValid_1 = io_source_1_readDataAddr_valid | io_source_1_writeDataAddr_valid; + wire sourceValid_2 = io_source_2_readDataAddr_valid | io_source_2_writeDataAddr_valid; assign io_source_0_readData_bits = io_port_readData_bits; assign io_source_1_readData_valid = io_port_readData_valid; assign io_source_1_readData_bits = io_port_readData_bits; - assign io_fabricBusy = source0Valid; + assign io_source_2_readData_valid = io_port_readData_valid; + assign io_source_2_readData_bits = io_port_readData_bits; + assign io_fabricBusy_1 = sourceValid_0; assign io_port_readDataAddr_valid = - source0Valid ? io_source_0_readDataAddr_valid : io_source_1_readDataAddr_valid; + sourceValid_0 + ? io_source_0_readDataAddr_valid + : sourceValid_1 + ? io_source_1_readDataAddr_valid + : sourceValid_2 & io_source_2_readDataAddr_valid; assign io_port_readDataAddr_bits = - source0Valid ? io_source_0_readDataAddr_bits : io_source_1_readDataAddr_bits; + sourceValid_0 + ? io_source_0_readDataAddr_bits + : sourceValid_1 + ? io_source_1_readDataAddr_bits + : sourceValid_2 ? io_source_2_readDataAddr_bits : 32'h0; assign io_port_writeDataAddr_valid = - source0Valid ? io_source_0_writeDataAddr_valid : io_source_1_writeDataAddr_valid; + sourceValid_0 + ? io_source_0_writeDataAddr_valid + : sourceValid_1 + ? io_source_1_writeDataAddr_valid + : sourceValid_2 & io_source_2_writeDataAddr_valid; assign io_port_writeDataAddr_bits = - source0Valid ? io_source_0_writeDataAddr_bits : io_source_1_writeDataAddr_bits; + sourceValid_0 + ? io_source_0_writeDataAddr_bits + : sourceValid_1 + ? io_source_1_writeDataAddr_bits + : sourceValid_2 ? io_source_2_writeDataAddr_bits : 32'h0; assign io_port_writeDataBits = - source0Valid ? io_source_0_writeDataBits : io_source_1_writeDataBits; + sourceValid_0 + ? io_source_0_writeDataBits + : sourceValid_1 + ? io_source_1_writeDataBits + : sourceValid_2 ? io_source_2_writeDataBits : 128'h0; assign io_port_writeDataStrb = - source0Valid ? io_source_0_writeDataStrb : io_source_1_writeDataStrb; + sourceValid_0 + ? io_source_0_writeDataStrb + : sourceValid_1 + ? io_source_1_writeDataStrb + : sourceValid_2 ? io_source_2_writeDataStrb : 16'h0; +endmodule + +module IBus2Axi( + input clock, + reset, + io_ibus_valid, + output io_ibus_ready, + input [31:0] io_ibus_addr, + output [127:0] io_ibus_rdata, + output io_ibus_fault_valid, + input io_axi_addr_ready, + output io_axi_addr_valid, + output [31:0] io_axi_addr_bits_addr, + input io_axi_data_valid, + input [127:0] io_axi_data_bits_data, + input [1:0] io_axi_data_bits_resp +); + + reg sraddrActive; + reg [31:0] saddrReg; + reg [127:0] sdata; + reg [1:0] sresp; + reg sdataValid; + wire [31:0] saddr = {io_ibus_addr[31:4], 4'h0}; + wire io_ibus_ready_0 = + (io_axi_data_valid & sraddrActive | sdataValid) & saddr == saddrReg; + wire io_axi_addr_valid_0 = + io_ibus_valid & ~sraddrActive & (~sdataValid | saddr != saddrReg); + wire _saddrReg_T = io_axi_addr_ready & io_axi_addr_valid_0; + always @(posedge clock or posedge reset) begin + if (reset) begin + sraddrActive <= 1'h0; + saddrReg <= 32'h0; + sdata <= 128'h0; + sresp <= 2'h0; + sdataValid <= 1'h0; + end + else begin + sraddrActive <= ~io_axi_data_valid & (_saddrReg_T | sraddrActive); + if (_saddrReg_T) + saddrReg <= saddr; + if (io_axi_data_valid) begin + sdata <= io_axi_data_bits_data; + sresp <= io_axi_data_bits_resp; + end + sdataValid <= + io_axi_data_valid + ? ~io_ibus_ready_0 + : ~(io_ibus_ready_0 & io_ibus_valid | _saddrReg_T) & sdataValid; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + sraddrActive = 1'h0; + saddrReg = 32'h0; + sdata = 128'h0; + sresp = 2'h0; + sdataValid = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_ibus_ready = io_ibus_ready_0; + assign io_ibus_rdata = sdata; + assign io_ibus_fault_valid = + io_ibus_ready_0 & (|(io_axi_data_valid ? io_axi_data_bits_resp : sresp)); + assign io_axi_addr_valid = io_axi_addr_valid_0; + assign io_axi_addr_bits_addr = saddr; endmodule module SRAM_2048x128( input clock, + reset, input [10:0] io_addr, input io_enable, io_write, @@ -14469,19 +20666,92 @@ module SRAM_2048x128( output [127:0] io_rdata ); - Sram_2048x128 sramModules_0 ( + wire [127:0] _sramModules_3_rdata; + wire [127:0] _sramModules_2_rdata; + wire [127:0] _sramModules_1_rdata; + wire [127:0] _sramModules_0_rdata; + reg [1:0] selectedSramRead; + wire [3:0][127:0] _GEN = + {{_sramModules_3_rdata}, + {_sramModules_2_rdata}, + {_sramModules_1_rdata}, + {_sramModules_0_rdata}}; + always @(posedge clock or posedge reset) begin + if (reset) + selectedSramRead <= 2'h0; + else + selectedSramRead <= io_addr[10:9]; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) + selectedSramRead = 2'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Sram #( + .GLOBAL_BASE_ADDR(65536), + .NUM_ENTRIES(512) + ) sramModules_0 ( .clock (clock), - .enable (io_enable), + .enable (io_addr[10:9] == 2'h0 & io_enable), .write (io_write), - .addr (io_addr), + .addr (io_addr[8:0]), + .wdata (io_wdata), + .wmask (io_wmask), + .rdata (_sramModules_0_rdata), + .rvalid (/* unused */) + ); + Sram #( + .GLOBAL_BASE_ADDR(73728), + .NUM_ENTRIES(512) + ) sramModules_1 ( + .clock (clock), + .enable (io_addr[10:9] == 2'h1 & io_enable), + .write (io_write), + .addr (io_addr[8:0]), + .wdata (io_wdata), + .wmask (io_wmask), + .rdata (_sramModules_1_rdata), + .rvalid (/* unused */) + ); + Sram #( + .GLOBAL_BASE_ADDR(81920), + .NUM_ENTRIES(512) + ) sramModules_2 ( + .clock (clock), + .enable (io_addr[10:9] == 2'h2 & io_enable), + .write (io_write), + .addr (io_addr[8:0]), + .wdata (io_wdata), + .wmask (io_wmask), + .rdata (_sramModules_2_rdata), + .rvalid (/* unused */) + ); + Sram #( + .GLOBAL_BASE_ADDR(90112), + .NUM_ENTRIES(512) + ) sramModules_3 ( + .clock (clock), + .enable ((&(io_addr[10:9])) & io_enable), + .write (io_write), + .addr (io_addr[8:0]), .wdata (io_wdata), .wmask (io_wmask), - .rdata (io_rdata) + .rdata (_sramModules_3_rdata), + .rvalid (/* unused */) ); + assign io_rdata = _GEN[selectedSramRead]; endmodule module TCM128_1( input clock, + reset, input [10:0] io_addr, input io_enable, io_write, @@ -14538,6 +20808,7 @@ module TCM128_1( wire [127:0] _sram_io_rdata; SRAM_2048x128 sram ( .clock (clock), + .reset (reset), .io_addr (io_addr), .io_enable (io_enable), .io_write (io_write), @@ -14670,15 +20941,7 @@ module SRAM_1( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - readIssued = _RANDOM[/*Zero width*/ 1'b0][0]; - `endif // RANDOMIZE_REG_INIT if (reset) readIssued = 1'h0; end // initial @@ -14707,10 +20970,9 @@ module SRAM_1( io_sram_readData_15} : 128'h0; assign io_sram_address = - io_fabric_writeDataAddr_valid - ? io_fabric_writeDataAddr_bits[14:4] - : io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[14:4] : 11'h0; - assign io_sram_enable = io_fabric_readDataAddr_valid | io_fabric_writeDataAddr_valid; + (io_fabric_writeDataAddr_valid ? io_fabric_writeDataAddr_bits[14:4] : 11'h0) + | (io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[14:4] : 11'h0); + assign io_sram_enable = io_fabric_writeDataAddr_valid | io_fabric_readDataAddr_valid; assign io_sram_isWrite = io_fabric_writeDataAddr_valid; assign io_sram_writeData_0 = io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h0; @@ -14804,12 +21066,11 @@ module FabricMux( wire sourceValid = io_source_readDataAddr_valid | io_source_writeDataAddr_valid; wire [31:0] addr = - io_source_readDataAddr_valid - ? io_source_readDataAddr_bits - : io_source_writeDataAddr_valid ? io_source_writeDataAddr_bits : 32'h0; + (io_source_readDataAddr_valid ? io_source_readDataAddr_bits : 32'h0) + | (io_source_writeDataAddr_valid ? io_source_writeDataAddr_bits : 32'h0); wire _selected_T_5 = sourceValid & addr < 32'h2000; wire _selected_T_11 = sourceValid & (|(addr[31:16])) & addr < 32'h18000; - wire _selected_T_18_valid = sourceValid & addr > 32'h2FFFF & addr < 32'h32000; + wire _selected_T_18_valid = sourceValid & addr > 32'h2FFFF & addr < 32'h31000; wire selected_valid = _selected_T_5 | _selected_T_11 | _selected_T_18_valid; wire [1:0] selected_bits = _selected_T_5 ? 2'h0 : _selected_T_11 ? 2'h1 : {_selected_T_18_valid, 1'h0}; @@ -14830,8 +21091,7 @@ module FabricMux( lastReadSelected_valid & lastReadSelected_bits == 2'h1; wire _io_source_readData_T_5 = lastReadSelected_valid & lastReadSelected_bits == 2'h2; - wire _lastReadSelected_T_3_valid = - _portSelected_T_7 & io_source_readDataAddr_valid; + wire _lastReadSelected_T_19 = _portSelected_T_7 & io_source_readDataAddr_valid; always @(posedge clock or posedge reset) begin if (reset) begin lastReadSelected_valid <= 1'h0; @@ -14840,27 +21100,16 @@ module FabricMux( else begin lastReadSelected_valid <= io_ports_0_readDataAddr_valid_0 | io_ports_1_readDataAddr_valid_0 - | _lastReadSelected_T_3_valid; + | _lastReadSelected_T_19; lastReadSelected_bits <= - io_ports_0_readDataAddr_valid_0 - ? 2'h0 - : io_ports_1_readDataAddr_valid_0 ? 2'h1 : {_lastReadSelected_T_3_valid, 1'h0}; + {1'h0, io_ports_1_readDataAddr_valid_0} | {_lastReadSelected_T_19, 1'h0}; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - lastReadSelected_valid = _RANDOM[/*Zero width*/ 1'b0][0]; - lastReadSelected_bits = _RANDOM[/*Zero width*/ 1'b0][2:1]; - `endif // RANDOMIZE_REG_INIT if (reset) begin lastReadSelected_valid = 1'h0; lastReadSelected_bits = 2'h0; @@ -14871,23 +21120,17 @@ module FabricMux( `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ assign io_source_readData_valid = - _io_source_readData_T_1 - ? io_ports_0_readData_valid - : _io_source_readData_T_3 - ? io_ports_1_readData_valid - : _io_source_readData_T_5 & io_ports_2_readData_valid; + _io_source_readData_T_1 & io_ports_0_readData_valid | _io_source_readData_T_3 + & io_ports_1_readData_valid | _io_source_readData_T_5 & io_ports_2_readData_valid; assign io_source_readData_bits = - _io_source_readData_T_1 - ? io_ports_0_readData_bits - : _io_source_readData_T_3 - ? io_ports_1_readData_bits - : _io_source_readData_T_5 ? io_ports_2_readData_bits : 128'h0; + (_io_source_readData_T_1 ? io_ports_0_readData_bits : 128'h0) + | (_io_source_readData_T_3 ? io_ports_1_readData_bits : 128'h0) + | (_io_source_readData_T_5 ? io_ports_2_readData_bits : 128'h0); assign io_source_writeResp = portSelected_0 | portSelected_1 | _portSelected_T_7 & io_ports_2_writeResp; assign io_fabricBusy = - selected_valid & _io_fabricBusy_T - ? io_periBusy_0 - : selected_valid & _io_fabricBusy_T_2 & io_periBusy_1; + selected_valid & _io_fabricBusy_T & io_periBusy_0 | selected_valid + & _io_fabricBusy_T_2 & io_periBusy_1; assign io_ports_0_readDataAddr_valid = io_ports_0_readDataAddr_valid_0; assign io_ports_0_readDataAddr_bits = portSelected_0 ? io_source_readDataAddr_bits : 32'h0; @@ -14913,7 +21156,7 @@ module FabricMux( assign io_ports_2_writeDataBits = _portSelected_T_7 ? io_source_writeDataBits : 128'h0; endmodule -module CoralNPURRArbiter( +module CoralNPURRArbiter_1( input clock, reset, output io_in_0_ready, @@ -14970,15 +21213,7 @@ module CoralNPURRArbiter( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - ctrl_validMask_grantMask_lastGrant = _RANDOM[/*Zero width*/ 1'b0][0]; - `endif // RANDOMIZE_REG_INIT if (reset) ctrl_validMask_grantMask_lastGrant = 1'h0; end // initial @@ -15005,7 +21240,7 @@ module CoralNPURRArbiter( assign io_chosen = io_chosen_choice; endmodule -// VCS coverage exclude_module +// VCS coverage exclude_file module ram_2x67( input R0_addr, R0_en, @@ -15019,23 +21254,9 @@ module ram_2x67( reg [66:0] Memory[0:1]; always @(posedge W0_clk) begin - if (W0_en & 1'h1) + if (W0_en) Memory[W0_addr] <= W0_data; end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ - reg [95:0] _RANDOM_MEM; - initial begin - `INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_MEM_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - for (logic [6:0] j = 7'h0; j < 7'h60; j += 7'h20) begin - _RANDOM_MEM[j +: 32] = `RANDOM; - end - Memory[i[0]] = _RANDOM_MEM[66:0]; - end - `endif // RANDOMIZE_MEM_INIT - end // initial - `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 67'bx; endmodule @@ -15069,26 +21290,26 @@ module Queue2_AxiAddress( ); wire [66:0] _ram_ext_R0_data; - reg wrap; - reg wrap_1; + reg enq_ptr_value; + reg deq_ptr_value; reg maybe_full; - wire ptr_match = wrap == wrap_1; + wire ptr_match = enq_ptr_value == deq_ptr_value; wire empty = ptr_match & ~maybe_full; wire full = ptr_match & maybe_full; wire do_enq = ~full & io_enq_valid; wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - wrap <= 1'h0; - wrap_1 <= 1'h0; + enq_ptr_value <= 1'h0; + deq_ptr_value <= 1'h0; maybe_full <= 1'h0; end else begin if (do_enq) - wrap <= wrap - 1'h1; + enq_ptr_value <= enq_ptr_value - 1'h1; if (do_deq) - wrap_1 <= wrap_1 - 1'h1; - if (~(do_enq == do_deq)) + deq_ptr_value <= deq_ptr_value - 1'h1; + if (do_enq != do_deq) maybe_full <= do_enq; end end // always @(posedge, posedge) @@ -15096,20 +21317,10 @@ module Queue2_AxiAddress( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - wrap = _RANDOM[/*Zero width*/ 1'b0][0]; - wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; - maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - wrap = 1'h0; - wrap_1 = 1'h0; + enq_ptr_value = 1'h0; + deq_ptr_value = 1'h0; maybe_full = 1'h0; end end // initial @@ -15118,11 +21329,11 @@ module Queue2_AxiAddress( `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ ram_2x67 ram_ext ( - .R0_addr (wrap_1), + .R0_addr (deq_ptr_value), .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), - .W0_addr (wrap), + .W0_addr (enq_ptr_value), .W0_en (do_enq), .W0_clk (clock), .W0_data @@ -15178,13 +21389,15 @@ module Queue1_RWAxiAddress( ); reg [67:0] ram; - reg full; - wire do_enq = ~full & io_enq_valid; + wire io_enq_ready_0; + reg maybe_full; + wire do_enq = io_enq_ready_0 & io_enq_valid; + assign io_enq_ready_0 = io_deq_ready | ~maybe_full; always @(posedge clock or posedge reset) begin if (reset) - full <= 1'h0; - else if (~(do_enq == (io_deq_ready & full))) - full <= do_enq; + maybe_full <= 1'h0; + else if (do_enq != (io_deq_ready & maybe_full)) + maybe_full <= do_enq; end // always @(posedge, posedge) always @(posedge clock) begin if (do_enq) @@ -15205,27 +21418,16 @@ module Queue1_RWAxiAddress( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; - end - full = _RANDOM[2'h0][0]; - ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2][4:0]}; - `endif // RANDOMIZE_REG_INIT if (reset) - full = 1'h0; + maybe_full = 1'h0; end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - assign io_enq_ready = ~full; - assign io_deq_valid = full; + assign io_enq_ready = io_enq_ready_0; + assign io_deq_valid = maybe_full; assign io_deq_bits_addr_addr = ram[67:36]; assign io_deq_bits_addr_id = ram[32:27]; assign io_deq_bits_addr_len = ram[26:19]; @@ -15234,41 +21436,27 @@ module Queue1_RWAxiAddress( assign io_deq_bits_write = ram[0]; endmodule -// VCS coverage exclude_module -module ram_2x145( - input R0_addr, - R0_en, +// VCS coverage exclude_file +module ram_3x145( + input [1:0] R0_addr, + input R0_en, R0_clk, output [144:0] R0_data, - input W0_addr, - W0_en, + input [1:0] W0_addr, + input W0_en, W0_clk, input [144:0] W0_data ); - reg [144:0] Memory[0:1]; + reg [144:0] Memory[0:2]; always @(posedge W0_clk) begin - if (W0_en & 1'h1) + if (W0_en) Memory[W0_addr] <= W0_data; end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ - reg [159:0] _RANDOM_MEM; - initial begin - `INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_MEM_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - for (logic [7:0] j = 8'h0; j < 8'hA0; j += 8'h20) begin - _RANDOM_MEM[j +: 32] = `RANDOM; - end - Memory[i[0]] = _RANDOM_MEM[144:0]; - end - `endif // RANDOMIZE_MEM_INIT - end // initial - `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 145'bx; endmodule -module Queue2_AxiWriteData( +module Queue3_AxiWriteData( input clock, reset, output io_enq_ready, @@ -15284,26 +21472,26 @@ module Queue2_AxiWriteData( ); wire [144:0] _ram_ext_R0_data; - reg wrap; - reg wrap_1; + reg [1:0] enq_ptr_value; + reg [1:0] deq_ptr_value; reg maybe_full; - wire ptr_match = wrap == wrap_1; + wire ptr_match = enq_ptr_value == deq_ptr_value; wire empty = ptr_match & ~maybe_full; wire full = ptr_match & maybe_full; wire do_enq = ~full & io_enq_valid; wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - wrap <= 1'h0; - wrap_1 <= 1'h0; + enq_ptr_value <= 2'h0; + deq_ptr_value <= 2'h0; maybe_full <= 1'h0; end else begin if (do_enq) - wrap <= wrap - 1'h1; + enq_ptr_value <= enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1; if (do_deq) - wrap_1 <= wrap_1 - 1'h1; - if (~(do_enq == do_deq)) + deq_ptr_value <= deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1; + if (do_enq != do_deq) maybe_full <= do_enq; end end // always @(posedge, posedge) @@ -15311,20 +21499,10 @@ module Queue2_AxiWriteData( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - wrap = _RANDOM[/*Zero width*/ 1'b0][0]; - wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; - maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - wrap = 1'h0; - wrap_1 = 1'h0; + enq_ptr_value = 2'h0; + deq_ptr_value = 2'h0; maybe_full = 1'h0; end end // initial @@ -15332,12 +21510,12 @@ module Queue2_AxiWriteData( `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - ram_2x145 ram_ext ( - .R0_addr (wrap_1), + ram_3x145 ram_ext ( + .R0_addr (deq_ptr_value), .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), - .W0_addr (wrap), + .W0_addr (enq_ptr_value), .W0_en (do_enq), .W0_clk (clock), .W0_data ({io_enq_bits_data, io_enq_bits_last, io_enq_bits_strb}) @@ -15349,7 +21527,7 @@ module Queue2_AxiWriteData( assign io_deq_bits_strb = _ram_ext_R0_data[15:0]; endmodule -// VCS coverage exclude_module +// VCS coverage exclude_file module ram_2x8( input R0_addr, R0_en, @@ -15363,21 +21541,9 @@ module ram_2x8( reg [7:0] Memory[0:1]; always @(posedge W0_clk) begin - if (W0_en & 1'h1) + if (W0_en) Memory[W0_addr] <= W0_data; end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ - reg [31:0] _RANDOM_MEM; - initial begin - `INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_MEM_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM_MEM = `RANDOM; - Memory[i[0]] = _RANDOM_MEM[7:0]; - end - `endif // RANDOMIZE_MEM_INIT - end // initial - `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; endmodule @@ -15395,26 +21561,26 @@ module Queue2_AxiWriteResponse( ); wire [7:0] _ram_ext_R0_data; - reg wrap; - reg wrap_1; + reg enq_ptr_value; + reg deq_ptr_value; reg maybe_full; - wire ptr_match = wrap == wrap_1; + wire ptr_match = enq_ptr_value == deq_ptr_value; wire empty = ptr_match & ~maybe_full; wire full = ptr_match & maybe_full; wire do_enq = ~full & io_enq_valid; wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - wrap <= 1'h0; - wrap_1 <= 1'h0; + enq_ptr_value <= 1'h0; + deq_ptr_value <= 1'h0; maybe_full <= 1'h0; end else begin if (do_enq) - wrap <= wrap - 1'h1; + enq_ptr_value <= enq_ptr_value - 1'h1; if (do_deq) - wrap_1 <= wrap_1 - 1'h1; - if (~(do_enq == do_deq)) + deq_ptr_value <= deq_ptr_value - 1'h1; + if (do_enq != do_deq) maybe_full <= do_enq; end end // always @(posedge, posedge) @@ -15422,20 +21588,10 @@ module Queue2_AxiWriteResponse( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - wrap = _RANDOM[/*Zero width*/ 1'b0][0]; - wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; - maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - wrap = 1'h0; - wrap_1 = 1'h0; + enq_ptr_value = 1'h0; + deq_ptr_value = 1'h0; maybe_full = 1'h0; end end // initial @@ -15444,11 +21600,11 @@ module Queue2_AxiWriteResponse( `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ ram_2x8 ram_ext ( - .R0_addr (wrap_1), + .R0_addr (deq_ptr_value), .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), - .W0_addr (wrap), + .W0_addr (enq_ptr_value), .W0_en (do_enq), .W0_clk (clock), .W0_data ({io_enq_bits_id, io_enq_bits_resp}) @@ -15459,45 +21615,30 @@ module Queue2_AxiWriteResponse( assign io_deq_bits_resp = _ram_ext_R0_data[1:0]; endmodule -// VCS coverage exclude_module -module ram_2x137( - input R0_addr, - R0_en, +// VCS coverage exclude_file +module ram_3x137( + input [1:0] R0_addr, + input R0_en, R0_clk, output [136:0] R0_data, - input W0_addr, - W0_en, + input [1:0] W0_addr, + input W0_en, W0_clk, input [136:0] W0_data ); - reg [136:0] Memory[0:1]; + reg [136:0] Memory[0:2]; always @(posedge W0_clk) begin - if (W0_en & 1'h1) + if (W0_en) Memory[W0_addr] <= W0_data; end // always @(posedge) - `ifdef ENABLE_INITIAL_MEM_ - reg [159:0] _RANDOM_MEM; - initial begin - `INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_MEM_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - for (logic [7:0] j = 8'h0; j < 8'hA0; j += 8'h20) begin - _RANDOM_MEM[j +: 32] = `RANDOM; - end - Memory[i[0]] = _RANDOM_MEM[136:0]; - end - `endif // RANDOMIZE_MEM_INIT - end // initial - `endif // ENABLE_INITIAL_MEM_ assign R0_data = R0_en ? Memory[R0_addr] : 137'bx; endmodule -module Queue2_AxiReadData( +module Queue3_AxiReadData( input clock, reset, - output io_enq_ready, - input io_enq_valid, + io_enq_valid, input [127:0] io_enq_bits_data, input [5:0] io_enq_bits_id, input [1:0] io_enq_bits_resp, @@ -15511,27 +21652,29 @@ module Queue2_AxiReadData( output [1:0] io_count ); + wire io_enq_ready; wire [136:0] _ram_ext_R0_data; - reg wrap; - reg wrap_1; + reg [1:0] enq_ptr_value; + reg [1:0] deq_ptr_value; reg maybe_full; - wire ptr_match = wrap == wrap_1; + wire ptr_match = enq_ptr_value == deq_ptr_value; wire empty = ptr_match & ~maybe_full; - wire full = ptr_match & maybe_full; - wire do_enq = ~full & io_enq_valid; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~(ptr_match & maybe_full); + wire [1:0] _ptr_diff_T = enq_ptr_value - deq_ptr_value; wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - wrap <= 1'h0; - wrap_1 <= 1'h0; + enq_ptr_value <= 2'h0; + deq_ptr_value <= 2'h0; maybe_full <= 1'h0; end else begin if (do_enq) - wrap <= wrap - 1'h1; + enq_ptr_value <= enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1; if (do_deq) - wrap_1 <= wrap_1 - 1'h1; - if (~(do_enq == do_deq)) + deq_ptr_value <= deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1; + if (do_enq != do_deq) maybe_full <= do_enq; end end // always @(posedge, posedge) @@ -15539,20 +21682,10 @@ module Queue2_AxiReadData( `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - wrap = _RANDOM[/*Zero width*/ 1'b0][0]; - wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; - maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - wrap = 1'h0; - wrap_1 = 1'h0; + enq_ptr_value = 2'h0; + deq_ptr_value = 2'h0; maybe_full = 1'h0; end end // initial @@ -15560,23 +21693,25 @@ module Queue2_AxiReadData( `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - ram_2x137 ram_ext ( - .R0_addr (wrap_1), + ram_3x137 ram_ext ( + .R0_addr (deq_ptr_value), .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), - .W0_addr (wrap), + .W0_addr (enq_ptr_value), .W0_en (do_enq), .W0_clk (clock), .W0_data ({io_enq_bits_data, io_enq_bits_id, io_enq_bits_resp, io_enq_bits_last}) ); - assign io_enq_ready = ~full; assign io_deq_valid = ~empty; assign io_deq_bits_data = _ram_ext_R0_data[136:9]; assign io_deq_bits_id = _ram_ext_R0_data[8:3]; assign io_deq_bits_resp = _ram_ext_R0_data[2:1]; assign io_deq_bits_last = _ram_ext_R0_data[0]; - assign io_count = {full, wrap - wrap_1}; + assign io_count = + ptr_match + ? {2{maybe_full}} + : deq_ptr_value > enq_ptr_value ? _ptr_diff_T - 2'h1 : _ptr_diff_T; endmodule module AxiSlave( @@ -15633,8 +21768,6 @@ module AxiSlave( io_periBusy ); - wire _readDataQueue_io_enq_ready; - wire _readDataQueue_io_deq_valid; wire [1:0] _readDataQueue_io_count; wire _io_axi_write_resp_q_io_enq_ready; wire _writeData_q_io_deq_valid; @@ -15691,78 +21824,71 @@ module AxiSlave( wire writeData_q_io_deq_ready = maybeWriteData & ~io_periBusy; wire writeResponse_valid = writeData_q_io_deq_ready & _writeData_q_io_deq_bits_last; - reg readIssued; + reg readIssued_valid; + reg [5:0] readIssued_bits_id; + reg readIssued_bits_last; reg [8:0] readsIssued; + wire [1:0] _maybeIssueRead_T = 2'h3 - _readDataQueue_io_count; + wire maybeIssueRead = readActive & _maybeIssueRead_T[1]; + wire issueRead = maybeIssueRead & ~io_periBusy; wire [8:0] _GEN = {1'h0, _axiAddrCmd_q_io_deq_bits_addr_len}; - wire maybeIssueRead = - readActive - & (|(4'h2 - - ({1'h0, {1'h0, _readDataQueue_io_count} + {2'h0, readIssued}} - - {3'h0, io_axi_read_data_ready & _readDataQueue_io_deq_valid}))) - & readsIssued <= _GEN; - wire readDataQueue_io_enq_bits_last = readsIssued == _GEN + 9'h1; + wire lastRead = readsIssued == _GEN; + wire axiAddrCmd_q_io_deq_ready = + writeActive ? writeResponse_valid : readActive & issueRead & lastRead; + wire [15:0] _wrapWindowSize_T_1 = + {7'h0, _GEN + 9'h1} << _axiAddrCmd_q_io_deq_bits_addr_size; wire [31:0] cmdAddrBase = - _axiAddrCmd_q_io_deq_bits_addr_addr - & {25'h1FFFFFF, - _axiAddrCmd_q_io_deq_bits_addr_size != 3'h7, - _axiAddrCmd_q_io_deq_bits_addr_size[2:1] != 2'h3, - _axiAddrCmd_q_io_deq_bits_addr_size < 3'h5, - ~(_axiAddrCmd_q_io_deq_bits_addr_size[2]), - _axiAddrCmd_q_io_deq_bits_addr_size < 3'h3, - _axiAddrCmd_q_io_deq_bits_addr_size < 3'h2, - _axiAddrCmd_q_io_deq_bits_addr_size == 3'h0}; - wire [31:0] _GEN_0 = {24'h0, 8'h1 << _axiAddrCmd_q_io_deq_bits_addr_size}; - wire [31:0] _addrNext_newAddr_T_1 = cmdAddr + _GEN_0; + _axiAddrCmd_q_io_deq_bits_addr_addr & ~({16'h0, _wrapWindowSize_T_1} - 32'h1); wire _addrNext_T = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h0; wire _addrNext_T_2 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h1; wire _addrNext_T_7 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h2; wire validBurst = _axiAddrCmd_q_io_deq_valid & (_addrNext_T | _addrNext_T_2 | _addrNext_T_7); - wire issueRead = maybeIssueRead & ~io_periBusy; - wire _cmdAddr_T = _axiAddrCmd_q_io_enq_ready & _addrArbiter_io_out_valid; + wire _addrNext_T_1 = validBurst & _addrNext_T; + wire _addrNext_T_3 = validBurst & _addrNext_T_2; + wire [7:0] _addrNext_newAddr_T = 8'h1 << _axiAddrCmd_q_io_deq_bits_addr_size; + wire _addrNext_T_8 = validBurst & _addrNext_T_7; + wire [32:0] addrNext_newAddr = {1'h0, cmdAddr} + {25'h0, _addrNext_newAddr_T}; always @(posedge clock or posedge reset) begin if (reset) begin cmdAddr <= 32'h0; - readIssued <= 1'h0; + readIssued_valid <= 1'h0; + readIssued_bits_id <= 6'h0; + readIssued_bits_last <= 1'h0; readsIssued <= 9'h0; end else begin - if (_cmdAddr_T) + if (_axiAddrCmd_q_io_enq_ready & _addrArbiter_io_out_valid) cmdAddr <= _addrArbiter_io_out_bits_addr; - else if (~(maybeWriteData & ~io_periBusy | maybeIssueRead & ~io_periBusy) - | validBurst & _addrNext_T) begin - end - else if (validBurst & _addrNext_T_2) - cmdAddr <= cmdAddr + _GEN_0; - else if (validBurst & _addrNext_T_7) + else if (maybeWriteData & ~io_periBusy | maybeIssueRead & ~io_periBusy) cmdAddr <= - _addrNext_newAddr_T_1 >= cmdAddrBase + 32'h10 - ? cmdAddrBase - : _addrNext_newAddr_T_1; - readIssued <= issueRead; - readsIssued <= _cmdAddr_T ? 9'h0 : readsIssued + {8'h0, issueRead}; + (_addrNext_T_1 ? cmdAddr : 32'h0) + | (_addrNext_T_3 ? cmdAddr + {24'h0, _addrNext_newAddr_T} : 32'h0) + | (_addrNext_T_8 + ? (addrNext_newAddr >= {17'h0, _wrapWindowSize_T_1} + {1'h0, cmdAddrBase} + ? cmdAddrBase + : addrNext_newAddr[31:0]) + : 32'h0) + | (_addrNext_T_1 | _addrNext_T_3 | _addrNext_T_8 ? 32'h0 : cmdAddr); + readIssued_valid <= issueRead; + readIssued_bits_id <= _axiAddrCmd_q_io_deq_bits_addr_id; + readIssued_bits_last <= lastRead; + readsIssued <= + axiAddrCmd_q_io_deq_ready & _axiAddrCmd_q_io_deq_valid + ? 9'h0 + : readsIssued + {8'h0, issueRead}; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:1]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin - _RANDOM[i[0]] = `RANDOM; - end - cmdAddr = _RANDOM[1'h0]; - readIssued = _RANDOM[1'h1][0]; - readsIssued = _RANDOM[1'h1][9:1]; - `endif // RANDOMIZE_REG_INIT if (reset) begin cmdAddr = 32'h0; - readIssued = 1'h0; + readIssued_valid = 1'h0; + readIssued_bits_id = 6'h0; + readIssued_bits_last = 1'h0; readsIssued = 9'h0; end end // initial @@ -15770,7 +21896,7 @@ module AxiSlave( `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - CoralNPURRArbiter addrArbiter ( + CoralNPURRArbiter_1 addrArbiter ( .clock (clock), .reset (reset), .io_in_0_ready (_addrArbiter_io_in_0_ready), @@ -15883,11 +22009,7 @@ module AxiSlave( .io_enq_bits_addr_qos (_addrArbiter_io_out_bits_qos), .io_enq_bits_addr_region (_addrArbiter_io_out_bits_region), .io_enq_bits_write (_addrArbiter_io_chosen), - .io_deq_ready - (writeActive - ? writeResponse_valid - : readActive & _readDataQueue_io_enq_ready & readIssued - & readDataQueue_io_enq_bits_last), + .io_deq_ready (axiAddrCmd_q_io_deq_ready), .io_deq_valid (_axiAddrCmd_q_io_deq_valid), .io_deq_bits_addr_addr (_axiAddrCmd_q_io_deq_bits_addr_addr), .io_deq_bits_addr_id (_axiAddrCmd_q_io_deq_bits_addr_id), @@ -15896,7 +22018,7 @@ module AxiSlave( .io_deq_bits_addr_burst (_axiAddrCmd_q_io_deq_bits_addr_burst), .io_deq_bits_write (_axiAddrCmd_q_io_deq_bits_write) ); - Queue2_AxiWriteData writeData_q ( + Queue3_AxiWriteData writeData_q ( .clock (clock), .reset (reset), .io_enq_ready (io_axi_write_data_ready), @@ -15922,603 +22044,134 @@ module AxiSlave( .io_deq_bits_id (io_axi_write_resp_bits_id), .io_deq_bits_resp (io_axi_write_resp_bits_resp) ); - Queue2_AxiReadData readDataQueue ( + Queue3_AxiReadData readDataQueue ( .clock (clock), .reset (reset), - .io_enq_ready (_readDataQueue_io_enq_ready), - .io_enq_valid (readIssued), + .io_enq_valid (readIssued_valid), .io_enq_bits_data (io_fabric_readData_bits), - .io_enq_bits_id (_axiAddrCmd_q_io_deq_bits_addr_id), + .io_enq_bits_id (readIssued_bits_id), .io_enq_bits_resp ({~io_fabric_readData_valid, 1'h0}), - .io_enq_bits_last (readDataQueue_io_enq_bits_last), + .io_enq_bits_last (readIssued_bits_last), .io_deq_ready (io_axi_read_data_ready), - .io_deq_valid (_readDataQueue_io_deq_valid), + .io_deq_valid (io_axi_read_data_valid), .io_deq_bits_data (io_axi_read_data_bits_data), .io_deq_bits_id (io_axi_read_data_bits_id), .io_deq_bits_resp (io_axi_read_data_bits_resp), .io_deq_bits_last (io_axi_read_data_bits_last), .io_count (_readDataQueue_io_count) ); - assign io_axi_read_data_valid = _readDataQueue_io_deq_valid; assign io_fabric_readDataAddr_valid = maybeIssueRead; assign io_fabric_readDataAddr_bits = cmdAddr; assign io_fabric_writeDataAddr_valid = maybeWriteData; assign io_fabric_writeDataAddr_bits = cmdAddr; endmodule -module Slice_2( - input clock, - reset, - output io_in_ready, - input io_in_valid, - input [31:0] io_in_bits_addr, - input [2:0] io_in_bits_prot, - input [5:0] io_in_bits_id, - input [7:0] io_in_bits_len, - input [2:0] io_in_bits_size, - input [1:0] io_in_bits_burst, - input io_in_bits_lock, - input [3:0] io_in_bits_cache, - io_in_bits_qos, - io_in_bits_region, - input io_out_ready, - output io_out_valid, - output [31:0] io_out_bits_addr, - output [2:0] io_out_bits_prot, - output [5:0] io_out_bits_id, - output [7:0] io_out_bits_len, - output [2:0] io_out_bits_size, - output [1:0] io_out_bits_burst, - output io_out_bits_lock, - output [3:0] io_out_bits_cache, - io_out_bits_qos, - io_out_bits_region -); - - reg ipos; - reg opos; - reg [31:0] mem_0_addr; - reg [2:0] mem_0_prot; - reg [5:0] mem_0_id; - reg [7:0] mem_0_len; - reg [2:0] mem_0_size; - reg [1:0] mem_0_burst; - reg mem_0_lock; - reg [3:0] mem_0_cache; - reg [3:0] mem_0_qos; - reg [3:0] mem_0_region; - wire io_in_ready_0 = ipos == opos | io_out_ready; - wire io_out_valid_0 = ipos != opos; - always @(posedge clock or posedge reset) begin - if (reset) begin - ipos <= 1'h0; - opos <= 1'h0; - mem_0_addr <= 32'h0; - mem_0_prot <= 3'h0; - mem_0_id <= 6'h0; - mem_0_len <= 8'h0; - mem_0_size <= 3'h0; - mem_0_burst <= 2'h0; - mem_0_lock <= 1'h0; - mem_0_cache <= 4'h0; - mem_0_qos <= 4'h0; - mem_0_region <= 4'h0; - end - else begin - if (io_in_valid & io_in_ready_0) begin - ipos <= ipos - 1'h1; - mem_0_addr <= io_in_bits_addr; - mem_0_prot <= io_in_bits_prot; - mem_0_id <= io_in_bits_id; - mem_0_len <= io_in_bits_len; - mem_0_size <= io_in_bits_size; - mem_0_burst <= io_in_bits_burst; - mem_0_lock <= io_in_bits_lock; - mem_0_cache <= io_in_bits_cache; - mem_0_qos <= io_in_bits_qos; - mem_0_region <= io_in_bits_region; - end - if (io_out_valid_0 & io_out_ready) - opos <= opos - 1'h1; - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ - `ifdef FIRRTL_BEFORE_INITIAL - `FIRRTL_BEFORE_INITIAL - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:2]; - initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin - _RANDOM[i] = `RANDOM; - end - ipos = _RANDOM[2'h0][0]; - opos = _RANDOM[2'h0][1]; - mem_0_addr = {_RANDOM[2'h0][31:3], _RANDOM[2'h1][2:0]}; - mem_0_prot = _RANDOM[2'h1][5:3]; - mem_0_id = _RANDOM[2'h1][11:6]; - mem_0_len = _RANDOM[2'h1][19:12]; - mem_0_size = _RANDOM[2'h1][22:20]; - mem_0_burst = _RANDOM[2'h1][24:23]; - mem_0_lock = _RANDOM[2'h1][25]; - mem_0_cache = _RANDOM[2'h1][29:26]; - mem_0_qos = {_RANDOM[2'h1][31:30], _RANDOM[2'h2][1:0]}; - mem_0_region = _RANDOM[2'h2][5:2]; - `endif // RANDOMIZE_REG_INIT - if (reset) begin - ipos = 1'h0; - opos = 1'h0; - mem_0_addr = 32'h0; - mem_0_prot = 3'h0; - mem_0_id = 6'h0; - mem_0_len = 8'h0; - mem_0_size = 3'h0; - mem_0_burst = 2'h0; - mem_0_lock = 1'h0; - mem_0_cache = 4'h0; - mem_0_qos = 4'h0; - mem_0_region = 4'h0; - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_in_ready = io_in_ready_0; - assign io_out_valid = io_out_valid_0; - assign io_out_bits_addr = mem_0_addr; - assign io_out_bits_prot = mem_0_prot; - assign io_out_bits_id = mem_0_id; - assign io_out_bits_len = mem_0_len; - assign io_out_bits_size = mem_0_size; - assign io_out_bits_burst = mem_0_burst; - assign io_out_bits_lock = mem_0_lock; - assign io_out_bits_cache = mem_0_cache; - assign io_out_bits_qos = mem_0_qos; - assign io_out_bits_region = mem_0_region; -endmodule - -module FifoX_1( - input clock, - reset, - io_in_valid, - input [31:0] io_in_bits_0_bits_addr, - input [7:0] io_in_bits_0_bits_len, - input [2:0] io_in_bits_0_bits_size, - input io_in_bits_1_valid, - input [31:0] io_in_bits_1_bits_addr, - input [2:0] io_in_bits_1_bits_size, - input io_out_ready, - output io_out_valid, - output [31:0] io_out_bits_addr, - output [2:0] io_out_bits_prot, - output [5:0] io_out_bits_id, - output [7:0] io_out_bits_len, - output [2:0] io_out_bits_size, - output [1:0] io_out_bits_burst, - output io_out_bits_lock, - output [3:0] io_out_bits_cache, - io_out_bits_qos, - io_out_bits_region, - output [1:0] io_count -); - - wire io_in_ready; - wire _mslice_io_in_ready; - wire _mslice_io_out_valid; - reg [31:0] mem_0_addr; - reg [2:0] mem_0_prot; - reg [7:0] mem_0_len; - reg [2:0] mem_0_size; - reg [1:0] mem_0_burst; - reg [31:0] mem_1_addr; - reg [2:0] mem_1_prot; - reg [7:0] mem_1_len; - reg [2:0] mem_1_size; - reg [1:0] mem_1_burst; - reg inxpos_0; - reg inxpos_1; - reg [1:0] outpos; - reg [1:0] mcount; - wire ivalid = io_in_valid & io_in_ready; - wire [1:0] _GEN = {1'h0, io_in_bits_1_valid}; - wire [1:0] icount = _GEN + 2'h1; - wire mslice_io_in_valid = (|mcount) ? io_out_ready : ivalid; - wire [3:0][31:0] _GEN_0 = {{mem_0_addr}, {32'h0}, {mem_1_addr}, {mem_0_addr}}; - wire [3:0][2:0] _GEN_1 = {{mem_0_prot}, {3'h0}, {mem_1_prot}, {mem_0_prot}}; - wire [3:0][7:0] _GEN_2 = {{mem_0_len}, {8'h0}, {mem_1_len}, {mem_0_len}}; - wire [3:0][2:0] _GEN_3 = {{mem_0_size}, {3'h0}, {mem_1_size}, {mem_0_size}}; - wire [3:0][1:0] _GEN_4 = {{mem_0_burst}, {2'h0}, {mem_1_burst}, {mem_0_burst}}; - assign io_in_ready = mcount <= 2'h2 - icount; - wire [2:0] outpos_c = {1'h0, outpos} + 3'h1; - wire dec = mslice_io_in_valid & _mslice_io_in_ready; - wire _inxvalid_T_7 = _GEN + 2'h1 == 2'h1 & io_in_bits_1_valid; - wire _inxvalid_T_20 = _GEN + 2'h1 == 2'h2 & io_in_bits_1_valid; - always @(posedge clock or posedge reset) begin - if (reset) begin - mem_0_addr <= 32'h0; - mem_0_prot <= 3'h0; - mem_0_len <= 8'h0; - mem_0_size <= 3'h0; - mem_0_burst <= 2'h0; - mem_1_addr <= 32'h0; - mem_1_prot <= 3'h0; - mem_1_len <= 8'h0; - mem_1_size <= 3'h0; - mem_1_burst <= 2'h0; - inxpos_0 <= 1'h0; - inxpos_1 <= 1'h1; - outpos <= 2'h0; - mcount <= 2'h0; - end - else begin - if (ivalid - & (|({1'h0, ~inxpos_0} - + {1'h0, ~inxpos_0 & _inxvalid_T_7 | ~inxpos_1 & _inxvalid_T_20}))) begin - mem_0_addr <= inxpos_0 ? io_in_bits_1_bits_addr : io_in_bits_0_bits_addr; - mem_0_prot <= 3'h2; - mem_0_len <= inxpos_0 ? 8'h0 : io_in_bits_0_bits_len; - mem_0_size <= inxpos_0 ? io_in_bits_1_bits_size : io_in_bits_0_bits_size; - mem_0_burst <= 2'h1; - end - if (ivalid - & (|({1'h0, inxpos_0} - + {1'h0, inxpos_0 & _inxvalid_T_7 | inxpos_1 & _inxvalid_T_20}))) begin - mem_1_addr <= inxpos_0 ? io_in_bits_0_bits_addr : io_in_bits_1_bits_addr; - mem_1_prot <= 3'h2; - mem_1_len <= inxpos_0 ? io_in_bits_0_bits_len : 8'h0; - mem_1_size <= inxpos_0 ? io_in_bits_0_bits_size : io_in_bits_1_bits_size; - mem_1_burst <= 2'h1; - end - if (ivalid) begin - inxpos_0 <= inxpos_0 + icount[0]; - inxpos_1 <= inxpos_1 + icount[0]; - end - if (dec) - outpos <= outpos_c < 3'h2 ? outpos_c[1:0] : outpos - 2'h1; - if (ivalid | dec) - mcount <= mcount + (ivalid ? icount : 2'h0) - {1'h0, dec}; - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ - `ifdef FIRRTL_BEFORE_INITIAL - `FIRRTL_BEFORE_INITIAL - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:6]; - initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - mem_0_addr = _RANDOM[3'h0]; - mem_0_prot = _RANDOM[3'h1][2:0]; - mem_0_len = _RANDOM[3'h1][16:9]; - mem_0_size = _RANDOM[3'h1][19:17]; - mem_0_burst = _RANDOM[3'h1][21:20]; - mem_1_addr = {_RANDOM[3'h2][31:3], _RANDOM[3'h3][2:0]}; - mem_1_prot = _RANDOM[3'h3][5:3]; - mem_1_len = _RANDOM[3'h3][19:12]; - mem_1_size = _RANDOM[3'h3][22:20]; - mem_1_burst = _RANDOM[3'h3][24:23]; - inxpos_0 = _RANDOM[3'h6][9]; - inxpos_1 = _RANDOM[3'h6][10]; - outpos = _RANDOM[3'h6][12:11]; - mcount = _RANDOM[3'h6][14:13]; - `endif // RANDOMIZE_REG_INIT - if (reset) begin - mem_0_addr = 32'h0; - mem_0_prot = 3'h0; - mem_0_len = 8'h0; - mem_0_size = 3'h0; - mem_0_burst = 2'h0; - mem_1_addr = 32'h0; - mem_1_prot = 3'h0; - mem_1_len = 8'h0; - mem_1_size = 3'h0; - mem_1_burst = 2'h0; - inxpos_0 = 1'h0; - inxpos_1 = 1'h1; - outpos = 2'h0; - mcount = 2'h0; - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - Slice_2 mslice ( - .clock (clock), - .reset (reset), - .io_in_ready (_mslice_io_in_ready), - .io_in_valid (mslice_io_in_valid), - .io_in_bits_addr ((|mcount) ? _GEN_0[outpos] : io_in_bits_0_bits_addr), - .io_in_bits_prot ((|mcount) ? _GEN_1[outpos] : 3'h2), - .io_in_bits_id (6'h0), - .io_in_bits_len ((|mcount) ? _GEN_2[outpos] : io_in_bits_0_bits_len), - .io_in_bits_size ((|mcount) ? _GEN_3[outpos] : io_in_bits_0_bits_size), - .io_in_bits_burst ((|mcount) ? _GEN_4[outpos] : 2'h1), - .io_in_bits_lock (1'h0), - .io_in_bits_cache (4'h0), - .io_in_bits_qos (4'h0), - .io_in_bits_region (4'h0), - .io_out_ready (io_out_ready), - .io_out_valid (_mslice_io_out_valid), - .io_out_bits_addr (io_out_bits_addr), - .io_out_bits_prot (io_out_bits_prot), - .io_out_bits_id (io_out_bits_id), - .io_out_bits_len (io_out_bits_len), - .io_out_bits_size (io_out_bits_size), - .io_out_bits_burst (io_out_bits_burst), - .io_out_bits_lock (io_out_bits_lock), - .io_out_bits_cache (io_out_bits_cache), - .io_out_bits_qos (io_out_bits_qos), - .io_out_bits_region (io_out_bits_region) - ); - assign io_out_valid = _mslice_io_out_valid; - assign io_count = mcount + {1'h0, _mslice_io_out_valid}; -endmodule - -module Slice_4( - input clock, - reset, - output io_in_ready, - input io_in_valid, - input [127:0] io_in_bits_data, - input io_in_bits_last, - input [15:0] io_in_bits_strb, - input io_out_ready, - output io_out_valid, - output [127:0] io_out_bits_data, - output io_out_bits_last, - output [15:0] io_out_bits_strb +// VCS coverage exclude_file +module ram_2x145( + input R0_addr, + R0_en, + R0_clk, + output [144:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [144:0] W0_data ); - reg ipos; - reg opos; - reg [127:0] mem_0_data; - reg mem_0_last; - reg [15:0] mem_0_strb; - wire io_in_ready_0 = ipos == opos | io_out_ready; - wire io_out_valid_0 = ipos != opos; - always @(posedge clock or posedge reset) begin - if (reset) begin - ipos <= 1'h0; - opos <= 1'h0; - mem_0_data <= 128'h0; - mem_0_last <= 1'h0; - mem_0_strb <= 16'h0; - end - else begin - if (io_in_valid & io_in_ready_0) begin - ipos <= ipos - 1'h1; - mem_0_data <= io_in_bits_data; - mem_0_last <= io_in_bits_last; - mem_0_strb <= io_in_bits_strb; - end - if (io_out_valid_0 & io_out_ready) - opos <= opos - 1'h1; - end - end // always @(posedge, posedge) - `ifdef ENABLE_INITIAL_REG_ - `ifdef FIRRTL_BEFORE_INITIAL - `FIRRTL_BEFORE_INITIAL - `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:4]; - initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - ipos = _RANDOM[3'h0][0]; - opos = _RANDOM[3'h0][1]; - mem_0_data = - {_RANDOM[3'h0][31:3], - _RANDOM[3'h1], - _RANDOM[3'h2], - _RANDOM[3'h3], - _RANDOM[3'h4][2:0]}; - mem_0_last = _RANDOM[3'h4][3]; - mem_0_strb = _RANDOM[3'h4][19:4]; - `endif // RANDOMIZE_REG_INIT - if (reset) begin - ipos = 1'h0; - opos = 1'h0; - mem_0_data = 128'h0; - mem_0_last = 1'h0; - mem_0_strb = 16'h0; - end - end // initial - `ifdef FIRRTL_AFTER_INITIAL - `FIRRTL_AFTER_INITIAL - `endif // FIRRTL_AFTER_INITIAL - `endif // ENABLE_INITIAL_REG_ - assign io_in_ready = io_in_ready_0; - assign io_out_valid = io_out_valid_0; - assign io_out_bits_data = mem_0_data; - assign io_out_bits_last = mem_0_last; - assign io_out_bits_strb = mem_0_strb; + reg [144:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 145'bx; endmodule -module FifoX_3( +module Queue2_AxiWriteData( input clock, reset, - io_in_valid, - input [127:0] io_in_bits_0_bits_data, - input [15:0] io_in_bits_0_bits_strb, - input io_in_bits_1_valid, - input [127:0] io_in_bits_1_bits_data, - input [15:0] io_in_bits_1_bits_strb, - input io_out_ready, - output io_out_valid, - output [127:0] io_out_bits_data, - output io_out_bits_last, - output [15:0] io_out_bits_strb, - output [1:0] io_count + output io_enq_ready, + input io_enq_valid, + input [127:0] io_enq_bits_data, + input io_enq_bits_last, + input [15:0] io_enq_bits_strb, + input io_deq_ready, + output io_deq_valid, + output [127:0] io_deq_bits_data, + output io_deq_bits_last, + output [15:0] io_deq_bits_strb ); - wire io_in_ready; - wire _mslice_io_in_ready; - wire _mslice_io_out_valid; - reg [127:0] mem_0_data; - reg mem_0_last; - reg [15:0] mem_0_strb; - reg [127:0] mem_1_data; - reg mem_1_last; - reg [15:0] mem_1_strb; - reg inxpos_0; - reg inxpos_1; - reg [1:0] outpos; - reg [1:0] mcount; - wire ivalid = io_in_valid & io_in_ready; - wire [1:0] _GEN = {1'h0, io_in_bits_1_valid}; - wire [1:0] icount = _GEN + 2'h1; - wire mslice_io_in_valid = (|mcount) ? io_out_ready : ivalid; - wire [3:0][127:0] _GEN_0 = {{mem_0_data}, {128'h0}, {mem_1_data}, {mem_0_data}}; - wire [3:0] _GEN_1 = {{mem_0_last}, {1'h0}, {mem_1_last}, {mem_0_last}}; - wire [3:0][15:0] _GEN_2 = {{mem_0_strb}, {16'h0}, {mem_1_strb}, {mem_0_strb}}; - assign io_in_ready = mcount <= 2'h2 - icount; - wire [2:0] outpos_c = {1'h0, outpos} + 3'h1; - wire dec = mslice_io_in_valid & _mslice_io_in_ready; - wire _inxvalid_T_7 = _GEN + 2'h1 == 2'h1 & io_in_bits_1_valid; - wire _inxvalid_T_20 = _GEN + 2'h1 == 2'h2 & io_in_bits_1_valid; - wire _GEN_3 = - ivalid - & (|({1'h0, ~inxpos_0} - + {1'h0, ~inxpos_0 & _inxvalid_T_7 | ~inxpos_1 & _inxvalid_T_20})); - wire _GEN_4 = - ivalid - & (|({1'h0, inxpos_0} - + {1'h0, inxpos_0 & _inxvalid_T_7 | inxpos_1 & _inxvalid_T_20})); + wire [144:0] _ram_ext_R0_data; + reg enq_ptr_value; + reg deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; always @(posedge clock or posedge reset) begin if (reset) begin - mem_0_data <= 128'h0; - mem_0_last <= 1'h0; - mem_0_strb <= 16'h0; - mem_1_data <= 128'h0; - mem_1_last <= 1'h0; - mem_1_strb <= 16'h0; - inxpos_0 <= 1'h0; - inxpos_1 <= 1'h1; - outpos <= 2'h0; - mcount <= 2'h0; + enq_ptr_value <= 1'h0; + deq_ptr_value <= 1'h0; + maybe_full <= 1'h0; end else begin - if (_GEN_3) begin - mem_0_data <= inxpos_0 ? io_in_bits_1_bits_data : io_in_bits_0_bits_data; - mem_0_strb <= inxpos_0 ? io_in_bits_1_bits_strb : io_in_bits_0_bits_strb; - end - mem_0_last <= _GEN_3 | mem_0_last; - if (_GEN_4) begin - mem_1_data <= inxpos_0 ? io_in_bits_0_bits_data : io_in_bits_1_bits_data; - mem_1_strb <= inxpos_0 ? io_in_bits_0_bits_strb : io_in_bits_1_bits_strb; - end - mem_1_last <= _GEN_4 | mem_1_last; - if (ivalid) begin - inxpos_0 <= inxpos_0 + icount[0]; - inxpos_1 <= inxpos_1 + icount[0]; - end - if (dec) - outpos <= outpos_c < 3'h2 ? outpos_c[1:0] : outpos - 2'h1; - if (ivalid | dec) - mcount <= mcount + (ivalid ? icount : 2'h0) - {1'h0, dec}; + if (do_enq) + enq_ptr_value <= enq_ptr_value - 1'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value - 1'h1; + if (do_enq != do_deq) + maybe_full <= do_enq; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:13]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin - _RANDOM[i] = `RANDOM; - end - mem_0_data = {_RANDOM[4'h0], _RANDOM[4'h1], _RANDOM[4'h2], _RANDOM[4'h3]}; - mem_0_last = _RANDOM[4'h4][0]; - mem_0_strb = _RANDOM[4'h4][16:1]; - mem_1_data = - {_RANDOM[4'h4][31:17], - _RANDOM[4'h5], - _RANDOM[4'h6], - _RANDOM[4'h7], - _RANDOM[4'h8][16:0]}; - mem_1_last = _RANDOM[4'h8][17]; - mem_1_strb = {_RANDOM[4'h8][31:18], _RANDOM[4'h9][1:0]}; - inxpos_0 = _RANDOM[4'hD][19]; - inxpos_1 = _RANDOM[4'hD][20]; - outpos = _RANDOM[4'hD][22:21]; - mcount = _RANDOM[4'hD][24:23]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - mem_0_data = 128'h0; - mem_0_last = 1'h0; - mem_0_strb = 16'h0; - mem_1_data = 128'h0; - mem_1_last = 1'h0; - mem_1_strb = 16'h0; - inxpos_0 = 1'h0; - inxpos_1 = 1'h1; - outpos = 2'h0; - mcount = 2'h0; + enq_ptr_value = 1'h0; + deq_ptr_value = 1'h0; + maybe_full = 1'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - Slice_4 mslice ( - .clock (clock), - .reset (reset), - .io_in_ready (_mslice_io_in_ready), - .io_in_valid (mslice_io_in_valid), - .io_in_bits_data ((|mcount) ? _GEN_0[outpos] : io_in_bits_0_bits_data), - .io_in_bits_last (~(|mcount) | _GEN_1[outpos]), - .io_in_bits_strb ((|mcount) ? _GEN_2[outpos] : io_in_bits_0_bits_strb), - .io_out_ready (io_out_ready), - .io_out_valid (_mslice_io_out_valid), - .io_out_bits_data (io_out_bits_data), - .io_out_bits_last (io_out_bits_last), - .io_out_bits_strb (io_out_bits_strb) + ram_2x145 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_data, io_enq_bits_last, io_enq_bits_strb}) ); - assign io_out_valid = _mslice_io_out_valid; - assign io_count = mcount + {1'h0, _mslice_io_out_valid}; + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[144:17]; + assign io_deq_bits_last = _ram_ext_R0_data[16]; + assign io_deq_bits_strb = _ram_ext_R0_data[15:0]; endmodule -module DBus2AxiV1( +module DBus2AxiV2( input clock, reset, io_dbus_valid, output io_dbus_ready, input io_dbus_write, - input [31:0] io_dbus_pc, - io_dbus_addr, + input [31:0] io_dbus_addr, input [4:0] io_dbus_size, input [127:0] io_dbus_wdata, + input [15:0] io_dbus_wmask, output [127:0] io_dbus_rdata, input io_axi_write_addr_ready, output io_axi_write_addr_valid, output [31:0] io_axi_write_addr_bits_addr, - output [2:0] io_axi_write_addr_bits_prot, - output [5:0] io_axi_write_addr_bits_id, - output [7:0] io_axi_write_addr_bits_len, output [2:0] io_axi_write_addr_bits_size, - output [1:0] io_axi_write_addr_bits_burst, - output io_axi_write_addr_bits_lock, - output [3:0] io_axi_write_addr_bits_cache, - io_axi_write_addr_bits_qos, - io_axi_write_addr_bits_region, input io_axi_write_data_ready, output io_axi_write_data_valid, output [127:0] io_axi_write_data_bits_data, @@ -16526,469 +22179,219 @@ module DBus2AxiV1( output [15:0] io_axi_write_data_bits_strb, output io_axi_write_resp_ready, input io_axi_write_resp_valid, - input [5:0] io_axi_write_resp_bits_id, input [1:0] io_axi_write_resp_bits_resp, input io_axi_read_addr_ready, output io_axi_read_addr_valid, output [31:0] io_axi_read_addr_bits_addr, - output [2:0] io_axi_read_addr_bits_prot, - output [5:0] io_axi_read_addr_bits_id, - output [7:0] io_axi_read_addr_bits_len, output [2:0] io_axi_read_addr_bits_size, - output [1:0] io_axi_read_addr_bits_burst, - output io_axi_read_addr_bits_lock, - output [3:0] io_axi_read_addr_bits_cache, - io_axi_read_addr_bits_qos, - io_axi_read_addr_bits_region, output io_axi_read_data_ready, input io_axi_read_data_valid, input [127:0] io_axi_read_data_bits_data, - input [5:0] io_axi_read_data_bits_id, input [1:0] io_axi_read_data_bits_resp, - input io_axi_read_data_bits_last, - output io_fault_valid, - io_fault_bits_write, - output [31:0] io_fault_bits_addr, - io_fault_bits_epc + output io_fault_valid ); - wire _writeDataQ_io_out_valid; - wire [1:0] _writeDataQ_io_count; - wire _writeAddrQ_io_out_valid; - wire [1:0] _writeAddrQ_io_count; - wire _readAddrQ_io_out_valid; - wire [1:0] _readAddrQ_io_count; - reg txnActive; - wire newTxn = io_dbus_valid & ~txnActive; - reg [127:0] sdata; - wire [4:0] _dbusAddrAligned_T = io_dbus_size - 5'h1; - wire [4:0] misalignment = io_dbus_addr[4:0] & _dbusAddrAligned_T; - wire [31:0] _crossLineBoundary_T_4 = - {26'h0, {2'h0, io_dbus_addr[3:0]} + {1'h0, io_dbus_size}}; - wire crossLineBoundary = _crossLineBoundary_T_4 > 32'h10; - wire [2:0] belowLineBoundary = 3'h0 - io_dbus_addr[2:0]; - wire [1:0] txnCount = (|misalignment) | crossLineBoundary ? 2'h2 : 2'h1; - wire [4:0] txnSizes_0 = - crossLineBoundary - ? {2'h0, belowLineBoundary} - : (|misalignment) ? io_dbus_size - misalignment : io_dbus_size; - wire [4:0] txnSizes_1 = - crossLineBoundary - ? io_dbus_size - {2'h0, belowLineBoundary} - : (|misalignment) ? misalignment : 5'h0; - wire [31:0] writeAddrQ_io_in_bits_0_bits_addr = - io_dbus_addr - {27'h0, io_dbus_addr[4:0] & _dbusAddrAligned_T}; - reg [1:0] transactionsCompleted; - wire [1:0] _io_dbus_ready_T_11 = transactionsCompleted + 2'h1; - wire _mask0_T_40 = txnSizes_0 > 5'h2; - wire _mask0_T_42 = txnSizes_0 > 5'h4; - wire _mask0_T_43 = txnSizes_0 > 5'h5; - wire _mask0_T_44 = txnSizes_0 > 5'h6; - wire _mask0_T_46 = txnSizes_0 > 5'h8; - wire _mask0_T_47 = txnSizes_0 > 5'h9; - wire _mask0_T_48 = txnSizes_0 > 5'hA; - wire _mask0_T_49 = txnSizes_0 > 5'hB; - wire _mask0_T_50 = txnSizes_0 > 5'hC; - wire _mask0_T_51 = txnSizes_0 > 5'hD; - wire _mask0_T_52 = txnSizes_0 > 5'hE; - wire _mask1_T_42 = txnSizes_1 > 5'h2; - wire _mask1_T_44 = txnSizes_1 > 5'h4; - wire _mask1_T_45 = txnSizes_1 > 5'h5; - wire _mask1_T_46 = txnSizes_1 > 5'h6; - wire _mask1_T_48 = txnSizes_1 > 5'h8; - wire _mask1_T_49 = txnSizes_1 > 5'h9; - wire _mask1_T_50 = txnSizes_1 > 5'hA; - wire _mask1_T_51 = txnSizes_1 > 5'hB; - wire _mask1_T_52 = txnSizes_1 > 5'hC; - wire _mask1_T_53 = txnSizes_1 > 5'hD; - wire _mask1_T_54 = txnSizes_1 > 5'hE; - wire writeDataQ_io_in_valid = newTxn & io_dbus_write; - wire [15:0] _mask0_T_63 = - io_dbus_addr[0] - ? {_mask0_T_52, - _mask0_T_51, - _mask0_T_50, - _mask0_T_49, - _mask0_T_48, - _mask0_T_47, - _mask0_T_46, - |(txnSizes_0[4:3]), - _mask0_T_44, - _mask0_T_43, - _mask0_T_42, - |(txnSizes_0[4:2]), - _mask0_T_40, - |(txnSizes_0[4:1]), - |txnSizes_0, - txnSizes_0[4]} - : {txnSizes_0[4], - _mask0_T_52, - _mask0_T_51, - _mask0_T_50, - _mask0_T_49, - _mask0_T_48, - _mask0_T_47, - _mask0_T_46, - |(txnSizes_0[4:3]), - _mask0_T_44, - _mask0_T_43, - _mask0_T_42, - |(txnSizes_0[4:2]), - _mask0_T_40, - |(txnSizes_0[4:1]), - |txnSizes_0}; - wire [15:0] _mask0_T_67 = - io_dbus_addr[1] ? {_mask0_T_63[13:0], _mask0_T_63[15:14]} : _mask0_T_63; - wire [15:0] _mask0_T_71 = - io_dbus_addr[2] ? {_mask0_T_67[11:0], _mask0_T_67[15:12]} : _mask0_T_67; - wire [15:0] wmask0 = - io_dbus_addr[3] ? {_mask0_T_71[7:0], _mask0_T_71[15:8]} : _mask0_T_71; - wire [3:0] _mask1_T_57 = io_dbus_addr[3:0] + txnSizes_0[3:0]; - wire [15:0] _mask1_T_67 = - _mask1_T_57[0] - ? {_mask1_T_54, - _mask1_T_53, - _mask1_T_52, - _mask1_T_51, - _mask1_T_50, - _mask1_T_49, - _mask1_T_48, - |(txnSizes_1[4:3]), - _mask1_T_46, - _mask1_T_45, - _mask1_T_44, - |(txnSizes_1[4:2]), - _mask1_T_42, - |(txnSizes_1[4:1]), - |txnSizes_1, - txnSizes_1[4]} - : {txnSizes_1[4], - _mask1_T_54, - _mask1_T_53, - _mask1_T_52, - _mask1_T_51, - _mask1_T_50, - _mask1_T_49, - _mask1_T_48, - |(txnSizes_1[4:3]), - _mask1_T_46, - _mask1_T_45, - _mask1_T_44, - |(txnSizes_1[4:2]), - _mask1_T_42, - |(txnSizes_1[4:1]), - |txnSizes_1}; - wire [15:0] _mask1_T_71 = - _mask1_T_57[1] ? {_mask1_T_67[13:0], _mask1_T_67[15:14]} : _mask1_T_67; - wire [15:0] _mask1_T_75 = - _mask1_T_57[2] ? {_mask1_T_71[11:0], _mask1_T_71[15:12]} : _mask1_T_71; - wire [15:0] wmask1 = - _mask1_T_57[3] ? {_mask1_T_75[7:0], _mask1_T_75[15:8]} : _mask1_T_75; - wire io_dbus_ready_0 = - io_dbus_write - ? io_axi_write_resp_valid & _writeAddrQ_io_count == 2'h0 - & _writeDataQ_io_count == 2'h0 & _io_dbus_ready_T_11 == txnCount - : io_axi_read_data_valid & io_axi_read_data_bits_last - & _io_dbus_ready_T_11 == txnCount; - wire [15:0] _mask0_T_25 = - io_dbus_addr[0] - ? {_mask0_T_52, - _mask0_T_51, - _mask0_T_50, - _mask0_T_49, - _mask0_T_48, - _mask0_T_47, - _mask0_T_46, - |(txnSizes_0[4:3]), - _mask0_T_44, - _mask0_T_43, - _mask0_T_42, - |(txnSizes_0[4:2]), - _mask0_T_40, - |(txnSizes_0[4:1]), - |txnSizes_0, - txnSizes_0[4]} - : {txnSizes_0[4], - _mask0_T_52, - _mask0_T_51, - _mask0_T_50, - _mask0_T_49, - _mask0_T_48, - _mask0_T_47, - _mask0_T_46, - |(txnSizes_0[4:3]), - _mask0_T_44, - _mask0_T_43, - _mask0_T_42, - |(txnSizes_0[4:2]), - _mask0_T_40, - |(txnSizes_0[4:1]), - |txnSizes_0}; - wire [15:0] _mask0_T_29 = - io_dbus_addr[1] ? {_mask0_T_25[13:0], _mask0_T_25[15:14]} : _mask0_T_25; - wire [15:0] _mask0_T_33 = - io_dbus_addr[2] ? {_mask0_T_29[11:0], _mask0_T_29[15:12]} : _mask0_T_29; - wire [15:0] rmask0 = - io_dbus_addr[3] ? {_mask0_T_33[7:0], _mask0_T_33[15:8]} : _mask0_T_33; - wire [3:0] _mask1_T_17 = io_dbus_addr[3:0] + txnSizes_0[3:0]; - wire [15:0] _mask1_T_27 = - _mask1_T_17[0] - ? {_mask1_T_54, - _mask1_T_53, - _mask1_T_52, - _mask1_T_51, - _mask1_T_50, - _mask1_T_49, - _mask1_T_48, - |(txnSizes_1[4:3]), - _mask1_T_46, - _mask1_T_45, - _mask1_T_44, - |(txnSizes_1[4:2]), - _mask1_T_42, - |(txnSizes_1[4:1]), - |txnSizes_1, - txnSizes_1[4]} - : {txnSizes_1[4], - _mask1_T_54, - _mask1_T_53, - _mask1_T_52, - _mask1_T_51, - _mask1_T_50, - _mask1_T_49, - _mask1_T_48, - |(txnSizes_1[4:3]), - _mask1_T_46, - _mask1_T_45, - _mask1_T_44, - |(txnSizes_1[4:2]), - _mask1_T_42, - |(txnSizes_1[4:1]), - |txnSizes_1}; - wire [15:0] _mask1_T_31 = - _mask1_T_17[1] ? {_mask1_T_27[13:0], _mask1_T_27[15:14]} : _mask1_T_27; - wire [15:0] _mask1_T_35 = - _mask1_T_17[2] ? {_mask1_T_31[11:0], _mask1_T_31[15:12]} : _mask1_T_31; - wire [15:0] rmask1 = - _mask1_T_17[3] ? {_mask1_T_35[7:0], _mask1_T_35[15:8]} : _mask1_T_35; - wire [15:0] rbitmask = - crossLineBoundary - ? (transactionsCompleted == 2'h1 - ? rmask1 - : transactionsCompleted == 2'h0 ? rmask0 : 16'h0) - : rmask1 == 16'h0 | ~io_axi_read_data_bits_last ? rmask0 : rmask1; - wire [127:0] rbytemask = - {{8{rbitmask[15]}}, - {8{rbitmask[14]}}, - {8{rbitmask[13]}}, - {8{rbitmask[12]}}, - {8{rbitmask[11]}}, - {8{rbitmask[10]}}, - {8{rbitmask[9]}}, - {8{rbitmask[8]}}, - {8{rbitmask[7]}}, - {8{rbitmask[6]}}, - {8{rbitmask[5]}}, - {8{rbitmask[4]}}, - {8{rbitmask[3]}}, - {8{rbitmask[2]}}, - {8{rbitmask[1]}}, - {8{rbitmask[0]}}}; + wire _wdataQueue_io_enq_ready; + reg waddrFired; + wire io_axi_write_addr_valid_0 = ~waddrFired & io_dbus_valid & io_dbus_write; + reg wdataFired; + wire wdataQueue_io_enq_valid = ~wdataFired & io_dbus_valid & io_dbus_write; + reg wrespReceived; + wire io_axi_write_resp_ready_0 = ~wrespReceived & io_dbus_valid & io_dbus_write; + wire _waddrFired_T = io_axi_write_addr_ready & io_axi_write_addr_valid_0; + wire _wdataFired_T = _wdataQueue_io_enq_ready & wdataQueue_io_enq_valid; + wire _wrespReceived_T = io_axi_write_resp_ready_0 & io_axi_write_resp_valid; + wire writeFinished = + (_waddrFired_T | waddrFired) & (_wdataFired_T | wdataFired) + & (_wrespReceived_T | wrespReceived); + reg raddrFired; + wire io_axi_read_addr_valid_0 = ~raddrFired & io_dbus_valid & ~io_dbus_write; + reg rdataReceived_valid; + reg [127:0] rdataReceived_bits; + wire io_axi_read_data_ready_0 = + ~rdataReceived_valid & io_dbus_valid & ~io_dbus_write; + wire _raddrFired_T = io_axi_read_addr_ready & io_axi_read_addr_valid_0; + wire _readNext_T = io_axi_read_data_ready_0 & io_axi_read_data_valid; + wire readFinished = + (_raddrFired_T | raddrFired) & (_readNext_T | rdataReceived_valid); + reg [127:0] readNext; always @(posedge clock or posedge reset) begin if (reset) begin - txnActive <= 1'h0; - sdata <= 128'h0; - transactionsCompleted <= 2'h0; + waddrFired <= 1'h0; + wdataFired <= 1'h0; + wrespReceived <= 1'h0; + raddrFired <= 1'h0; + rdataReceived_valid <= 1'h0; + rdataReceived_bits <= 128'h0; + readNext <= 128'h0; end else begin - txnActive <= ~(io_dbus_valid & io_dbus_ready_0) & (io_dbus_valid | txnActive); - if (io_axi_read_data_valid) - sdata <= sdata & ~rbytemask | io_axi_read_data_bits_data & rbytemask; - else if (newTxn) - sdata <= 128'h0; - if (newTxn) - transactionsCompleted <= 2'h0; - else if (txnActive & io_dbus_write & io_axi_write_resp_valid | txnActive - & ~io_dbus_write & io_axi_read_data_valid) - transactionsCompleted <= _io_dbus_ready_T_11; + waddrFired <= ~writeFinished & (_waddrFired_T | waddrFired); + wdataFired <= ~writeFinished & (_wdataFired_T | wdataFired); + wrespReceived <= ~writeFinished & (_wrespReceived_T | wrespReceived); + raddrFired <= ~readFinished & (_raddrFired_T | raddrFired); + rdataReceived_valid <= ~readFinished & (_readNext_T | rdataReceived_valid); + if (readFinished) begin + rdataReceived_bits <= 128'h0; + readNext <= _readNext_T ? io_axi_read_data_bits_data : rdataReceived_bits; + end + else if (_readNext_T) + rdataReceived_bits <= io_axi_read_data_bits_data; end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:4]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin - _RANDOM[i] = `RANDOM; - end - txnActive = _RANDOM[3'h0][0]; - sdata = - {_RANDOM[3'h0][31:1], - _RANDOM[3'h1], - _RANDOM[3'h2], - _RANDOM[3'h3], - _RANDOM[3'h4][0]}; - transactionsCompleted = _RANDOM[3'h4][2:1]; - `endif // RANDOMIZE_REG_INIT if (reset) begin - txnActive = 1'h0; - sdata = 128'h0; - transactionsCompleted = 2'h0; + waddrFired = 1'h0; + wdataFired = 1'h0; + wrespReceived = 1'h0; + raddrFired = 1'h0; + rdataReceived_valid = 1'h0; + rdataReceived_bits = 128'h0; + readNext = 128'h0; end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif // FIRRTL_AFTER_INITIAL `endif // ENABLE_INITIAL_REG_ - FifoX_1 readAddrQ ( - .clock (clock), - .reset (reset), - .io_in_valid (newTxn & ~io_dbus_write), - .io_in_bits_0_bits_addr (io_dbus_addr), - .io_in_bits_0_bits_len ({7'h0, (|misalignment) & _crossLineBoundary_T_4 < 32'h11}), - .io_in_bits_0_bits_size - (io_dbus_size[0] - ? 3'h0 - : io_dbus_size[1] - ? 3'h1 - : io_dbus_size[2] - ? 3'h2 - : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), - .io_in_bits_1_valid (crossLineBoundary), - .io_in_bits_1_bits_addr (io_dbus_addr + 32'h10 & 32'hFFFFFFF0), - .io_in_bits_1_bits_size - (io_dbus_size[0] - ? 3'h0 - : io_dbus_size[1] - ? 3'h1 - : io_dbus_size[2] - ? 3'h2 - : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), - .io_out_ready (io_axi_read_addr_ready & _readAddrQ_io_out_valid), - .io_out_valid (_readAddrQ_io_out_valid), - .io_out_bits_addr (io_axi_read_addr_bits_addr), - .io_out_bits_prot (io_axi_read_addr_bits_prot), - .io_out_bits_id (io_axi_read_addr_bits_id), - .io_out_bits_len (io_axi_read_addr_bits_len), - .io_out_bits_size (io_axi_read_addr_bits_size), - .io_out_bits_burst (io_axi_read_addr_bits_burst), - .io_out_bits_lock (io_axi_read_addr_bits_lock), - .io_out_bits_cache (io_axi_read_addr_bits_cache), - .io_out_bits_qos (io_axi_read_addr_bits_qos), - .io_out_bits_region (io_axi_read_addr_bits_region), - .io_count (_readAddrQ_io_count) - ); - FifoX_1 writeAddrQ ( - .clock (clock), - .reset (reset), - .io_in_valid (writeDataQ_io_in_valid), - .io_in_bits_0_bits_addr (writeAddrQ_io_in_bits_0_bits_addr), - .io_in_bits_0_bits_len (8'h0), - .io_in_bits_0_bits_size - (io_dbus_size[0] - ? 3'h0 - : io_dbus_size[1] - ? 3'h1 - : io_dbus_size[2] - ? 3'h2 - : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), - .io_in_bits_1_valid (txnCount[1]), - .io_in_bits_1_bits_addr (writeAddrQ_io_in_bits_0_bits_addr + {27'h0, io_dbus_size}), - .io_in_bits_1_bits_size - (io_dbus_size[0] - ? 3'h0 - : io_dbus_size[1] - ? 3'h1 - : io_dbus_size[2] - ? 3'h2 - : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), - .io_out_ready (io_axi_write_addr_ready & _writeAddrQ_io_out_valid), - .io_out_valid (_writeAddrQ_io_out_valid), - .io_out_bits_addr (io_axi_write_addr_bits_addr), - .io_out_bits_prot (io_axi_write_addr_bits_prot), - .io_out_bits_id (io_axi_write_addr_bits_id), - .io_out_bits_len (io_axi_write_addr_bits_len), - .io_out_bits_size (io_axi_write_addr_bits_size), - .io_out_bits_burst (io_axi_write_addr_bits_burst), - .io_out_bits_lock (io_axi_write_addr_bits_lock), - .io_out_bits_cache (io_axi_write_addr_bits_cache), - .io_out_bits_qos (io_axi_write_addr_bits_qos), - .io_out_bits_region (io_axi_write_addr_bits_region), - .io_count (_writeAddrQ_io_count) - ); - FifoX_3 writeDataQ ( - .clock (clock), - .reset (reset), - .io_in_valid (writeDataQ_io_in_valid), - .io_in_bits_0_bits_data - (io_dbus_wdata - & {{8{wmask0[15]}}, - {8{wmask0[14]}}, - {8{wmask0[13]}}, - {8{wmask0[12]}}, - {8{wmask0[11]}}, - {8{wmask0[10]}}, - {8{wmask0[9]}}, - {8{wmask0[8]}}, - {8{wmask0[7]}}, - {8{wmask0[6]}}, - {8{wmask0[5]}}, - {8{wmask0[4]}}, - {8{wmask0[3]}}, - {8{wmask0[2]}}, - {8{wmask0[1]}}, - {8{wmask0[0]}}}), - .io_in_bits_0_bits_strb (wmask0), - .io_in_bits_1_valid (txnCount[1]), - .io_in_bits_1_bits_data - (io_dbus_wdata - & {{8{wmask1[15]}}, - {8{wmask1[14]}}, - {8{wmask1[13]}}, - {8{wmask1[12]}}, - {8{wmask1[11]}}, - {8{wmask1[10]}}, - {8{wmask1[9]}}, - {8{wmask1[8]}}, - {8{wmask1[7]}}, - {8{wmask1[6]}}, - {8{wmask1[5]}}, - {8{wmask1[4]}}, - {8{wmask1[3]}}, - {8{wmask1[2]}}, - {8{wmask1[1]}}, - {8{wmask1[0]}}}), - .io_in_bits_1_bits_strb (wmask1), - .io_out_ready (io_axi_write_data_ready & _writeDataQ_io_out_valid), - .io_out_valid (_writeDataQ_io_out_valid), - .io_out_bits_data (io_axi_write_data_bits_data), - .io_out_bits_last (io_axi_write_data_bits_last), - .io_out_bits_strb (io_axi_write_data_bits_strb), - .io_count (_writeDataQ_io_count) + Queue2_AxiWriteData wdataQueue ( + .clock (clock), + .reset (reset), + .io_enq_ready (_wdataQueue_io_enq_ready), + .io_enq_valid (wdataQueue_io_enq_valid), + .io_enq_bits_data (io_dbus_wdata), + .io_enq_bits_last (1'h1), + .io_enq_bits_strb (io_dbus_wmask), + .io_deq_ready (io_axi_write_data_ready), + .io_deq_valid (io_axi_write_data_valid), + .io_deq_bits_data (io_axi_write_data_bits_data), + .io_deq_bits_last (io_axi_write_data_bits_last), + .io_deq_bits_strb (io_axi_write_data_bits_strb) ); - assign io_dbus_ready = io_dbus_ready_0; - assign io_dbus_rdata = sdata; - assign io_axi_write_addr_valid = _writeAddrQ_io_out_valid; - assign io_axi_write_data_valid = _writeDataQ_io_out_valid; - assign io_axi_write_resp_ready = io_axi_write_resp_valid; - assign io_axi_read_addr_valid = _readAddrQ_io_out_valid; - assign io_axi_read_data_ready = io_axi_read_data_valid; + assign io_dbus_ready = io_dbus_write ? writeFinished : readFinished; + assign io_dbus_rdata = readNext; + assign io_axi_write_addr_valid = io_axi_write_addr_valid_0; + assign io_axi_write_addr_bits_addr = io_dbus_addr; + assign io_axi_write_addr_bits_size = + io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] ? 3'h2 : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}; + assign io_axi_write_resp_ready = io_axi_write_resp_ready_0; + assign io_axi_read_addr_valid = io_axi_read_addr_valid_0; + assign io_axi_read_addr_bits_addr = io_dbus_addr; + assign io_axi_read_addr_bits_size = + io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] ? 3'h2 : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}; + assign io_axi_read_data_ready = io_axi_read_data_ready_0; assign io_fault_valid = - io_axi_write_resp_valid - ? (|io_axi_write_resp_bits_resp) & io_axi_write_resp_bits_resp != 2'h1 - : io_axi_read_data_valid & io_axi_read_data_bits_last - & (|io_axi_read_data_bits_resp) & io_axi_read_data_bits_resp != 2'h1; - assign io_fault_bits_write = io_axi_write_resp_valid; - assign io_fault_bits_addr = io_dbus_addr; - assign io_fault_bits_epc = io_dbus_pc; + io_dbus_valid + & (io_dbus_write + ? io_axi_write_resp_valid & (|io_axi_write_resp_bits_resp) + : io_axi_read_data_valid & (|io_axi_read_data_bits_resp)); +endmodule + +// VCS coverage exclude_file +module ram_2x136( + input R0_addr, + R0_en, + R0_clk, + output [135:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [135:0] W0_data +); + + reg [135:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + assign R0_data = R0_en ? Memory[R0_addr] : 136'bx; +endmodule + +module Queue2_AxiReadData( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [127:0] io_enq_bits_data, + input [5:0] io_enq_bits_id, + input [1:0] io_enq_bits_resp, + input io_enq_bits_last, + io_deq_ready, + output io_deq_valid, + output [127:0] io_deq_bits_data, + output [5:0] io_deq_bits_id, + output [1:0] io_deq_bits_resp +); + + wire [135:0] _ram_ext_R0_data; + reg enq_ptr_value; + reg deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + enq_ptr_value <= 1'h0; + deq_ptr_value <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + enq_ptr_value <= enq_ptr_value - 1'h1; + if (do_deq) + deq_ptr_value <= deq_ptr_value - 1'h1; + if (do_enq != do_deq) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + initial begin + if (reset) begin + enq_ptr_value = 1'h0; + deq_ptr_value = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x136 ram_ext ( + .R0_addr (deq_ptr_value), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (enq_ptr_value), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_data, io_enq_bits_id, io_enq_bits_resp}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[135:8]; + assign io_deq_bits_id = _ram_ext_R0_data[7:2]; + assign io_deq_bits_resp = _ram_ext_R0_data[1:0]; endmodule -module CoreMiniAxi( +module CoreMiniCoreAxi( input io_aclk, io_aresetn, output io_axi_slave_write_addr_ready, @@ -17073,78 +22476,64 @@ module CoreMiniAxi( io_fault, io_wfi, input io_irq, - output [3:0] io_debug_en, - output [31:0] io_debug_addr_0, - io_debug_addr_1, - io_debug_addr_2, - io_debug_addr_3, - io_debug_inst_0, - io_debug_inst_1, - io_debug_inst_2, - io_debug_inst_3, - io_debug_cycles, - output io_debug_dbus_valid, - output [31:0] io_debug_dbus_bits_addr, - output [127:0] io_debug_dbus_bits_wdata, - output io_debug_dbus_bits_write, - io_debug_dispatch_0_instFire, - output [31:0] io_debug_dispatch_0_instAddr, - io_debug_dispatch_0_instInst, - output io_debug_dispatch_1_instFire, - output [31:0] io_debug_dispatch_1_instAddr, - io_debug_dispatch_1_instInst, - output io_debug_dispatch_2_instFire, - output [31:0] io_debug_dispatch_2_instAddr, - io_debug_dispatch_2_instInst, - output io_debug_dispatch_3_instFire, - output [31:0] io_debug_dispatch_3_instAddr, - io_debug_dispatch_3_instInst, - output io_debug_regfile_writeAddr_0_valid, - output [4:0] io_debug_regfile_writeAddr_0_bits, - output io_debug_regfile_writeAddr_1_valid, - output [4:0] io_debug_regfile_writeAddr_1_bits, - output io_debug_regfile_writeAddr_2_valid, - output [4:0] io_debug_regfile_writeAddr_2_bits, - output io_debug_regfile_writeAddr_3_valid, - output [4:0] io_debug_regfile_writeAddr_3_bits, - output io_debug_regfile_writeData_0_valid, - output [4:0] io_debug_regfile_writeData_0_bits_addr, - output [31:0] io_debug_regfile_writeData_0_bits_data, - output io_debug_regfile_writeData_1_valid, - output [4:0] io_debug_regfile_writeData_1_bits_addr, - output [31:0] io_debug_regfile_writeData_1_bits_data, - output io_debug_regfile_writeData_2_valid, - output [4:0] io_debug_regfile_writeData_2_bits_addr, - output [31:0] io_debug_regfile_writeData_2_bits_data, - output io_debug_regfile_writeData_3_valid, - output [4:0] io_debug_regfile_writeData_3_bits_addr, - output [31:0] io_debug_regfile_writeData_3_bits_data, - output io_debug_regfile_writeData_4_valid, - output [4:0] io_debug_regfile_writeData_4_bits_addr, - output [31:0] io_debug_regfile_writeData_4_bits_data, - output io_debug_regfile_writeData_5_valid, - output [4:0] io_debug_regfile_writeData_5_bits_addr, - output [31:0] io_debug_regfile_writeData_5_bits_data, - output io_debug_float_writeAddr_valid, - output [4:0] io_debug_float_writeAddr_bits, - output io_debug_float_writeData_0_valid, - output [31:0] io_debug_float_writeData_0_bits_addr, - io_debug_float_writeData_0_bits_data, - output io_debug_float_writeData_1_valid, - output [31:0] io_debug_float_writeData_1_bits_addr, - io_debug_float_writeData_1_bits_data, - output io_slog_valid, - output [4:0] io_slog_addr, - output [31:0] io_slog_data, + input [31:0] io_boot_addr, + input io_timer_irq, + io_software_irq, + output io_dm_req_ready, + input io_dm_req_valid, + input [31:0] io_dm_req_bits_address, + io_dm_req_bits_data, + input [1:0] io_dm_req_bits_op, + input io_dm_rsp_ready, + output io_dm_rsp_valid, + output [31:0] io_dm_rsp_bits_data, + output [1:0] io_dm_rsp_bits_op, input io_te ); + wire dm_io_ext_rsp_ready; + wire _readDataSkid_q_io_enq_ready; + wire _readDataSkid_q_io_deq_valid; + wire [127:0] _readDataSkid_q_io_deq_bits_data; + wire [5:0] _readDataSkid_q_io_deq_bits_id; + wire [1:0] _readDataSkid_q_io_deq_bits_resp; + wire _io_axi_master_read_addr_q_io_enq_ready; + wire _io_axi_master_read_addr_q_io_deq_valid; + wire _readAddrArb_io_in_0_ready; + wire _readAddrArb_io_in_1_ready; + wire _readAddrArb_io_out_valid; + wire [31:0] _readAddrArb_io_out_bits_addr; + wire [2:0] _readAddrArb_io_out_bits_prot; + wire [5:0] _readAddrArb_io_out_bits_id; + wire [7:0] _readAddrArb_io_out_bits_len; + wire [2:0] _readAddrArb_io_out_bits_size; + wire [1:0] _readAddrArb_io_out_bits_burst; + wire _readAddrArb_io_out_bits_lock; + wire [3:0] _readAddrArb_io_out_bits_cache; + wire [3:0] _readAddrArb_io_out_bits_qos; + wire [3:0] _readAddrArb_io_out_bits_region; + wire _ebus2axi_io_axi_write_resp_q_io_enq_ready; + wire _ebus2axi_io_axi_write_resp_q_io_deq_valid; + wire [1:0] _ebus2axi_io_axi_write_resp_q_io_deq_bits_resp; + wire _io_axi_master_write_data_q_io_enq_ready; + wire _io_axi_master_write_data_q_io_deq_valid; + wire _io_axi_master_write_addr_q_io_enq_ready; + wire _io_axi_master_write_addr_q_io_deq_valid; wire _ebus2axi_io_dbus_ready; wire [127:0] _ebus2axi_io_dbus_rdata; + wire _ebus2axi_io_axi_write_addr_valid; + wire [31:0] _ebus2axi_io_axi_write_addr_bits_addr; + wire [2:0] _ebus2axi_io_axi_write_addr_bits_size; + wire _ebus2axi_io_axi_write_data_valid; + wire [127:0] _ebus2axi_io_axi_write_data_bits_data; + wire _ebus2axi_io_axi_write_data_bits_last; + wire [15:0] _ebus2axi_io_axi_write_data_bits_strb; + wire _ebus2axi_io_axi_write_resp_ready; + wire _ebus2axi_io_axi_read_addr_valid; + wire [31:0] _ebus2axi_io_axi_read_addr_bits_addr; + wire [2:0] _ebus2axi_io_axi_read_addr_bits_size; + wire _ebus2axi_io_axi_read_data_ready; wire _ebus2axi_io_fault_valid; - wire _ebus2axi_io_fault_bits_write; - wire [31:0] _ebus2axi_io_fault_bits_addr; - wire [31:0] _ebus2axi_io_fault_bits_epc; wire _axiSlave_io_axi_write_addr_ready; wire _axiSlave_io_axi_write_data_ready; wire _axiSlave_io_axi_write_resp_valid; @@ -17179,7 +22568,9 @@ module CoreMiniAxi( wire [127:0] _dtcmArbiter_io_source_0_readData_bits; wire _dtcmArbiter_io_source_1_readData_valid; wire [127:0] _dtcmArbiter_io_source_1_readData_bits; - wire _dtcmArbiter_io_fabricBusy; + wire _dtcmArbiter_io_source_2_readData_valid; + wire [127:0] _dtcmArbiter_io_source_2_readData_bits; + wire _dtcmArbiter_io_fabricBusy_1; wire _dtcmArbiter_io_port_readDataAddr_valid; wire [31:0] _dtcmArbiter_io_port_readDataAddr_bits; wire _dtcmArbiter_io_port_writeDataAddr_valid; @@ -17239,10 +22630,17 @@ module CoreMiniAxi( wire [7:0] _dtcm_io_rdata_13; wire [7:0] _dtcm_io_rdata_14; wire [7:0] _dtcm_io_rdata_15; + wire _ibus2axi_io_ibus_ready; + wire [127:0] _ibus2axi_io_ibus_rdata; + wire _ibus2axi_io_ibus_fault_valid; + wire _ibus2axi_io_axi_addr_valid; + wire [31:0] _ibus2axi_io_axi_addr_bits_addr; wire [127:0] _itcmArbiter_io_source_0_readData_bits; wire _itcmArbiter_io_source_1_readData_valid; wire [127:0] _itcmArbiter_io_source_1_readData_bits; - wire _itcmArbiter_io_fabricBusy; + wire _itcmArbiter_io_source_2_readData_valid; + wire [127:0] _itcmArbiter_io_source_2_readData_bits; + wire _itcmArbiter_io_fabricBusy_1; wire _itcmArbiter_io_port_readDataAddr_valid; wire [31:0] _itcmArbiter_io_port_readDataAddr_bits; wire _itcmArbiter_io_port_writeDataAddr_valid; @@ -17310,9 +22708,18 @@ module CoreMiniAxi( wire [31:0] _core_io_csr_out_value_5; wire [31:0] _core_io_csr_out_value_6; wire [31:0] _core_io_csr_out_value_7; + wire [31:0] _core_io_csr_out_value_8; wire _core_io_halted; wire _core_io_fault; wire _core_io_wfi; + wire _core_io_dm_csr_rd_valid; + wire [31:0] _core_io_dm_csr_rd_bits; + wire _core_io_dm_scalar_rd_ready; + wire [31:0] _core_io_dm_scalar_rs_data; + wire [22:0] _core_io_dm_float_rs_data_mantissa; + wire [7:0] _core_io_dm_float_rs_data_exponent; + wire _core_io_dm_float_rs_data_sign; + wire _core_io_dm_debug_mode; wire _core_io_ibus_valid; wire [31:0] _core_io_ibus_addr; wire _core_io_dbus_valid; @@ -17322,10 +22729,56 @@ module CoreMiniAxi( wire [15:0] _core_io_dbus_wmask; wire _core_io_ebus_dbus_valid; wire _core_io_ebus_dbus_write; - wire [31:0] _core_io_ebus_dbus_pc; wire [31:0] _core_io_ebus_dbus_addr; wire [4:0] _core_io_ebus_dbus_size; wire [127:0] _core_io_ebus_dbus_wdata; + wire [15:0] _core_io_ebus_dbus_wmask; + wire _inflight_io_enq_ready; + wire _inflight_io_deq_valid; + wire _inflight_io_deq_bits; + wire _dmReqArbiter_io_in_0_ready; + wire _dmReqArbiter_io_in_1_ready; + wire _dmReqArbiter_io_out_valid; + wire [31:0] _dmReqArbiter_io_out_bits_address; + wire [31:0] _dmReqArbiter_io_out_bits_data; + wire [1:0] _dmReqArbiter_io_out_bits_op; + wire _dmReqArbiter_io_chosen; + wire _dm_io_ext_req_ready; + wire _dm_io_ext_rsp_valid; + wire [31:0] _dm_io_ext_rsp_bits_data; + wire [1:0] _dm_io_ext_rsp_bits_op; + wire _dm_io_csr_valid; + wire [4:0] _dm_io_csr_bits_addr; + wire [11:0] _dm_io_csr_bits_index; + wire [4:0] _dm_io_csr_bits_rs1; + wire [1:0] _dm_io_csr_bits_op; + wire [31:0] _dm_io_csr_rs1; + wire _dm_io_scalar_rd_valid; + wire [4:0] _dm_io_scalar_rd_bits_addr; + wire [31:0] _dm_io_scalar_rd_bits_data; + wire [4:0] _dm_io_scalar_rs_idx; + wire _dm_io_float_rd_valid; + wire [4:0] _dm_io_float_rd_addr; + wire [22:0] _dm_io_float_rd_data_mantissa; + wire [7:0] _dm_io_float_rd_data_exponent; + wire _dm_io_float_rd_data_sign; + wire _dm_io_float_rs_valid; + wire [4:0] _dm_io_float_rs_addr; + wire _dm_io_itcm_readDataAddr_valid; + wire [31:0] _dm_io_itcm_readDataAddr_bits; + wire _dm_io_itcm_writeDataAddr_valid; + wire [31:0] _dm_io_itcm_writeDataAddr_bits; + wire [127:0] _dm_io_itcm_writeDataBits; + wire [15:0] _dm_io_itcm_writeDataStrb; + wire _dm_io_dtcm_readDataAddr_valid; + wire [31:0] _dm_io_dtcm_readDataAddr_bits; + wire _dm_io_dtcm_writeDataAddr_valid; + wire [31:0] _dm_io_dtcm_writeDataAddr_bits; + wire [127:0] _dm_io_dtcm_writeDataBits; + wire [15:0] _dm_io_dtcm_writeDataStrb; + wire _dm_io_haltreq_0; + wire _dm_io_resumereq_0; + wire _dm_io_ndmreset; wire _cg_clk_o; wire _csr_io_fabric_readData_valid; wire [127:0] _csr_io_fabric_readData_bits; @@ -17333,31 +22786,61 @@ module CoreMiniAxi( wire _csr_io_reset; wire _csr_io_cg; wire [31:0] _csr_io_pcStart; + wire _csr_io_debug_req_valid; + wire [31:0] _csr_io_debug_req_bits_address; + wire [31:0] _csr_io_debug_req_bits_data; + wire [1:0] _csr_io_debug_req_bits_op; + wire _csr_io_debug_rsp_ready; wire _rst_sync_clk_o; wire _rst_sync_rstn_o; wire _global_reset_T_2 = ~(io_te ? io_aresetn : _rst_sync_rstn_o); - reg axiSlaveEnable; + reg dmEnable; + wire _io_dm_rsp_valid_T = _dm_io_ext_rsp_valid & _inflight_io_deq_valid; + assign dm_io_ext_rsp_ready = + _inflight_io_deq_valid + & (_inflight_io_deq_bits ? _csr_io_debug_rsp_ready : io_dm_rsp_ready); + reg irq_reg; + reg timer_irq_reg; + reg software_irq_reg; + reg dm_io_resumeack_0_REG; + wire inItcm = _core_io_ibus_addr < 32'h2000; + reg inItcmReg; + reg axiEnable; + wire _ibus2axi_io_axi_data_valid_T = _readDataSkid_q_io_deq_bits_id == 6'h1; always @(posedge _rst_sync_clk_o or posedge _global_reset_T_2) begin - if (_global_reset_T_2) - axiSlaveEnable <= 1'h0; - else - axiSlaveEnable <= 1'h1; + if (_global_reset_T_2) begin + dmEnable <= 1'h0; + irq_reg <= 1'h0; + timer_irq_reg <= 1'h0; + software_irq_reg <= 1'h0; + dm_io_resumeack_0_REG <= 1'h0; + inItcmReg <= 1'h1; + axiEnable <= 1'h0; + end + else begin + dmEnable <= 1'h1; + irq_reg <= io_irq; + timer_irq_reg <= io_timer_irq; + software_irq_reg <= io_software_irq; + dm_io_resumeack_0_REG <= _core_io_dm_debug_mode; + inItcmReg <= inItcm; + axiEnable <= 1'h1; + end end // always @(posedge, posedge) `ifdef ENABLE_INITIAL_REG_ `ifdef FIRRTL_BEFORE_INITIAL `FIRRTL_BEFORE_INITIAL `endif // FIRRTL_BEFORE_INITIAL - logic [31:0] _RANDOM[0:0]; initial begin - `ifdef INIT_RANDOM_PROLOG_ - `INIT_RANDOM_PROLOG_ - `endif // INIT_RANDOM_PROLOG_ - `ifdef RANDOMIZE_REG_INIT - _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; - axiSlaveEnable = _RANDOM[/*Zero width*/ 1'b0][0]; - `endif // RANDOMIZE_REG_INIT - if (_global_reset_T_2) - axiSlaveEnable = 1'h0; + if (_global_reset_T_2) begin + dmEnable = 1'h0; + irq_reg = 1'h0; + timer_irq_reg = 1'h0; + software_irq_reg = 1'h0; + dm_io_resumeack_0_REG = 1'h0; + inItcmReg = 1'h1; + axiEnable = 1'h0; + end end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL @@ -17384,6 +22867,7 @@ module CoreMiniAxi( .io_reset (_csr_io_reset), .io_cg (_csr_io_cg), .io_pcStart (_csr_io_pcStart), + .io_bootAddr (io_boot_addr), .io_halted (_core_io_halted), .io_fault (_core_io_fault), .io_coralnpu_csr_value_0 (_core_io_csr_out_value_0), @@ -17393,117 +22877,185 @@ module CoreMiniAxi( .io_coralnpu_csr_value_4 (_core_io_csr_out_value_4), .io_coralnpu_csr_value_5 (_core_io_csr_out_value_5), .io_coralnpu_csr_value_6 (_core_io_csr_out_value_6), - .io_coralnpu_csr_value_7 (_core_io_csr_out_value_7) + .io_coralnpu_csr_value_7 (_core_io_csr_out_value_7), + .io_coralnpu_csr_value_8 (_core_io_csr_out_value_8), + .io_debug_req_ready (_dmReqArbiter_io_in_1_ready & dmEnable), + .io_debug_req_valid (_csr_io_debug_req_valid), + .io_debug_req_bits_address (_csr_io_debug_req_bits_address), + .io_debug_req_bits_data (_csr_io_debug_req_bits_data), + .io_debug_req_bits_op (_csr_io_debug_req_bits_op), + .io_debug_rsp_ready (_csr_io_debug_rsp_ready), + .io_debug_rsp_valid (_io_dm_rsp_valid_T & _inflight_io_deq_bits), + .io_debug_rsp_bits_data (_dm_io_ext_rsp_bits_data), + .io_debug_rsp_bits_op (_dm_io_ext_rsp_bits_op) ); ClockGate cg ( .clk_i (_rst_sync_clk_o), - .enable (io_irq | ~_csr_io_cg & ~_core_io_wfi), + .enable + (irq_reg | timer_irq_reg | software_irq_reg | ~_csr_io_cg & ~_core_io_wfi + | _dm_io_haltreq_0), .te (io_te), .clk_o (_cg_clk_o) ); - CoreMini core ( - .clock (_cg_clk_o), - .reset (io_te ? ~io_aresetn : _csr_io_reset), - .io_csr_in_value_0 (_csr_io_pcStart), - .io_csr_out_value_0 (_core_io_csr_out_value_0), - .io_csr_out_value_1 (_core_io_csr_out_value_1), - .io_csr_out_value_2 (_core_io_csr_out_value_2), - .io_csr_out_value_3 (_core_io_csr_out_value_3), - .io_csr_out_value_4 (_core_io_csr_out_value_4), - .io_csr_out_value_5 (_core_io_csr_out_value_5), - .io_csr_out_value_6 (_core_io_csr_out_value_6), - .io_csr_out_value_7 (_core_io_csr_out_value_7), - .io_halted (_core_io_halted), - .io_fault (_core_io_fault), - .io_wfi (_core_io_wfi), - .io_irq (io_irq), - .io_ibus_valid (_core_io_ibus_valid), - .io_ibus_addr (_core_io_ibus_addr), - .io_ibus_rdata (_itcmArbiter_io_source_0_readData_bits), - .io_ibus_fault_valid - (_core_io_ibus_valid & (|(_core_io_ibus_addr[31:13]))), - .io_ibus_fault_bits_epc (_core_io_ibus_addr), - .io_dbus_valid (_core_io_dbus_valid), - .io_dbus_write (_core_io_dbus_write), - .io_dbus_addr (_core_io_dbus_addr), - .io_dbus_wdata (_core_io_dbus_wdata), - .io_dbus_wmask (_core_io_dbus_wmask), - .io_dbus_rdata (_dtcmArbiter_io_source_0_readData_bits), - .io_ebus_dbus_valid (_core_io_ebus_dbus_valid), - .io_ebus_dbus_ready (_ebus2axi_io_dbus_ready), - .io_ebus_dbus_write (_core_io_ebus_dbus_write), - .io_ebus_dbus_pc (_core_io_ebus_dbus_pc), - .io_ebus_dbus_addr (_core_io_ebus_dbus_addr), - .io_ebus_dbus_size (_core_io_ebus_dbus_size), - .io_ebus_dbus_wdata (_core_io_ebus_dbus_wdata), - .io_ebus_dbus_rdata (_ebus2axi_io_dbus_rdata), - .io_ebus_fault_valid (_ebus2axi_io_fault_valid), - .io_ebus_fault_bits_write (_ebus2axi_io_fault_bits_write), - .io_ebus_fault_bits_addr (_ebus2axi_io_fault_bits_addr), - .io_ebus_fault_bits_epc (_ebus2axi_io_fault_bits_epc), - .io_slog_valid (io_slog_valid), - .io_slog_addr (io_slog_addr), - .io_slog_data (io_slog_data), - .io_debug_en (io_debug_en), - .io_debug_addr_0 (io_debug_addr_0), - .io_debug_addr_1 (io_debug_addr_1), - .io_debug_addr_2 (io_debug_addr_2), - .io_debug_addr_3 (io_debug_addr_3), - .io_debug_inst_0 (io_debug_inst_0), - .io_debug_inst_1 (io_debug_inst_1), - .io_debug_inst_2 (io_debug_inst_2), - .io_debug_inst_3 (io_debug_inst_3), - .io_debug_cycles (io_debug_cycles), - .io_debug_dbus_valid (io_debug_dbus_valid), - .io_debug_dbus_bits_addr (io_debug_dbus_bits_addr), - .io_debug_dbus_bits_wdata (io_debug_dbus_bits_wdata), - .io_debug_dbus_bits_write (io_debug_dbus_bits_write), - .io_debug_dispatch_0_instFire (io_debug_dispatch_0_instFire), - .io_debug_dispatch_0_instAddr (io_debug_dispatch_0_instAddr), - .io_debug_dispatch_0_instInst (io_debug_dispatch_0_instInst), - .io_debug_dispatch_1_instFire (io_debug_dispatch_1_instFire), - .io_debug_dispatch_1_instAddr (io_debug_dispatch_1_instAddr), - .io_debug_dispatch_1_instInst (io_debug_dispatch_1_instInst), - .io_debug_dispatch_2_instFire (io_debug_dispatch_2_instFire), - .io_debug_dispatch_2_instAddr (io_debug_dispatch_2_instAddr), - .io_debug_dispatch_2_instInst (io_debug_dispatch_2_instInst), - .io_debug_dispatch_3_instFire (io_debug_dispatch_3_instFire), - .io_debug_dispatch_3_instAddr (io_debug_dispatch_3_instAddr), - .io_debug_dispatch_3_instInst (io_debug_dispatch_3_instInst), - .io_debug_regfile_writeAddr_0_valid (io_debug_regfile_writeAddr_0_valid), - .io_debug_regfile_writeAddr_0_bits (io_debug_regfile_writeAddr_0_bits), - .io_debug_regfile_writeAddr_1_valid (io_debug_regfile_writeAddr_1_valid), - .io_debug_regfile_writeAddr_1_bits (io_debug_regfile_writeAddr_1_bits), - .io_debug_regfile_writeAddr_2_valid (io_debug_regfile_writeAddr_2_valid), - .io_debug_regfile_writeAddr_2_bits (io_debug_regfile_writeAddr_2_bits), - .io_debug_regfile_writeAddr_3_valid (io_debug_regfile_writeAddr_3_valid), - .io_debug_regfile_writeAddr_3_bits (io_debug_regfile_writeAddr_3_bits), - .io_debug_regfile_writeData_0_valid (io_debug_regfile_writeData_0_valid), - .io_debug_regfile_writeData_0_bits_addr (io_debug_regfile_writeData_0_bits_addr), - .io_debug_regfile_writeData_0_bits_data (io_debug_regfile_writeData_0_bits_data), - .io_debug_regfile_writeData_1_valid (io_debug_regfile_writeData_1_valid), - .io_debug_regfile_writeData_1_bits_addr (io_debug_regfile_writeData_1_bits_addr), - .io_debug_regfile_writeData_1_bits_data (io_debug_regfile_writeData_1_bits_data), - .io_debug_regfile_writeData_2_valid (io_debug_regfile_writeData_2_valid), - .io_debug_regfile_writeData_2_bits_addr (io_debug_regfile_writeData_2_bits_addr), - .io_debug_regfile_writeData_2_bits_data (io_debug_regfile_writeData_2_bits_data), - .io_debug_regfile_writeData_3_valid (io_debug_regfile_writeData_3_valid), - .io_debug_regfile_writeData_3_bits_addr (io_debug_regfile_writeData_3_bits_addr), - .io_debug_regfile_writeData_3_bits_data (io_debug_regfile_writeData_3_bits_data), - .io_debug_regfile_writeData_4_valid (io_debug_regfile_writeData_4_valid), - .io_debug_regfile_writeData_4_bits_addr (io_debug_regfile_writeData_4_bits_addr), - .io_debug_regfile_writeData_4_bits_data (io_debug_regfile_writeData_4_bits_data), - .io_debug_regfile_writeData_5_valid (io_debug_regfile_writeData_5_valid), - .io_debug_regfile_writeData_5_bits_addr (io_debug_regfile_writeData_5_bits_addr), - .io_debug_regfile_writeData_5_bits_data (io_debug_regfile_writeData_5_bits_data), - .io_debug_float_writeAddr_valid (io_debug_float_writeAddr_valid), - .io_debug_float_writeAddr_bits (io_debug_float_writeAddr_bits), - .io_debug_float_writeData_0_valid (io_debug_float_writeData_0_valid), - .io_debug_float_writeData_0_bits_addr (io_debug_float_writeData_0_bits_addr), - .io_debug_float_writeData_0_bits_data (io_debug_float_writeData_0_bits_data), - .io_debug_float_writeData_1_valid (io_debug_float_writeData_1_valid), - .io_debug_float_writeData_1_bits_addr (io_debug_float_writeData_1_bits_addr), - .io_debug_float_writeData_1_bits_data (io_debug_float_writeData_1_bits_data) + DebugModule dm ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_ext_req_ready (_dm_io_ext_req_ready), + .io_ext_req_valid (_dmReqArbiter_io_out_valid & _inflight_io_enq_ready), + .io_ext_req_bits_address (_dmReqArbiter_io_out_bits_address), + .io_ext_req_bits_data (_dmReqArbiter_io_out_bits_data), + .io_ext_req_bits_op (_dmReqArbiter_io_out_bits_op), + .io_ext_rsp_ready (dm_io_ext_rsp_ready), + .io_ext_rsp_valid (_dm_io_ext_rsp_valid), + .io_ext_rsp_bits_data (_dm_io_ext_rsp_bits_data), + .io_ext_rsp_bits_op (_dm_io_ext_rsp_bits_op), + .io_csr_valid (_dm_io_csr_valid), + .io_csr_bits_addr (_dm_io_csr_bits_addr), + .io_csr_bits_index (_dm_io_csr_bits_index), + .io_csr_bits_rs1 (_dm_io_csr_bits_rs1), + .io_csr_bits_op (_dm_io_csr_bits_op), + .io_csr_rs1 (_dm_io_csr_rs1), + .io_csr_rd_valid (_core_io_dm_csr_rd_valid), + .io_csr_rd_bits (_core_io_dm_csr_rd_bits), + .io_scalar_rd_ready (_core_io_dm_scalar_rd_ready), + .io_scalar_rd_valid (_dm_io_scalar_rd_valid), + .io_scalar_rd_bits_addr (_dm_io_scalar_rd_bits_addr), + .io_scalar_rd_bits_data (_dm_io_scalar_rd_bits_data), + .io_scalar_rs_idx (_dm_io_scalar_rs_idx), + .io_scalar_rs_data (_core_io_dm_scalar_rs_data), + .io_float_rd_valid (_dm_io_float_rd_valid), + .io_float_rd_addr (_dm_io_float_rd_addr), + .io_float_rd_data_mantissa (_dm_io_float_rd_data_mantissa), + .io_float_rd_data_exponent (_dm_io_float_rd_data_exponent), + .io_float_rd_data_sign (_dm_io_float_rd_data_sign), + .io_float_rs_valid (_dm_io_float_rs_valid), + .io_float_rs_addr (_dm_io_float_rs_addr), + .io_float_rs_data_mantissa (_core_io_dm_float_rs_data_mantissa), + .io_float_rs_data_exponent (_core_io_dm_float_rs_data_exponent), + .io_float_rs_data_sign (_core_io_dm_float_rs_data_sign), + .io_itcm_readDataAddr_valid (_dm_io_itcm_readDataAddr_valid), + .io_itcm_readDataAddr_bits (_dm_io_itcm_readDataAddr_bits), + .io_itcm_readData_valid (_itcmArbiter_io_source_2_readData_valid), + .io_itcm_readData_bits (_itcmArbiter_io_source_2_readData_bits), + .io_itcm_writeDataAddr_valid (_dm_io_itcm_writeDataAddr_valid), + .io_itcm_writeDataAddr_bits (_dm_io_itcm_writeDataAddr_bits), + .io_itcm_writeDataBits (_dm_io_itcm_writeDataBits), + .io_itcm_writeDataStrb (_dm_io_itcm_writeDataStrb), + .io_itcm_writeResp (1'h1), + .io_dtcm_readDataAddr_valid (_dm_io_dtcm_readDataAddr_valid), + .io_dtcm_readDataAddr_bits (_dm_io_dtcm_readDataAddr_bits), + .io_dtcm_readData_valid (_dtcmArbiter_io_source_2_readData_valid), + .io_dtcm_readData_bits (_dtcmArbiter_io_source_2_readData_bits), + .io_dtcm_writeDataAddr_valid (_dm_io_dtcm_writeDataAddr_valid), + .io_dtcm_writeDataAddr_bits (_dm_io_dtcm_writeDataAddr_bits), + .io_dtcm_writeDataBits (_dm_io_dtcm_writeDataBits), + .io_dtcm_writeDataStrb (_dm_io_dtcm_writeDataStrb), + .io_dtcm_writeResp (1'h1), + .io_haltreq_0 (_dm_io_haltreq_0), + .io_resumereq_0 (_dm_io_resumereq_0), + .io_resumeack_0 (~_core_io_dm_debug_mode & dm_io_resumeack_0_REG), + .io_ndmreset (_dm_io_ndmreset), + .io_halted_0 (_core_io_dm_debug_mode), + .io_running_0 (~_core_io_dm_debug_mode), + .io_havereset_0 (1'h0) + ); + CoralNPURRArbiter dmReqArbiter ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_in_0_ready (_dmReqArbiter_io_in_0_ready), + .io_in_0_valid (io_dm_req_valid & dmEnable), + .io_in_0_bits_address (io_dm_req_bits_address), + .io_in_0_bits_data (io_dm_req_bits_data), + .io_in_0_bits_op (io_dm_req_bits_op), + .io_in_1_ready (_dmReqArbiter_io_in_1_ready), + .io_in_1_valid (_csr_io_debug_req_valid & dmEnable), + .io_in_1_bits_address (_csr_io_debug_req_bits_address), + .io_in_1_bits_data (_csr_io_debug_req_bits_data), + .io_in_1_bits_op (_csr_io_debug_req_bits_op), + .io_out_ready (_dm_io_ext_req_ready & _inflight_io_enq_ready), + .io_out_valid (_dmReqArbiter_io_out_valid), + .io_out_bits_address (_dmReqArbiter_io_out_bits_address), + .io_out_bits_data (_dmReqArbiter_io_out_bits_data), + .io_out_bits_op (_dmReqArbiter_io_out_bits_op), + .io_chosen (_dmReqArbiter_io_chosen) + ); + Queue1_UInt1 inflight ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_inflight_io_enq_ready), + .io_enq_valid (_dmReqArbiter_io_out_valid & _dm_io_ext_req_ready), + .io_enq_bits (_dmReqArbiter_io_chosen), + .io_deq_ready (dm_io_ext_rsp_ready & _dm_io_ext_rsp_valid), + .io_deq_valid (_inflight_io_deq_valid), + .io_deq_bits (_inflight_io_deq_bits) + ); + CoreMiniCore core ( + .clock (_cg_clk_o), + .reset (io_te ? ~io_aresetn : _csr_io_reset | _dm_io_ndmreset), + .io_csr_in_value_0 (_csr_io_pcStart), + .io_csr_out_value_0 (_core_io_csr_out_value_0), + .io_csr_out_value_1 (_core_io_csr_out_value_1), + .io_csr_out_value_2 (_core_io_csr_out_value_2), + .io_csr_out_value_3 (_core_io_csr_out_value_3), + .io_csr_out_value_4 (_core_io_csr_out_value_4), + .io_csr_out_value_5 (_core_io_csr_out_value_5), + .io_csr_out_value_6 (_core_io_csr_out_value_6), + .io_csr_out_value_7 (_core_io_csr_out_value_7), + .io_csr_out_value_8 (_core_io_csr_out_value_8), + .io_halted (_core_io_halted), + .io_fault (_core_io_fault), + .io_wfi (_core_io_wfi), + .io_irq (irq_reg | _dm_io_haltreq_0), + .io_timer_irq (timer_irq_reg), + .io_software_irq (software_irq_reg), + .io_dm_debug_req (_dm_io_haltreq_0), + .io_dm_resume_req (_dm_io_resumereq_0), + .io_dm_csr_valid (_dm_io_csr_valid), + .io_dm_csr_bits_addr (_dm_io_csr_bits_addr), + .io_dm_csr_bits_index (_dm_io_csr_bits_index), + .io_dm_csr_bits_rs1 (_dm_io_csr_bits_rs1), + .io_dm_csr_bits_op (_dm_io_csr_bits_op), + .io_dm_csr_rs1 (_dm_io_csr_rs1), + .io_dm_csr_rd_valid (_core_io_dm_csr_rd_valid), + .io_dm_csr_rd_bits (_core_io_dm_csr_rd_bits), + .io_dm_scalar_rd_ready (_core_io_dm_scalar_rd_ready), + .io_dm_scalar_rd_valid (_dm_io_scalar_rd_valid), + .io_dm_scalar_rd_bits_addr (_dm_io_scalar_rd_bits_addr), + .io_dm_scalar_rd_bits_data (_dm_io_scalar_rd_bits_data), + .io_dm_scalar_rs_idx (_dm_io_scalar_rs_idx), + .io_dm_scalar_rs_data (_core_io_dm_scalar_rs_data), + .io_dm_float_rd_valid (_dm_io_float_rd_valid), + .io_dm_float_rd_addr (_dm_io_float_rd_addr), + .io_dm_float_rd_data_mantissa (_dm_io_float_rd_data_mantissa), + .io_dm_float_rd_data_exponent (_dm_io_float_rd_data_exponent), + .io_dm_float_rd_data_sign (_dm_io_float_rd_data_sign), + .io_dm_float_rs_valid (_dm_io_float_rs_valid), + .io_dm_float_rs_addr (_dm_io_float_rs_addr), + .io_dm_float_rs_data_mantissa (_core_io_dm_float_rs_data_mantissa), + .io_dm_float_rs_data_exponent (_core_io_dm_float_rs_data_exponent), + .io_dm_float_rs_data_sign (_core_io_dm_float_rs_data_sign), + .io_dm_debug_mode (_core_io_dm_debug_mode), + .io_ibus_valid (_core_io_ibus_valid), + .io_ibus_ready (inItcm ? inItcmReg : _ibus2axi_io_ibus_ready), + .io_ibus_addr (_core_io_ibus_addr), + .io_ibus_rdata + (inItcmReg ? _itcmArbiter_io_source_0_readData_bits : _ibus2axi_io_ibus_rdata), + .io_ibus_fault_valid (_ibus2axi_io_ibus_fault_valid), + .io_dbus_valid (_core_io_dbus_valid), + .io_dbus_write (_core_io_dbus_write), + .io_dbus_addr (_core_io_dbus_addr), + .io_dbus_wdata (_core_io_dbus_wdata), + .io_dbus_wmask (_core_io_dbus_wmask), + .io_dbus_rdata (_dtcmArbiter_io_source_0_readData_bits), + .io_ebus_dbus_valid (_core_io_ebus_dbus_valid), + .io_ebus_dbus_ready (_ebus2axi_io_dbus_ready), + .io_ebus_dbus_write (_core_io_ebus_dbus_write), + .io_ebus_dbus_addr (_core_io_ebus_dbus_addr), + .io_ebus_dbus_size (_core_io_ebus_dbus_size), + .io_ebus_dbus_wdata (_core_io_ebus_dbus_wdata), + .io_ebus_dbus_wmask (_core_io_ebus_dbus_wmask), + .io_ebus_dbus_rdata (_ebus2axi_io_dbus_rdata), + .io_ebus_fault_valid (_ebus2axi_io_fault_valid) ); TCM128 itcm ( .clock (_rst_sync_clk_o), @@ -17623,9 +23175,7 @@ module CoreMiniAxi( .io_sram_mask_15 (_itcmWrapper_io_sram_mask_15) ); FabricArbiter itcmArbiter ( - .clock (_rst_sync_clk_o), - .reset (_global_reset_T_2), - .io_source_0_readDataAddr_valid (_core_io_ibus_valid), + .io_source_0_readDataAddr_valid (_core_io_ibus_valid & inItcm), .io_source_0_readDataAddr_bits (_core_io_ibus_addr), .io_source_0_readData_bits (_itcmArbiter_io_source_0_readData_bits), .io_source_0_writeDataAddr_valid (1'h0), @@ -17640,7 +23190,15 @@ module CoreMiniAxi( .io_source_1_writeDataAddr_bits (_fabricMux_io_ports_0_writeDataAddr_bits), .io_source_1_writeDataBits (_fabricMux_io_ports_0_writeDataBits), .io_source_1_writeDataStrb (_fabricMux_io_ports_0_writeDataStrb), - .io_fabricBusy (_itcmArbiter_io_fabricBusy), + .io_source_2_readDataAddr_valid (_dm_io_itcm_readDataAddr_valid), + .io_source_2_readDataAddr_bits (_dm_io_itcm_readDataAddr_bits), + .io_source_2_readData_valid (_itcmArbiter_io_source_2_readData_valid), + .io_source_2_readData_bits (_itcmArbiter_io_source_2_readData_bits), + .io_source_2_writeDataAddr_valid (_dm_io_itcm_writeDataAddr_valid), + .io_source_2_writeDataAddr_bits (_dm_io_itcm_writeDataAddr_bits), + .io_source_2_writeDataBits (_dm_io_itcm_writeDataBits), + .io_source_2_writeDataStrb (_dm_io_itcm_writeDataStrb), + .io_fabricBusy_1 (_itcmArbiter_io_fabricBusy_1), .io_port_readDataAddr_valid (_itcmArbiter_io_port_readDataAddr_valid), .io_port_readDataAddr_bits (_itcmArbiter_io_port_readDataAddr_bits), .io_port_readData_valid (_itcmWrapper_io_fabric_readData_valid), @@ -17650,8 +23208,24 @@ module CoreMiniAxi( .io_port_writeDataBits (_itcmArbiter_io_port_writeDataBits), .io_port_writeDataStrb (_itcmArbiter_io_port_writeDataStrb) ); + IBus2Axi ibus2axi ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_ibus_valid (_core_io_ibus_valid & (|(_core_io_ibus_addr[31:13]))), + .io_ibus_ready (_ibus2axi_io_ibus_ready), + .io_ibus_addr (_core_io_ibus_addr), + .io_ibus_rdata (_ibus2axi_io_ibus_rdata), + .io_ibus_fault_valid (_ibus2axi_io_ibus_fault_valid), + .io_axi_addr_ready (_readAddrArb_io_in_1_ready), + .io_axi_addr_valid (_ibus2axi_io_axi_addr_valid), + .io_axi_addr_bits_addr (_ibus2axi_io_axi_addr_bits_addr), + .io_axi_data_valid (_readDataSkid_q_io_deq_valid & _ibus2axi_io_axi_data_valid_T), + .io_axi_data_bits_data (_readDataSkid_q_io_deq_bits_data), + .io_axi_data_bits_resp (_readDataSkid_q_io_deq_bits_resp) + ); TCM128_1 dtcm ( .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), .io_addr (_dtcmWrapper_io_sram_address), .io_enable (_dtcmWrapper_io_sram_enable), .io_write (_dtcmWrapper_io_sram_isWrite), @@ -17768,8 +23342,6 @@ module CoreMiniAxi( .io_sram_mask_15 (_dtcmWrapper_io_sram_mask_15) ); FabricArbiter dtcmArbiter ( - .clock (_rst_sync_clk_o), - .reset (_global_reset_T_2), .io_source_0_readDataAddr_valid (_core_io_dbus_valid & ~_core_io_dbus_write), .io_source_0_readDataAddr_bits (_core_io_dbus_addr), .io_source_0_readData_bits (_dtcmArbiter_io_source_0_readData_bits), @@ -17785,7 +23357,15 @@ module CoreMiniAxi( .io_source_1_writeDataAddr_bits (_fabricMux_io_ports_1_writeDataAddr_bits), .io_source_1_writeDataBits (_fabricMux_io_ports_1_writeDataBits), .io_source_1_writeDataStrb (_fabricMux_io_ports_1_writeDataStrb), - .io_fabricBusy (_dtcmArbiter_io_fabricBusy), + .io_source_2_readDataAddr_valid (_dm_io_dtcm_readDataAddr_valid), + .io_source_2_readDataAddr_bits (_dm_io_dtcm_readDataAddr_bits), + .io_source_2_readData_valid (_dtcmArbiter_io_source_2_readData_valid), + .io_source_2_readData_bits (_dtcmArbiter_io_source_2_readData_bits), + .io_source_2_writeDataAddr_valid (_dm_io_dtcm_writeDataAddr_valid), + .io_source_2_writeDataAddr_bits (_dm_io_dtcm_writeDataAddr_bits), + .io_source_2_writeDataBits (_dm_io_dtcm_writeDataBits), + .io_source_2_writeDataStrb (_dm_io_dtcm_writeDataStrb), + .io_fabricBusy_1 (_dtcmArbiter_io_fabricBusy_1), .io_port_readDataAddr_valid (_dtcmArbiter_io_port_readDataAddr_valid), .io_port_readDataAddr_bits (_dtcmArbiter_io_port_readDataAddr_bits), .io_port_readData_valid (_dtcmWrapper_io_fabric_readData_valid), @@ -17831,14 +23411,14 @@ module CoreMiniAxi( .io_ports_2_writeDataAddr_bits (_fabricMux_io_ports_2_writeDataAddr_bits), .io_ports_2_writeDataBits (_fabricMux_io_ports_2_writeDataBits), .io_ports_2_writeResp (_csr_io_fabric_writeResp), - .io_periBusy_0 (_itcmArbiter_io_fabricBusy), - .io_periBusy_1 (_dtcmArbiter_io_fabricBusy) + .io_periBusy_0 (_itcmArbiter_io_fabricBusy_1), + .io_periBusy_1 (_dtcmArbiter_io_fabricBusy_1) ); AxiSlave axiSlave ( .clock (_rst_sync_clk_o), .reset (_global_reset_T_2), .io_axi_write_addr_ready (_axiSlave_io_axi_write_addr_ready), - .io_axi_write_addr_valid (io_axi_slave_write_addr_valid & axiSlaveEnable), + .io_axi_write_addr_valid (io_axi_slave_write_addr_valid & axiEnable), .io_axi_write_addr_bits_addr (io_axi_slave_write_addr_bits_addr), .io_axi_write_addr_bits_prot (io_axi_slave_write_addr_bits_prot), .io_axi_write_addr_bits_id (io_axi_slave_write_addr_bits_id), @@ -17850,2269 +23430,442 @@ module CoreMiniAxi( .io_axi_write_addr_bits_qos (io_axi_slave_write_addr_bits_qos), .io_axi_write_addr_bits_region (io_axi_slave_write_addr_bits_region), .io_axi_write_data_ready (_axiSlave_io_axi_write_data_ready), - .io_axi_write_data_valid (io_axi_slave_write_data_valid & axiSlaveEnable), + .io_axi_write_data_valid (io_axi_slave_write_data_valid & axiEnable), .io_axi_write_data_bits_data (io_axi_slave_write_data_bits_data), .io_axi_write_data_bits_last (io_axi_slave_write_data_bits_last), .io_axi_write_data_bits_strb (io_axi_slave_write_data_bits_strb), - .io_axi_write_resp_ready (io_axi_slave_write_resp_ready & axiSlaveEnable), + .io_axi_write_resp_ready (io_axi_slave_write_resp_ready & axiEnable), .io_axi_write_resp_valid (_axiSlave_io_axi_write_resp_valid), .io_axi_write_resp_bits_id (io_axi_slave_write_resp_bits_id), .io_axi_write_resp_bits_resp (io_axi_slave_write_resp_bits_resp), .io_axi_read_addr_ready (_axiSlave_io_axi_read_addr_ready), - .io_axi_read_addr_valid (io_axi_slave_read_addr_valid & axiSlaveEnable), + .io_axi_read_addr_valid (io_axi_slave_read_addr_valid & axiEnable), .io_axi_read_addr_bits_addr (io_axi_slave_read_addr_bits_addr), .io_axi_read_addr_bits_prot (io_axi_slave_read_addr_bits_prot), .io_axi_read_addr_bits_id (io_axi_slave_read_addr_bits_id), - .io_axi_read_addr_bits_len (io_axi_slave_read_addr_bits_len), - .io_axi_read_addr_bits_size (io_axi_slave_read_addr_bits_size), - .io_axi_read_addr_bits_burst (io_axi_slave_read_addr_bits_burst), - .io_axi_read_addr_bits_lock (io_axi_slave_read_addr_bits_lock), - .io_axi_read_addr_bits_cache (io_axi_slave_read_addr_bits_cache), - .io_axi_read_addr_bits_qos (io_axi_slave_read_addr_bits_qos), - .io_axi_read_addr_bits_region (io_axi_slave_read_addr_bits_region), - .io_axi_read_data_ready (io_axi_slave_read_data_ready & axiSlaveEnable), - .io_axi_read_data_valid (_axiSlave_io_axi_read_data_valid), - .io_axi_read_data_bits_data (io_axi_slave_read_data_bits_data), - .io_axi_read_data_bits_id (io_axi_slave_read_data_bits_id), - .io_axi_read_data_bits_resp (io_axi_slave_read_data_bits_resp), - .io_axi_read_data_bits_last (io_axi_slave_read_data_bits_last), - .io_fabric_readDataAddr_valid (_axiSlave_io_fabric_readDataAddr_valid), - .io_fabric_readDataAddr_bits (_axiSlave_io_fabric_readDataAddr_bits), - .io_fabric_readData_valid (_fabricMux_io_source_readData_valid), - .io_fabric_readData_bits (_fabricMux_io_source_readData_bits), - .io_fabric_writeDataAddr_valid (_axiSlave_io_fabric_writeDataAddr_valid), - .io_fabric_writeDataAddr_bits (_axiSlave_io_fabric_writeDataAddr_bits), - .io_fabric_writeDataBits (_axiSlave_io_fabric_writeDataBits), - .io_fabric_writeDataStrb (_axiSlave_io_fabric_writeDataStrb), - .io_fabric_writeResp (_fabricMux_io_source_writeResp), - .io_periBusy (_fabricMux_io_fabricBusy) - ); - DBus2AxiV1 ebus2axi ( - .clock (_rst_sync_clk_o), - .reset (_global_reset_T_2), - .io_dbus_valid (_core_io_ebus_dbus_valid), - .io_dbus_ready (_ebus2axi_io_dbus_ready), - .io_dbus_write (_core_io_ebus_dbus_write), - .io_dbus_pc (_core_io_ebus_dbus_pc), - .io_dbus_addr (_core_io_ebus_dbus_addr), - .io_dbus_size (_core_io_ebus_dbus_size), - .io_dbus_wdata (_core_io_ebus_dbus_wdata), - .io_dbus_rdata (_ebus2axi_io_dbus_rdata), - .io_axi_write_addr_ready (io_axi_master_write_addr_ready), - .io_axi_write_addr_valid (io_axi_master_write_addr_valid), - .io_axi_write_addr_bits_addr (io_axi_master_write_addr_bits_addr), - .io_axi_write_addr_bits_prot (io_axi_master_write_addr_bits_prot), - .io_axi_write_addr_bits_id (io_axi_master_write_addr_bits_id), - .io_axi_write_addr_bits_len (io_axi_master_write_addr_bits_len), - .io_axi_write_addr_bits_size (io_axi_master_write_addr_bits_size), - .io_axi_write_addr_bits_burst (io_axi_master_write_addr_bits_burst), - .io_axi_write_addr_bits_lock (io_axi_master_write_addr_bits_lock), - .io_axi_write_addr_bits_cache (io_axi_master_write_addr_bits_cache), - .io_axi_write_addr_bits_qos (io_axi_master_write_addr_bits_qos), - .io_axi_write_addr_bits_region (io_axi_master_write_addr_bits_region), - .io_axi_write_data_ready (io_axi_master_write_data_ready), - .io_axi_write_data_valid (io_axi_master_write_data_valid), - .io_axi_write_data_bits_data (io_axi_master_write_data_bits_data), - .io_axi_write_data_bits_last (io_axi_master_write_data_bits_last), - .io_axi_write_data_bits_strb (io_axi_master_write_data_bits_strb), - .io_axi_write_resp_ready (io_axi_master_write_resp_ready), - .io_axi_write_resp_valid (io_axi_master_write_resp_valid), - .io_axi_write_resp_bits_id (io_axi_master_write_resp_bits_id), - .io_axi_write_resp_bits_resp (io_axi_master_write_resp_bits_resp), - .io_axi_read_addr_ready (io_axi_master_read_addr_ready), - .io_axi_read_addr_valid (io_axi_master_read_addr_valid), - .io_axi_read_addr_bits_addr (io_axi_master_read_addr_bits_addr), - .io_axi_read_addr_bits_prot (io_axi_master_read_addr_bits_prot), - .io_axi_read_addr_bits_id (io_axi_master_read_addr_bits_id), - .io_axi_read_addr_bits_len (io_axi_master_read_addr_bits_len), - .io_axi_read_addr_bits_size (io_axi_master_read_addr_bits_size), - .io_axi_read_addr_bits_burst (io_axi_master_read_addr_bits_burst), - .io_axi_read_addr_bits_lock (io_axi_master_read_addr_bits_lock), - .io_axi_read_addr_bits_cache (io_axi_master_read_addr_bits_cache), - .io_axi_read_addr_bits_qos (io_axi_master_read_addr_bits_qos), - .io_axi_read_addr_bits_region (io_axi_master_read_addr_bits_region), - .io_axi_read_data_ready (io_axi_master_read_data_ready), - .io_axi_read_data_valid (io_axi_master_read_data_valid), - .io_axi_read_data_bits_data (io_axi_master_read_data_bits_data), - .io_axi_read_data_bits_id (io_axi_master_read_data_bits_id), - .io_axi_read_data_bits_resp (io_axi_master_read_data_bits_resp), - .io_axi_read_data_bits_last (io_axi_master_read_data_bits_last), - .io_fault_valid (_ebus2axi_io_fault_valid), - .io_fault_bits_write (_ebus2axi_io_fault_bits_write), - .io_fault_bits_addr (_ebus2axi_io_fault_bits_addr), - .io_fault_bits_epc (_ebus2axi_io_fault_bits_epc) - ); - assign io_axi_slave_write_addr_ready = - _axiSlave_io_axi_write_addr_ready & axiSlaveEnable; - assign io_axi_slave_write_data_ready = - _axiSlave_io_axi_write_data_ready & axiSlaveEnable; - assign io_axi_slave_write_resp_valid = - _axiSlave_io_axi_write_resp_valid & axiSlaveEnable; - assign io_axi_slave_read_addr_ready = _axiSlave_io_axi_read_addr_ready & axiSlaveEnable; - assign io_axi_slave_read_data_valid = _axiSlave_io_axi_read_data_valid & axiSlaveEnable; - assign io_halted = _core_io_halted; - assign io_fault = _core_io_fault; - assign io_wfi = _core_io_wfi; -endmodule - - -// ----- 8< ----- FILE "verification/cover/layers-CoreMiniAxi-Verification_Cover.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 -`ifndef layers_CoreMiniAxi_Verification_Cover -`define layers_CoreMiniAxi_Verification_Cover -`endif // layers_CoreMiniAxi_Verification_Cover - -// ----- 8< ----- FILE "verification/assume/layers-CoreMiniAxi-Verification_Assume.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 -`ifndef layers_CoreMiniAxi_Verification_Assume -`define layers_CoreMiniAxi_Verification_Assume -`endif // layers_CoreMiniAxi_Verification_Assume - -// ----- 8< ----- FILE "verification/assert/layers-CoreMiniAxi-Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 -`ifndef layers_CoreMiniAxi_Verification_Assert -`define layers_CoreMiniAxi_Verification_Assert -bind Regfile Regfile_Verification_Assert verification_Assert ( - ._GEN (valid_1), - ._GEN_0 (valid_2), - ._GEN_1 (_valid_T), - ._GEN_2 (_valid_T_8), - ._GEN_3 (_valid_T_10), - ._GEN_4 (valid_3), - .reset (reset), - ._GEN_5 (1'h1), - ._GEN_6 (valid_1_1), - ._GEN_7 (valid_2_1), - ._GEN_8 (_valid_T_12), - ._GEN_9 (_valid_T_20), - ._GEN_10 (_valid_T_22), - ._GEN_11 (valid_3_1), - ._GEN_12 (valid_1_2), - ._GEN_13 (valid_2_2), - ._GEN_14 (_valid_T_24), - ._GEN_15 (_valid_T_32), - ._GEN_16 (_valid_T_34), - ._GEN_17 (valid_3_2), - ._GEN_18 (valid_1_3), - ._GEN_19 (valid_2_3), - ._GEN_20 (_valid_T_36), - ._GEN_21 (_valid_T_44), - ._GEN_22 (_valid_T_46), - ._GEN_23 (valid_3_3), - ._GEN_24 (valid_1_4), - ._GEN_25 (valid_2_4), - ._GEN_26 (_valid_T_48), - ._GEN_27 (_valid_T_56), - ._GEN_28 (_valid_T_58), - ._GEN_29 (valid_3_4), - ._GEN_30 (valid_1_5), - ._GEN_31 (valid_2_5), - ._GEN_32 (_valid_T_60), - ._GEN_33 (_valid_T_68), - ._GEN_34 (_valid_T_70), - ._GEN_35 (valid_3_5), - ._GEN_36 (valid_1_6), - ._GEN_37 (valid_2_6), - ._GEN_38 (_valid_T_72), - ._GEN_39 (_valid_T_80), - ._GEN_40 (_valid_T_82), - ._GEN_41 (valid_3_6), - ._GEN_42 (valid_1_7), - ._GEN_43 (valid_2_7), - ._GEN_44 (_valid_T_84), - ._GEN_45 (_valid_T_92), - ._GEN_46 (_valid_T_94), - ._GEN_47 (valid_3_7), - ._GEN_48 (valid_1_8), - ._GEN_49 (valid_2_8), - ._GEN_50 (_valid_T_96), - ._GEN_51 (_valid_T_104), - ._GEN_52 (_valid_T_106), - ._GEN_53 (valid_3_8), - ._GEN_54 (valid_1_9), - ._GEN_55 (valid_2_9), - ._GEN_56 (_valid_T_108), - ._GEN_57 (_valid_T_116), - ._GEN_58 (_valid_T_118), - ._GEN_59 (valid_3_9), - ._GEN_60 (valid_1_10), - ._GEN_61 (valid_2_10), - ._GEN_62 (_valid_T_120), - ._GEN_63 (_valid_T_128), - ._GEN_64 (_valid_T_130), - ._GEN_65 (valid_3_10), - ._GEN_66 (valid_1_11), - ._GEN_67 (valid_2_11), - ._GEN_68 (_valid_T_132), - ._GEN_69 (_valid_T_140), - ._GEN_70 (_valid_T_142), - ._GEN_71 (valid_3_11), - ._GEN_72 (valid_1_12), - ._GEN_73 (valid_2_12), - ._GEN_74 (_valid_T_144), - ._GEN_75 (_valid_T_152), - ._GEN_76 (_valid_T_154), - ._GEN_77 (valid_3_12), - ._GEN_78 (valid_1_13), - ._GEN_79 (valid_2_13), - ._GEN_80 (_valid_T_156), - ._GEN_81 (_valid_T_164), - ._GEN_82 (_valid_T_166), - ._GEN_83 (valid_3_13), - ._GEN_84 (valid_1_14), - ._GEN_85 (valid_2_14), - ._GEN_86 (_valid_T_168), - ._GEN_87 (_valid_T_176), - ._GEN_88 (_valid_T_178), - ._GEN_89 (valid_3_14), - ._GEN_90 (valid_1_15), - ._GEN_91 (valid_2_15), - ._GEN_92 (_valid_T_180), - ._GEN_93 (_valid_T_188), - ._GEN_94 (_valid_T_190), - ._GEN_95 (valid_3_15), - ._GEN_96 (valid_1_16), - ._GEN_97 (valid_2_16), - ._GEN_98 (_valid_T_192), - ._GEN_99 (_valid_T_200), - ._GEN_100 (_valid_T_202), - ._GEN_101 (valid_3_16), - ._GEN_102 (valid_1_17), - ._GEN_103 (valid_2_17), - ._GEN_104 (_valid_T_204), - ._GEN_105 (_valid_T_212), - ._GEN_106 (_valid_T_214), - ._GEN_107 (valid_3_17), - ._GEN_108 (valid_1_18), - ._GEN_109 (valid_2_18), - ._GEN_110 (_valid_T_216), - ._GEN_111 (_valid_T_224), - ._GEN_112 (_valid_T_226), - ._GEN_113 (valid_3_18), - ._GEN_114 (valid_1_19), - ._GEN_115 (valid_2_19), - ._GEN_116 (_valid_T_228), - ._GEN_117 (_valid_T_236), - ._GEN_118 (_valid_T_238), - ._GEN_119 (valid_3_19), - ._GEN_120 (valid_1_20), - ._GEN_121 (valid_2_20), - ._GEN_122 (_valid_T_240), - ._GEN_123 (_valid_T_248), - ._GEN_124 (_valid_T_250), - ._GEN_125 (valid_3_20), - ._GEN_126 (valid_1_21), - ._GEN_127 (valid_2_21), - ._GEN_128 (_valid_T_252), - ._GEN_129 (_valid_T_260), - ._GEN_130 (_valid_T_262), - ._GEN_131 (valid_3_21), - ._GEN_132 (valid_1_22), - ._GEN_133 (valid_2_22), - ._GEN_134 (_valid_T_264), - ._GEN_135 (_valid_T_272), - ._GEN_136 (_valid_T_274), - ._GEN_137 (valid_3_22), - ._GEN_138 (valid_1_23), - ._GEN_139 (valid_2_23), - ._GEN_140 (_valid_T_276), - ._GEN_141 (_valid_T_284), - ._GEN_142 (_valid_T_286), - ._GEN_143 (valid_3_23), - ._GEN_144 (valid_1_24), - ._GEN_145 (valid_2_24), - ._GEN_146 (_valid_T_288), - ._GEN_147 (_valid_T_296), - ._GEN_148 (_valid_T_298), - ._GEN_149 (valid_3_24), - ._GEN_150 (valid_1_25), - ._GEN_151 (valid_2_25), - ._GEN_152 (_valid_T_300), - ._GEN_153 (_valid_T_308), - ._GEN_154 (_valid_T_310), - ._GEN_155 (valid_3_25), - ._GEN_156 (valid_1_26), - ._GEN_157 (valid_2_26), - ._GEN_158 (_valid_T_312), - ._GEN_159 (_valid_T_320), - ._GEN_160 (_valid_T_322), - ._GEN_161 (valid_3_26), - ._GEN_162 (valid_1_27), - ._GEN_163 (valid_2_27), - ._GEN_164 (_valid_T_324), - ._GEN_165 (_valid_T_332), - ._GEN_166 (_valid_T_334), - ._GEN_167 (valid_3_27), - ._GEN_168 (valid_1_28), - ._GEN_169 (valid_2_28), - ._GEN_170 (_valid_T_336), - ._GEN_171 (_valid_T_344), - ._GEN_172 (_valid_T_346), - ._GEN_173 (valid_3_28), - ._GEN_174 (valid_1_29), - ._GEN_175 (valid_2_29), - ._GEN_176 (_valid_T_348), - ._GEN_177 (_valid_T_356), - ._GEN_178 (_valid_T_358), - ._GEN_179 (valid_3_29), - ._GEN_180 (valid_1_30), - ._GEN_181 (valid_2_30), - ._GEN_182 (_valid_T_360), - ._GEN_183 (_valid_T_368), - ._GEN_184 (_valid_T_370), - ._GEN_185 (valid_3_30), - .write_fail (write_fail), - .write_fail_1 (write_fail_1), - .write_fail_2 (write_fail_2), - .write_fail_3 (write_fail_3), - .write_fail_4 (write_fail_4), - .write_fail_5 (write_fail_5), - .write_fail_6 (write_fail_6), - .write_fail_7 (write_fail_7), - .write_fail_8 (write_fail_8), - .write_fail_9 (write_fail_9), - .write_fail_10 (write_fail_10), - .write_fail_11 (write_fail_11), - .write_fail_12 (write_fail_12), - .write_fail_13 (write_fail_13), - .write_fail_14 (write_fail_14), - .scoreboard_error (scoreboard_error), - .clock (clock) -); -bind CircularBufferMulti CircularBufferMulti_Verification_Assert verification_Assert ( - .io_nEnqueued (nEnqueued), - .io_enqValid (io_enqValid), - .io_deqReady (io_deqReady), - .reset (reset), - ._GEN (4'h8), - .clock (clock) -); -bind InstructionBuffer InstructionBuffer_Verification_Assert verification_Assert ( - ._GEN (_nReady_T), - ._GEN_0 (_nReady_T_1), - ._GEN_1 (_nReady_T_2), - ._GEN_2 (_nReady_T_3), - .reset (reset), - .clock (clock) -); -bind Csr Csr_Verification_Assert verification_Assert ( - ._GEN (fflagsEn), - ._GEN_0 (frmEn), - .csr_address (req_pipe_b_index), - ._GEN_1 (fcsrEn), - ._GEN_2 (mstatusEn), - ._GEN_3 (misaEn), - ._GEN_4 (mieEn), - ._GEN_5 (mtvecEn), - ._GEN_6 (mscratchEn), - ._GEN_7 (mepcEn), - ._GEN_8 (mcauseEn), - ._GEN_9 (mtvalEn), - ._GEN_10 (mcontext0En), - ._GEN_11 (mcontext1En), - ._GEN_12 (mcontext2En), - ._GEN_13 (mcontext3En), - ._GEN_14 (mcontext4En), - ._GEN_15 (mcontext5En), - ._GEN_16 (mcontext6En), - ._GEN_17 (mcontext7En), - ._GEN_18 (mpcEn), - ._GEN_19 (mspEn), - ._GEN_20 (mcycleEn), - ._GEN_21 (minstretEn), - ._GEN_22 (mcyclehEn), - ._GEN_23 (minstrethEn), - ._GEN_24 (mvendoridEn), - ._GEN_25 (marchidEn), - ._GEN_26 (mimpidEn), - ._GEN_27 (mhartidEn), - ._GEN_28 (kisaEn), - ._GEN_29 (kscm0En), - ._GEN_30 (kscm1En), - ._GEN_31 (kscm2En), - ._GEN_32 (kscm3En), - ._GEN_33 (kscm4En), - .req_valid (req_pipe_v), - .reset (reset), - .io_halted (halted), - .io_wfi (wfi), - .io_fault (fault), - .io_rs1_valid (io_rs1_valid), - .clock (clock) -); -bind Alu Alu_Verification_Assert verification_Assert ( - .io_rs1_valid (io_rs1_valid), - ._GEN (op == 5'hA), - .valid (valid), - .reset (reset), - .io_rs2_valid (io_rs2_valid), - ._rs1Only_WIRE_5 (op == 5'h15), - ._rs1Only_WIRE_4 (op == 5'h16), - ._rs1Only_WIRE_7 (op == 5'h1A), - ._rs1Only_WIRE_6 (op == 5'h19), - ._rs1Only_WIRE_1 (op == 5'hF), - ._rs1Only_WIRE_0 (op == 5'hE), - ._rs1Only_WIRE_3 (op == 5'h1B), - ._rs1Only_WIRE_2 (op == 5'h10), - .clock (clock) -); -bind Bru Bru_Verification_Assert verification_Assert ( - .io_rs1_valid (io_rs1_valid), - .stateReg_valid (stateReg_valid), - ._ignore_WIRE_5 (_ignore_T_5), - ._ignore_WIRE_4 (_ignore_T_4), - ._ignore_WIRE_7 (_ignore_T_7), - ._ignore_WIRE_6 (_ignore_T_6), - ._ignore_WIRE_1 (stateReg_bits_op == 4'h1), - ._ignore_WIRE_0 (~(|stateReg_bits_op)), - ._ignore_WIRE_3 (_ignore_T_3), - ._ignore_WIRE_2 (_ignore_T_2), - .reset (reset), - .io_rs2_valid (io_rs2_valid), - .clock (clock) -); -bind Bru_1 Bru_1_Verification_Assert verification_Assert ( - ._GEN (_ignore_T_6), - ._GEN_0 (_ignore_T_5), - ._GEN_1 (_ignore_T_3), - ._GEN_2 (_ignore_T_2), - ._GEN_3 (_ignore_T_4), - .reset (reset), - .io_rs1_valid (io_rs1_valid), - .stateReg_valid (stateReg_valid), - ._ignore_WIRE_5 (_ignore_T_5), - ._ignore_WIRE_4 (_ignore_T_4), - ._ignore_WIRE_7 (stateReg_bits_op == 4'hD), - ._ignore_WIRE_6 (_ignore_T_6), - ._ignore_WIRE_1 (stateReg_bits_op == 4'h1), - ._ignore_WIRE_0 (~(|stateReg_bits_op)), - ._ignore_WIRE_3 (_ignore_T_3), - ._ignore_WIRE_2 (_ignore_T_2), - .io_rs2_valid (io_rs2_valid), - .clock (clock) -); -bind FifoX FifoX_Verification_Assert verification_Assert ( - .reset (reset), - .mcount (mcount), - ._GEN (4'h8), - .clock (clock) -); -bind LsuV1 LsuV1_Verification_Assert verification_Assert ( - .ctrl_io_out_bits_addr (_ctrl_io_out_bits_addr), - .io_dbus_valid (io_dbus_valid_0), - .reset (reset), - .io_dbus_addr (io_dbus_addr_0), - .io_dbus_adrx ({1'h0, _ctrl_io_out_bits_adrx[30:0]}), - .ctrl_io_out_bits_fldst (_ctrl_io_out_bits_fldst), - .ctrl_io_out_bits_sldst (_ctrl_io_out_bits_sldst), - .ctrl_io_out_bits_vldst (_ctrl_io_out_bits_vldst), - ._GEN (1'h1), - .ctrl_io_out_valid (_ctrl_io_out_valid), - .data_io_out_bits_fldst (_data_io_out_bits_fldst), - .data_io_out_bits_sldst (_data_io_out_bits_sldst), - .data_io_out_valid (_data_io_out_valid), - .clock (clock) -); -bind Mlu Mlu_Verification_Assert verification_Assert ( - .io_rs1_0_valid (io_rs1_0_valid), - .stage2Input_q_io_deq_valid (_stage2Input_q_io_deq_valid), - ._GEN (_stage2Input_q_io_deq_bits_sel[0]), - .reset (reset), - .io_rs2_0_valid (io_rs2_0_valid), - .io_rs1_1_valid (io_rs1_1_valid), - ._GEN_0 (_stage2Input_q_io_deq_bits_sel[1]), - .io_rs2_1_valid (io_rs2_1_valid), - .io_rs1_2_valid (io_rs1_2_valid), - ._GEN_1 (_stage2Input_q_io_deq_bits_sel[2]), - .io_rs2_2_valid (io_rs2_2_valid), - .io_rs1_3_valid (io_rs1_3_valid), - ._GEN_2 (_stage2Input_q_io_deq_bits_sel[3]), - .io_rs2_3_valid (io_rs2_3_valid), - .clock (clock) -); -bind FloatCore FloatCore_Verification_Assert verification_Assert ( - .io_csr_out_frm (io_csr_out_frm), - ._GEN (1'h1), - ._GEN_0 (2'h2), - ._GEN_1 (2'h3), - ._GEN_2 (3'h4), - ._GEN_3 (3'h5), - ._GEN_4 (reset), - .clock (clock) -); -bind FRegfile FRegfile_Verification_Assert verification_Assert ( - .reset (reset), - .scoreboard_error (scoreboard_error), - .clock (clock) -); -bind SCore SCore_Verification_Assert verification_Assert ( - .csr_io_rd_valid (_csr_io_rd_valid), - .alu_0_io_rd_valid (_alu_0_io_rd_valid), - .bru_0_io_rd_valid (_bru_0_io_rd_valid), - .reset (reset), - ._GEN (1'h1), - .alu_1_io_rd_valid (_alu_1_io_rd_valid), - .bru_1_io_rd_valid (_bru_1_io_rd_valid), - .alu_2_io_rd_valid (_alu_2_io_rd_valid), - .bru_2_io_rd_valid (_bru_2_io_rd_valid), - .alu_3_io_rd_valid (_alu_3_io_rd_valid), - .bru_3_io_rd_valid (_bru_3_io_rd_valid), - .clock (clock) -); -bind FabricArbiter FabricArbiter_Verification_Assert verification_Assert ( - .io_source_0_readDataAddr_valid (io_source_0_readDataAddr_valid), - .io_source_0_writeDataAddr_valid (io_source_0_writeDataAddr_valid), - .reset (reset), - .io_source_1_readDataAddr_valid (io_source_1_readDataAddr_valid), - .io_source_1_writeDataAddr_valid (io_source_1_writeDataAddr_valid), - .clock (clock) -); -bind FabricMux FabricMux_Verification_Assert verification_Assert ( - .io_source_readDataAddr_valid (io_source_readDataAddr_valid), - .io_source_writeDataAddr_valid (io_source_writeDataAddr_valid), - .reset (reset), - ._GEN (portSelected_1), - ._GEN_0 (_portSelected_T_7), - ._GEN_1 (portSelected_0), - ._GEN_2 (1'h1), - .clock (clock) -); -bind AxiSlave AxiSlave_Verification_Assert verification_Assert ( - .readIssued (readIssued), - .reset (reset), - .readDataQueue_io_enq_ready (_readDataQueue_io_enq_ready), - .clock (clock) -); -bind FifoX_1 FifoX_1_Verification_Assert verification_Assert ( - .reset (reset), - .mcount (mcount), - ._GEN (2'h2), - .clock (clock) -); -bind FifoX_3 FifoX_3_Verification_Assert verification_Assert ( - .reset (reset), - .mcount (mcount), - ._GEN (2'h2), - .clock (clock) -); -bind DBus2AxiV1 DBus2AxiV1_Verification_Assert verification_Assert ( - .io_dbus_size (io_dbus_size), - ._GEN (1'h1), - .io_dbus_valid (io_dbus_valid), - .reset (reset), - .txnActive (txnActive), - ._GEN_0 (txnCount), - .readAddrQ_io_count (_readAddrQ_io_count), - ._GEN_1 (newTxn), - .io_axi_read_data_bits_id (io_axi_read_data_bits_id), - .io_axi_read_data_valid (io_axi_read_data_valid), - .writeAddrQ_io_count (_writeAddrQ_io_count), - .writeDataQ_io_count (_writeDataQ_io_count), - .io_axi_write_resp_bits_id (io_axi_write_resp_bits_id), - .io_axi_write_resp_valid (io_axi_write_resp_valid), - .clock (clock) -); -`endif // layers_CoreMiniAxi_Verification_Assert - -// ----- 8< ----- FILE "verification/assert/Regfile_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Regfile_Verification_Assert( - input _GEN, - _GEN_0, - _GEN_1, - _GEN_2, - _GEN_3, - _GEN_4, - reset, - _GEN_5, - _GEN_6, - _GEN_7, - _GEN_8, - _GEN_9, - _GEN_10, - _GEN_11, - _GEN_12, - _GEN_13, - _GEN_14, - _GEN_15, - _GEN_16, - _GEN_17, - _GEN_18, - _GEN_19, - _GEN_20, - _GEN_21, - _GEN_22, - _GEN_23, - _GEN_24, - _GEN_25, - _GEN_26, - _GEN_27, - _GEN_28, - _GEN_29, - _GEN_30, - _GEN_31, - _GEN_32, - _GEN_33, - _GEN_34, - _GEN_35, - _GEN_36, - _GEN_37, - _GEN_38, - _GEN_39, - _GEN_40, - _GEN_41, - _GEN_42, - _GEN_43, - _GEN_44, - _GEN_45, - _GEN_46, - _GEN_47, - _GEN_48, - _GEN_49, - _GEN_50, - _GEN_51, - _GEN_52, - _GEN_53, - _GEN_54, - _GEN_55, - _GEN_56, - _GEN_57, - _GEN_58, - _GEN_59, - _GEN_60, - _GEN_61, - _GEN_62, - _GEN_63, - _GEN_64, - _GEN_65, - _GEN_66, - _GEN_67, - _GEN_68, - _GEN_69, - _GEN_70, - _GEN_71, - _GEN_72, - _GEN_73, - _GEN_74, - _GEN_75, - _GEN_76, - _GEN_77, - _GEN_78, - _GEN_79, - _GEN_80, - _GEN_81, - _GEN_82, - _GEN_83, - _GEN_84, - _GEN_85, - _GEN_86, - _GEN_87, - _GEN_88, - _GEN_89, - _GEN_90, - _GEN_91, - _GEN_92, - _GEN_93, - _GEN_94, - _GEN_95, - _GEN_96, - _GEN_97, - _GEN_98, - _GEN_99, - _GEN_100, - _GEN_101, - _GEN_102, - _GEN_103, - _GEN_104, - _GEN_105, - _GEN_106, - _GEN_107, - _GEN_108, - _GEN_109, - _GEN_110, - _GEN_111, - _GEN_112, - _GEN_113, - _GEN_114, - _GEN_115, - _GEN_116, - _GEN_117, - _GEN_118, - _GEN_119, - _GEN_120, - _GEN_121, - _GEN_122, - _GEN_123, - _GEN_124, - _GEN_125, - _GEN_126, - _GEN_127, - _GEN_128, - _GEN_129, - _GEN_130, - _GEN_131, - _GEN_132, - _GEN_133, - _GEN_134, - _GEN_135, - _GEN_136, - _GEN_137, - _GEN_138, - _GEN_139, - _GEN_140, - _GEN_141, - _GEN_142, - _GEN_143, - _GEN_144, - _GEN_145, - _GEN_146, - _GEN_147, - _GEN_148, - _GEN_149, - _GEN_150, - _GEN_151, - _GEN_152, - _GEN_153, - _GEN_154, - _GEN_155, - _GEN_156, - _GEN_157, - _GEN_158, - _GEN_159, - _GEN_160, - _GEN_161, - _GEN_162, - _GEN_163, - _GEN_164, - _GEN_165, - _GEN_166, - _GEN_167, - _GEN_168, - _GEN_169, - _GEN_170, - _GEN_171, - _GEN_172, - _GEN_173, - _GEN_174, - _GEN_175, - _GEN_176, - _GEN_177, - _GEN_178, - _GEN_179, - _GEN_180, - _GEN_181, - _GEN_182, - _GEN_183, - _GEN_184, - _GEN_185, - write_fail, - write_fail_1, - write_fail_2, - write_fail_3, - write_fail_4, - write_fail_5, - write_fail_6, - write_fail_7, - write_fail_8, - write_fail_9, - write_fail_10, - write_fail_11, - write_fail_12, - write_fail_13, - write_fail_14, - scoreboard_error, - clock -); - - `ifndef SYNTHESIS - wire [2:0] _GEN_186 = {2'h0, _GEN_5}; - always @(posedge clock) begin - if (~reset & {1'h0, {1'h0, _GEN_1} + {1'h0, _GEN} + {1'h0, _GEN_0}} - + {1'h0, {1'h0, _GEN_4} + {1'h0, _GEN_2} + {1'h0, _GEN_3}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_8} + {1'h0, _GEN_6} + {1'h0, _GEN_7}} - + {1'h0, {1'h0, _GEN_11} + {1'h0, _GEN_9} + {1'h0, _GEN_10}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_14} + {1'h0, _GEN_12} + {1'h0, _GEN_13}} - + {1'h0, {1'h0, _GEN_17} + {1'h0, _GEN_15} + {1'h0, _GEN_16}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_20} + {1'h0, _GEN_18} + {1'h0, _GEN_19}} - + {1'h0, {1'h0, _GEN_23} + {1'h0, _GEN_21} + {1'h0, _GEN_22}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_26} + {1'h0, _GEN_24} + {1'h0, _GEN_25}} - + {1'h0, {1'h0, _GEN_29} + {1'h0, _GEN_27} + {1'h0, _GEN_28}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_32} + {1'h0, _GEN_30} + {1'h0, _GEN_31}} - + {1'h0, {1'h0, _GEN_35} + {1'h0, _GEN_33} + {1'h0, _GEN_34}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_38} + {1'h0, _GEN_36} + {1'h0, _GEN_37}} - + {1'h0, {1'h0, _GEN_41} + {1'h0, _GEN_39} + {1'h0, _GEN_40}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_44} + {1'h0, _GEN_42} + {1'h0, _GEN_43}} - + {1'h0, {1'h0, _GEN_47} + {1'h0, _GEN_45} + {1'h0, _GEN_46}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_50} + {1'h0, _GEN_48} + {1'h0, _GEN_49}} - + {1'h0, {1'h0, _GEN_53} + {1'h0, _GEN_51} + {1'h0, _GEN_52}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_56} + {1'h0, _GEN_54} + {1'h0, _GEN_55}} - + {1'h0, {1'h0, _GEN_59} + {1'h0, _GEN_57} + {1'h0, _GEN_58}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_62} + {1'h0, _GEN_60} + {1'h0, _GEN_61}} - + {1'h0, {1'h0, _GEN_65} + {1'h0, _GEN_63} + {1'h0, _GEN_64}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_68} + {1'h0, _GEN_66} + {1'h0, _GEN_67}} - + {1'h0, {1'h0, _GEN_71} + {1'h0, _GEN_69} + {1'h0, _GEN_70}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_74} + {1'h0, _GEN_72} + {1'h0, _GEN_73}} - + {1'h0, {1'h0, _GEN_77} + {1'h0, _GEN_75} + {1'h0, _GEN_76}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_80} + {1'h0, _GEN_78} + {1'h0, _GEN_79}} - + {1'h0, {1'h0, _GEN_83} + {1'h0, _GEN_81} + {1'h0, _GEN_82}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_86} + {1'h0, _GEN_84} + {1'h0, _GEN_85}} - + {1'h0, {1'h0, _GEN_89} + {1'h0, _GEN_87} + {1'h0, _GEN_88}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_92} + {1'h0, _GEN_90} + {1'h0, _GEN_91}} - + {1'h0, {1'h0, _GEN_95} + {1'h0, _GEN_93} + {1'h0, _GEN_94}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_98} + {1'h0, _GEN_96} + {1'h0, _GEN_97}} - + {1'h0, - {1'h0, _GEN_101} + {1'h0, _GEN_99} + {1'h0, _GEN_100}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_104} + {1'h0, _GEN_102} + {1'h0, _GEN_103}} - + {1'h0, - {1'h0, _GEN_107} + {1'h0, _GEN_105} + {1'h0, _GEN_106}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_110} + {1'h0, _GEN_108} + {1'h0, _GEN_109}} - + {1'h0, - {1'h0, _GEN_113} + {1'h0, _GEN_111} + {1'h0, _GEN_112}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_116} + {1'h0, _GEN_114} + {1'h0, _GEN_115}} - + {1'h0, - {1'h0, _GEN_119} + {1'h0, _GEN_117} + {1'h0, _GEN_118}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_122} + {1'h0, _GEN_120} + {1'h0, _GEN_121}} - + {1'h0, - {1'h0, _GEN_125} + {1'h0, _GEN_123} + {1'h0, _GEN_124}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_128} + {1'h0, _GEN_126} + {1'h0, _GEN_127}} - + {1'h0, - {1'h0, _GEN_131} + {1'h0, _GEN_129} + {1'h0, _GEN_130}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_134} + {1'h0, _GEN_132} + {1'h0, _GEN_133}} - + {1'h0, - {1'h0, _GEN_137} + {1'h0, _GEN_135} + {1'h0, _GEN_136}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_140} + {1'h0, _GEN_138} + {1'h0, _GEN_139}} - + {1'h0, - {1'h0, _GEN_143} + {1'h0, _GEN_141} + {1'h0, _GEN_142}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_146} + {1'h0, _GEN_144} + {1'h0, _GEN_145}} - + {1'h0, - {1'h0, _GEN_149} + {1'h0, _GEN_147} + {1'h0, _GEN_148}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_152} + {1'h0, _GEN_150} + {1'h0, _GEN_151}} - + {1'h0, - {1'h0, _GEN_155} + {1'h0, _GEN_153} + {1'h0, _GEN_154}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_158} + {1'h0, _GEN_156} + {1'h0, _GEN_157}} - + {1'h0, - {1'h0, _GEN_161} + {1'h0, _GEN_159} + {1'h0, _GEN_160}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_164} + {1'h0, _GEN_162} + {1'h0, _GEN_163}} - + {1'h0, - {1'h0, _GEN_167} + {1'h0, _GEN_165} + {1'h0, _GEN_166}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_170} + {1'h0, _GEN_168} + {1'h0, _GEN_169}} - + {1'h0, - {1'h0, _GEN_173} + {1'h0, _GEN_171} + {1'h0, _GEN_172}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_176} + {1'h0, _GEN_174} + {1'h0, _GEN_175}} - + {1'h0, - {1'h0, _GEN_179} + {1'h0, _GEN_177} + {1'h0, _GEN_178}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, {1'h0, _GEN_182} + {1'h0, _GEN_180} + {1'h0, _GEN_181}} - + {1'h0, - {1'h0, _GEN_185} + {1'h0, _GEN_183} + {1'h0, _GEN_184}} > _GEN_186) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:148\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_1) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_2) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_3) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_4) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_5) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_6) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_7) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_8) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_9) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_10) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_11) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_12) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_13) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & write_fail_14) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:234\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & scoreboard_error) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Regfile.scala:241\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/CircularBufferMulti_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module CircularBufferMulti_Verification_Assert( - input [3:0] io_nEnqueued, - input [2:0] io_enqValid, - io_deqReady, - input reset, - input [3:0] _GEN, - input clock -); - - `ifndef SYNTHESIS - wire [4:0] _GEN_0 = {1'h0, io_nEnqueued}; - wire [4:0] _GEN_1 = {2'h0, io_enqValid}; - always @(posedge clock) begin - if (~reset & {1'h0, _GEN_0 + _GEN_1} - {3'h0, io_deqReady} > {2'h0, _GEN}) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at CircularBufferMulti.scala:43\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_1 > {1'h0, _GEN} - _GEN_0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at CircularBufferMulti.scala:44\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, io_deqReady} > io_nEnqueued) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at CircularBufferMulti.scala:46\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/InstructionBuffer_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module InstructionBuffer_Verification_Assert( - input _GEN, - _GEN_0, - _GEN_1, - _GEN_2, - reset, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & (~_GEN & _GEN_0 | ~_GEN_0 & _GEN_1 | ~_GEN_1 & _GEN_2)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed: OneHotInOrder - Instructions not dispatched in order.\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/Csr_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Csr_Verification_Assert( - input _GEN, - _GEN_0, - input [11:0] csr_address, - input _GEN_1, - _GEN_2, - _GEN_3, - _GEN_4, - _GEN_5, - _GEN_6, - _GEN_7, - _GEN_8, - _GEN_9, - _GEN_10, - _GEN_11, - _GEN_12, - _GEN_13, - _GEN_14, - _GEN_15, - _GEN_16, - _GEN_17, - _GEN_18, - _GEN_19, - _GEN_20, - _GEN_21, - _GEN_22, - _GEN_23, - _GEN_24, - _GEN_25, - _GEN_26, - _GEN_27, - _GEN_28, - _GEN_29, - _GEN_30, - _GEN_31, - _GEN_32, - _GEN_33, - req_valid, - reset, - io_halted, - io_wfi, - io_fault, - io_rs1_valid, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & req_valid - & ~(_GEN | _GEN_0 | _GEN_1 | csr_address == 12'h8 | csr_address == 12'h9 - | csr_address == 12'hA | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 - | _GEN_8 | _GEN_9 | csr_address == 12'h7A0 | csr_address == 12'h7A1 - | csr_address == 12'h7A2 | csr_address == 12'h7A4 | csr_address == 12'h7B0 - | csr_address == 12'h7B1 | csr_address == 12'h7B2 | csr_address == 12'h7B3 - | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13 | _GEN_14 | _GEN_15 | _GEN_16 - | _GEN_17 | _GEN_18 | _GEN_19 | _GEN_20 | _GEN_21 | _GEN_22 | _GEN_23 - | csr_address == 12'hC20 | csr_address == 12'hC21 | csr_address == 12'hC22 - | _GEN_24 | _GEN_25 | _GEN_26 | _GEN_27 | _GEN_28 | _GEN_29 | _GEN_30 - | _GEN_31 | _GEN_32 | _GEN_33)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Csr.scala:301\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_fault & ~io_halted & ~io_wfi) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Csr.scala:373\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & req_valid & ~io_rs1_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Csr.scala:603\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/Alu_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Alu_Verification_Assert( - input io_rs1_valid, - _GEN, - valid, - reset, - io_rs2_valid, - _rs1Only_WIRE_5, - _rs1Only_WIRE_4, - _rs1Only_WIRE_7, - _rs1Only_WIRE_6, - _rs1Only_WIRE_1, - _rs1Only_WIRE_0, - _rs1Only_WIRE_3, - _rs1Only_WIRE_2, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & valid & ~io_rs1_valid & ~_GEN) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Alu.scala:159\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & valid & ~io_rs2_valid - & {_rs1Only_WIRE_7, - _rs1Only_WIRE_6, - _rs1Only_WIRE_5, - _rs1Only_WIRE_4, - _rs1Only_WIRE_3, - _rs1Only_WIRE_2, - _rs1Only_WIRE_1, - _rs1Only_WIRE_0} == 8'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Alu.scala:160\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/Bru_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Bru_Verification_Assert( - input io_rs1_valid, - stateReg_valid, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_1, - _ignore_WIRE_0, - _ignore_WIRE_3, - _ignore_WIRE_2, - reset, - io_rs2_valid, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset - & {~(stateReg_valid & ~io_rs1_valid), - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_3, - _ignore_WIRE_2, - _ignore_WIRE_1, - _ignore_WIRE_0} == 9'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Bru.scala:264\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {~(stateReg_valid & ~io_rs2_valid), - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_3, - _ignore_WIRE_2, - _ignore_WIRE_1, - _ignore_WIRE_0} == 9'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Bru.scala:265\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/Bru_1_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Bru_1_Verification_Assert( - input _GEN, - _GEN_0, - _GEN_1, - _GEN_2, - _GEN_3, - reset, - io_rs1_valid, - stateReg_valid, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_1, - _ignore_WIRE_0, - _ignore_WIRE_3, - _ignore_WIRE_2, - io_rs2_valid, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & (|{_GEN, _GEN_0, _GEN_3, _GEN_1, _GEN_2})) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Bru.scala:162\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {~(stateReg_valid & ~io_rs1_valid), - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_3, - _ignore_WIRE_2, - _ignore_WIRE_1, - _ignore_WIRE_0} == 9'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Bru.scala:264\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {~(stateReg_valid & ~io_rs2_valid), - _ignore_WIRE_7, - _ignore_WIRE_6, - _ignore_WIRE_5, - _ignore_WIRE_4, - _ignore_WIRE_3, - _ignore_WIRE_2, - _ignore_WIRE_1, - _ignore_WIRE_0} == 9'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Bru.scala:265\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FifoX_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FifoX_Verification_Assert( - input reset, - input [3:0] mcount, - _GEN, - input clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & mcount > _GEN) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at FifoX.scala:158\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/LsuV1_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module LsuV1_Verification_Assert( - input [31:0] ctrl_io_out_bits_addr, - input io_dbus_valid, - reset, - input [31:0] io_dbus_addr, - io_dbus_adrx, - input ctrl_io_out_bits_fldst, - ctrl_io_out_bits_sldst, - ctrl_io_out_bits_vldst, - _GEN, - ctrl_io_out_valid, - data_io_out_bits_fldst, - data_io_out_bits_sldst, - data_io_out_valid, - clock -); - - `ifndef SYNTHESIS - wire [1:0] _GEN_0 = {1'h0, _GEN}; - always @(posedge clock) begin - if (~reset & io_dbus_valid & ctrl_io_out_bits_addr[31]) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Lsu.scala:949\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_dbus_valid & io_dbus_addr[31]) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Lsu.scala:950\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_dbus_valid & io_dbus_adrx[31]) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Lsu.scala:951\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & ~(~ctrl_io_out_valid | {1'h0, ctrl_io_out_bits_vldst} - + {1'h0, ctrl_io_out_bits_sldst} - + {1'h0, ctrl_io_out_bits_fldst} <= _GEN_0)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Lsu.scala:1108\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & ~(~data_io_out_valid | {1'h0, data_io_out_bits_sldst} - + {1'h0, data_io_out_bits_fldst} <= _GEN_0)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Lsu.scala:1109\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/Mlu_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module Mlu_Verification_Assert( - input io_rs1_0_valid, - stage2Input_q_io_deq_valid, - _GEN, - reset, - io_rs2_0_valid, - io_rs1_1_valid, - _GEN_0, - io_rs2_1_valid, - io_rs1_2_valid, - _GEN_1, - io_rs2_2_valid, - io_rs1_3_valid, - _GEN_2, - io_rs2_3_valid, - clock -); - - `ifndef SYNTHESIS - wire _GEN_3 = stage2Input_q_io_deq_valid & _GEN; - wire _GEN_4 = stage2Input_q_io_deq_valid & _GEN_0; - wire _GEN_5 = stage2Input_q_io_deq_valid & _GEN_1; - wire _GEN_6 = stage2Input_q_io_deq_valid & _GEN_2; - always @(posedge clock) begin - if (~reset & _GEN_3 & ~io_rs1_0_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:120\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_3 & ~io_rs2_0_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:121\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_4 & ~io_rs1_1_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:120\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_4 & ~io_rs2_1_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:121\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_5 & ~io_rs1_2_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:120\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_5 & ~io_rs2_2_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:121\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_6 & ~io_rs1_3_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:120\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_6 & ~io_rs2_3_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Mlu.scala:121\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FloatCore_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FloatCore_Verification_Assert( - input [2:0] io_csr_out_frm, - input _GEN, - input [1:0] _GEN_0, - _GEN_1, - input [2:0] _GEN_2, - _GEN_3, - input _GEN_4, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~_GEN_4 - & ~(io_csr_out_frm == 3'h0 | io_csr_out_frm == {2'h0, _GEN} - | io_csr_out_frm == {1'h0, _GEN_0} | io_csr_out_frm == {1'h0, _GEN_1} - | io_csr_out_frm == _GEN_2 | io_csr_out_frm == _GEN_3 - | (&io_csr_out_frm))) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at FloatCore.scala:311\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FRegfile_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FRegfile_Verification_Assert( - input reset, - scoreboard_error, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & scoreboard_error) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at FRegfile.scala:47\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/SCore_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module SCore_Verification_Assert( - input csr_io_rd_valid, - alu_0_io_rd_valid, - bru_0_io_rd_valid, - reset, - _GEN, - alu_1_io_rd_valid, - bru_1_io_rd_valid, - alu_2_io_rd_valid, - bru_2_io_rd_valid, - alu_3_io_rd_valid, - bru_3_io_rd_valid, - clock -); - - `ifndef SYNTHESIS - wire [2:0] _GEN_0 = {2'h0, _GEN}; - always @(posedge clock) begin - if (~reset & {1'h0, {1'h0, csr_io_rd_valid} + {1'h0, alu_0_io_rd_valid}} - + {2'h0, bru_0_io_rd_valid} > _GEN_0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at SCore.scala:335\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {1'h0, {1'h0, alu_1_io_rd_valid} + {1'h0, bru_1_io_rd_valid}} > _GEN_0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at SCore.scala:335\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {1'h0, {1'h0, alu_2_io_rd_valid} + {1'h0, bru_2_io_rd_valid}} > _GEN_0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at SCore.scala:335\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset - & {1'h0, {1'h0, alu_3_io_rd_valid} + {1'h0, bru_3_io_rd_valid}} > _GEN_0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at SCore.scala:335\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FabricArbiter_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FabricArbiter_Verification_Assert( - input io_source_0_readDataAddr_valid, - io_source_0_writeDataAddr_valid, - reset, - io_source_1_readDataAddr_valid, - io_source_1_writeDataAddr_valid, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & io_source_0_readDataAddr_valid & io_source_0_writeDataAddr_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Fabric.scala:31\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_source_1_readDataAddr_valid & io_source_1_writeDataAddr_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Fabric.scala:32\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FabricMux_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FabricMux_Verification_Assert( - input io_source_readDataAddr_valid, - io_source_writeDataAddr_valid, - reset, - _GEN, - _GEN_0, - _GEN_1, - _GEN_2, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & io_source_readDataAddr_valid & io_source_writeDataAddr_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Fabric.scala:68\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & {1'h0, _GEN_1} + {1'h0, _GEN} + {1'h0, _GEN_0} > {1'h0, _GEN_2}) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at Fabric.scala:84\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/AxiSlave_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module AxiSlave_Verification_Assert( - input readIssued, - reset, - readDataQueue_io_enq_ready, - clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & ~(~readIssued | readDataQueue_io_enq_ready)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at AxiSlave.scala:115\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FifoX_1_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FifoX_1_Verification_Assert( - input reset, - input [1:0] mcount, - _GEN, - input clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & mcount > _GEN) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at FifoX.scala:158\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS -endmodule - - -// ----- 8< ----- FILE "verification/assert/FifoX_3_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module FifoX_3_Verification_Assert( - input reset, - input [1:0] mcount, - _GEN, - input clock -); - - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & mcount > _GEN) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at FifoX.scala:158\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS + .io_axi_read_addr_bits_len (io_axi_slave_read_addr_bits_len), + .io_axi_read_addr_bits_size (io_axi_slave_read_addr_bits_size), + .io_axi_read_addr_bits_burst (io_axi_slave_read_addr_bits_burst), + .io_axi_read_addr_bits_lock (io_axi_slave_read_addr_bits_lock), + .io_axi_read_addr_bits_cache (io_axi_slave_read_addr_bits_cache), + .io_axi_read_addr_bits_qos (io_axi_slave_read_addr_bits_qos), + .io_axi_read_addr_bits_region (io_axi_slave_read_addr_bits_region), + .io_axi_read_data_ready (io_axi_slave_read_data_ready & axiEnable), + .io_axi_read_data_valid (_axiSlave_io_axi_read_data_valid), + .io_axi_read_data_bits_data (io_axi_slave_read_data_bits_data), + .io_axi_read_data_bits_id (io_axi_slave_read_data_bits_id), + .io_axi_read_data_bits_resp (io_axi_slave_read_data_bits_resp), + .io_axi_read_data_bits_last (io_axi_slave_read_data_bits_last), + .io_fabric_readDataAddr_valid (_axiSlave_io_fabric_readDataAddr_valid), + .io_fabric_readDataAddr_bits (_axiSlave_io_fabric_readDataAddr_bits), + .io_fabric_readData_valid (_fabricMux_io_source_readData_valid), + .io_fabric_readData_bits (_fabricMux_io_source_readData_bits), + .io_fabric_writeDataAddr_valid (_axiSlave_io_fabric_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits (_axiSlave_io_fabric_writeDataAddr_bits), + .io_fabric_writeDataBits (_axiSlave_io_fabric_writeDataBits), + .io_fabric_writeDataStrb (_axiSlave_io_fabric_writeDataStrb), + .io_fabric_writeResp (_fabricMux_io_source_writeResp), + .io_periBusy (_fabricMux_io_fabricBusy) + ); + DBus2AxiV2 ebus2axi ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_dbus_valid (_core_io_ebus_dbus_valid), + .io_dbus_ready (_ebus2axi_io_dbus_ready), + .io_dbus_write (_core_io_ebus_dbus_write), + .io_dbus_addr (_core_io_ebus_dbus_addr), + .io_dbus_size (_core_io_ebus_dbus_size), + .io_dbus_wdata (_core_io_ebus_dbus_wdata), + .io_dbus_wmask (_core_io_ebus_dbus_wmask), + .io_dbus_rdata (_ebus2axi_io_dbus_rdata), + .io_axi_write_addr_ready (_io_axi_master_write_addr_q_io_enq_ready), + .io_axi_write_addr_valid (_ebus2axi_io_axi_write_addr_valid), + .io_axi_write_addr_bits_addr (_ebus2axi_io_axi_write_addr_bits_addr), + .io_axi_write_addr_bits_size (_ebus2axi_io_axi_write_addr_bits_size), + .io_axi_write_data_ready (_io_axi_master_write_data_q_io_enq_ready), + .io_axi_write_data_valid (_ebus2axi_io_axi_write_data_valid), + .io_axi_write_data_bits_data (_ebus2axi_io_axi_write_data_bits_data), + .io_axi_write_data_bits_last (_ebus2axi_io_axi_write_data_bits_last), + .io_axi_write_data_bits_strb (_ebus2axi_io_axi_write_data_bits_strb), + .io_axi_write_resp_ready (_ebus2axi_io_axi_write_resp_ready), + .io_axi_write_resp_valid (_ebus2axi_io_axi_write_resp_q_io_deq_valid), + .io_axi_write_resp_bits_resp (_ebus2axi_io_axi_write_resp_q_io_deq_bits_resp), + .io_axi_read_addr_ready (_readAddrArb_io_in_0_ready), + .io_axi_read_addr_valid (_ebus2axi_io_axi_read_addr_valid), + .io_axi_read_addr_bits_addr (_ebus2axi_io_axi_read_addr_bits_addr), + .io_axi_read_addr_bits_size (_ebus2axi_io_axi_read_addr_bits_size), + .io_axi_read_data_ready (_ebus2axi_io_axi_read_data_ready), + .io_axi_read_data_valid + (_readDataSkid_q_io_deq_valid & _readDataSkid_q_io_deq_bits_id == 6'h0), + .io_axi_read_data_bits_data (_readDataSkid_q_io_deq_bits_data), + .io_axi_read_data_bits_resp (_readDataSkid_q_io_deq_bits_resp), + .io_fault_valid (_ebus2axi_io_fault_valid) + ); + Queue2_AxiAddress io_axi_master_write_addr_q ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_io_axi_master_write_addr_q_io_enq_ready), + .io_enq_valid (_ebus2axi_io_axi_write_addr_valid), + .io_enq_bits_addr (_ebus2axi_io_axi_write_addr_bits_addr), + .io_enq_bits_prot (3'h2), + .io_enq_bits_id (6'h0), + .io_enq_bits_len (8'h0), + .io_enq_bits_size (_ebus2axi_io_axi_write_addr_bits_size), + .io_enq_bits_burst (2'h1), + .io_enq_bits_lock (1'h0), + .io_enq_bits_cache (4'h0), + .io_enq_bits_qos (4'h0), + .io_enq_bits_region (4'h0), + .io_deq_ready (io_axi_master_write_addr_ready & axiEnable), + .io_deq_valid (_io_axi_master_write_addr_q_io_deq_valid), + .io_deq_bits_addr (io_axi_master_write_addr_bits_addr), + .io_deq_bits_prot (io_axi_master_write_addr_bits_prot), + .io_deq_bits_id (io_axi_master_write_addr_bits_id), + .io_deq_bits_len (io_axi_master_write_addr_bits_len), + .io_deq_bits_size (io_axi_master_write_addr_bits_size), + .io_deq_bits_burst (io_axi_master_write_addr_bits_burst), + .io_deq_bits_lock (io_axi_master_write_addr_bits_lock), + .io_deq_bits_cache (io_axi_master_write_addr_bits_cache), + .io_deq_bits_qos (io_axi_master_write_addr_bits_qos), + .io_deq_bits_region (io_axi_master_write_addr_bits_region) + ); + Queue2_AxiWriteData io_axi_master_write_data_q ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_io_axi_master_write_data_q_io_enq_ready), + .io_enq_valid (_ebus2axi_io_axi_write_data_valid), + .io_enq_bits_data (_ebus2axi_io_axi_write_data_bits_data), + .io_enq_bits_last (_ebus2axi_io_axi_write_data_bits_last), + .io_enq_bits_strb (_ebus2axi_io_axi_write_data_bits_strb), + .io_deq_ready (io_axi_master_write_data_ready & axiEnable), + .io_deq_valid (_io_axi_master_write_data_q_io_deq_valid), + .io_deq_bits_data (io_axi_master_write_data_bits_data), + .io_deq_bits_last (io_axi_master_write_data_bits_last), + .io_deq_bits_strb (io_axi_master_write_data_bits_strb) + ); + Queue2_AxiWriteResponse ebus2axi_io_axi_write_resp_q ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_ebus2axi_io_axi_write_resp_q_io_enq_ready), + .io_enq_valid (io_axi_master_write_resp_valid & axiEnable), + .io_enq_bits_id (io_axi_master_write_resp_bits_id), + .io_enq_bits_resp (io_axi_master_write_resp_bits_resp), + .io_deq_ready (_ebus2axi_io_axi_write_resp_ready), + .io_deq_valid (_ebus2axi_io_axi_write_resp_q_io_deq_valid), + .io_deq_bits_id (/* unused */), + .io_deq_bits_resp (_ebus2axi_io_axi_write_resp_q_io_deq_bits_resp) + ); + CoralNPURRArbiter_1 readAddrArb ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_in_0_ready (_readAddrArb_io_in_0_ready), + .io_in_0_valid (_ebus2axi_io_axi_read_addr_valid), + .io_in_0_bits_addr (_ebus2axi_io_axi_read_addr_bits_addr), + .io_in_0_bits_prot (3'h2), + .io_in_0_bits_id (6'h0), + .io_in_0_bits_len (8'h0), + .io_in_0_bits_size (_ebus2axi_io_axi_read_addr_bits_size), + .io_in_0_bits_burst (2'h1), + .io_in_0_bits_lock (1'h0), + .io_in_0_bits_cache (4'h0), + .io_in_0_bits_qos (4'h0), + .io_in_0_bits_region (4'h0), + .io_in_1_ready (_readAddrArb_io_in_1_ready), + .io_in_1_valid (_ibus2axi_io_axi_addr_valid), + .io_in_1_bits_addr (_ibus2axi_io_axi_addr_bits_addr), + .io_in_1_bits_prot (3'h2), + .io_in_1_bits_id (6'h1), + .io_in_1_bits_len (8'h0), + .io_in_1_bits_size (3'h4), + .io_in_1_bits_burst (2'h1), + .io_in_1_bits_lock (1'h0), + .io_in_1_bits_cache (4'h0), + .io_in_1_bits_qos (4'h0), + .io_in_1_bits_region (4'h0), + .io_out_ready (_io_axi_master_read_addr_q_io_enq_ready), + .io_out_valid (_readAddrArb_io_out_valid), + .io_out_bits_addr (_readAddrArb_io_out_bits_addr), + .io_out_bits_prot (_readAddrArb_io_out_bits_prot), + .io_out_bits_id (_readAddrArb_io_out_bits_id), + .io_out_bits_len (_readAddrArb_io_out_bits_len), + .io_out_bits_size (_readAddrArb_io_out_bits_size), + .io_out_bits_burst (_readAddrArb_io_out_bits_burst), + .io_out_bits_lock (_readAddrArb_io_out_bits_lock), + .io_out_bits_cache (_readAddrArb_io_out_bits_cache), + .io_out_bits_qos (_readAddrArb_io_out_bits_qos), + .io_out_bits_region (_readAddrArb_io_out_bits_region), + .io_chosen (/* unused */) + ); + Queue2_AxiAddress io_axi_master_read_addr_q ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_io_axi_master_read_addr_q_io_enq_ready), + .io_enq_valid (_readAddrArb_io_out_valid), + .io_enq_bits_addr (_readAddrArb_io_out_bits_addr), + .io_enq_bits_prot (_readAddrArb_io_out_bits_prot), + .io_enq_bits_id (_readAddrArb_io_out_bits_id), + .io_enq_bits_len (_readAddrArb_io_out_bits_len), + .io_enq_bits_size (_readAddrArb_io_out_bits_size), + .io_enq_bits_burst (_readAddrArb_io_out_bits_burst), + .io_enq_bits_lock (_readAddrArb_io_out_bits_lock), + .io_enq_bits_cache (_readAddrArb_io_out_bits_cache), + .io_enq_bits_qos (_readAddrArb_io_out_bits_qos), + .io_enq_bits_region (_readAddrArb_io_out_bits_region), + .io_deq_ready (io_axi_master_read_addr_ready & axiEnable), + .io_deq_valid (_io_axi_master_read_addr_q_io_deq_valid), + .io_deq_bits_addr (io_axi_master_read_addr_bits_addr), + .io_deq_bits_prot (io_axi_master_read_addr_bits_prot), + .io_deq_bits_id (io_axi_master_read_addr_bits_id), + .io_deq_bits_len (io_axi_master_read_addr_bits_len), + .io_deq_bits_size (io_axi_master_read_addr_bits_size), + .io_deq_bits_burst (io_axi_master_read_addr_bits_burst), + .io_deq_bits_lock (io_axi_master_read_addr_bits_lock), + .io_deq_bits_cache (io_axi_master_read_addr_bits_cache), + .io_deq_bits_qos (io_axi_master_read_addr_bits_qos), + .io_deq_bits_region (io_axi_master_read_addr_bits_region) + ); + Queue2_AxiReadData readDataSkid_q ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_enq_ready (_readDataSkid_q_io_enq_ready), + .io_enq_valid (io_axi_master_read_data_valid & axiEnable), + .io_enq_bits_data (io_axi_master_read_data_bits_data), + .io_enq_bits_id (io_axi_master_read_data_bits_id), + .io_enq_bits_resp (io_axi_master_read_data_bits_resp), + .io_enq_bits_last (io_axi_master_read_data_bits_last), + .io_deq_ready (_ibus2axi_io_axi_data_valid_T | _ebus2axi_io_axi_read_data_ready), + .io_deq_valid (_readDataSkid_q_io_deq_valid), + .io_deq_bits_data (_readDataSkid_q_io_deq_bits_data), + .io_deq_bits_id (_readDataSkid_q_io_deq_bits_id), + .io_deq_bits_resp (_readDataSkid_q_io_deq_bits_resp) + ); + assign io_axi_slave_write_addr_ready = _axiSlave_io_axi_write_addr_ready & axiEnable; + assign io_axi_slave_write_data_ready = _axiSlave_io_axi_write_data_ready & axiEnable; + assign io_axi_slave_write_resp_valid = _axiSlave_io_axi_write_resp_valid & axiEnable; + assign io_axi_slave_read_addr_ready = _axiSlave_io_axi_read_addr_ready & axiEnable; + assign io_axi_slave_read_data_valid = _axiSlave_io_axi_read_data_valid & axiEnable; + assign io_axi_master_write_addr_valid = + _io_axi_master_write_addr_q_io_deq_valid & axiEnable; + assign io_axi_master_write_data_valid = + _io_axi_master_write_data_q_io_deq_valid & axiEnable; + assign io_axi_master_write_resp_ready = + _ebus2axi_io_axi_write_resp_q_io_enq_ready & axiEnable; + assign io_axi_master_read_addr_valid = + _io_axi_master_read_addr_q_io_deq_valid & axiEnable; + assign io_axi_master_read_data_ready = _readDataSkid_q_io_enq_ready & axiEnable; + assign io_halted = _core_io_halted; + assign io_fault = _core_io_fault; + assign io_wfi = _core_io_wfi; + assign io_dm_req_ready = _dmReqArbiter_io_in_0_ready & dmEnable; + assign io_dm_rsp_valid = _io_dm_rsp_valid_T & ~_inflight_io_deq_bits; + assign io_dm_rsp_bits_data = _dm_io_ext_rsp_bits_data; + assign io_dm_rsp_bits_op = _dm_io_ext_rsp_bits_op; endmodule - -// ----- 8< ----- FILE "verification/assert/DBus2AxiV1_Verification_Assert.sv" ----- 8< ----- - -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 - -// Users can define 'STOP_COND' to add an extra gate to stop conditions. -`ifndef STOP_COND_ - `ifdef STOP_COND - `define STOP_COND_ (`STOP_COND) - `else // STOP_COND - `define STOP_COND_ 1 - `endif // STOP_COND -`endif // not def STOP_COND_ - -// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. -`ifndef ASSERT_VERBOSE_COND_ - `ifdef ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) - `else // ASSERT_VERBOSE_COND - `define ASSERT_VERBOSE_COND_ 1 - `endif // ASSERT_VERBOSE_COND -`endif // not def ASSERT_VERBOSE_COND_ -module DBus2AxiV1_Verification_Assert( - input [4:0] io_dbus_size, - input _GEN, - io_dbus_valid, - reset, - txnActive, - input [1:0] _GEN_0, - readAddrQ_io_count, - input _GEN_1, - input [5:0] io_axi_read_data_bits_id, - input io_axi_read_data_valid, - input [1:0] writeAddrQ_io_count, - writeDataQ_io_count, - input [5:0] io_axi_write_resp_bits_id, - input io_axi_write_resp_valid, - clock +module CoreMiniAxi( + output io_dm_req_ready, + input io_dm_req_valid, + input [31:0] io_dm_req_bits_address, + io_dm_req_bits_data, + input [1:0] io_dm_req_bits_op, + input io_dm_rsp_ready, + output io_dm_rsp_valid, + output [31:0] io_dm_rsp_bits_data, + output [1:0] io_dm_rsp_bits_op, + input io_software_irq, + io_timer_irq, + input [31:0] io_boot_addr, + input io_irq, + output io_wfi, + io_fault, + io_halted, + input io_axi_master_write_addr_ready, + output io_axi_master_write_addr_valid, + output [31:0] io_axi_master_write_addr_bits_addr, + output [2:0] io_axi_master_write_addr_bits_prot, + output [5:0] io_axi_master_write_addr_bits_id, + output [7:0] io_axi_master_write_addr_bits_len, + output [2:0] io_axi_master_write_addr_bits_size, + output [1:0] io_axi_master_write_addr_bits_burst, + output io_axi_master_write_addr_bits_lock, + output [3:0] io_axi_master_write_addr_bits_cache, + io_axi_master_write_addr_bits_qos, + io_axi_master_write_addr_bits_region, + input io_axi_master_write_data_ready, + output io_axi_master_write_data_valid, + output [127:0] io_axi_master_write_data_bits_data, + output io_axi_master_write_data_bits_last, + output [15:0] io_axi_master_write_data_bits_strb, + output io_axi_master_write_resp_ready, + input io_axi_master_write_resp_valid, + input [5:0] io_axi_master_write_resp_bits_id, + input [1:0] io_axi_master_write_resp_bits_resp, + input io_axi_master_read_addr_ready, + output io_axi_master_read_addr_valid, + output [31:0] io_axi_master_read_addr_bits_addr, + output [2:0] io_axi_master_read_addr_bits_prot, + output [5:0] io_axi_master_read_addr_bits_id, + output [7:0] io_axi_master_read_addr_bits_len, + output [2:0] io_axi_master_read_addr_bits_size, + output [1:0] io_axi_master_read_addr_bits_burst, + output io_axi_master_read_addr_bits_lock, + output [3:0] io_axi_master_read_addr_bits_cache, + io_axi_master_read_addr_bits_qos, + io_axi_master_read_addr_bits_region, + output io_axi_master_read_data_ready, + input io_axi_master_read_data_valid, + input [127:0] io_axi_master_read_data_bits_data, + input [5:0] io_axi_master_read_data_bits_id, + input [1:0] io_axi_master_read_data_bits_resp, + input io_axi_master_read_data_bits_last, + output io_axi_slave_write_addr_ready, + input io_axi_slave_write_addr_valid, + input [31:0] io_axi_slave_write_addr_bits_addr, + input [2:0] io_axi_slave_write_addr_bits_prot, + input [5:0] io_axi_slave_write_addr_bits_id, + input [7:0] io_axi_slave_write_addr_bits_len, + input [2:0] io_axi_slave_write_addr_bits_size, + input [1:0] io_axi_slave_write_addr_bits_burst, + input io_axi_slave_write_addr_bits_lock, + input [3:0] io_axi_slave_write_addr_bits_cache, + io_axi_slave_write_addr_bits_qos, + io_axi_slave_write_addr_bits_region, + output io_axi_slave_write_data_ready, + input io_axi_slave_write_data_valid, + input [127:0] io_axi_slave_write_data_bits_data, + input io_axi_slave_write_data_bits_last, + input [15:0] io_axi_slave_write_data_bits_strb, + input io_axi_slave_write_resp_ready, + output io_axi_slave_write_resp_valid, + output [5:0] io_axi_slave_write_resp_bits_id, + output [1:0] io_axi_slave_write_resp_bits_resp, + output io_axi_slave_read_addr_ready, + input io_axi_slave_read_addr_valid, + input [31:0] io_axi_slave_read_addr_bits_addr, + input [2:0] io_axi_slave_read_addr_bits_prot, + input [5:0] io_axi_slave_read_addr_bits_id, + input [7:0] io_axi_slave_read_addr_bits_len, + input [2:0] io_axi_slave_read_addr_bits_size, + input [1:0] io_axi_slave_read_addr_bits_burst, + input io_axi_slave_read_addr_bits_lock, + input [3:0] io_axi_slave_read_addr_bits_cache, + io_axi_slave_read_addr_bits_qos, + io_axi_slave_read_addr_bits_region, + input io_axi_slave_read_data_ready, + output io_axi_slave_read_data_valid, + output [127:0] io_axi_slave_read_data_bits_data, + output [5:0] io_axi_slave_read_data_bits_id, + output [1:0] io_axi_slave_read_data_bits_resp, + output io_axi_slave_read_data_bits_last, + input io_aresetn, + io_aclk ); - `ifndef SYNTHESIS - always @(posedge clock) begin - if (~reset & io_dbus_valid - & {1'h0, {1'h0, io_dbus_size[0]} + {1'h0, io_dbus_size[1]}} - + {1'h0, - {1'h0, io_dbus_size[2]} + {1'h0, io_dbus_size[3]} - + {1'h0, io_dbus_size[4]}} != {2'h0, _GEN}) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:57\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & txnActive & ~io_dbus_valid) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:63\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_dbus_valid & _GEN_0 == 2'h0) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:86\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_1 & (|readAddrQ_io_count)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:93\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_axi_read_data_valid & (|io_axi_read_data_bits_id)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:133\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_1 & (|writeAddrQ_io_count)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:141\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & _GEN_1 & (|writeDataQ_io_count)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:164\n"); - if (`STOP_COND_) - $fatal; - end - if (~reset & io_axi_write_resp_valid & (|io_axi_write_resp_bits_id)) begin - if (`ASSERT_VERBOSE_COND_) - $error("Assertion failed at DBus2Axi.scala:191\n"); - if (`STOP_COND_) - $fatal; - end - end // always @(posedge) - `endif // not def SYNTHESIS + CoreMiniCoreAxi core ( + .io_aclk (io_aclk), + .io_aresetn (io_aresetn), + .io_axi_slave_write_addr_ready (io_axi_slave_write_addr_ready), + .io_axi_slave_write_addr_valid (io_axi_slave_write_addr_valid), + .io_axi_slave_write_addr_bits_addr (io_axi_slave_write_addr_bits_addr), + .io_axi_slave_write_addr_bits_prot (io_axi_slave_write_addr_bits_prot), + .io_axi_slave_write_addr_bits_id (io_axi_slave_write_addr_bits_id), + .io_axi_slave_write_addr_bits_len (io_axi_slave_write_addr_bits_len), + .io_axi_slave_write_addr_bits_size (io_axi_slave_write_addr_bits_size), + .io_axi_slave_write_addr_bits_burst (io_axi_slave_write_addr_bits_burst), + .io_axi_slave_write_addr_bits_lock (io_axi_slave_write_addr_bits_lock), + .io_axi_slave_write_addr_bits_cache (io_axi_slave_write_addr_bits_cache), + .io_axi_slave_write_addr_bits_qos (io_axi_slave_write_addr_bits_qos), + .io_axi_slave_write_addr_bits_region (io_axi_slave_write_addr_bits_region), + .io_axi_slave_write_data_ready (io_axi_slave_write_data_ready), + .io_axi_slave_write_data_valid (io_axi_slave_write_data_valid), + .io_axi_slave_write_data_bits_data (io_axi_slave_write_data_bits_data), + .io_axi_slave_write_data_bits_last (io_axi_slave_write_data_bits_last), + .io_axi_slave_write_data_bits_strb (io_axi_slave_write_data_bits_strb), + .io_axi_slave_write_resp_ready (io_axi_slave_write_resp_ready), + .io_axi_slave_write_resp_valid (io_axi_slave_write_resp_valid), + .io_axi_slave_write_resp_bits_id (io_axi_slave_write_resp_bits_id), + .io_axi_slave_write_resp_bits_resp (io_axi_slave_write_resp_bits_resp), + .io_axi_slave_read_addr_ready (io_axi_slave_read_addr_ready), + .io_axi_slave_read_addr_valid (io_axi_slave_read_addr_valid), + .io_axi_slave_read_addr_bits_addr (io_axi_slave_read_addr_bits_addr), + .io_axi_slave_read_addr_bits_prot (io_axi_slave_read_addr_bits_prot), + .io_axi_slave_read_addr_bits_id (io_axi_slave_read_addr_bits_id), + .io_axi_slave_read_addr_bits_len (io_axi_slave_read_addr_bits_len), + .io_axi_slave_read_addr_bits_size (io_axi_slave_read_addr_bits_size), + .io_axi_slave_read_addr_bits_burst (io_axi_slave_read_addr_bits_burst), + .io_axi_slave_read_addr_bits_lock (io_axi_slave_read_addr_bits_lock), + .io_axi_slave_read_addr_bits_cache (io_axi_slave_read_addr_bits_cache), + .io_axi_slave_read_addr_bits_qos (io_axi_slave_read_addr_bits_qos), + .io_axi_slave_read_addr_bits_region (io_axi_slave_read_addr_bits_region), + .io_axi_slave_read_data_ready (io_axi_slave_read_data_ready), + .io_axi_slave_read_data_valid (io_axi_slave_read_data_valid), + .io_axi_slave_read_data_bits_data (io_axi_slave_read_data_bits_data), + .io_axi_slave_read_data_bits_id (io_axi_slave_read_data_bits_id), + .io_axi_slave_read_data_bits_resp (io_axi_slave_read_data_bits_resp), + .io_axi_slave_read_data_bits_last (io_axi_slave_read_data_bits_last), + .io_axi_master_write_addr_ready (io_axi_master_write_addr_ready), + .io_axi_master_write_addr_valid (io_axi_master_write_addr_valid), + .io_axi_master_write_addr_bits_addr (io_axi_master_write_addr_bits_addr), + .io_axi_master_write_addr_bits_prot (io_axi_master_write_addr_bits_prot), + .io_axi_master_write_addr_bits_id (io_axi_master_write_addr_bits_id), + .io_axi_master_write_addr_bits_len (io_axi_master_write_addr_bits_len), + .io_axi_master_write_addr_bits_size (io_axi_master_write_addr_bits_size), + .io_axi_master_write_addr_bits_burst (io_axi_master_write_addr_bits_burst), + .io_axi_master_write_addr_bits_lock (io_axi_master_write_addr_bits_lock), + .io_axi_master_write_addr_bits_cache (io_axi_master_write_addr_bits_cache), + .io_axi_master_write_addr_bits_qos (io_axi_master_write_addr_bits_qos), + .io_axi_master_write_addr_bits_region (io_axi_master_write_addr_bits_region), + .io_axi_master_write_data_ready (io_axi_master_write_data_ready), + .io_axi_master_write_data_valid (io_axi_master_write_data_valid), + .io_axi_master_write_data_bits_data (io_axi_master_write_data_bits_data), + .io_axi_master_write_data_bits_last (io_axi_master_write_data_bits_last), + .io_axi_master_write_data_bits_strb (io_axi_master_write_data_bits_strb), + .io_axi_master_write_resp_ready (io_axi_master_write_resp_ready), + .io_axi_master_write_resp_valid (io_axi_master_write_resp_valid), + .io_axi_master_write_resp_bits_id (io_axi_master_write_resp_bits_id), + .io_axi_master_write_resp_bits_resp (io_axi_master_write_resp_bits_resp), + .io_axi_master_read_addr_ready (io_axi_master_read_addr_ready), + .io_axi_master_read_addr_valid (io_axi_master_read_addr_valid), + .io_axi_master_read_addr_bits_addr (io_axi_master_read_addr_bits_addr), + .io_axi_master_read_addr_bits_prot (io_axi_master_read_addr_bits_prot), + .io_axi_master_read_addr_bits_id (io_axi_master_read_addr_bits_id), + .io_axi_master_read_addr_bits_len (io_axi_master_read_addr_bits_len), + .io_axi_master_read_addr_bits_size (io_axi_master_read_addr_bits_size), + .io_axi_master_read_addr_bits_burst (io_axi_master_read_addr_bits_burst), + .io_axi_master_read_addr_bits_lock (io_axi_master_read_addr_bits_lock), + .io_axi_master_read_addr_bits_cache (io_axi_master_read_addr_bits_cache), + .io_axi_master_read_addr_bits_qos (io_axi_master_read_addr_bits_qos), + .io_axi_master_read_addr_bits_region (io_axi_master_read_addr_bits_region), + .io_axi_master_read_data_ready (io_axi_master_read_data_ready), + .io_axi_master_read_data_valid (io_axi_master_read_data_valid), + .io_axi_master_read_data_bits_data (io_axi_master_read_data_bits_data), + .io_axi_master_read_data_bits_id (io_axi_master_read_data_bits_id), + .io_axi_master_read_data_bits_resp (io_axi_master_read_data_bits_resp), + .io_axi_master_read_data_bits_last (io_axi_master_read_data_bits_last), + .io_halted (io_halted), + .io_fault (io_fault), + .io_wfi (io_wfi), + .io_irq (io_irq), + .io_boot_addr (io_boot_addr), + .io_timer_irq (io_timer_irq), + .io_software_irq (io_software_irq), + .io_dm_req_ready (io_dm_req_ready), + .io_dm_req_valid (io_dm_req_valid), + .io_dm_req_bits_address (io_dm_req_bits_address), + .io_dm_req_bits_data (io_dm_req_bits_data), + .io_dm_req_bits_op (io_dm_req_bits_op), + .io_dm_rsp_ready (io_dm_rsp_ready), + .io_dm_rsp_valid (io_dm_rsp_valid), + .io_dm_rsp_bits_data (io_dm_rsp_bits_data), + .io_dm_rsp_bits_op (io_dm_rsp_bits_op), + .io_te (1'h0) + ); endmodule // ----- 8< ----- FILE "./RstSync.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2024 Google LLC // // Licensed under the Apache License, Version 2.0 (the "License"); @@ -20131,43 +23884,43 @@ endmodule // an internal synchronous deassert reset // Clock is disabled while reset is asserted to prevent a race // between clock and reset. -module RstSync - ( - // Input clock - input clk_i, - // Input active-low async reset - input rstn_i, - // Functional clock gate enable. clk_o is enabled when clk_en - // is 1, and we are out of reset - // clk_en is assumed to be synchronous to clk_o or clk_i - input clk_en, - input te, - - // Output clock - output clk_o, - // Output reset active low - output rstn_o); +module RstSync ( + // Input clock + input clk_i, + // Input active-low async reset + input rstn_i, + // Functional clock gate enable. clk_o is enabled when clk_en + // is 1, and we are out of reset + // clk_en is assumed to be synchronous to clk_o or clk_i + input clk_en, + input te, + + // Output clock + output clk_o, + // Output reset active low + output rstn_o +); localparam RST_DELAY = 2; localparam CLK_DELAY = 2; logic [RST_DELAY + CLK_DELAY - 1 : 0] rst_delay_reg; always_ff @(posedge clk_i or negedge rstn_i) begin - if (~rstn_i) - rst_delay_reg <= '0; - else - rst_delay_reg <= {rst_delay_reg[RST_DELAY + CLK_DELAY - 2 : 0], 1'b1}; + if (~rstn_i) rst_delay_reg <= '0; + else rst_delay_reg <= {rst_delay_reg[RST_DELAY+CLK_DELAY-2 : 0], 1'b1}; end - assign rstn_o = rst_delay_reg[RST_DELAY - 1]; + assign rstn_o = rst_delay_reg[RST_DELAY-1]; logic clk_en_int; - assign clk_en_int = clk_en & rst_delay_reg[CLK_DELAY + RST_DELAY - 1]; + assign clk_en_int = clk_en & rst_delay_reg[CLK_DELAY+RST_DELAY-1]; - ClockGate icg(.clk_i(clk_i), - .enable(clk_en_int), - .te(te), - .clk_o(clk_o)); + ClockGate icg ( + .clk_i(clk_i), + .enable(clk_en_int), + .te(te), + .clk_o(clk_o) + ); `ifndef SYNTHESIS initial begin @@ -20178,7 +23931,7 @@ module RstSync endmodule // ----- 8< ----- FILE "./ClockGate.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2023 Google LLC // // Licensed under the Apache License, Version 2.0 (the "License"); @@ -20198,26 +23951,185 @@ endmodule // Default: ASIC implementation // USE_GENERIC default: Verilator implementation (adapted from OpenTitan) // USE_GENERIC and FPGA_XILINX: UltraScale Plus specific clockgate. -module ClockGate( - input clk_i, - input enable, // '1' passthrough, '0' disable. - input te, // test enable - output clk_o +module ClockGate ( + input clk_i, + input enable, // '1' passthrough, '0' disable. + input te, // test enable + output clk_o ); -/////////////////////////// -/// ClockGate Selection /// -/////////////////////////// + /////////////////////////// + /// ClockGate Selection /// + /////////////////////////// +`ifdef USE_TSMC12FFC + // TSMC12FFC Specific ClockGate + CKLNQD10BWP6T20P96CPDLVT u_cg ( + .TE(te), + .E (enable), + .CP(clk_i), + .Q (clk_o) + ); +`elsif USE_GF12LPP + // GF12 Specific Clockgate + // ICG_CELL must be defined at compile time (e.g. via -DICG_CELL=) + `ICG_CELL u_clkgate ( + .ECK(clk_o), + .E (enable), + .SE (te), + .CK (clk_i) + ); +`elsif USE_GF22_116A + // GF22 116A Specific ClockGate -- MUST BE BEFORE USE_GF22 (USE_GF22 must also be set for SRAMs) + UDBSLT20_CKGTPLT_V5_8 u_cg ( + .CK(clk_i), + .EN(enable), + .SE(te), + .Q (clk_o) + ); +`elsif USE_GF22 + // GF22 Specific ClockGate + SC7P5T_CKGPRELATNX8_CSC36L u_cg ( + .CLK(clk_i), + .E (enable), + .TE (te), + .Z (clk_o) + ); + +`elsif FPGA_XILINX + // Xilinx FPGA Specific ClockGate + BUFGCE #( + .SIM_DEVICE("ULTRASCALE_PLUS") + ) u_bufgce ( + .I (clk_i), + .CE(enable | te), + .O (clk_o) + ); +`else // Default: Verilator implementation - logic en_latch /* verilator clock_enable */; + logic en_latch /* verilator clock_enable */; always_latch begin if (!clk_i) begin en_latch = enable | te; end end assign clk_o = en_latch & clk_i; +`endif endmodule // ClockGate +// ----- 8< ----- FILE "./Aligner.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.133.0 +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A module that moves valid inputs to the front of the output. +// Example: +// valid_in = [0, 1, 0, 1], data_in = [A, B, C, D] +// valid_out = [1, 1, 0, 0], data_out = [B, D, X, X] +module Aligner#(type T=logic [7:0], parameter N = 8) +( + // Command input. + input logic [N-1:0] valid_in, + input T [N-1:0] data_in, + + // Command output. + output logic [N-1:0] valid_out, + output T [N-1:0] data_out +); +/* verilator lint_off WIDTHEXPAND */ +/* verilator lint_off WIDTHTRUNC */ + localparam COUNTBITS = $clog2(N); + typedef logic [COUNTBITS-1:0] count_t; + + // Build count + count_t valid_count [N-1:0]; + always_comb begin + valid_count[0] = 0; + for (int i = 0; i < N-1; i++) begin + valid_count[i+1] = valid_count[i] + valid_in[i]; + end + end + + logic [N-1:0][N-1:0] output_valid_map; + count_t valid_idx [N-1:0]; + always_comb begin + + for (int o = 0; o < N; o++) begin + valid_idx[o] = 0; + for (int i = 0; i < N; i++) begin + output_valid_map[o][i] = (valid_count[i] == o) && valid_in[i]; + valid_idx[o] = valid_idx[o] | (output_valid_map[o][i] ? i : 0); + end + + // Assign outputs + valid_out[o] = |output_valid_map[o]; + data_out[o] = data_in[valid_idx[o]]; + end + end +/* verilator lint_on WIDTHTRUNC */ +/* verilator lint_on WIDTHEXPAND */ + +endmodule +// ----- 8< ----- FILE "./Aligner_111_4.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.133.0 +module Aligner_111_4( + input logic in_0_valid, + input logic in_1_valid, + input logic in_2_valid, + input logic in_3_valid, + input logic [111-1:0] in_0_bits, + input logic [111-1:0] in_1_bits, + input logic [111-1:0] in_2_bits, + input logic [111-1:0] in_3_bits, + output logic out_0_valid, + output logic out_1_valid, + output logic out_2_valid, + output logic out_3_valid, + output logic [111-1:0] out_0_bits, + output logic [111-1:0] out_1_bits, + output logic [111-1:0] out_2_bits, + output logic [111-1:0] out_3_bits); + + logic [4-1:0] valid_in; + assign valid_in[0] = in_0_valid; + assign valid_in[1] = in_1_valid; + assign valid_in[2] = in_2_valid; + assign valid_in[3] = in_3_valid; + logic [4-1:0][111-1:0] data_in; + assign data_in[0] = in_0_bits; + assign data_in[1] = in_1_bits; + assign data_in[2] = in_2_bits; + assign data_in[3] = in_3_bits; + logic [4-1:0] valid_out; + assign out_0_valid = valid_out[0]; + assign out_1_valid = valid_out[1]; + assign out_2_valid = valid_out[2]; + assign out_3_valid = valid_out[3]; + logic [4-1:0][111-1:0] data_out; + assign out_0_bits = data_out[0]; + assign out_1_bits = data_out[1]; + assign out_2_bits = data_out[2]; + assign out_3_bits = data_out[3]; + + Aligner#(.T (logic [111-1:0]), .N(4)) aligner( + valid_in, + data_in, + valid_out, + data_out + ); +endmodule // ----- 8< ----- FILE "./registers.svh" ----- 8< ----- // Copyright 2018 ETH Zurich and University of Bologna. @@ -20446,7 +24358,7 @@ endmodule // ClockGate `endif // ----- 8< ----- FILE "./cf_math_pkg.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2016 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in @@ -20461,7 +24373,7 @@ endmodule // ClockGate /// /// This package contains a collection of mathematical functions that are commonly used when defining /// the value of constants in HDL code. These functions are implemented as Verilog constants -/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (?? 10.3.5) is a +/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (§ 10.3.5) is a /// function whose value can be evaluated at compile time or during elaboration. A constant function /// must be called with arguments that are constants. package cf_math_pkg; @@ -20510,7 +24422,7 @@ package cf_math_pkg; endpackage // ----- 8< ----- FILE "./lzc.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright (c) 2018 - 2019 ETH Zurich, University of Bologna // All rights reserved. // @@ -20625,7 +24537,7 @@ module lzc #( endmodule : lzc // ----- 8< ----- FILE "./rr_arb_tree.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in @@ -20975,7 +24887,7 @@ module rr_arb_tree #( endmodule : rr_arb_tree // ----- 8< ----- FILE "./fpnew_pkg.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -21098,9 +25010,19 @@ package fpnew_pkg; FMADD, FNMSUB, ADD, MUL, // ADDMUL operation group DIV, SQRT, // DIVSQRT operation group SGNJ, MINMAX, CMP, CLASSIFY, // NONCOMP operation group - F2F, F2I, I2F, CPKAB, CPKCD // CONV operation group + F2F, F2I, I2F, CPKAB, CPKCD, // CONV operation group + ADDS // ADDMUL operation group (ADDS is added here to preserve bit encoding of operations) } operation_e; + // ------------- + // DIVSQRT UNIT + // ------------- + typedef enum logic[1:0] { + PULP, // "PULP" instantiates the PULP DivSqrt unit supports FP64, FP32, FP16, FP16ALT, FP8 and SIMD operations + TH32, // "TH32" instantiates the E906 DivSqrt unit supports only FP32 (no SIMD support) + THMULTI // "THMULTI" instantiates the C910 DivSqrt unit supports FP64, FP32, FP16, FP16ALT and SIMD operations + } divsqrt_unit_t; + // ------------------- // RISC-V FP-SPECIFIC // ------------------- @@ -21112,6 +25034,7 @@ package fpnew_pkg; RUP = 3'b011, RMM = 3'b100, ROD = 3'b101, // This mode is not defined in RISC-V FP-SPEC + R_UNREACH_1 = 3'b110, DYN = 3'b111 } roundmode_e; @@ -21345,11 +25268,11 @@ package fpnew_pkg; // Returns the operation group of the given operation function automatic opgroup_e get_opgroup(operation_e op); unique case (op) - FMADD, FNMSUB, ADD, MUL: return ADDMUL; - DIV, SQRT: return DIVSQRT; - SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP; - F2F, F2I, I2F, CPKAB, CPKCD: return CONV; - default: return NONCOMP; + FMADD, FNMSUB, ADD, ADDS, MUL: return ADDMUL; + DIV, SQRT: return DIVSQRT; + SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP; + F2F, F2I, I2F, CPKAB, CPKCD: return CONV; + default: return NONCOMP; endcase endfunction @@ -21386,6 +25309,21 @@ package fpnew_pkg; end endfunction + // Returns the maximum number of lanes in the FPU according to width, format config and vectors + function automatic int unsigned num_divsqrt_lanes(int unsigned width, fmt_logic_t cfg, logic vec, divsqrt_unit_t DivSqrtSel); + automatic fmt_logic_t cfg_tmp; + if (DivSqrtSel == THMULTI) begin + cfg_tmp = cfg & 5'b11101; + end else begin + cfg_tmp = cfg; + end + if (vec) begin + return width / min_fp_width(cfg_tmp); + end else begin + return 1; + end + endfunction + // Returns a mask of active FP formats that are present in lane lane_no of a multiformat slice function automatic fmt_logic_t get_lane_formats(int unsigned width, fmt_logic_t cfg, @@ -21485,7 +25423,7 @@ package fpnew_pkg; endpackage // ----- 8< ----- FILE "./fpnew_cast_multi.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -21512,10 +25450,9 @@ module fpnew_cast_multi #( parameter type TagType = logic, parameter type AuxType = logic, // Do not change - localparam int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig), - fpnew_pkg::max_int_width(IntFmtConfig)), - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig), fpnew_pkg::max_int_width(IntFmtConfig)), + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -21548,7 +25485,9 @@ module fpnew_cast_multi #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); // ---------- @@ -21692,10 +25631,12 @@ module fpnew_cast_multi #( localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); if (FpFmtConfig[fmt]) begin : active_format + localparam fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(fmt); + // Classify input fpnew_classifier #( - .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), - .NumOperands ( 1 ) + .FpFormat ( FpFormat ), + .NumOperands ( 1 ) ) i_fpnew_classifier ( .operands_i ( operands_q[FP_WIDTH-1:0] ), .is_boxed_i ( is_boxed_q[fmt] ), @@ -21934,8 +25875,7 @@ module fpnew_cast_multi #( if ((input_exp_q >= signed'(fpnew_pkg::int_width(int_fmt_q2) - 1 + op_mod_q2)) // Exponent larger than max int range, && !(!op_mod_q2 // unless cast to signed int && input_sign_q // and input value is larges negative int value - && (input_exp_q == signed'(fpnew_pkg::int_width(int_fmt_q2) - 1)) - && (input_mant_q == {1'b1, {INT_MAN_WIDTH-1{1'b0}}}))) begin + && (input_exp_q == signed'(fpnew_pkg::int_width(int_fmt_q2) - 1)))) begin denorm_shamt = '0; // prevent shifting of_before_round = 1'b1; // underflow @@ -21945,9 +25885,12 @@ module fpnew_cast_multi #( end // Handle FP over-/underflows end else begin - // Overflow or infinities (for proper rounding) - if ((destination_exp_q >= signed'(2**fpnew_pkg::exp_bits(dst_fmt_q2))-1) || - (~src_is_int_q && info_q.is_inf)) begin + // Infinities + if (~src_is_int_q && info_q.is_inf) begin + final_exp = unsigned'(2**fpnew_pkg::exp_bits(dst_fmt_q2)-1); // largest exponent + preshift_mant = '0; + // Overflow (for proper rounding) + end else if (destination_exp_q >= signed'(2**fpnew_pkg::exp_bits(dst_fmt_q2))-1) begin final_exp = unsigned'(2**fpnew_pkg::exp_bits(dst_fmt_q2)-2); // largest normal value preshift_mant = '1; // largest normal value and RS bits set of_before_round = 1'b1; @@ -21993,14 +25936,16 @@ module fpnew_cast_multi #( logic [NUM_FORMATS-1:0] fmt_of_after_round; logic [NUM_FORMATS-1:0] fmt_uf_after_round; - logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_pre_round_abs; // per format + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_pre_round_abs; // per format + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_rounded_signed_res; // per format logic [NUM_INT_FORMATS-1:0] ifmt_of_after_round; logic rounded_sign; logic [WIDTH-1:0] rounded_abs; // absolute value of result after rounding logic result_true_zero; - logic [WIDTH-1:0] rounded_int_res; // after possible inversion + logic [WIDTH-1:0] rounded_uint_res; // after possible inversion + logic [WIDTH-1:0] rounded_int_res; // sign-extended, after possible inversion logic rounded_int_res_zero; // after rounding @@ -22019,15 +25964,15 @@ module fpnew_cast_multi #( end end - // Sign-extend integer result - for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_sign_ext + // Zero-extend integer result + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_zero_ext // Set up some constants localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); if (IntFmtConfig[ifmt]) begin : active_format always_comb begin : assemble_result - // sign-extend reusult - ifmt_pre_round_abs[ifmt] = '{default: final_int[INT_WIDTH-1]}; + // zero-extend absolute value result + ifmt_pre_round_abs[ifmt] = '0; ifmt_pre_round_abs[ifmt][INT_WIDTH-1:0] = final_int[INT_WIDTH-1:0]; end end else begin : inactive_format @@ -22063,7 +26008,9 @@ module fpnew_cast_multi #( if (FpFmtConfig[fmt]) begin : active_format always_comb begin : post_process // detect of / uf - fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal + fmt_uf_after_round[fmt] = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal + || ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && + ((round_sticky_bits != 2'b11) || (!destination_mant[NUM_FP_STICKY-1] && ((rnd_mode_q == fpnew_pkg::RNE) || (rnd_mode_q == fpnew_pkg::RMM))))); fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. // Assemble regular result, nan box short ones. Int zeroes need to be detected` @@ -22080,8 +26027,26 @@ module fpnew_cast_multi #( end // Negative integer result needs to be brought into two's complement - assign rounded_int_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs; - assign rounded_int_res_zero = (rounded_int_res == '0); + assign rounded_uint_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs; + + // Sign-extend integer result + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_sign_ext + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : assemble_result + // zero-extend absolute value result + ifmt_rounded_signed_res[ifmt] = '{default: rounded_uint_res[INT_WIDTH-1]}; + ifmt_rounded_signed_res[ifmt][INT_WIDTH-1:0] = rounded_uint_res[INT_WIDTH-1:0]; + end + end else begin : inactive_format + assign ifmt_rounded_signed_res[ifmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + assign rounded_int_res = ifmt_rounded_signed_res[int_fmt_q2]; + assign rounded_int_res_zero = (rounded_int_res == '0) && (pre_round_abs == '0); // Detect integer overflows after rounding (only positives) for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_overflow @@ -22096,6 +26061,14 @@ module fpnew_cast_multi #( // Check whether the rounded MSB differs from unrounded MSB ifmt_of_after_round[ifmt] = ~rounded_int_res[INT_WIDTH-2+op_mod_q2]; end + // Negative overflow: value at exp=INT_WIDTH-1 rounded more negative than INT_MIN + // This can happen with RDN/RNE when fractional bits cause rounding away from zero. + // Detect by checking if the negated magnitude overflowed INT_MIN's bit position. + if (!op_mod_q2 && rounded_sign && input_exp_q == signed'(INT_WIDTH - 1)) begin + ifmt_of_after_round[ifmt] = ~rounded_uint_res[INT_WIDTH-1]; + // If bit INT_WIDTH-1 is set in the two's complement negative result, it means + // -(magnitude) underflowed past INT_MIN = -2^(INT_WIDTH-1) + end end end else begin : inactive_format assign ifmt_of_after_round[ifmt] = fpnew_pkg::DONT_CARE; @@ -22206,13 +26179,13 @@ module fpnew_cast_multi #( logic [WIDTH-1:0] fp_result, int_result; fpnew_pkg::status_t fp_status, int_status; - assign fp_regular_status.NV = src_is_int_q & (of_before_round | of_after_round); // overflow is invalid for I2F casts + assign fp_regular_status.NV = 1'b0; // floating-point results are always valid assign fp_regular_status.DZ = 1'b0; // no divisions - assign fp_regular_status.OF = ~src_is_int_q & (~info_q.is_inf & (of_before_round | of_after_round)); // inf casts no OF + assign fp_regular_status.OF = (src_is_int_q | ~info_q.is_inf) & (of_before_round | of_after_round); // inf casts no OF assign fp_regular_status.UF = uf_after_round & fp_regular_status.NX; - assign fp_regular_status.NX = src_is_int_q ? (| fp_round_sticky_bits) // overflow is invalid in i2f - : (| fp_round_sticky_bits) | (~info_q.is_inf & (of_before_round | of_after_round)); - assign int_regular_status = '{NX: (| int_round_sticky_bits), default: 1'b0}; + assign fp_regular_status.NX = (| fp_round_sticky_bits) | ((src_is_int_q | ~info_q.is_inf) & (of_before_round | of_after_round)); + assign int_regular_status = '{NV: of_before_round | of_after_round, // overflow is invalid for F2I casts + NX: (| int_round_sticky_bits), default: 1'b0}; assign fp_result = fp_result_is_special ? fp_special_result : fmt_result[dst_fmt_q2]; assign fp_status = fp_result_is_special ? fp_special_status : fp_regular_status; @@ -22286,10 +26259,25 @@ module fpnew_cast_multi #( assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); + + // Early valid_o signal. This is used for dispatching instructions for dual-issue processor. + if (NUM_OUT_REGS > 0) begin + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], + out_pipe_valid_q[NUM_OUT_REGS-1]}; + end else if (NUM_MID_REGS > 0) begin + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS], + mid_pipe_valid_q[NUM_MID_REGS-1]}; + end else if (NUM_INP_REGS > 0) begin + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], + inp_pipe_valid_q[NUM_INP_REGS-1]}; + end else begin + assign early_out_valid_o = 1'b0; + end + endmodule // ----- 8< ----- FILE "./fpnew_classifier.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -22309,15 +26297,15 @@ module fpnew_classifier #( parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), parameter int unsigned NumOperands = 1, // Do not change - localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) + parameter int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) ) ( input logic [NumOperands-1:0][WIDTH-1:0] operands_i, input logic [NumOperands-1:0] is_boxed_i, output fpnew_pkg::fp_info_t [NumOperands-1:0] info_o ); - localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); - localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + parameter int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + parameter int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); // Type definition typedef struct packed { @@ -22416,9 +26404,9 @@ assign SE = pad_yy_icg_scan_en; assign clk_out = clk_in; endmodule -// ----- 8< ----- FILE "./pa_fdsu_ctrl.v" ----- 8< ----- +// ----- 8< ----- FILE "./ct_vfdsu_ctrl.v" ----- 8< ----- -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -22433,438 +26421,240 @@ See the License for the specific language governing permissions and limitations under the License. */ +// &Depend("cpu_cfig.h"); @22 // &ModuleBeg; @23 -module pa_fdsu_ctrl( - cp0_fpu_icg_en, +module ct_vfdsu_ctrl( + cp0_vfpu_icg_en, cp0_yy_clk_en, cpurst_b, - ctrl_fdsu_ex1_sel, - ctrl_xx_ex1_cmplt_dp, - ctrl_xx_ex1_inst_vld, - ctrl_xx_ex1_stall, - ctrl_xx_ex1_warm_up, - ctrl_xx_ex2_warm_up, - ctrl_xx_ex3_warm_up, - ex1_div, - ex1_expnt_adder_op0, - ex1_of_result_lfn, - ex1_op0_id, - ex1_op0_norm, - ex1_op1_id_vld, - ex1_op1_norm, - ex1_op1_sel, - ex1_oper_id_expnt, - ex1_oper_id_expnt_f, + dp_vfdsu_ex1_pipex_sel, + dp_vfdsu_fdiv_gateclk_issue, + dp_vfdsu_idu_fdiv_issue, + ex1_data_clk, + ex1_double, ex1_pipedown, - ex1_pipedown_gate, - ex1_result_sign, - ex1_rm, - ex1_save_op0, - ex1_save_op0_gate, - ex1_sqrt, - ex1_srt_skip, - ex2_expnt_adder_op0, - ex2_of, - ex2_pipe_clk, + ex1_single, + ex1_half, + ex1_bfloat, + ex2_data_clk, ex2_pipedown, - ex2_potnt_of, - ex2_potnt_uf, - ex2_result_inf, - ex2_result_lfn, - ex2_rslt_denorm, - ex2_srt_expnt_rst, ex2_srt_first_round, - ex2_uf, - ex2_uf_srt_skip, - ex3_expnt_adjust_result, + ex3_data_clk, ex3_pipedown, - ex3_rslt_denorm, - fdsu_ex1_sel, - fdsu_fpu_debug_info, - fdsu_fpu_ex1_cmplt, - fdsu_fpu_ex1_cmplt_dp, - fdsu_fpu_ex1_stall, - fdsu_fpu_no_op, - fdsu_frbus_wb_vld, - fdsu_yy_div, - fdsu_yy_expnt_rst, - fdsu_yy_of, - fdsu_yy_of_rm_lfn, - fdsu_yy_op0_norm, - fdsu_yy_op1_norm, - fdsu_yy_potnt_of, - fdsu_yy_potnt_uf, - fdsu_yy_result_inf, - fdsu_yy_result_lfn, - fdsu_yy_result_sign, - fdsu_yy_rm, - fdsu_yy_rslt_denorm, - fdsu_yy_sqrt, - fdsu_yy_uf, - fdsu_yy_wb_freg, forever_cpuclk, - frbus_fdsu_wb_grant, - idu_fpu_ex1_dst_freg, - idu_fpu_ex1_eu_sel, pad_yy_icg_scan_en, - rtu_xx_ex1_cancel, - rtu_xx_ex2_cancel, - rtu_yy_xx_async_flush, + pipex_dp_vfdsu_inst_vld, rtu_yy_xx_flush, - srt_remainder_zero, - srt_sm_on + srt_ctrl_rem_zero, + srt_ctrl_skip_srt, + srt_secd_round, + srt_sm_on, + vfdsu_dp_fdiv_busy, + vfdsu_dp_inst_wb_req, + vfdsu_ex2_double, + vfdsu_ex2_single, + vfdsu_ex2_half, + vfdsu_ex2_bfloat, + vfdsu_ifu_debug_ex2_wait, + vfdsu_ifu_debug_idle, + vfdsu_ifu_debug_pipe_busy ); // &Ports; @24 -input cp0_fpu_icg_en; -input cp0_yy_clk_en; -input cpurst_b; -input ctrl_fdsu_ex1_sel; -input ctrl_xx_ex1_cmplt_dp; -input ctrl_xx_ex1_inst_vld; -input ctrl_xx_ex1_stall; -input ctrl_xx_ex1_warm_up; -input ctrl_xx_ex2_warm_up; -input ctrl_xx_ex3_warm_up; -input ex1_div; -input [12:0] ex1_expnt_adder_op0; -input ex1_of_result_lfn; -input ex1_op0_id; -input ex1_op0_norm; -input ex1_op1_id_vld; -input ex1_op1_norm; -input [12:0] ex1_oper_id_expnt; -input ex1_result_sign; -input [2 :0] ex1_rm; -input ex1_sqrt; -input ex1_srt_skip; -input ex2_of; -input ex2_potnt_of; -input ex2_potnt_uf; -input ex2_result_inf; -input ex2_result_lfn; -input ex2_rslt_denorm; -input [9 :0] ex2_srt_expnt_rst; -input ex2_uf; -input ex2_uf_srt_skip; -input [9 :0] ex3_expnt_adjust_result; -input ex3_rslt_denorm; -input forever_cpuclk; -input frbus_fdsu_wb_grant; -input [4 :0] idu_fpu_ex1_dst_freg; -input [2 :0] idu_fpu_ex1_eu_sel; -input pad_yy_icg_scan_en; -input rtu_xx_ex1_cancel; -input rtu_xx_ex2_cancel; -input rtu_yy_xx_async_flush; -input rtu_yy_xx_flush; -input srt_remainder_zero; -output ex1_op1_sel; -output [12:0] ex1_oper_id_expnt_f; -output ex1_pipedown; -output ex1_pipedown_gate; -output ex1_save_op0; -output ex1_save_op0_gate; -output [9 :0] ex2_expnt_adder_op0; -output ex2_pipe_clk; -output ex2_pipedown; -output ex2_srt_first_round; -output ex3_pipedown; -output fdsu_ex1_sel; -output [4 :0] fdsu_fpu_debug_info; -output fdsu_fpu_ex1_cmplt; -output fdsu_fpu_ex1_cmplt_dp; -output fdsu_fpu_ex1_stall; -output fdsu_fpu_no_op; -output fdsu_frbus_wb_vld; -output fdsu_yy_div; -output [9 :0] fdsu_yy_expnt_rst; -output fdsu_yy_of; -output fdsu_yy_of_rm_lfn; -output fdsu_yy_op0_norm; -output fdsu_yy_op1_norm; -output fdsu_yy_potnt_of; -output fdsu_yy_potnt_uf; -output fdsu_yy_result_inf; -output fdsu_yy_result_lfn; -output fdsu_yy_result_sign; -output [2 :0] fdsu_yy_rm; -output fdsu_yy_rslt_denorm; -output fdsu_yy_sqrt; -output fdsu_yy_uf; -output [4 :0] fdsu_yy_wb_freg; -output srt_sm_on; +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input dp_vfdsu_ex1_pipex_sel; +input dp_vfdsu_fdiv_gateclk_issue; +input dp_vfdsu_idu_fdiv_issue; +input ex1_double; +input ex1_single; +input ex1_half; +input ex1_bfloat; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input rtu_yy_xx_flush; +input srt_ctrl_rem_zero; +input srt_ctrl_skip_srt; +input vfdsu_ex2_double; +input vfdsu_ex2_single; +input vfdsu_ex2_half; +input vfdsu_ex2_bfloat; +output ex1_data_clk; +output ex1_pipedown; +output ex2_data_clk; +output ex2_pipedown; +output ex2_srt_first_round; +output ex3_data_clk; +output ex3_pipedown; +output pipex_dp_vfdsu_inst_vld; +output srt_secd_round; +output srt_sm_on; +output vfdsu_dp_fdiv_busy; +output vfdsu_dp_inst_wb_req; +output vfdsu_ifu_debug_ex2_wait; +output vfdsu_ifu_debug_idle; +output vfdsu_ifu_debug_pipe_busy; // &Regs; @25 -reg ex2_srt_first_round; -reg [2 :0] fdsu_cur_state; -reg fdsu_div; -reg [9 :0] fdsu_expnt_rst; -reg [2 :0] fdsu_next_state; -reg fdsu_of; -reg fdsu_of_rm_lfn; -reg fdsu_potnt_of; -reg fdsu_potnt_uf; -reg fdsu_result_inf; -reg fdsu_result_lfn; -reg fdsu_result_sign; -reg [2 :0] fdsu_rm; -reg fdsu_sqrt; -reg fdsu_uf; -reg [4 :0] fdsu_wb_freg; -reg fdsu_yy_rslt_denorm; -reg [4 :0] srt_cnt; -reg [1 :0] wb_cur_state; -reg [1 :0] wb_nxt_state; +reg [3:0] div_cur_state; +reg [3:0] div_next_state; +reg ex2_srt_first_round; +reg ex2_srt_secd_round; +reg [4:0] srt_cnt; +reg srt_cur_state; +reg srt_nxt_state; +reg vfdsu_ex3_vld; +reg vfdsu_ex4_vld; // &Wires; @26 -wire cp0_fpu_icg_en; -wire cp0_yy_clk_en; -wire cpurst_b; -wire ctrl_fdsu_ex1_sel; -wire ctrl_fdsu_ex1_stall; -wire ctrl_fdsu_wb_vld; -wire ctrl_iter_start; -wire ctrl_iter_start_gate; -wire ctrl_pack; -wire ctrl_result_vld; -wire ctrl_round; -wire ctrl_sm_cmplt; -wire ctrl_sm_ex1; -wire ctrl_sm_idle; -wire ctrl_sm_start; -wire ctrl_sm_start_gate; -wire ctrl_srt_idle; -wire ctrl_srt_itering; -wire ctrl_wb_idle; -wire ctrl_wb_sm_cmplt; -wire ctrl_wb_sm_ex2; -wire ctrl_wb_sm_idle; -wire ctrl_wfi2; -wire ctrl_wfwb; -wire ctrl_xx_ex1_cmplt_dp; -wire ctrl_xx_ex1_inst_vld; -wire ctrl_xx_ex1_stall; -wire ctrl_xx_ex1_warm_up; -wire ctrl_xx_ex2_warm_up; -wire ctrl_xx_ex3_warm_up; -wire ex1_div; -wire [12:0] ex1_expnt_adder_op0; -wire ex1_of_result_lfn; -wire ex1_op0_id; -wire ex1_op1_id_vld; -wire ex1_op1_sel; -wire [12:0] ex1_oper_id_expnt; -wire [12:0] ex1_oper_id_expnt_f; -wire ex1_pipe_clk; -wire ex1_pipe_clk_en; -wire ex1_pipedown; -wire ex1_pipedown_gate; -wire ex1_result_sign; -wire [2 :0] ex1_rm; -wire ex1_save_op0; -wire ex1_save_op0_gate; -wire ex1_sqrt; -wire ex1_srt_skip; -wire [4 :0] ex1_wb_freg; -wire [9 :0] ex2_expnt_adder_op0; -wire ex2_of; -wire ex2_pipe_clk; -wire ex2_pipe_clk_en; -wire ex2_pipedown; -wire ex2_potnt_of; -wire ex2_potnt_uf; -wire ex2_result_inf; -wire ex2_result_lfn; -wire ex2_rslt_denorm; -wire [9 :0] ex2_srt_expnt_rst; -wire ex2_uf; -wire ex2_uf_srt_skip; -wire [9 :0] ex3_expnt_adjust_result; -wire ex3_pipedown; -wire ex3_rslt_denorm; -wire expnt_rst_clk; -wire expnt_rst_clk_en; -wire fdsu_busy; -wire fdsu_clk; -wire fdsu_clk_en; -wire fdsu_dn_stall; -wire fdsu_ex1_inst_vld; -wire fdsu_ex1_res_vld; -wire fdsu_ex1_sel; -wire fdsu_flush; -wire [4 :0] fdsu_fpu_debug_info; -wire fdsu_fpu_ex1_cmplt; -wire fdsu_fpu_ex1_cmplt_dp; -wire fdsu_fpu_ex1_stall; -wire fdsu_fpu_no_op; -wire fdsu_frbus_wb_vld; -wire fdsu_op0_norm; -wire fdsu_op1_norm; -wire fdsu_wb_grant; -wire fdsu_yy_div; -wire [9 :0] fdsu_yy_expnt_rst; -wire fdsu_yy_of; -wire fdsu_yy_of_rm_lfn; -wire fdsu_yy_op0_norm; -wire fdsu_yy_op1_norm; -wire fdsu_yy_potnt_of; -wire fdsu_yy_potnt_uf; -wire fdsu_yy_result_inf; -wire fdsu_yy_result_lfn; -wire fdsu_yy_result_sign; -wire [2 :0] fdsu_yy_rm; -wire fdsu_yy_sqrt; -wire fdsu_yy_uf; -wire [4 :0] fdsu_yy_wb_freg; -wire forever_cpuclk; -wire frbus_fdsu_wb_grant; -wire [4 :0] idu_fpu_ex1_dst_freg; -wire [2 :0] idu_fpu_ex1_eu_sel; -wire pad_yy_icg_scan_en; -wire rtu_xx_ex1_cancel; -wire rtu_xx_ex2_cancel; -wire rtu_yy_xx_async_flush; -wire rtu_yy_xx_flush; -wire [4 :0] srt_cnt_ini; -wire srt_cnt_zero; -wire srt_last_round; -wire srt_remainder_zero; -wire srt_skip; -wire srt_sm_on; +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire div_sm_clk; +wire div_sm_clk_en; +wire div_st_ex2; +wire dp_vfdsu_ex1_pipex_sel; +wire dp_vfdsu_fdiv_gateclk_issue; +wire dp_vfdsu_idu_fdiv_issue; +wire ex1_data_clk; +wire ex1_data_clk_en; +wire ex1_double; +wire ex1_pipedown; +wire ex1_single; +wire ex1_half; +wire ex1_bfloat; +wire ex2_data_clk; +wire ex2_data_clk_en; +wire ex2_pipe_clk; +wire ex2_pipe_clk_en; +wire ex2_pipedown; +wire ex2_srt_secd_round_pre; +wire ex3_data_clk; +wire ex3_data_clk_en; +wire ex3_pipe_clk; +wire ex3_pipe_clk_en; +wire ex3_pipedown; +wire ex4_pipedown; +wire forever_cpuclk; +wire pad_yy_icg_scan_en; +wire pipex_dp_vfdsu_inst_vld; +wire rtu_yy_xx_flush; +wire skip_srt; +wire [4:0] srt_cnt_ini; +wire srt_cnt_zero; +wire srt_ctrl_rem_zero; +wire srt_ctrl_skip_srt; +wire srt_last_round; +wire srt_secd_round; +wire srt_secd_round_pre; +wire srt_sm_clk; +wire srt_sm_clk_en; +wire srt_sm_on; +wire vfdsu_dp_fdiv_busy; +wire vfdsu_dp_inst_wb_req; +wire vfdsu_ex2_double; +wire vfdsu_ex2_single; +wire vfdsu_ex2_half; +wire vfdsu_ex2_bfloat; +wire vfdsu_ex2_vld; +wire vfdsu_ifu_debug_ex2_wait; +wire vfdsu_ifu_debug_idle; +wire vfdsu_ifu_debug_pipe_busy; //========================================================== -// Input Signal +// EX1 Stage Control Signal //========================================================== -assign ex1_wb_freg[4:0] = idu_fpu_ex1_dst_freg[4:0]; -assign fdsu_ex1_inst_vld = ctrl_xx_ex1_inst_vld && ctrl_fdsu_ex1_sel; -assign fdsu_ex1_sel = idu_fpu_ex1_eu_sel[2]; -// &Force("input", "idu_fpu_ex1_eu_sel"); &Force("bus", "idu_fpu_ex1_eu_sel", 2, 0); @34 +//vfdsu ex1 pipedown signal +assign ex1_pipedown = dp_vfdsu_ex1_pipex_sel; +// &Force("output","ex1_pipedown"); @34 //========================================================== -// FDSU Main State Machine +// EX2 Stage Control Signal //========================================================== -assign fdsu_ex1_res_vld = fdsu_ex1_inst_vld && ex1_srt_skip; -assign fdsu_wb_grant = frbus_fdsu_wb_grant; - -assign ctrl_iter_start = ctrl_sm_start && !fdsu_dn_stall - || ctrl_wfi2; -assign ctrl_iter_start_gate = ctrl_sm_start_gate && !fdsu_dn_stall - || ctrl_wfi2; -assign ctrl_sm_start = fdsu_ex1_inst_vld && ctrl_srt_idle - && !ex1_srt_skip; -assign ctrl_sm_start_gate = fdsu_ex1_inst_vld && ctrl_srt_idle; - -assign srt_last_round = (srt_skip || - srt_remainder_zero || - srt_cnt_zero) && - ctrl_srt_itering; -assign srt_skip = ex2_of || - ex2_uf_srt_skip; -assign srt_cnt_zero = ~|srt_cnt[4:0]; -assign fdsu_dn_stall = ctrl_sm_start && ex1_op1_id_vld; +//state parameter +parameter SRT_IDLE = 1'b0; +parameter SRT_BUSY = 1'b1; -parameter IDLE = 3'b000; -parameter WFI2 = 3'b001; -parameter ITER = 3'b010; -parameter RND = 3'b011; -parameter PACK = 3'b100; -parameter WFWB = 3'b101; +//gate clk +// &Instance("gated_clk_cell","x_srt_sm_clk"); @43 +gated_clk_cell x_srt_sm_clk ( + .clk_in (forever_cpuclk ), + .clk_out (srt_sm_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (srt_sm_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); -always @ (posedge fdsu_clk or negedge cpurst_b) +// &Connect( .clk_in (forever_cpuclk), @44 +// .clk_out (srt_sm_clk),//Out Clock @45 +// .external_en (1'b0), @46 +// .global_en (cp0_yy_clk_en), @47 +// .local_en (srt_sm_clk_en),//Local Condition @48 +// .module_en (cp0_vfpu_icg_en) @49 +// ); @50 +assign srt_sm_clk_en = srt_cur_state || + ex1_pipedown || + rtu_yy_xx_flush; + +//state machine +always @(posedge srt_sm_clk or negedge cpurst_b) begin - if (!cpurst_b) - fdsu_cur_state[2:0] <= IDLE; - else if (fdsu_flush) - fdsu_cur_state[2:0] <= IDLE; + if(!cpurst_b) + srt_cur_state <= SRT_IDLE; + else if(rtu_yy_xx_flush) + srt_cur_state <= SRT_IDLE; else - fdsu_cur_state[2:0] <= fdsu_next_state[2:0]; + srt_cur_state <= srt_nxt_state; end -// &CombBeg; @76 -always @( ctrl_sm_start - or fdsu_dn_stall +// &CombBeg; @66 +always @( ex1_pipedown or srt_last_round - or fdsu_cur_state[2:0] - or fdsu_wb_grant) + or srt_cur_state) begin -case (fdsu_cur_state[2:0]) - IDLE: - begin - if (ctrl_sm_start) - if (fdsu_dn_stall) - fdsu_next_state[2:0] = WFI2; - else - fdsu_next_state[2:0] = ITER; - else - fdsu_next_state[2:0] = IDLE; - end - WFI2: - fdsu_next_state[2:0] = ITER; - ITER: - begin - if (srt_last_round) - fdsu_next_state[2:0] = RND; - else - fdsu_next_state[2:0] = ITER; - end - RND: - fdsu_next_state[2:0] = PACK; - PACK: - begin - if (fdsu_wb_grant) - if (ctrl_sm_start) - if (fdsu_dn_stall) - fdsu_next_state[2:0] = WFI2; - else - fdsu_next_state[2:0] = ITER; - else - fdsu_next_state[2:0] = IDLE; - else - fdsu_next_state[2:0] = WFWB; - end - WFWB: - begin - if (fdsu_wb_grant) - if (ctrl_sm_start) - if (fdsu_dn_stall) - fdsu_next_state[2:0] = WFI2; - else - fdsu_next_state[2:0] = ITER; - else - fdsu_next_state[2:0] = IDLE; - else - fdsu_next_state[2:0] = WFWB; - end - default: - fdsu_next_state[2:0] = IDLE; +case(srt_cur_state) +SRT_IDLE : if(ex1_pipedown) + srt_nxt_state = SRT_BUSY; + else + srt_nxt_state = SRT_IDLE; +SRT_BUSY : if(srt_last_round) + srt_nxt_state = SRT_IDLE; + else + srt_nxt_state = SRT_BUSY; +default : srt_nxt_state = SRT_IDLE; endcase -// &CombEnd; @128 +// &CombEnd; @78 end -assign ctrl_sm_idle = fdsu_cur_state[2:0] == IDLE; -assign ctrl_wfi2 = fdsu_cur_state[2:0] == WFI2; -assign ctrl_srt_itering = fdsu_cur_state[2:0] == ITER; -assign ctrl_round = fdsu_cur_state[2:0] == RND; -assign ctrl_pack = fdsu_cur_state[2:0] == PACK; -assign ctrl_wfwb = fdsu_cur_state[2:0] == WFWB; - -assign ctrl_sm_cmplt = ctrl_pack || ctrl_wfwb; -assign ctrl_srt_idle = ctrl_sm_idle - || fdsu_wb_grant; -assign ctrl_sm_ex1 = ctrl_srt_idle || ctrl_wfi2; - -//========================================================== -// Iteration Counter -//========================================================== -always @ (posedge fdsu_clk) +//srt sm state +//assign srt_sm_idle = ~srt_cur_state; +assign srt_sm_on = srt_cur_state; +// &Force("output","srt_sm_on"); @83 +//state machine control signal +//srt_last_round on three condition : +// 1.srt need not execute +// 2.srt rem is zero +// 3.srt cnt zero +assign srt_last_round = (skip_srt || + srt_ctrl_rem_zero || + srt_cnt_zero) && + srt_sm_on; +assign skip_srt = srt_ctrl_skip_srt; +assign srt_cnt_zero = ~|srt_cnt[4:0]; +//srt counter +always @(posedge srt_sm_clk or negedge cpurst_b) begin - if (fdsu_flush) + if(!cpurst_b) srt_cnt[4:0] <= 5'b0; - else if (ctrl_iter_start) + else if(rtu_yy_xx_flush) + srt_cnt[4:0] <= 5'b0; + else if(ex1_pipedown) srt_cnt[4:0] <= srt_cnt_ini[4:0]; - else if (ctrl_srt_itering) + else if(srt_sm_on) srt_cnt[4:0] <= srt_cnt[4:0] - 5'b1; else srt_cnt[4:0] <= srt_cnt[4:0]; @@ -22873,337 +26663,287 @@ end //srt_cnt_ini[4:0] //For Double, initial is 5'b11100('d28), calculate 29 round //For Single, initial is 5'b01110('d14), calculate 15 round -assign srt_cnt_ini[4:0] = 5'b01110; - -//fdsu srt first round signal -//For srt calculate special use -always @(posedge fdsu_clk or negedge cpurst_b) -begin - if(!cpurst_b) - ex2_srt_first_round <= 1'b0; - else if(fdsu_flush) - ex2_srt_first_round <= 1'b0; - else if(ex1_pipedown) - ex2_srt_first_round <= 1'b1; - else - ex2_srt_first_round <= 1'b0; -end - -//========================================================== -// Write Back State Machine -//========================================================== -parameter WB_IDLE = 2'b00, - WB_EX2 = 2'b10, - WB_CMPLT = 2'b01; - -always @ (posedge fdsu_clk or negedge cpurst_b) -begin - if (!cpurst_b) - wb_cur_state[1:0] <= WB_IDLE; - else if (fdsu_flush) - wb_cur_state[1:0] <= WB_IDLE; - else - wb_cur_state[1:0] <= wb_nxt_state[1:0]; -end - -// &CombBeg; @215 -always @( ctrl_fdsu_wb_vld - or fdsu_dn_stall - or ctrl_xx_ex1_stall - or fdsu_ex1_inst_vld - or ctrl_iter_start - or fdsu_ex1_res_vld - or wb_cur_state[1:0]) +assign srt_cnt_ini[4:0] = (ex1_double) ? 5'b01101 : + (ex1_single) ? 5'b00110 : + (ex1_half) ? 5'b00011 + : 5'b00010; + +//vfdsu ex2 pipedown signal +assign ex2_pipedown = srt_last_round && div_st_ex2; +// &Force("output","ex2_pipedown"); @157 +// &Force("output","ex2_srt_first_round"); @172 +always @(posedge srt_sm_clk or negedge cpurst_b) begin - case(wb_cur_state[1:0]) - WB_IDLE: - if (fdsu_ex1_inst_vld) - if (ctrl_xx_ex1_stall || fdsu_ex1_res_vld || fdsu_dn_stall) - wb_nxt_state[1:0] = WB_IDLE; - else - wb_nxt_state[1:0] = WB_EX2; - else - wb_nxt_state[1:0] = WB_IDLE; - WB_EX2: - // if (ctrl_xx_ex2_stall) - // wb_nxt_state[1:0] = WB_EX2; - // else - if (ctrl_fdsu_wb_vld) - if (ctrl_iter_start && !ctrl_xx_ex1_stall) - wb_nxt_state[1:0] = WB_EX2; - else - wb_nxt_state[1:0] = WB_IDLE; - else - wb_nxt_state[1:0] = WB_CMPLT; - WB_CMPLT: - if (ctrl_fdsu_wb_vld) - if (ctrl_iter_start && !ctrl_xx_ex1_stall) - wb_nxt_state[1:0] = WB_EX2; - else - wb_nxt_state[1:0] = WB_IDLE; - else - wb_nxt_state[1:0] = WB_CMPLT; - default: - wb_nxt_state[1:0] = WB_IDLE; - endcase -// &CombEnd; @247 + if(!cpurst_b) + ex2_srt_first_round <= 1'b0; + else if(rtu_yy_xx_flush) + ex2_srt_first_round <= 1'b0; + else if(ex1_pipedown) + ex2_srt_first_round <= 1'h1; + else + ex2_srt_first_round <= 1'b0; end - -assign ctrl_wb_idle = wb_cur_state[1:0] == WB_IDLE - || wb_cur_state[1:0] == WB_CMPLT && ctrl_fdsu_wb_vld; -assign ctrl_wb_sm_idle = wb_cur_state[1:0] == WB_IDLE; -assign ctrl_wb_sm_ex2 = wb_cur_state[1:0] == WB_EX2; -assign ctrl_wb_sm_cmplt = wb_cur_state[1:0] == WB_EX2 - || wb_cur_state[1:0] == WB_CMPLT; - -assign ctrl_result_vld = ctrl_sm_cmplt && ctrl_wb_sm_cmplt; -assign ctrl_fdsu_wb_vld = ctrl_result_vld && frbus_fdsu_wb_grant; - -assign ctrl_fdsu_ex1_stall = fdsu_ex1_inst_vld && !ctrl_sm_ex1 && !ctrl_wb_idle - || fdsu_ex1_inst_vld && fdsu_dn_stall; - -//========================================================== -// Flops -//========================================================== -always @(posedge ex1_pipe_clk) +// &Force("output","ex2_srt_first_round"); @195 +always @(posedge srt_sm_clk or negedge cpurst_b) begin - if(ex1_pipedown) - begin - fdsu_wb_freg[4:0] <= ex1_wb_freg[4:0]; - fdsu_result_sign <= ex1_result_sign; - fdsu_of_rm_lfn <= ex1_of_result_lfn; - fdsu_div <= ex1_div; - fdsu_sqrt <= ex1_sqrt; - fdsu_rm[2:0] <= ex1_rm[2:0]; - end + if(!cpurst_b) + ex2_srt_secd_round <= 1'b0; + else if(rtu_yy_xx_flush) + ex2_srt_secd_round <= 1'b0; else - begin - fdsu_wb_freg[4:0] <= fdsu_wb_freg[4:0]; - fdsu_result_sign <= fdsu_result_sign; - fdsu_of_rm_lfn <= fdsu_of_rm_lfn; - fdsu_div <= fdsu_div; - fdsu_sqrt <= fdsu_sqrt; - fdsu_rm[2:0] <= fdsu_rm[2:0]; - end + ex2_srt_secd_round <= {1{ex2_srt_secd_round_pre}}; end +assign srt_secd_round = ex2_srt_secd_round; -// In 906 FDSU, if one op0/1 is not norm, it will not enter EX2. -assign fdsu_op0_norm = 1'b1; -assign fdsu_op1_norm = 1'b1; -// &Force("input", "ex1_op0_norm"); @337 -// &Force("input", "ex1_op1_norm"); @338 -// fdsu_expnt_rst is used to save: -// 1. op0 denormal expnt; -// 2. op0 expnt; -// 3. result expnt. -// &Force("bus", "ex1_oper_id_expnt", 12, 0); @378 -// &Force("bus", "ex1_expnt_adder_op0", 12, 0); @379 +assign ex2_srt_secd_round_pre = srt_sm_on && srt_secd_round_pre; +assign srt_secd_round_pre = vfdsu_ex2_double ? srt_cnt[4:0]==5'b01101 : + vfdsu_ex2_single ? srt_cnt[4:0]==5'b00110 : + vfdsu_ex2_half ? srt_cnt[4:0]==5'b00011 + : srt_cnt[4:0]==5'b00010; +//========================================================== +// EX3 Stage Control Signal +//========================================================== +//gate clk +// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @217 +gated_clk_cell x_ex2_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex2_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex2_pipe_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); -always @ (posedge expnt_rst_clk) +// &Connect( .clk_in (forever_cpuclk), @218 +// .clk_out (ex2_pipe_clk),//Out Clock @219 +// .external_en (1'b0), @220 +// .global_en (cp0_yy_clk_en), @221 +// .local_en (ex2_pipe_clk_en),//Local Condition @222 +// .module_en (cp0_vfpu_icg_en) @223 +// ); @224 +assign ex2_pipe_clk_en = vfdsu_ex2_vld || + vfdsu_ex3_vld || + rtu_yy_xx_flush; +assign vfdsu_ex2_vld = ex2_pipedown; +//EX2 to EX3 pipedown +always @(posedge ex2_pipe_clk or negedge cpurst_b) begin - if (ex1_save_op0) - fdsu_expnt_rst[9:0] <= ex1_oper_id_expnt[9:0]; - else if (ex1_pipedown) - fdsu_expnt_rst[9:0] <= ex1_expnt_adder_op0[9:0]; - else if (ex2_pipedown) - fdsu_expnt_rst[9:0] <= ex2_srt_expnt_rst[9:0]; - else if (ex3_pipedown) - fdsu_expnt_rst[9:0] <= ex3_expnt_adjust_result[9:0]; + if(!cpurst_b) + vfdsu_ex3_vld <= 1'b0; + else if(rtu_yy_xx_flush) + vfdsu_ex3_vld <= 1'b0; + else if(ex2_pipedown) + vfdsu_ex3_vld <= 1'b1; else - fdsu_expnt_rst[9:0] <= fdsu_expnt_rst[9:0]; + vfdsu_ex3_vld <= 1'b0; end +assign ex3_pipedown = vfdsu_ex3_vld; +// &Force("output","ex3_pipedown"); @242 -assign ex1_oper_id_expnt_f[12:0] = {3'b1, fdsu_expnt_rst[9:0]}; +//========================================================== +// EX4 Stage Control Signal +//========================================================== +//gate clk +// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @248 +gated_clk_cell x_ex3_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex3_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex3_pipe_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); -always @ (posedge expnt_rst_clk) +// &Connect( .clk_in (forever_cpuclk), @249 +// .clk_out (ex3_pipe_clk),//Out Clock @250 +// .external_en (1'b0), @251 +// .global_en (cp0_yy_clk_en), @252 +// .local_en (ex3_pipe_clk_en),//Local Condition @253 +// .module_en (cp0_vfpu_icg_en) @254 +// ); @255 +assign ex3_pipe_clk_en = ex3_pipedown || + vfdsu_ex4_vld || + rtu_yy_xx_flush; + +//EX3 to EX4 pipedown +always @(posedge ex3_pipe_clk or negedge cpurst_b) begin - if (ex2_pipedown) - fdsu_yy_rslt_denorm <= ex2_rslt_denorm; - else if (ex3_pipedown) - fdsu_yy_rslt_denorm <= ex3_rslt_denorm; + if(!cpurst_b) + vfdsu_ex4_vld <= 1'b0; + else if(rtu_yy_xx_flush) + vfdsu_ex4_vld <= 1'b0; + else if(ex3_pipedown) + vfdsu_ex4_vld <= 1'b1; else - fdsu_yy_rslt_denorm <= fdsu_yy_rslt_denorm; + vfdsu_ex4_vld <= 1'b0; end -// &Force("output", "fdsu_yy_rslt_denorm"); @440 +assign ex4_pipedown = vfdsu_ex4_vld; -// EX2 signal used in EX3 & EX4 -always @ (posedge ex2_pipe_clk) -begin - if (ex2_pipedown) - begin - fdsu_result_inf <= ex2_result_inf; - fdsu_result_lfn <= ex2_result_lfn; - fdsu_of <= ex2_of; - fdsu_uf <= ex2_uf; - fdsu_potnt_of <= ex2_potnt_of; - fdsu_potnt_uf <= ex2_potnt_uf; - end - else - begin - fdsu_result_inf <= fdsu_result_inf; - fdsu_result_lfn <= fdsu_result_lfn; - fdsu_of <= fdsu_of; - fdsu_uf <= fdsu_uf; - fdsu_potnt_of <= fdsu_potnt_of; - fdsu_potnt_uf <= fdsu_potnt_uf; - end -end -//========================================================== -// Flush -//========================================================== -assign fdsu_flush = rtu_xx_ex1_cancel && ctrl_wb_idle - || rtu_xx_ex2_cancel && ctrl_wb_sm_ex2 - || ctrl_xx_ex1_warm_up - || rtu_yy_xx_async_flush; +//Div Write Back State Machine +parameter IDLE = 4'b0000; +parameter RF = 4'b0100; +parameter EX1 = 4'b0101; +parameter EX2 = 4'b0110; +parameter WB_REQ = 4'b0111; +parameter WB = 4'b1000; -//========================================================== -// ICG -//========================================================== -assign fdsu_busy = fdsu_ex1_inst_vld - || !ctrl_sm_idle - || !ctrl_wb_sm_idle; -assign fdsu_clk_en = fdsu_busy - || !ctrl_sm_idle - || rtu_yy_xx_flush; -// &Instance("gated_clk_cell", "x_fdsu_clk"); @514 -gated_clk_cell x_fdsu_clk ( +//GateClk +// &Instance("gated_clk_cell","x_div_sm_clk"); @284 +gated_clk_cell x_div_sm_clk ( .clk_in (forever_cpuclk ), - .clk_out (fdsu_clk ), + .clk_out (div_sm_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (fdsu_clk_en ), - .module_en (cp0_fpu_icg_en ), + .local_en (div_sm_clk_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect(.clk_in (forever_cpuclk), @515 -// .external_en (1'b0), @516 -// .global_en (cp0_yy_clk_en), @517 -// .module_en (cp0_fpu_icg_en), @518 -// .local_en (fdsu_clk_en), @519 -// .clk_out (fdsu_clk)); @520 +// &Connect( .clk_in (forever_cpuclk), @285 +// .clk_out (div_sm_clk),//Out Clock @286 +// .external_en (1'b0), @287 +// .global_en (cp0_yy_clk_en), @288 +// .local_en (div_sm_clk_en),//Local Condition @289 +// .module_en (cp0_vfpu_icg_en) @290 +// ); @291 +assign div_sm_clk_en = dp_vfdsu_fdiv_gateclk_issue || + !(div_cur_state[3:0] == IDLE); +//State Trans +always @(posedge div_sm_clk or negedge cpurst_b) +begin + if(!cpurst_b) + div_cur_state[3:0] <= IDLE; + else if(rtu_yy_xx_flush) + div_cur_state[3:0] <= IDLE; + else + div_cur_state[3:0] <= div_next_state[3:0]; +end +// &CombBeg; @304 +always @( dp_vfdsu_idu_fdiv_issue + or dp_vfdsu_ex1_pipex_sel + or ex4_pipedown + or srt_last_round + or div_cur_state[3:0]) +begin + case(div_cur_state[3:0]) + IDLE : if(dp_vfdsu_idu_fdiv_issue) + div_next_state[3:0] = RF; + else + div_next_state[3:0] = IDLE; + RF : div_next_state[3:0] = EX1; + EX1 : if(dp_vfdsu_ex1_pipex_sel) + div_next_state[3:0] = EX2; + else + div_next_state[3:0] = IDLE; + EX2 : if(srt_last_round) + div_next_state[3:0] = WB_REQ; + else + div_next_state[3:0] = EX2; + WB_REQ : if(ex4_pipedown) + div_next_state[3:0] = WB; + else + div_next_state[3:0] = WB_REQ; + WB : if(dp_vfdsu_idu_fdiv_issue) + div_next_state[3:0] = RF; + else + div_next_state[3:0] = IDLE; + default : div_next_state[3:0] = IDLE; + endcase +// &CombEnd; @329 +end +//Control Signal +assign div_st_ex2 = (div_cur_state[3:0] == EX2); + +//Div Rdy Signal +//assign vfdsu_vfpu_gateclk_en = div_cur_state[2] || div_cur_state[3] || +// ex4_pipedown; -assign ex1_pipe_clk_en = ex1_pipedown_gate; -// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @523 -gated_clk_cell x_ex1_pipe_clk ( + +//Active Data with VFPU +//GateClk +// &Instance("gated_clk_cell","x_ex1_data_clk"); @340 +gated_clk_cell x_ex1_data_clk ( .clk_in (forever_cpuclk ), - .clk_out (ex1_pipe_clk ), + .clk_out (ex1_data_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (ex1_pipe_clk_en ), - .module_en (cp0_fpu_icg_en ), + .local_en (ex1_data_clk_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect( .clk_in (forever_cpuclk), @524 -// .clk_out (ex1_pipe_clk),//Out Clock @525 -// .external_en (1'b0), @526 -// .global_en (cp0_yy_clk_en), @527 -// .local_en (ex1_pipe_clk_en),//Local Condition @528 -// .module_en (cp0_fpu_icg_en) @529 -// ); @530 - -assign ex2_pipe_clk_en = ex2_pipedown; -// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @533 -gated_clk_cell x_ex2_pipe_clk ( +// &Connect( .clk_in (forever_cpuclk), @341 +// .clk_out (ex1_data_clk),//Out Clock @342 +// .external_en (1'b0), @343 +// .global_en (cp0_yy_clk_en), @344 +// .local_en (ex1_data_clk_en),//Local Condition @345 +// .module_en (cp0_vfpu_icg_en) @346 +// ); @347 +assign ex1_data_clk_en = ex1_pipedown; + +// &Instance("gated_clk_cell","x_ex2_data_clk"); @350 +gated_clk_cell x_ex2_data_clk ( .clk_in (forever_cpuclk ), - .clk_out (ex2_pipe_clk ), + .clk_out (ex2_data_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (ex2_pipe_clk_en ), - .module_en (cp0_fpu_icg_en ), + .local_en (ex2_data_clk_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect( .clk_in (forever_cpuclk), @534 -// .clk_out (ex2_pipe_clk),//Out Clock @535 -// .external_en (1'b0), @536 -// .global_en (cp0_yy_clk_en), @537 -// .local_en (ex2_pipe_clk_en),//Local Condition @538 -// .module_en (cp0_fpu_icg_en) @539 -// ); @540 -// &Force("output", "ex2_pipe_clk"); @541 - -assign expnt_rst_clk_en = ex1_save_op0_gate - || ex1_pipedown_gate - || ex2_pipedown - || ex3_pipedown; -// &Instance("gated_clk_cell", "x_expnt_rst_clk"); @547 -gated_clk_cell x_expnt_rst_clk ( +// &Connect( .clk_in (forever_cpuclk), @351 +// .clk_out (ex2_data_clk),//Out Clock @352 +// .external_en (1'b0), @353 +// .global_en (cp0_yy_clk_en), @354 +// .local_en (ex2_data_clk_en),//Local Condition @355 +// .module_en (cp0_vfpu_icg_en) @356 +// ); @357 +assign ex2_data_clk_en = ex2_pipedown; + +// &Instance("gated_clk_cell","x_ex3_data_clk"); @360 +gated_clk_cell x_ex3_data_clk ( .clk_in (forever_cpuclk ), - .clk_out (expnt_rst_clk ), + .clk_out (ex3_data_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (expnt_rst_clk_en ), - .module_en (cp0_fpu_icg_en ), + .local_en (ex3_data_clk_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect(.clk_in (forever_cpuclk), @548 -// .external_en (1'b0), @549 -// .global_en (cp0_yy_clk_en), @550 -// .module_en (cp0_fpu_icg_en), @551 -// .local_en (expnt_rst_clk_en), @552 -// .clk_out (expnt_rst_clk)); @553 +// &Connect( .clk_in (forever_cpuclk), @361 +// .clk_out (ex3_data_clk),//Out Clock @362 +// .external_en (1'b0), @363 +// .global_en (cp0_yy_clk_en), @364 +// .local_en (ex3_data_clk_en),//Local Condition @365 +// .module_en (cp0_vfpu_icg_en) @366 +// ); @367 +assign ex3_data_clk_en = ex3_pipedown; -//========================================================== -// Output Signal -//========================================================== -assign fdsu_yy_wb_freg[4:0] = fdsu_wb_freg[4:0]; -assign fdsu_yy_result_sign = fdsu_result_sign; -assign fdsu_yy_op0_norm = fdsu_op0_norm; -assign fdsu_yy_op1_norm = fdsu_op1_norm; -assign fdsu_yy_of_rm_lfn = fdsu_of_rm_lfn; -assign fdsu_yy_div = fdsu_div; -assign fdsu_yy_sqrt = fdsu_sqrt; -assign fdsu_yy_rm[2:0] = fdsu_rm[2:0]; - -assign fdsu_yy_expnt_rst[9:0] = fdsu_expnt_rst[9:0]; -assign ex2_expnt_adder_op0[9:0] = fdsu_expnt_rst[9:0]; - -assign fdsu_yy_result_inf = fdsu_result_inf; -assign fdsu_yy_result_lfn = fdsu_result_lfn; -assign fdsu_yy_of = fdsu_of; -assign fdsu_yy_uf = fdsu_uf; -assign fdsu_yy_potnt_of = fdsu_potnt_of; -assign fdsu_yy_potnt_uf = fdsu_potnt_uf; - -assign ex1_pipedown = ctrl_iter_start || ctrl_xx_ex1_warm_up; -assign ex1_pipedown_gate = ctrl_iter_start_gate || ctrl_xx_ex1_warm_up; -assign ex2_pipedown = ctrl_srt_itering && srt_last_round || ctrl_xx_ex2_warm_up; -assign ex3_pipedown = ctrl_round || ctrl_xx_ex3_warm_up; -// &Force("output", "ex1_pipedown"); @589 -// &Force("output", "ex1_pipedown_gate"); @590 -// &Force("output", "ex2_pipedown"); @591 -// &Force("output", "ex3_pipedown"); @592 - -assign srt_sm_on = ctrl_srt_itering; - -assign fdsu_fpu_ex1_cmplt = fdsu_ex1_inst_vld; -assign fdsu_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[2]; -assign fdsu_fpu_ex1_stall = ctrl_fdsu_ex1_stall; -assign fdsu_frbus_wb_vld = ctrl_result_vld; -// &Force("bus","idu_fpu_ex1_eu_sel",2,0); @600 -assign fdsu_fpu_no_op = !fdsu_busy; -assign ex1_op1_sel = ctrl_wfi2; -assign ex1_save_op0 = ctrl_sm_start && ex1_op0_id && ex1_op1_id_vld; -assign ex1_save_op0_gate = ctrl_sm_start_gate && ex1_op0_id && ex1_op1_id_vld; -// &Force("output", "ex1_save_op0"); @605 -// &Force("output", "ex1_save_op0_gate"); @606 - -assign fdsu_fpu_debug_info[4:0] = {wb_cur_state[1:0], fdsu_cur_state[2:0]}; - -// &ModuleEnd; @610 -endmodule +assign pipex_dp_vfdsu_inst_vld = div_cur_state[3:0] == WB; +// this is used to apply write back port +assign vfdsu_dp_inst_wb_req = vfdsu_ex3_vld; +assign vfdsu_dp_fdiv_busy = div_cur_state[2]; +//Debug infor +assign vfdsu_ifu_debug_ex2_wait = 1'b0; +assign vfdsu_ifu_debug_idle = (div_cur_state[3:0] == IDLE); +assign vfdsu_ifu_debug_pipe_busy = 1'b0; -// ----- 8< ----- FILE "./pa_fdsu_ff1.v" ----- 8< ----- +// &ModuleEnd; @381 +endmodule -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +// ----- 8< ----- FILE "./ct_vfdsu_ff1.v" ----- 8< ----- + +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -23217,158 +26957,94 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ - -// &ModuleBeg; @23 -module pa_fdsu_ff1( +module ct_vfdsu_ff1( fanc_shift_num, frac_bin_val, frac_num ); -// &Ports; @24 +// &Ports; @22 input [51:0] frac_num; output [51:0] fanc_shift_num; output [12:0] frac_bin_val; -// &Regs; @25 +// &Regs; @23 reg [51:0] fanc_shift_num; reg [12:0] frac_bin_val; -// &Wires; @26 +// &Wires; @24 wire [51:0] frac_num; -// &CombBeg; @28 -always @( frac_num[51:0]) -begin -casez(frac_num[51:0]) - 52'b1???????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h0; - 52'b01??????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1fff; - 52'b001?????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffe; - 52'b0001????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffd; - 52'b00001???????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffc; - 52'b000001??????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffb; - 52'b0000001?????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffa; - 52'b00000001????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff9; - 52'b000000001???????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff8; - 52'b0000000001??????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff7; - 52'b00000000001?????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff6; - 52'b000000000001????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff5; - 52'b0000000000001???????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff4; - 52'b00000000000001??????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff3; - 52'b000000000000001?????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff2; - 52'b0000000000000001????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff1; - 52'b00000000000000001???????????????????????????????????: frac_bin_val[12:0] = 13'h1ff0; - 52'b000000000000000001??????????????????????????????????: frac_bin_val[12:0] = 13'h1fef; - 52'b0000000000000000001?????????????????????????????????: frac_bin_val[12:0] = 13'h1fee; - 52'b00000000000000000001????????????????????????????????: frac_bin_val[12:0] = 13'h1fed; - 52'b000000000000000000001???????????????????????????????: frac_bin_val[12:0] = 13'h1fec; - 52'b0000000000000000000001??????????????????????????????: frac_bin_val[12:0] = 13'h1feb; - 52'b00000000000000000000001?????????????????????????????: frac_bin_val[12:0] = 13'h1fea; - 52'b000000000000000000000001????????????????????????????: frac_bin_val[12:0] = 13'h1fe9; - 52'b0000000000000000000000001???????????????????????????: frac_bin_val[12:0] = 13'h1fe8; - 52'b00000000000000000000000001??????????????????????????: frac_bin_val[12:0] = 13'h1fe7; - 52'b000000000000000000000000001?????????????????????????: frac_bin_val[12:0] = 13'h1fe6; - 52'b0000000000000000000000000001????????????????????????: frac_bin_val[12:0] = 13'h1fe5; - 52'b00000000000000000000000000001???????????????????????: frac_bin_val[12:0] = 13'h1fe4; - 52'b000000000000000000000000000001??????????????????????: frac_bin_val[12:0] = 13'h1fe3; - 52'b0000000000000000000000000000001?????????????????????: frac_bin_val[12:0] = 13'h1fe2; - 52'b00000000000000000000000000000001????????????????????: frac_bin_val[12:0] = 13'h1fe1; - 52'b000000000000000000000000000000001???????????????????: frac_bin_val[12:0] = 13'h1fe0; - 52'b0000000000000000000000000000000001??????????????????: frac_bin_val[12:0] = 13'h1fdf; - 52'b00000000000000000000000000000000001?????????????????: frac_bin_val[12:0] = 13'h1fde; - 52'b000000000000000000000000000000000001????????????????: frac_bin_val[12:0] = 13'h1fdd; - 52'b0000000000000000000000000000000000001???????????????: frac_bin_val[12:0] = 13'h1fdc; - 52'b00000000000000000000000000000000000001??????????????: frac_bin_val[12:0] = 13'h1fdb; - 52'b000000000000000000000000000000000000001?????????????: frac_bin_val[12:0] = 13'h1fda; - 52'b0000000000000000000000000000000000000001????????????: frac_bin_val[12:0] = 13'h1fd9; - 52'b00000000000000000000000000000000000000001???????????: frac_bin_val[12:0] = 13'h1fd8; - 52'b000000000000000000000000000000000000000001??????????: frac_bin_val[12:0] = 13'h1fd7; - 52'b0000000000000000000000000000000000000000001?????????: frac_bin_val[12:0] = 13'h1fd6; - 52'b00000000000000000000000000000000000000000001????????: frac_bin_val[12:0] = 13'h1fd5; - 52'b000000000000000000000000000000000000000000001???????: frac_bin_val[12:0] = 13'h1fd4; - 52'b0000000000000000000000000000000000000000000001??????: frac_bin_val[12:0] = 13'h1fd3; - 52'b00000000000000000000000000000000000000000000001?????: frac_bin_val[12:0] = 13'h1fd2; - 52'b000000000000000000000000000000000000000000000001????: frac_bin_val[12:0] = 13'h1fd1; - 52'b0000000000000000000000000000000000000000000000001???: frac_bin_val[12:0] = 13'h1fd0; - 52'b00000000000000000000000000000000000000000000000001??: frac_bin_val[12:0] = 13'h1fcf; - 52'b000000000000000000000000000000000000000000000000001?: frac_bin_val[12:0] = 13'h1fce; - 52'b0000000000000000000000000000000000000000000000000001: frac_bin_val[12:0] = 13'h1fcd; - 52'b0000000000000000000000000000000000000000000000000000: frac_bin_val[12:0] = 13'h1fcc; - default : frac_bin_val[12:0] = 13'h000; -endcase -// &CombEnd; @85 -end - -// &CombBeg; @87 +// &CombBeg; @26 always @( frac_num[51:0]) begin casez(frac_num[51:0]) - 52'b1???????????????????????????????????????????????????: fanc_shift_num[51:0] = frac_num[51:0]; - 52'b01??????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[50:0],1'b0}; - 52'b001?????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[49:0],2'b0}; - 52'b0001????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[48:0],3'b0}; - 52'b00001???????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[47:0],4'b0}; - 52'b000001??????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[46:0],5'b0}; - 52'b0000001?????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[45:0],6'b0}; - 52'b00000001????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[44:0],7'b0}; - 52'b000000001???????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[43:0],8'b0}; - 52'b0000000001??????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[42:0],9'b0}; - 52'b00000000001?????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[41:0],10'b0}; - 52'b000000000001????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[40:0],11'b0}; - 52'b0000000000001???????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[39:0],12'b0}; - 52'b00000000000001??????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[38:0],13'b0}; - 52'b000000000000001?????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[37:0],14'b0}; - 52'b0000000000000001????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[36:0],15'b0}; - 52'b00000000000000001???????????????????????????????????: fanc_shift_num[51:0] = {frac_num[35:0],16'b0}; - 52'b000000000000000001??????????????????????????????????: fanc_shift_num[51:0] = {frac_num[34:0],17'b0}; - 52'b0000000000000000001?????????????????????????????????: fanc_shift_num[51:0] = {frac_num[33:0],18'b0}; - 52'b00000000000000000001????????????????????????????????: fanc_shift_num[51:0] = {frac_num[32:0],19'b0}; - 52'b000000000000000000001???????????????????????????????: fanc_shift_num[51:0] = {frac_num[31:0],20'b0}; - 52'b0000000000000000000001??????????????????????????????: fanc_shift_num[51:0] = {frac_num[30:0],21'b0}; - 52'b00000000000000000000001?????????????????????????????: fanc_shift_num[51:0] = {frac_num[29:0],22'b0}; - 52'b000000000000000000000001????????????????????????????: fanc_shift_num[51:0] = {frac_num[28:0],23'b0}; - 52'b0000000000000000000000001???????????????????????????: fanc_shift_num[51:0] = {frac_num[27:0],24'b0}; - 52'b00000000000000000000000001??????????????????????????: fanc_shift_num[51:0] = {frac_num[26:0],25'b0}; - 52'b000000000000000000000000001?????????????????????????: fanc_shift_num[51:0] = {frac_num[25:0],26'b0}; - 52'b0000000000000000000000000001????????????????????????: fanc_shift_num[51:0] = {frac_num[24:0],27'b0}; - 52'b00000000000000000000000000001???????????????????????: fanc_shift_num[51:0] = {frac_num[23:0],28'b0}; - 52'b000000000000000000000000000001??????????????????????: fanc_shift_num[51:0] = {frac_num[22:0],29'b0}; - 52'b0000000000000000000000000000001?????????????????????: fanc_shift_num[51:0] = {frac_num[21:0],30'b0}; - 52'b00000000000000000000000000000001????????????????????: fanc_shift_num[51:0] = {frac_num[20:0],31'b0}; - 52'b000000000000000000000000000000001???????????????????: fanc_shift_num[51:0] = {frac_num[19:0],32'b0}; - 52'b0000000000000000000000000000000001??????????????????: fanc_shift_num[51:0] = {frac_num[18:0],33'b0}; - 52'b00000000000000000000000000000000001?????????????????: fanc_shift_num[51:0] = {frac_num[17:0],34'b0}; - 52'b000000000000000000000000000000000001????????????????: fanc_shift_num[51:0] = {frac_num[16:0],35'b0}; - 52'b0000000000000000000000000000000000001???????????????: fanc_shift_num[51:0] = {frac_num[15:0],36'b0}; - 52'b00000000000000000000000000000000000001??????????????: fanc_shift_num[51:0] = {frac_num[14:0],37'b0}; - 52'b000000000000000000000000000000000000001?????????????: fanc_shift_num[51:0] = {frac_num[13:0],38'b0}; - 52'b0000000000000000000000000000000000000001????????????: fanc_shift_num[51:0] = {frac_num[12:0],39'b0}; - 52'b00000000000000000000000000000000000000001???????????: fanc_shift_num[51:0] = {frac_num[11:0],40'b0}; - 52'b000000000000000000000000000000000000000001??????????: fanc_shift_num[51:0] = {frac_num[10:0],41'b0}; - 52'b0000000000000000000000000000000000000000001?????????: fanc_shift_num[51:0] = {frac_num[9:0],42'b0}; - 52'b00000000000000000000000000000000000000000001????????: fanc_shift_num[51:0] = {frac_num[8:0],43'b0}; - 52'b000000000000000000000000000000000000000000001???????: fanc_shift_num[51:0] = {frac_num[7:0],44'b0}; - 52'b0000000000000000000000000000000000000000000001??????: fanc_shift_num[51:0] = {frac_num[6:0],45'b0}; - 52'b00000000000000000000000000000000000000000000001?????: fanc_shift_num[51:0] = {frac_num[5:0],46'b0}; - 52'b000000000000000000000000000000000000000000000001????: fanc_shift_num[51:0] = {frac_num[4:0],47'b0}; - 52'b0000000000000000000000000000000000000000000000001???: fanc_shift_num[51:0] = {frac_num[3:0],48'b0}; - 52'b00000000000000000000000000000000000000000000000001??: fanc_shift_num[51:0] = {frac_num[2:0],49'b0}; - 52'b000000000000000000000000000000000000000000000000001?: fanc_shift_num[51:0] = {frac_num[1:0],50'b0}; - 52'b0000000000000000000000000000000000000000000000000001: fanc_shift_num[51:0] = {frac_num[0:0],51'b0}; - 52'b0000000000000000000000000000000000000000000000000000: fanc_shift_num[51:0] = {52'b0}; - default : fanc_shift_num[51:0] = {52'b0}; -endcase -// &CombEnd; @144 + 52'b1???????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h0; fanc_shift_num[51:0] = frac_num[51:0]; end + 52'b01??????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fff; fanc_shift_num[51:0] = {frac_num[50:0],1'b0};end + 52'b001?????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffe; fanc_shift_num[51:0] = {frac_num[49:0],2'b0};end + 52'b0001????????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffd; fanc_shift_num[51:0] = {frac_num[48:0],3'b0};end + 52'b00001???????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffc; fanc_shift_num[51:0] = {frac_num[47:0],4'b0};end + 52'b000001??????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffb; fanc_shift_num[51:0] = {frac_num[46:0],5'b0};end + 52'b0000001?????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ffa; fanc_shift_num[51:0] = {frac_num[45:0],6'b0};end + 52'b00000001????????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff9; fanc_shift_num[51:0] = {frac_num[44:0],7'b0};end + 52'b000000001???????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff8; fanc_shift_num[51:0] = {frac_num[43:0],8'b0};end + 52'b0000000001??????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff7; fanc_shift_num[51:0] = {frac_num[42:0],9'b0};end + 52'b00000000001?????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff6; fanc_shift_num[51:0] = {frac_num[41:0],10'b0};end + 52'b000000000001????????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff5; fanc_shift_num[51:0] = {frac_num[40:0],11'b0};end + 52'b0000000000001???????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff4; fanc_shift_num[51:0] = {frac_num[39:0],12'b0};end + 52'b00000000000001??????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff3; fanc_shift_num[51:0] = {frac_num[38:0],13'b0};end + 52'b000000000000001?????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff2; fanc_shift_num[51:0] = {frac_num[37:0],14'b0};end + 52'b0000000000000001????????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff1; fanc_shift_num[51:0] = {frac_num[36:0],15'b0};end + 52'b00000000000000001???????????????????????????????????: begin frac_bin_val[12:0] = 13'h1ff0; fanc_shift_num[51:0] = {frac_num[35:0],16'b0};end + 52'b000000000000000001??????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fef; fanc_shift_num[51:0] = {frac_num[34:0],17'b0};end + 52'b0000000000000000001?????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fee; fanc_shift_num[51:0] = {frac_num[33:0],18'b0};end + 52'b00000000000000000001????????????????????????????????: begin frac_bin_val[12:0] = 13'h1fed; fanc_shift_num[51:0] = {frac_num[32:0],19'b0};end + 52'b000000000000000000001???????????????????????????????: begin frac_bin_val[12:0] = 13'h1fec; fanc_shift_num[51:0] = {frac_num[31:0],20'b0};end + 52'b0000000000000000000001??????????????????????????????: begin frac_bin_val[12:0] = 13'h1feb; fanc_shift_num[51:0] = {frac_num[30:0],21'b0};end + 52'b00000000000000000000001?????????????????????????????: begin frac_bin_val[12:0] = 13'h1fea; fanc_shift_num[51:0] = {frac_num[29:0],22'b0};end + 52'b000000000000000000000001????????????????????????????: begin frac_bin_val[12:0] = 13'h1fe9; fanc_shift_num[51:0] = {frac_num[28:0],23'b0};end + 52'b0000000000000000000000001???????????????????????????: begin frac_bin_val[12:0] = 13'h1fe8; fanc_shift_num[51:0] = {frac_num[27:0],24'b0};end + 52'b00000000000000000000000001??????????????????????????: begin frac_bin_val[12:0] = 13'h1fe7; fanc_shift_num[51:0] = {frac_num[26:0],25'b0};end + 52'b000000000000000000000000001?????????????????????????: begin frac_bin_val[12:0] = 13'h1fe6; fanc_shift_num[51:0] = {frac_num[25:0],26'b0};end + 52'b0000000000000000000000000001????????????????????????: begin frac_bin_val[12:0] = 13'h1fe5; fanc_shift_num[51:0] = {frac_num[24:0],27'b0};end + 52'b00000000000000000000000000001???????????????????????: begin frac_bin_val[12:0] = 13'h1fe4; fanc_shift_num[51:0] = {frac_num[23:0],28'b0};end + 52'b000000000000000000000000000001??????????????????????: begin frac_bin_val[12:0] = 13'h1fe3; fanc_shift_num[51:0] = {frac_num[22:0],29'b0};end + 52'b0000000000000000000000000000001?????????????????????: begin frac_bin_val[12:0] = 13'h1fe2; fanc_shift_num[51:0] = {frac_num[21:0],30'b0};end + 52'b00000000000000000000000000000001????????????????????: begin frac_bin_val[12:0] = 13'h1fe1; fanc_shift_num[51:0] = {frac_num[20:0],31'b0};end + 52'b000000000000000000000000000000001???????????????????: begin frac_bin_val[12:0] = 13'h1fe0; fanc_shift_num[51:0] = {frac_num[19:0],32'b0};end + 52'b0000000000000000000000000000000001??????????????????: begin frac_bin_val[12:0] = 13'h1fdf; fanc_shift_num[51:0] = {frac_num[18:0],33'b0};end + 52'b00000000000000000000000000000000001?????????????????: begin frac_bin_val[12:0] = 13'h1fde; fanc_shift_num[51:0] = {frac_num[17:0],34'b0};end + 52'b000000000000000000000000000000000001????????????????: begin frac_bin_val[12:0] = 13'h1fdd; fanc_shift_num[51:0] = {frac_num[16:0],35'b0};end + 52'b0000000000000000000000000000000000001???????????????: begin frac_bin_val[12:0] = 13'h1fdc; fanc_shift_num[51:0] = {frac_num[15:0],36'b0};end + 52'b00000000000000000000000000000000000001??????????????: begin frac_bin_val[12:0] = 13'h1fdb; fanc_shift_num[51:0] = {frac_num[14:0],37'b0};end + 52'b000000000000000000000000000000000000001?????????????: begin frac_bin_val[12:0] = 13'h1fda; fanc_shift_num[51:0] = {frac_num[13:0],38'b0};end + 52'b0000000000000000000000000000000000000001????????????: begin frac_bin_val[12:0] = 13'h1fd9; fanc_shift_num[51:0] = {frac_num[12:0],39'b0};end + 52'b00000000000000000000000000000000000000001???????????: begin frac_bin_val[12:0] = 13'h1fd8; fanc_shift_num[51:0] = {frac_num[11:0],40'b0};end + 52'b000000000000000000000000000000000000000001??????????: begin frac_bin_val[12:0] = 13'h1fd7; fanc_shift_num[51:0] = {frac_num[10:0],41'b0};end + 52'b0000000000000000000000000000000000000000001?????????: begin frac_bin_val[12:0] = 13'h1fd6; fanc_shift_num[51:0] = {frac_num[9:0],42'b0};end + 52'b00000000000000000000000000000000000000000001????????: begin frac_bin_val[12:0] = 13'h1fd5; fanc_shift_num[51:0] = {frac_num[8:0],43'b0};end + 52'b000000000000000000000000000000000000000000001???????: begin frac_bin_val[12:0] = 13'h1fd4; fanc_shift_num[51:0] = {frac_num[7:0],44'b0};end + 52'b0000000000000000000000000000000000000000000001??????: begin frac_bin_val[12:0] = 13'h1fd3; fanc_shift_num[51:0] = {frac_num[6:0],45'b0};end + 52'b00000000000000000000000000000000000000000000001?????: begin frac_bin_val[12:0] = 13'h1fd2; fanc_shift_num[51:0] = {frac_num[5:0],46'b0};end + 52'b000000000000000000000000000000000000000000000001????: begin frac_bin_val[12:0] = 13'h1fd1; fanc_shift_num[51:0] = {frac_num[4:0],47'b0};end + 52'b0000000000000000000000000000000000000000000000001???: begin frac_bin_val[12:0] = 13'h1fd0; fanc_shift_num[51:0] = {frac_num[3:0],48'b0};end + 52'b00000000000000000000000000000000000000000000000001??: begin frac_bin_val[12:0] = 13'h1fcf; fanc_shift_num[51:0] = {frac_num[2:0],49'b0};end + 52'b000000000000000000000000000000000000000000000000001?: begin frac_bin_val[12:0] = 13'h1fce; fanc_shift_num[51:0] = {frac_num[1:0],50'b0};end + 52'b0000000000000000000000000000000000000000000000000001: begin frac_bin_val[12:0] = 13'h1fcd; fanc_shift_num[51:0] = {frac_num[0:0],51'b0};end + 52'b0000000000000000000000000000000000000000000000000000: begin frac_bin_val[12:0] = 13'h1fcc; fanc_shift_num[51:0] = {52'b0};end + default:begin frac_bin_val[12:0] = 13'h000; fanc_shift_num[51:0] = {52'b0};end +endcase +// &CombEnd; @83 end - -// &ModuleEnd; @146 + +// &ModuleEnd; @85 endmodule -// ----- 8< ----- FILE "./pa_fdsu_pack_single.v" ----- 8< ----- +// ----- 8< ----- FILE "./ct_vfdsu_double.v" ----- 8< ----- -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -23383,269 +27059,854 @@ See the License for the specific language governing permissions and limitations under the License. */ +// &Depend("cpu_cfig.h"); @22 // &ModuleBeg; @23 -module pa_fdsu_pack_single( - fdsu_ex4_denorm_to_tiny_frac, - fdsu_ex4_frac, - fdsu_ex4_nx, - fdsu_ex4_potnt_norm, - fdsu_ex4_result_nor, - fdsu_frbus_data, - fdsu_frbus_fflags, - fdsu_frbus_freg, - fdsu_yy_expnt_rst, - fdsu_yy_of, - fdsu_yy_of_rm_lfn, - fdsu_yy_potnt_of, - fdsu_yy_potnt_uf, - fdsu_yy_result_inf, - fdsu_yy_result_lfn, - fdsu_yy_result_sign, - fdsu_yy_rslt_denorm, - fdsu_yy_uf, - fdsu_yy_wb_freg +module ct_vfdsu_double( + cp0_vfpu_icg_en, + cp0_yy_clk_en, + cpurst_b, + ex1_div, + ex1_double, + ex1_pipedown, + ex1_scalar, + ex1_single, + ex1_half, + ex1_bfloat, + ex1_sqrt, + ex1_src0, + ex1_src1, + ex1_static_rm, + ex2_pipedown, + ex2_srt_first_round, + ex3_pipedown, + ex4_out_expt, + ex4_out_result, + forever_cpuclk, + pad_yy_icg_scan_en, + srt_ctrl_rem_zero, + srt_ctrl_skip_srt, + srt_secd_round, + srt_sm_on, + vfpu_yy_xx_dqnan, + vfpu_yy_xx_rm ); // &Ports; @24 -input fdsu_ex4_denorm_to_tiny_frac; -input [25:0] fdsu_ex4_frac; -input fdsu_ex4_nx; -input [1 :0] fdsu_ex4_potnt_norm; -input fdsu_ex4_result_nor; -input [9 :0] fdsu_yy_expnt_rst; -input fdsu_yy_of; -input fdsu_yy_of_rm_lfn; -input fdsu_yy_potnt_of; -input fdsu_yy_potnt_uf; -input fdsu_yy_result_inf; -input fdsu_yy_result_lfn; -input fdsu_yy_result_sign; -input fdsu_yy_rslt_denorm; -input fdsu_yy_uf; -input [4 :0] fdsu_yy_wb_freg; -output [31:0] fdsu_frbus_data; -output [4 :0] fdsu_frbus_fflags; -output [4 :0] fdsu_frbus_freg; +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input ex1_div; +input ex1_double; +input ex1_pipedown; +input ex1_scalar; +input ex1_single; +input ex1_half; +input ex1_bfloat; +input ex1_sqrt; +input [63:0] ex1_src0; +input [63:0] ex1_src1; +input [2 :0] ex1_static_rm; +input ex2_pipedown; +input ex2_srt_first_round; +input ex3_pipedown; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input srt_secd_round; +input srt_sm_on; +input vfpu_yy_xx_dqnan; +input [2 :0] vfpu_yy_xx_rm; +output [4 :0] ex4_out_expt; +output [63:0] ex4_out_result; +output srt_ctrl_rem_zero; +output srt_ctrl_skip_srt; // &Regs; @25 -reg [22:0] ex4_frac_23; -reg [31:0] ex4_result; -reg [22:0] ex4_single_denorm_frac; -reg [9 :0] expnt_add_op1; // &Wires; @26 -wire ex4_cor_nx; -wire ex4_cor_uf; -wire ex4_denorm_potnt_norm; -wire [31:0] ex4_denorm_result; -wire [9 :0] ex4_expnt_rst; -wire [4 :0] ex4_expt; -wire ex4_final_rst_norm; -wire [25:0] ex4_frac; -wire ex4_of_plus; -wire ex4_result_inf; -wire ex4_result_lfn; -wire ex4_rslt_denorm; -wire [31:0] ex4_rst_inf; -wire [31:0] ex4_rst_lfn; -wire ex4_rst_nor; -wire [31:0] ex4_rst_norm; -wire ex4_uf_plus; -wire fdsu_ex4_denorm_to_tiny_frac; -wire fdsu_ex4_dz; -wire [9 :0] fdsu_ex4_expnt_rst; -wire [25:0] fdsu_ex4_frac; -wire fdsu_ex4_nv; -wire fdsu_ex4_nx; -wire fdsu_ex4_of; -wire fdsu_ex4_of_rst_lfn; -wire [1 :0] fdsu_ex4_potnt_norm; -wire fdsu_ex4_potnt_of; -wire fdsu_ex4_potnt_uf; -wire fdsu_ex4_result_inf; -wire fdsu_ex4_result_lfn; -wire fdsu_ex4_result_nor; -wire fdsu_ex4_result_sign; -wire fdsu_ex4_rslt_denorm; -wire fdsu_ex4_uf; -wire [31:0] fdsu_frbus_data; -wire [4 :0] fdsu_frbus_fflags; -wire [4 :0] fdsu_frbus_freg; -wire [9 :0] fdsu_yy_expnt_rst; -wire fdsu_yy_of; -wire fdsu_yy_of_rm_lfn; -wire fdsu_yy_potnt_of; -wire fdsu_yy_potnt_uf; -wire fdsu_yy_result_inf; -wire fdsu_yy_result_lfn; -wire fdsu_yy_result_sign; -wire fdsu_yy_rslt_denorm; -wire fdsu_yy_uf; -wire [4 :0] fdsu_yy_wb_freg; - - -assign fdsu_ex4_result_sign = fdsu_yy_result_sign; -assign fdsu_ex4_of_rst_lfn = fdsu_yy_of_rm_lfn; -assign fdsu_ex4_result_inf = fdsu_yy_result_inf; -assign fdsu_ex4_result_lfn = fdsu_yy_result_lfn; -assign fdsu_ex4_of = fdsu_yy_of; -assign fdsu_ex4_uf = fdsu_yy_uf; -assign fdsu_ex4_potnt_of = fdsu_yy_potnt_of; -assign fdsu_ex4_potnt_uf = fdsu_yy_potnt_uf; -assign fdsu_ex4_nv = 1'b0; -assign fdsu_ex4_dz = 1'b0; -assign fdsu_ex4_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; -assign fdsu_ex4_rslt_denorm = fdsu_yy_rslt_denorm; +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire ex1_div; +wire [52:0] ex1_divisor; +wire ex1_double; +wire ex1_pipedown; +wire [59:0] ex1_remainder; +wire ex1_scalar; +wire ex1_single; +wire ex1_half; +wire ex1_bfloat; +wire ex1_sqrt; +wire [63:0] ex1_src0; +wire [63:0] ex1_src1; +wire [2 :0] ex1_static_rm; +wire ex2_pipedown; +wire ex2_srt_first_round; +wire ex3_pipedown; +wire [4 :0] ex4_out_expt; +wire [63:0] ex4_out_result; +wire forever_cpuclk; +wire pad_yy_icg_scan_en; +wire srt_ctrl_rem_zero; +wire srt_ctrl_skip_srt; +wire srt_secd_round; +wire srt_sm_on; +wire [57:0] total_qt_rt_58; +wire vfdsu_ex2_div; +wire vfdsu_ex2_double; +wire vfdsu_ex2_dz; +wire [12:0] vfdsu_ex2_expnt_add0; +wire [12:0] vfdsu_ex2_expnt_add1; +wire vfdsu_ex2_nv; +wire vfdsu_ex2_of_rm_lfn; +wire vfdsu_ex2_op0_norm; +wire vfdsu_ex2_op1_norm; +wire [51:0] vfdsu_ex2_qnan_f; +wire vfdsu_ex2_qnan_sign; +wire vfdsu_ex2_result_inf; +wire vfdsu_ex2_result_qnan; +wire vfdsu_ex2_result_sign; +wire vfdsu_ex2_result_zero; +wire [2 :0] vfdsu_ex2_rm; +wire vfdsu_ex2_single; +wire vfdsu_ex2_half; +wire vfdsu_ex2_bfloat; +wire vfdsu_ex2_sqrt; +wire vfdsu_ex2_srt_skip; +wire [12:0] vfdsu_ex3_doub_expnt_rst; +wire vfdsu_ex3_double; +wire vfdsu_ex3_dz; +wire [12:0] vfdsu_ex3_half_expnt_rst; +wire [12:0] vfdsu_ex3_bfloat_expnt_rst; +wire vfdsu_ex3_id_srt_skip; +wire vfdsu_ex3_nv; +wire vfdsu_ex3_of; +wire vfdsu_ex3_potnt_of; +wire vfdsu_ex3_potnt_uf; +wire [51:0] vfdsu_ex3_qnan_f; +wire vfdsu_ex3_qnan_sign; +wire vfdsu_ex3_rem_sign; +wire vfdsu_ex3_rem_zero; +wire [52:0] vfdsu_ex3_result_denorm_round_add_num; +wire vfdsu_ex3_result_inf; +wire vfdsu_ex3_result_lfn; +wire vfdsu_ex3_result_qnan; +wire vfdsu_ex3_result_sign; +wire vfdsu_ex3_result_zero; +wire [2 :0] vfdsu_ex3_rm; +wire vfdsu_ex3_rslt_denorm; +wire [8 :0] vfdsu_ex3_sing_expnt_rst; +wire vfdsu_ex3_single; +wire vfdsu_ex3_half; +wire vfdsu_ex3_bfloat; +wire vfdsu_ex3_uf; +wire vfdsu_ex4_denorm_to_tiny_frac; +wire vfdsu_ex4_double; +wire vfdsu_ex4_dz; +wire [12:0] vfdsu_ex4_expnt_rst; +wire [54:0] vfdsu_ex4_frac; +wire vfdsu_ex4_nv; +wire vfdsu_ex4_nx; +wire vfdsu_ex4_of; +wire vfdsu_ex4_of_rst_lfn; +wire [1 :0] vfdsu_ex4_potnt_norm; +wire vfdsu_ex4_potnt_of; +wire vfdsu_ex4_potnt_uf; +wire [51:0] vfdsu_ex4_qnan_f; +wire vfdsu_ex4_qnan_sign; +wire vfdsu_ex4_result_inf; +wire vfdsu_ex4_result_lfn; +wire vfdsu_ex4_result_nor; +wire vfdsu_ex4_result_qnan; +wire vfdsu_ex4_result_sign; +wire vfdsu_ex4_result_zero; +wire vfdsu_ex4_rslt_denorm; +wire vfdsu_ex4_single; +wire vfdsu_ex4_half; +wire vfdsu_ex4_bfloat; +wire vfdsu_ex4_uf; +wire vfpu_yy_xx_dqnan; +wire [2 :0] vfpu_yy_xx_rm; + + +// &Instance("ct_vfdsu_prepare"); @28 +ct_vfdsu_prepare x_ct_vfdsu_prepare ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .ex1_div (ex1_div ), + .ex1_divisor (ex1_divisor ), + .ex1_double (ex1_double ), + .ex1_pipedown (ex1_pipedown ), + .ex1_remainder (ex1_remainder ), + .ex1_scalar (ex1_scalar ), + .ex1_single (ex1_single ), + .ex1_half (ex1_half ), + .ex1_bfloat (ex1_bfloat ), + .ex1_sqrt (ex1_sqrt ), + .ex1_src0 (ex1_src0 ), + .ex1_src1 (ex1_src1 ), + .ex1_static_rm (ex1_static_rm ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .vfdsu_ex2_div (vfdsu_ex2_div ), + .vfdsu_ex2_double (vfdsu_ex2_double ), + .vfdsu_ex2_dz (vfdsu_ex2_dz ), + .vfdsu_ex2_expnt_add0 (vfdsu_ex2_expnt_add0 ), + .vfdsu_ex2_expnt_add1 (vfdsu_ex2_expnt_add1 ), + .vfdsu_ex2_nv (vfdsu_ex2_nv ), + .vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ), + .vfdsu_ex2_op0_norm (vfdsu_ex2_op0_norm ), + .vfdsu_ex2_op1_norm (vfdsu_ex2_op1_norm ), + .vfdsu_ex2_qnan_f (vfdsu_ex2_qnan_f ), + .vfdsu_ex2_qnan_sign (vfdsu_ex2_qnan_sign ), + .vfdsu_ex2_result_inf (vfdsu_ex2_result_inf ), + .vfdsu_ex2_result_qnan (vfdsu_ex2_result_qnan), + .vfdsu_ex2_result_sign (vfdsu_ex2_result_sign), + .vfdsu_ex2_result_zero (vfdsu_ex2_result_zero), + .vfdsu_ex2_rm (vfdsu_ex2_rm ), + .vfdsu_ex2_single (vfdsu_ex2_single ), + .vfdsu_ex2_half (vfdsu_ex2_half ), + .vfdsu_ex2_bfloat (vfdsu_ex2_bfloat ), + .vfdsu_ex2_sqrt (vfdsu_ex2_sqrt ), + .vfdsu_ex2_srt_skip (vfdsu_ex2_srt_skip ), + .vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ), + .vfpu_yy_xx_rm (vfpu_yy_xx_rm ) +); + +// &Instance("ct_vfdsu_srt"); @29 +ct_vfdsu_srt x_ct_vfdsu_srt ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .ex1_div (ex1_div ), + .ex1_divisor (ex1_divisor ), + .ex1_pipedown (ex1_pipedown ), + .ex1_remainder (ex1_remainder ), + .ex1_sqrt (ex1_sqrt ), + .ex2_pipedown (ex2_pipedown ), + .ex2_srt_first_round (ex2_srt_first_round ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .srt_ctrl_rem_zero (srt_ctrl_rem_zero ), + .srt_ctrl_skip_srt (srt_ctrl_skip_srt ), + .srt_secd_round (srt_secd_round ), + .srt_sm_on (srt_sm_on ), + .total_qt_rt_58 (total_qt_rt_58 ), + .vfdsu_ex2_div (vfdsu_ex2_div ), + .vfdsu_ex2_double (vfdsu_ex2_double ), + .vfdsu_ex2_dz (vfdsu_ex2_dz ), + .vfdsu_ex2_expnt_add0 (vfdsu_ex2_expnt_add0 ), + .vfdsu_ex2_expnt_add1 (vfdsu_ex2_expnt_add1 ), + .vfdsu_ex2_nv (vfdsu_ex2_nv ), + .vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ), + .vfdsu_ex2_op0_norm (vfdsu_ex2_op0_norm ), + .vfdsu_ex2_op1_norm (vfdsu_ex2_op1_norm ), + .vfdsu_ex2_qnan_f (vfdsu_ex2_qnan_f ), + .vfdsu_ex2_qnan_sign (vfdsu_ex2_qnan_sign ), + .vfdsu_ex2_result_inf (vfdsu_ex2_result_inf ), + .vfdsu_ex2_result_qnan (vfdsu_ex2_result_qnan ), + .vfdsu_ex2_result_sign (vfdsu_ex2_result_sign ), + .vfdsu_ex2_result_zero (vfdsu_ex2_result_zero ), + .vfdsu_ex2_rm (vfdsu_ex2_rm ), + .vfdsu_ex2_single (vfdsu_ex2_single ), + .vfdsu_ex2_half (vfdsu_ex2_half ), + .vfdsu_ex2_bfloat (vfdsu_ex2_bfloat ), + .vfdsu_ex2_sqrt (vfdsu_ex2_sqrt ), + .vfdsu_ex2_srt_skip (vfdsu_ex2_srt_skip ), + .vfdsu_ex3_doub_expnt_rst (vfdsu_ex3_doub_expnt_rst ), + .vfdsu_ex3_double (vfdsu_ex3_double ), + .vfdsu_ex3_dz (vfdsu_ex3_dz ), + .vfdsu_ex3_half_expnt_rst (vfdsu_ex3_half_expnt_rst ), + .vfdsu_ex3_bfloat_expnt_rst (vfdsu_ex3_bfloat_expnt_rst ), + .vfdsu_ex3_id_srt_skip (vfdsu_ex3_id_srt_skip ), + .vfdsu_ex3_nv (vfdsu_ex3_nv ), + .vfdsu_ex3_of (vfdsu_ex3_of ), + .vfdsu_ex3_potnt_of (vfdsu_ex3_potnt_of ), + .vfdsu_ex3_potnt_uf (vfdsu_ex3_potnt_uf ), + .vfdsu_ex3_qnan_f (vfdsu_ex3_qnan_f ), + .vfdsu_ex3_qnan_sign (vfdsu_ex3_qnan_sign ), + .vfdsu_ex3_rem_sign (vfdsu_ex3_rem_sign ), + .vfdsu_ex3_rem_zero (vfdsu_ex3_rem_zero ), + .vfdsu_ex3_result_denorm_round_add_num (vfdsu_ex3_result_denorm_round_add_num), + .vfdsu_ex3_result_inf (vfdsu_ex3_result_inf ), + .vfdsu_ex3_result_lfn (vfdsu_ex3_result_lfn ), + .vfdsu_ex3_result_qnan (vfdsu_ex3_result_qnan ), + .vfdsu_ex3_result_sign (vfdsu_ex3_result_sign ), + .vfdsu_ex3_result_zero (vfdsu_ex3_result_zero ), + .vfdsu_ex3_rm (vfdsu_ex3_rm ), + .vfdsu_ex3_rslt_denorm (vfdsu_ex3_rslt_denorm ), + .vfdsu_ex3_sing_expnt_rst (vfdsu_ex3_sing_expnt_rst ), + .vfdsu_ex3_single (vfdsu_ex3_single ), + .vfdsu_ex3_half (vfdsu_ex3_half ), + .vfdsu_ex3_bfloat (vfdsu_ex3_bfloat ), + .vfdsu_ex3_uf (vfdsu_ex3_uf ) +); + +// &Instance("ct_vfdsu_round"); @30 +ct_vfdsu_round x_ct_vfdsu_round ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .ex3_pipedown (ex3_pipedown ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .total_qt_rt_58 (total_qt_rt_58 ), + .vfdsu_ex2_of_rm_lfn (vfdsu_ex2_of_rm_lfn ), + .vfdsu_ex3_doub_expnt_rst (vfdsu_ex3_doub_expnt_rst ), + .vfdsu_ex3_double (vfdsu_ex3_double ), + .vfdsu_ex3_dz (vfdsu_ex3_dz ), + .vfdsu_ex3_half_expnt_rst (vfdsu_ex3_half_expnt_rst ), + .vfdsu_ex3_bfloat_expnt_rst (vfdsu_ex3_bfloat_expnt_rst ), + .vfdsu_ex3_id_srt_skip (vfdsu_ex3_id_srt_skip ), + .vfdsu_ex3_nv (vfdsu_ex3_nv ), + .vfdsu_ex3_of (vfdsu_ex3_of ), + .vfdsu_ex3_potnt_of (vfdsu_ex3_potnt_of ), + .vfdsu_ex3_potnt_uf (vfdsu_ex3_potnt_uf ), + .vfdsu_ex3_qnan_f (vfdsu_ex3_qnan_f ), + .vfdsu_ex3_qnan_sign (vfdsu_ex3_qnan_sign ), + .vfdsu_ex3_rem_sign (vfdsu_ex3_rem_sign ), + .vfdsu_ex3_rem_zero (vfdsu_ex3_rem_zero ), + .vfdsu_ex3_result_denorm_round_add_num (vfdsu_ex3_result_denorm_round_add_num), + .vfdsu_ex3_result_inf (vfdsu_ex3_result_inf ), + .vfdsu_ex3_result_lfn (vfdsu_ex3_result_lfn ), + .vfdsu_ex3_result_qnan (vfdsu_ex3_result_qnan ), + .vfdsu_ex3_result_sign (vfdsu_ex3_result_sign ), + .vfdsu_ex3_result_zero (vfdsu_ex3_result_zero ), + .vfdsu_ex3_rm (vfdsu_ex3_rm ), + .vfdsu_ex3_rslt_denorm (vfdsu_ex3_rslt_denorm ), + .vfdsu_ex3_sing_expnt_rst (vfdsu_ex3_sing_expnt_rst ), + .vfdsu_ex3_single (vfdsu_ex3_single ), + .vfdsu_ex3_half (vfdsu_ex3_half ), + .vfdsu_ex3_bfloat (vfdsu_ex3_bfloat ), + .vfdsu_ex3_uf (vfdsu_ex3_uf ), + .vfdsu_ex4_denorm_to_tiny_frac (vfdsu_ex4_denorm_to_tiny_frac ), + .vfdsu_ex4_double (vfdsu_ex4_double ), + .vfdsu_ex4_dz (vfdsu_ex4_dz ), + .vfdsu_ex4_expnt_rst (vfdsu_ex4_expnt_rst ), + .vfdsu_ex4_frac (vfdsu_ex4_frac ), + .vfdsu_ex4_nv (vfdsu_ex4_nv ), + .vfdsu_ex4_nx (vfdsu_ex4_nx ), + .vfdsu_ex4_of (vfdsu_ex4_of ), + .vfdsu_ex4_of_rst_lfn (vfdsu_ex4_of_rst_lfn ), + .vfdsu_ex4_potnt_norm (vfdsu_ex4_potnt_norm ), + .vfdsu_ex4_potnt_of (vfdsu_ex4_potnt_of ), + .vfdsu_ex4_potnt_uf (vfdsu_ex4_potnt_uf ), + .vfdsu_ex4_qnan_f (vfdsu_ex4_qnan_f ), + .vfdsu_ex4_qnan_sign (vfdsu_ex4_qnan_sign ), + .vfdsu_ex4_result_inf (vfdsu_ex4_result_inf ), + .vfdsu_ex4_result_lfn (vfdsu_ex4_result_lfn ), + .vfdsu_ex4_result_nor (vfdsu_ex4_result_nor ), + .vfdsu_ex4_result_qnan (vfdsu_ex4_result_qnan ), + .vfdsu_ex4_result_sign (vfdsu_ex4_result_sign ), + .vfdsu_ex4_result_zero (vfdsu_ex4_result_zero ), + .vfdsu_ex4_rslt_denorm (vfdsu_ex4_rslt_denorm ), + .vfdsu_ex4_single (vfdsu_ex4_single ), + .vfdsu_ex4_half (vfdsu_ex4_half ), + .vfdsu_ex4_bfloat (vfdsu_ex4_bfloat ), + .vfdsu_ex4_uf (vfdsu_ex4_uf ) +); + +// &Instance("ct_vfdsu_pack"); @31 +ct_vfdsu_pack x_ct_vfdsu_pack ( + .ex4_out_expt (ex4_out_expt ), + .ex4_out_result (ex4_out_result ), + .vfdsu_ex4_denorm_to_tiny_frac (vfdsu_ex4_denorm_to_tiny_frac), + .vfdsu_ex4_double (vfdsu_ex4_double ), + .vfdsu_ex4_dz (vfdsu_ex4_dz ), + .vfdsu_ex4_expnt_rst (vfdsu_ex4_expnt_rst ), + .vfdsu_ex4_frac (vfdsu_ex4_frac ), + .vfdsu_ex4_nv (vfdsu_ex4_nv ), + .vfdsu_ex4_nx (vfdsu_ex4_nx ), + .vfdsu_ex4_of (vfdsu_ex4_of ), + .vfdsu_ex4_of_rst_lfn (vfdsu_ex4_of_rst_lfn ), + .vfdsu_ex4_potnt_norm (vfdsu_ex4_potnt_norm ), + .vfdsu_ex4_potnt_of (vfdsu_ex4_potnt_of ), + .vfdsu_ex4_potnt_uf (vfdsu_ex4_potnt_uf ), + .vfdsu_ex4_qnan_f (vfdsu_ex4_qnan_f ), + .vfdsu_ex4_qnan_sign (vfdsu_ex4_qnan_sign ), + .vfdsu_ex4_result_inf (vfdsu_ex4_result_inf ), + .vfdsu_ex4_result_lfn (vfdsu_ex4_result_lfn ), + .vfdsu_ex4_result_nor (vfdsu_ex4_result_nor ), + .vfdsu_ex4_result_qnan (vfdsu_ex4_result_qnan ), + .vfdsu_ex4_result_sign (vfdsu_ex4_result_sign ), + .vfdsu_ex4_result_zero (vfdsu_ex4_result_zero ), + .vfdsu_ex4_rslt_denorm (vfdsu_ex4_rslt_denorm ), + .vfdsu_ex4_single (vfdsu_ex4_single ), + .vfdsu_ex4_half (vfdsu_ex4_half ), + .vfdsu_ex4_bfloat (vfdsu_ex4_bfloat ), + .vfdsu_ex4_uf (vfdsu_ex4_uf ) +); + + + +// &ModuleEnd; @34 +endmodule + + +// ----- 8< ----- FILE "./ct_vfdsu_pack.v" ----- 8< ----- + +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module ct_vfdsu_pack( + ex4_out_expt, + ex4_out_result, + vfdsu_ex4_denorm_to_tiny_frac, + vfdsu_ex4_double, + vfdsu_ex4_dz, + vfdsu_ex4_expnt_rst, + vfdsu_ex4_frac, + vfdsu_ex4_nv, + vfdsu_ex4_nx, + vfdsu_ex4_of, + vfdsu_ex4_of_rst_lfn, + vfdsu_ex4_potnt_norm, + vfdsu_ex4_potnt_of, + vfdsu_ex4_potnt_uf, + vfdsu_ex4_qnan_f, + vfdsu_ex4_qnan_sign, + vfdsu_ex4_result_inf, + vfdsu_ex4_result_lfn, + vfdsu_ex4_result_nor, + vfdsu_ex4_result_qnan, + vfdsu_ex4_result_sign, + vfdsu_ex4_result_zero, + vfdsu_ex4_rslt_denorm, + vfdsu_ex4_single, + vfdsu_ex4_half, + vfdsu_ex4_bfloat, + vfdsu_ex4_uf +); + +// &Ports; @23 +input vfdsu_ex4_denorm_to_tiny_frac; +input vfdsu_ex4_double; +input vfdsu_ex4_dz; +input [12:0] vfdsu_ex4_expnt_rst; +input [54:0] vfdsu_ex4_frac; +input vfdsu_ex4_nv; +input vfdsu_ex4_nx; +input vfdsu_ex4_of; +input vfdsu_ex4_of_rst_lfn; +input [1 :0] vfdsu_ex4_potnt_norm; +input vfdsu_ex4_potnt_of; +input vfdsu_ex4_potnt_uf; +input [51:0] vfdsu_ex4_qnan_f; +input vfdsu_ex4_qnan_sign; +input vfdsu_ex4_result_inf; +input vfdsu_ex4_result_lfn; +input vfdsu_ex4_result_nor; +input vfdsu_ex4_result_qnan; +input vfdsu_ex4_result_sign; +input vfdsu_ex4_result_zero; +input vfdsu_ex4_rslt_denorm; +input vfdsu_ex4_single; +input vfdsu_ex4_half; +input vfdsu_ex4_bfloat; +input vfdsu_ex4_uf; +output [4 :0] ex4_out_expt; +output [63:0] ex4_out_result; + +// &Regs; @24 +reg [51:0] ex4_denorm_frac; +reg [51:0] ex4_frac_52; +reg [51:0] ex4_half_denorm_frac; +reg [51:0] ex4_bfloat_denorm_frac; +reg [63:0] ex4_out_result; +reg [51:0] ex4_single_denorm_frac; +reg [12:0] expnt_add_op1; + +// &Wires; @25 +wire ex4_cor_nx; +wire ex4_cor_uf; +wire ex4_denorm_potnt_norm; +wire [63:0] ex4_denorm_result; +wire [63:0] ex4_doub_lfn; +wire [63:0] ex4_doub_rst0; +wire [63:0] ex4_doub_rst_inf; +wire [63:0] ex4_doub_rst_norm; +wire [63:0] ex4_doub_rst_qnan; +wire [12:0] ex4_expnt_rst; +wire ex4_final_rst_norm; +wire [54:0] ex4_frac; +wire [63:0] ex4_half_lfn; +wire [63:0] ex4_half_rst0; +wire [63:0] ex4_half_rst_inf; +wire [63:0] ex4_half_rst_norm; +wire [63:0] ex4_half_rst_qnan; +wire [63:0] ex4_bfloat_lfn; +wire [63:0] ex4_bfloat_rst0; +wire [63:0] ex4_bfloat_rst_inf; +wire [63:0] ex4_bfloat_rst_norm; +wire [63:0] ex4_bfloat_rst_qnan; +wire ex4_of_plus; +wire [4 :0] ex4_out_expt; +wire ex4_result_inf; +wire ex4_result_lfn; +wire ex4_rslt_denorm; +wire [63:0] ex4_rst0; +wire [63:0] ex4_rst_inf; +wire [63:0] ex4_rst_lfn; +wire ex4_rst_nor; +wire [63:0] ex4_rst_norm; +wire [63:0] ex4_rst_qnan; +wire [63:0] ex4_sing_lfn; +wire [63:0] ex4_sing_rst0; +wire [63:0] ex4_sing_rst_inf; +wire [63:0] ex4_sing_rst_norm; +wire [63:0] ex4_sing_rst_qnan; +wire ex4_uf_plus; +wire vfdsu_ex4_denorm_to_tiny_frac; +wire vfdsu_ex4_double; +wire vfdsu_ex4_dz; +wire [12:0] vfdsu_ex4_expnt_rst; +wire [54:0] vfdsu_ex4_frac; +wire vfdsu_ex4_nv; +wire vfdsu_ex4_nx; +wire vfdsu_ex4_of; +wire vfdsu_ex4_of_rst_lfn; +wire [1 :0] vfdsu_ex4_potnt_norm; +wire vfdsu_ex4_potnt_of; +wire vfdsu_ex4_potnt_uf; +wire [51:0] vfdsu_ex4_qnan_f; +wire vfdsu_ex4_qnan_sign; +wire vfdsu_ex4_result_inf; +wire vfdsu_ex4_result_lfn; +wire vfdsu_ex4_result_nor; +wire vfdsu_ex4_result_qnan; +wire vfdsu_ex4_result_sign; +wire vfdsu_ex4_result_zero; +wire vfdsu_ex4_rslt_denorm; +wire vfdsu_ex4_single; +wire vfdsu_ex4_half; +wire vfdsu_ex4_bfloat; +wire vfdsu_ex4_uf; + + //============================EX4 STAGE===================== -assign ex4_frac[25:0] = fdsu_ex4_frac[25:0]; +assign ex4_frac[54:0] = vfdsu_ex4_frac[54:0]; //exponent adder -// &CombBeg; @43 -always @( ex4_frac[25:24]) +// &CombBeg; @30 +always @( ex4_frac[54:53]) begin -casez(ex4_frac[25:24]) - 2'b00 : expnt_add_op1[9:0] = 10'h1ff; //the expnt sub 1 - 2'b01 : expnt_add_op1[9:0] = 10'h0; //the expnt stay the origi - 2'b1? : expnt_add_op1[9:0] = 10'h1; // the exptn add 1 - default : expnt_add_op1[9:0] = 10'b0; +casez(ex4_frac[54:53]) + 2'b00 : expnt_add_op1[12:0] = 13'h0fff; //the expnt sub 1 + 2'b01 : expnt_add_op1[12:0] = 13'h0; //the expnt stay the origi + 2'b1? : expnt_add_op1[12:0] = 13'h1; // the exptn add 1 + default : expnt_add_op1[12:0] = 13'b0; endcase -// &CombEnd; @50 +// &CombEnd; @37 end -assign ex4_expnt_rst[9:0] = fdsu_ex4_expnt_rst[9:0] + - expnt_add_op1[9:0]; +assign ex4_expnt_rst[12:0] = vfdsu_ex4_expnt_rst[12:0] + + expnt_add_op1[12:0]; //==========================Result Pack===================== // result denormal pack // shift to the denormal number -// &CombBeg; @58 -always @( fdsu_ex4_expnt_rst[9:0] - or fdsu_ex4_denorm_to_tiny_frac - or ex4_frac[25:1]) +// &CombBeg; @45 +always @( vfdsu_ex4_expnt_rst[12:0] + or ex4_frac[54:1] + or vfdsu_ex4_denorm_to_tiny_frac) +begin +case(vfdsu_ex4_expnt_rst[12:0]) + 13'h1: ex4_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1 + 13'h0: ex4_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0 + 13'h1fff:ex4_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1 + 13'h1ffe:ex4_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2 + 13'h1ffd:ex4_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3 + 13'h1ffc:ex4_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4 + 13'h1ffb:ex4_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5 + 13'h1ffa:ex4_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6 + 13'h1ff9:ex4_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7 + 13'h1ff8:ex4_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8 + 13'h1ff7:ex4_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9 + 13'h1ff6:ex4_denorm_frac[51:0] = {9'b0, ex4_frac[54:12]}; //-1033 -10 + 13'h1ff5:ex4_denorm_frac[51:0] = {10'b0,ex4_frac[54:13]}; //-1034 -11 + 13'h1ff4:ex4_denorm_frac[51:0] = {11'b0,ex4_frac[54:14]}; //-1035 -12 + 13'h1ff3:ex4_denorm_frac[51:0] = {12'b0,ex4_frac[54:15]}; //-1036 -13 + 13'h1ff2:ex4_denorm_frac[51:0] = {13'b0,ex4_frac[54:16]}; // -1037 + 13'h1ff1:ex4_denorm_frac[51:0] = {14'b0,ex4_frac[54:17]}; //-1038 + 13'h1ff0:ex4_denorm_frac[51:0] = {15'b0,ex4_frac[54:18]}; //-1039 + 13'h1fef:ex4_denorm_frac[51:0] = {16'b0,ex4_frac[54:19]}; //-1040 + 13'h1fee:ex4_denorm_frac[51:0] = {17'b0,ex4_frac[54:20]}; //-1041 + 13'h1fed:ex4_denorm_frac[51:0] = {18'b0,ex4_frac[54:21]}; //-1042 + 13'h1fec:ex4_denorm_frac[51:0] = {19'b0,ex4_frac[54:22]}; //-1043 + 13'h1feb:ex4_denorm_frac[51:0] = {20'b0,ex4_frac[54:23]}; //-1044 + 13'h1fea:ex4_denorm_frac[51:0] = {21'b0,ex4_frac[54:24]}; //-1045 + 13'h1fe9:ex4_denorm_frac[51:0] = {22'b0,ex4_frac[54:25]}; //-1046 + 13'h1fe8:ex4_denorm_frac[51:0] = {23'b0,ex4_frac[54:26]}; //-1047 + 13'h1fe7:ex4_denorm_frac[51:0] = {24'b0,ex4_frac[54:27]}; //-1048 + 13'h1fe6:ex4_denorm_frac[51:0] = {25'b0,ex4_frac[54:28]}; //-1049 + 13'h1fe5:ex4_denorm_frac[51:0] = {26'b0,ex4_frac[54:29]}; //-1050 + 13'h1fe4:ex4_denorm_frac[51:0] = {27'b0,ex4_frac[54:30]}; //-1056 + 13'h1fe3:ex4_denorm_frac[51:0] = {28'b0,ex4_frac[54:31]}; //-1052 + 13'h1fe2:ex4_denorm_frac[51:0] = {29'b0,ex4_frac[54:32]}; //-1053 + 13'h1fe1:ex4_denorm_frac[51:0] = {30'b0,ex4_frac[54:33]}; //-1054 + 13'h1fe0:ex4_denorm_frac[51:0] = {31'b0,ex4_frac[54:34]}; //-1055 + 13'h1fdf:ex4_denorm_frac[51:0] = {32'b0,ex4_frac[54:35]}; //-1056 + 13'h1fde:ex4_denorm_frac[51:0] = {33'b0,ex4_frac[54:36]}; //-1057 + 13'h1fdd:ex4_denorm_frac[51:0] = {34'b0,ex4_frac[54:37]}; //-1058 + 13'h1fdc:ex4_denorm_frac[51:0] = {35'b0,ex4_frac[54:38]}; //-1059 + 13'h1fdb:ex4_denorm_frac[51:0] = {36'b0,ex4_frac[54:39]}; //-1060 + 13'h1fda:ex4_denorm_frac[51:0] = {37'b0,ex4_frac[54:40]}; //-1061 + 13'h1fd9:ex4_denorm_frac[51:0] = {38'b0,ex4_frac[54:41]}; //-1062 + 13'h1fd8:ex4_denorm_frac[51:0] = {39'b0,ex4_frac[54:42]}; //-1063 + 13'h1fd7:ex4_denorm_frac[51:0] = {40'b0,ex4_frac[54:43]}; //-1064 + 13'h1fd6:ex4_denorm_frac[51:0] = {41'b0,ex4_frac[54:44]}; //-1065 + 13'h1fd5:ex4_denorm_frac[51:0] = {42'b0,ex4_frac[54:45]}; //-1066 + 13'h1fd4:ex4_denorm_frac[51:0] = {43'b0,ex4_frac[54:46]}; //-1067 + 13'h1fd3:ex4_denorm_frac[51:0] = {44'b0,ex4_frac[54:47]}; //-1068 + 13'h1fd2:ex4_denorm_frac[51:0] = {45'b0,ex4_frac[54:48]}; //-1069 + 13'h1fd1:ex4_denorm_frac[51:0] = {46'b0,ex4_frac[54:49]}; //-1070 + 13'h1fd0:ex4_denorm_frac[51:0] = {47'b0,ex4_frac[54:50]}; //-1071 + 13'h1fcf:ex4_denorm_frac[51:0] = {48'b0,ex4_frac[54:51]}; //-1072 + 13'h1fce:ex4_denorm_frac[51:0] = {49'b0,ex4_frac[54:52]}; //-1073 + 13'h1fcd:ex4_denorm_frac[51:0] = {50'b0,ex4_frac[54:53]}; //-1074 + default: ex4_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ? 52'b1 : 52'b0; +endcase +// &CombEnd; @102 +end +// &CombBeg; @103 +always @( vfdsu_ex4_expnt_rst[12:0] + or ex4_frac[54:1] + or vfdsu_ex4_denorm_to_tiny_frac) begin -case(fdsu_ex4_expnt_rst[9:0]) - 10'h1: ex4_single_denorm_frac[22:0] = { ex4_frac[23:1]}; //-1022 1 - 10'h0: ex4_single_denorm_frac[22:0] = { ex4_frac[24:2]}; //-1023 0 - 10'h3ff:ex4_single_denorm_frac[22:0] = { ex4_frac[25:3]}; //-1024 -1 - 10'h3fe:ex4_single_denorm_frac[22:0] = {1'b0, ex4_frac[25:4]}; //-1025 -2 - 10'h3fd:ex4_single_denorm_frac[22:0] = {2'b0, ex4_frac[25:5]}; //-1026 -3 - 10'h3fc:ex4_single_denorm_frac[22:0] = {3'b0, ex4_frac[25:6]}; //-1027 -4 - 10'h3fb:ex4_single_denorm_frac[22:0] = {4'b0, ex4_frac[25:7]}; //-1028 -5 - 10'h3fa:ex4_single_denorm_frac[22:0] = {5'b0, ex4_frac[25:8]}; //-1029 -6 - 10'h3f9:ex4_single_denorm_frac[22:0] = {6'b0, ex4_frac[25:9]}; //-1030 -7 - 10'h3f8:ex4_single_denorm_frac[22:0] = {7'b0, ex4_frac[25:10]}; //-1031 -8 - 10'h3f7:ex4_single_denorm_frac[22:0] = {8'b0, ex4_frac[25:11]}; //-1032 -9 - 10'h3f6:ex4_single_denorm_frac[22:0] = {9'b0, ex4_frac[25:12]}; //-1033 -10 - 10'h3f5:ex4_single_denorm_frac[22:0] = {10'b0,ex4_frac[25:13]}; //-1034 -11 - 10'h3f4:ex4_single_denorm_frac[22:0] = {11'b0,ex4_frac[25:14]}; //-1035 -12 - 10'h3f3:ex4_single_denorm_frac[22:0] = {12'b0,ex4_frac[25:15]}; //-1036 -13 - 10'h3f2:ex4_single_denorm_frac[22:0] = {13'b0,ex4_frac[25:16]}; // -1037 - 10'h3f1:ex4_single_denorm_frac[22:0] = {14'b0,ex4_frac[25:17]}; //-1038 - 10'h3f0:ex4_single_denorm_frac[22:0] = {15'b0,ex4_frac[25:18]}; //-1039 - 10'h3ef:ex4_single_denorm_frac[22:0] = {16'b0,ex4_frac[25:19]}; //-1040 - 10'h3ee:ex4_single_denorm_frac[22:0] = {17'b0,ex4_frac[25:20]}; //-1041 - 10'h3ed:ex4_single_denorm_frac[22:0] = {18'b0,ex4_frac[25:21]}; //-1042 - 10'h3ec:ex4_single_denorm_frac[22:0] = {19'b0,ex4_frac[25:22]}; //-1043 - 10'h3eb:ex4_single_denorm_frac[22:0] = {20'b0,ex4_frac[25:23]}; //-1044 - 10'h3ea:ex4_single_denorm_frac[22:0] = {21'b0,ex4_frac[25:24]}; //-1044 - default :ex4_single_denorm_frac[22:0] = fdsu_ex4_denorm_to_tiny_frac ? 23'b1 : 23'b0; //-1045 +case(vfdsu_ex4_expnt_rst[12:0]) + 13'h1: ex4_single_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1 + 13'h0: ex4_single_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0 + 13'h1fff:ex4_single_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1 + 13'h1ffe:ex4_single_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2 + 13'h1ffd:ex4_single_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3 + 13'h1ffc:ex4_single_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4 + 13'h1ffb:ex4_single_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5 + 13'h1ffa:ex4_single_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6 + 13'h1ff9:ex4_single_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7 + 13'h1ff8:ex4_single_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8 + 13'h1ff7:ex4_single_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9 + 13'h1ff6:ex4_single_denorm_frac[51:0] = {9'b0, ex4_frac[54:12]}; //-1033 -10 + 13'h1ff5:ex4_single_denorm_frac[51:0] = {10'b0,ex4_frac[54:13]}; //-1034 -11 + 13'h1ff4:ex4_single_denorm_frac[51:0] = {11'b0,ex4_frac[54:14]}; //-1035 -12 + 13'h1ff3:ex4_single_denorm_frac[51:0] = {12'b0,ex4_frac[54:15]}; //-1036 -13 + 13'h1ff2:ex4_single_denorm_frac[51:0] = {13'b0,ex4_frac[54:16]}; // -1037 + 13'h1ff1:ex4_single_denorm_frac[51:0] = {14'b0,ex4_frac[54:17]}; //-1038 + 13'h1ff0:ex4_single_denorm_frac[51:0] = {15'b0,ex4_frac[54:18]}; //-1039 + 13'h1fef:ex4_single_denorm_frac[51:0] = {16'b0,ex4_frac[54:19]}; //-1040 + 13'h1fee:ex4_single_denorm_frac[51:0] = {17'b0,ex4_frac[54:20]}; //-1041 + 13'h1fed:ex4_single_denorm_frac[51:0] = {18'b0,ex4_frac[54:21]}; //-1042 + 13'h1fec:ex4_single_denorm_frac[51:0] = {19'b0,ex4_frac[54:22]}; //-1043 + 13'h1feb:ex4_single_denorm_frac[51:0] = {20'b0,ex4_frac[54:23]}; //-1044 + 13'h1fea:ex4_single_denorm_frac[51:0] = {21'b0,ex4_frac[54:24]}; //-1044 + default :ex4_single_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ?{23'b1,29'b0} : 52'b0; //-1045 endcase -// &CombEnd; @86 +// &CombEnd; @131 +end +// &CombBeg; @132 +always @( vfdsu_ex4_expnt_rst[12:0] + or ex4_frac[54:1] + or vfdsu_ex4_denorm_to_tiny_frac) +begin +case(vfdsu_ex4_expnt_rst[12:0]) + 13'h1: ex4_half_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1 + 13'h0: ex4_half_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0 + 13'h1fff:ex4_half_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1 + 13'h1ffe:ex4_half_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2 + 13'h1ffd:ex4_half_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3 + 13'h1ffc:ex4_half_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4 + 13'h1ffb:ex4_half_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5 + 13'h1ffa:ex4_half_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6 + 13'h1ff9:ex4_half_denorm_frac[51:0] = {6'b0, ex4_frac[54:9]}; //-1030 -7 + 13'h1ff8:ex4_half_denorm_frac[51:0] = {7'b0, ex4_frac[54:10]}; //-1031 -8 + 13'h1ff7:ex4_half_denorm_frac[51:0] = {8'b0, ex4_frac[54:11]}; //-1032 -9 + default :ex4_half_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ?{10'b1,42'b0} : 52'b0; //-1045 +endcase +// &CombEnd; @147 +end + +always @( vfdsu_ex4_expnt_rst[12:0] + or ex4_frac[54:1] + or vfdsu_ex4_denorm_to_tiny_frac) +begin +case(vfdsu_ex4_expnt_rst[12:0]) + 13'h1: ex4_bfloat_denorm_frac[51:0] = { ex4_frac[52:1]}; //-1022 1 + 13'h0: ex4_bfloat_denorm_frac[51:0] = { ex4_frac[53:2]}; //-1023 0 + 13'h1fff:ex4_bfloat_denorm_frac[51:0] = { ex4_frac[54:3]}; //-1024 -1 + 13'h1ffe:ex4_bfloat_denorm_frac[51:0] = {1'b0, ex4_frac[54:4]}; //-1025 -2 + 13'h1ffd:ex4_bfloat_denorm_frac[51:0] = {2'b0, ex4_frac[54:5]}; //-1026 -3 + 13'h1ffc:ex4_bfloat_denorm_frac[51:0] = {3'b0, ex4_frac[54:6]}; //-1027 -4 + 13'h1ffb:ex4_bfloat_denorm_frac[51:0] = {4'b0, ex4_frac[54:7]}; //-1028 -5 + 13'h1ffa:ex4_bfloat_denorm_frac[51:0] = {5'b0, ex4_frac[54:8]}; //-1029 -6 + default :ex4_bfloat_denorm_frac[51:0] = vfdsu_ex4_denorm_to_tiny_frac ?{7'b1,45'b0} : 52'b0; //-1045 +endcase end + //here when denormal number round to add1, it will become normal number -assign ex4_denorm_potnt_norm = (fdsu_ex4_potnt_norm[1] && ex4_frac[24]) || - (fdsu_ex4_potnt_norm[0] && ex4_frac[25]) ; -assign ex4_rslt_denorm = fdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm; -assign ex4_denorm_result[31:0] = {fdsu_ex4_result_sign, - 8'h0,ex4_single_denorm_frac[22:0]}; - - +assign ex4_denorm_potnt_norm = (vfdsu_ex4_potnt_norm[1] && ex4_frac[53]) || + (vfdsu_ex4_potnt_norm[0] && ex4_frac[54]) ; +assign ex4_rslt_denorm = !vfdsu_ex4_result_qnan + && !vfdsu_ex4_result_zero + && (vfdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm); +assign ex4_denorm_result[63:0] = vfdsu_ex4_double ? + {vfdsu_ex4_result_sign,11'h0,ex4_denorm_frac[51:0]} : + vfdsu_ex4_single ? {32'hffffffff,vfdsu_ex4_result_sign, + 8'h0,ex4_single_denorm_frac[51:29]} : + vfdsu_ex4_half ? {48'hffffffffffff,vfdsu_ex4_result_sign,5'h0, + ex4_half_denorm_frac[51:42]} + : {48'hffffffffffff,vfdsu_ex4_result_sign,8'h0, + ex4_bfloat_denorm_frac[51:45]}; + + + +assign ex4_half_lfn[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,5'h1e,{10{1'b1}}}; +assign ex4_half_rst_qnan[63:0] = {48'hffffffffffff,vfdsu_ex4_qnan_sign, 5'h1f,1'b1, vfdsu_ex4_qnan_f[8:0]}; +assign ex4_half_rst_inf[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,5'h1f,10'b0}; +assign ex4_half_rst_norm[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign, + ex4_expnt_rst[4:0], + ex4_frac_52[51:42]}; +assign ex4_half_rst0[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,15'h0}; + +assign ex4_bfloat_lfn[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,8'hfe,{7{1'b1}}}; +assign ex4_bfloat_rst_qnan[63:0] = {48'hffffffffffff,vfdsu_ex4_qnan_sign, 8'hff,1'b1, vfdsu_ex4_qnan_f[5:0]}; +assign ex4_bfloat_rst_inf[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,8'hff,7'b0}; +assign ex4_bfloat_rst_norm[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign, + ex4_expnt_rst[7:0], + ex4_frac_52[51:45]}; +assign ex4_bfloat_rst0[63:0] = {48'hffffffffffff,vfdsu_ex4_result_sign,15'h0}; + //ex4 overflow/underflow plus -assign ex4_rst_nor = fdsu_ex4_result_nor; -assign ex4_of_plus = fdsu_ex4_potnt_of && - (|ex4_frac[25:24]) && +assign ex4_rst_nor = vfdsu_ex4_result_nor; +assign ex4_of_plus = vfdsu_ex4_potnt_of && + (|ex4_frac[54:53]) && ex4_rst_nor; -assign ex4_uf_plus = fdsu_ex4_potnt_uf && - (~|ex4_frac[25:24]) && +assign ex4_uf_plus = vfdsu_ex4_potnt_uf && + (~|ex4_frac[54:53]) && ex4_rst_nor; //ex4 overflow round result -assign ex4_result_lfn = (ex4_of_plus && fdsu_ex4_of_rst_lfn) || - fdsu_ex4_result_lfn; -assign ex4_result_inf = (ex4_of_plus && !fdsu_ex4_of_rst_lfn) || - fdsu_ex4_result_inf; +assign ex4_result_lfn = (ex4_of_plus && vfdsu_ex4_of_rst_lfn) || + vfdsu_ex4_result_lfn; +assign ex4_result_inf = (ex4_of_plus && !vfdsu_ex4_of_rst_lfn) || + vfdsu_ex4_result_inf; //Special Result Form // result largest finity number -assign ex4_rst_lfn[31:0] = {fdsu_ex4_result_sign,8'hfe,{23{1'b1}}}; +assign ex4_doub_lfn[63:0] = {vfdsu_ex4_result_sign,11'h7fe,{52{1'b1}}}; +assign ex4_sing_lfn[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,8'hfe,{23{1'b1}}}; +// result 0 +assign ex4_doub_rst0[63:0] = {vfdsu_ex4_result_sign,63'b0}; +assign ex4_sing_rst0[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,31'b0}; +//result qNaN +// &Force("bus","vfdsu_ex4_qnan_f",51,0); @192 +assign ex4_doub_rst_qnan[63:0] = { vfdsu_ex4_qnan_sign, 11'h7ff, 1'b1, vfdsu_ex4_qnan_f[50:0]}; +assign ex4_sing_rst_qnan[63:0] = {32'hffffffff,vfdsu_ex4_qnan_sign, 8'hff, 1'b1, vfdsu_ex4_qnan_f[21:0]}; //result infinity -assign ex4_rst_inf[31:0] = {fdsu_ex4_result_sign,8'hff,23'b0}; +assign ex4_doub_rst_inf[63:0] = {vfdsu_ex4_result_sign,11'h7ff,52'b0}; +assign ex4_sing_rst_inf[63:0] = {32'hffffffff,vfdsu_ex4_result_sign,8'hff,23'b0}; //result normal -// &CombBeg; @114 -always @( ex4_frac[25:0]) +// &CombBeg; @199 +always @( ex4_frac[54:0]) begin -casez(ex4_frac[25:24]) - 2'b00 : ex4_frac_23[22:0] = ex4_frac[22:0]; - 2'b01 : ex4_frac_23[22:0] = ex4_frac[23:1]; - 2'b1? : ex4_frac_23[22:0] = ex4_frac[24:2]; - default : ex4_frac_23[22:0] = 23'b0; +casez(ex4_frac[54:53]) + 2'b00 : ex4_frac_52[51:0] = ex4_frac[51:0]; + 2'b01 : ex4_frac_52[51:0] = ex4_frac[52:1]; + 2'b1? : ex4_frac_52[51:0] = ex4_frac[53:2]; + default : ex4_frac_52[51:0] = 52'b0; endcase -// &CombEnd; @121 +// &CombEnd; @206 end -assign ex4_rst_norm[31:0] = {fdsu_ex4_result_sign, +assign ex4_doub_rst_norm[63:0] = {vfdsu_ex4_result_sign, + ex4_expnt_rst[10:0], + ex4_frac_52[51:0]}; +assign ex4_sing_rst_norm[63:0] = {32'hffffffff,vfdsu_ex4_result_sign, ex4_expnt_rst[7:0], - ex4_frac_23[22:0]}; -assign ex4_cor_uf = (fdsu_ex4_uf || ex4_denorm_potnt_norm || ex4_uf_plus) - && fdsu_ex4_nx; -assign ex4_cor_nx = fdsu_ex4_nx - || fdsu_ex4_of + ex4_frac_52[51:29]}; +assign ex4_rst_lfn[63:0] = (vfdsu_ex4_double) ? ex4_doub_lfn[63:0] : + vfdsu_ex4_single ? ex4_sing_lfn[63:0] : + vfdsu_ex4_half ? ex4_half_lfn[63:0] : ex4_bfloat_lfn[63:0]; + +assign ex4_rst0[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst0[63:0] : + vfdsu_ex4_single ? ex4_sing_rst0[63:0] : + vfdsu_ex4_half ? ex4_half_rst0[63:0] : ex4_bfloat_rst0[63:0]; + +assign ex4_rst_qnan[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_qnan[63:0] : + vfdsu_ex4_single ? ex4_sing_rst_qnan[63:0] : + vfdsu_ex4_half ? ex4_half_rst_qnan[63:0] : ex4_bfloat_rst_qnan[63:0]; + +assign ex4_rst_norm[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_norm[63:0] : + vfdsu_ex4_single ? ex4_sing_rst_norm[63:0] : + vfdsu_ex4_half ? ex4_half_rst_norm[63:0] : ex4_bfloat_rst_norm[63:0]; +assign ex4_rst_inf[63:0] = (vfdsu_ex4_double) ? ex4_doub_rst_inf[63:0] : + vfdsu_ex4_single ? ex4_sing_rst_inf[63:0] : + vfdsu_ex4_half ? ex4_half_rst_inf[63:0] : ex4_bfloat_rst_inf[63:0]; + + +assign ex4_cor_uf = (vfdsu_ex4_uf || ex4_denorm_potnt_norm || ex4_uf_plus) + && vfdsu_ex4_nx; +assign ex4_cor_nx = vfdsu_ex4_nx + || vfdsu_ex4_of || ex4_of_plus; -assign ex4_expt[4:0] = { - fdsu_ex4_nv, - fdsu_ex4_dz, - fdsu_ex4_of | ex4_of_plus, +assign ex4_out_expt[4:0] = { + vfdsu_ex4_nv, + vfdsu_ex4_dz, + vfdsu_ex4_of | ex4_of_plus, ex4_cor_uf, ex4_cor_nx}; -assign ex4_final_rst_norm = !ex4_result_inf && - !ex4_result_lfn && +assign ex4_final_rst_norm = !vfdsu_ex4_result_qnan && + !ex4_result_inf && + !ex4_result_lfn && + !vfdsu_ex4_result_zero && !ex4_rslt_denorm; -// &CombBeg; @141 -always @( ex4_denorm_result[31:0] +// &CombBeg; @249 +always @( ex4_rst_norm[63:0] or ex4_result_lfn + or vfdsu_ex4_result_qnan + or ex4_rst_qnan[63:0] + or ex4_rst0[63:0] + or ex4_rslt_denorm + or ex4_denorm_result[63:0] or ex4_result_inf or ex4_final_rst_norm - or ex4_rst_norm[31:0] - or ex4_rst_lfn[31:0] - or ex4_rst_inf[31:0] - or ex4_rslt_denorm) + or ex4_rst_lfn[63:0] + or vfdsu_ex4_result_zero + or ex4_rst_inf[63:0]) begin case({ex4_rslt_denorm, + vfdsu_ex4_result_qnan, ex4_result_inf, ex4_result_lfn, + vfdsu_ex4_result_zero, ex4_final_rst_norm}) - 4'b1000 : ex4_result[31:0] = ex4_denorm_result[31:0]; - 4'b0100 : ex4_result[31:0] = ex4_rst_inf[31:0]; - 4'b0010 : ex4_result[31:0] = ex4_rst_lfn[31:0]; - 4'b0001 : ex4_result[31:0] = ex4_rst_norm[31:0]; - default : ex4_result[31:0] = 32'b0; + 6'b100000 : ex4_out_result[63:0] = ex4_denorm_result[63:0]; + 6'b010000 : ex4_out_result[63:0] = ex4_rst_qnan[63:0]; + 6'b001000 : ex4_out_result[63:0] = ex4_rst_inf[63:0]; + 6'b000100 : ex4_out_result[63:0] = ex4_rst_lfn[63:0]; + 6'b000010 : ex4_out_result[63:0] = ex4_rst0[63:0]; + 6'b000001 : ex4_out_result[63:0] = ex4_rst_norm[63:0]; + default : ex4_out_result[63:0] = 64'b0; endcase -// &CombEnd; @152 +// &CombEnd; @264 end -//========================================================== -// Result Generate -//========================================================== -assign fdsu_frbus_freg[4:0] = fdsu_yy_wb_freg[4:0]; -assign fdsu_frbus_data[31:0] = ex4_result[31:0]; -assign fdsu_frbus_fflags[4:0] = ex4_expt[4:0]; - -// &ModuleEnd; @161 +// &ModuleEnd; @266 endmodule +// ----- 8< ----- FILE "./ct_vfdsu_prepare.v" ----- 8< ----- -// ----- 8< ----- FILE "./pa_fdsu_prepare.v" ----- 8< ----- - -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -23660,178 +27921,436 @@ See the License for the specific language governing permissions and limitations under the License. */ -// &ModuleBeg; @23 -module pa_fdsu_prepare( - dp_xx_ex1_rm, +// &ModuleBeg; @22 +module ct_vfdsu_prepare( + cp0_vfpu_icg_en, + cp0_yy_clk_en, + cpurst_b, ex1_div, ex1_divisor, - ex1_expnt_adder_op0, - ex1_expnt_adder_op1, - ex1_of_result_lfn, - ex1_op0_id, - ex1_op0_sign, - ex1_op1_id, - ex1_op1_id_vld, - ex1_op1_sel, - ex1_oper_id_expnt, - ex1_oper_id_expnt_f, - ex1_oper_id_frac, - ex1_oper_id_frac_f, + ex1_double, + ex1_pipedown, ex1_remainder, - ex1_result_sign, - ex1_rm, + ex1_scalar, + ex1_single, + ex1_half, + ex1_bfloat, ex1_sqrt, - fdsu_ex1_sel, - idu_fpu_ex1_func, - idu_fpu_ex1_srcf0, - idu_fpu_ex1_srcf1 + ex1_src0, + ex1_src1, + ex1_static_rm, + forever_cpuclk, + pad_yy_icg_scan_en, + vfdsu_ex2_div, + vfdsu_ex2_double, + vfdsu_ex2_dz, + vfdsu_ex2_expnt_add0, + vfdsu_ex2_expnt_add1, + vfdsu_ex2_nv, + vfdsu_ex2_of_rm_lfn, + vfdsu_ex2_op0_norm, + vfdsu_ex2_op1_norm, + vfdsu_ex2_qnan_f, + vfdsu_ex2_qnan_sign, + vfdsu_ex2_result_inf, + vfdsu_ex2_result_qnan, + vfdsu_ex2_result_sign, + vfdsu_ex2_result_zero, + vfdsu_ex2_rm, + vfdsu_ex2_single, + vfdsu_ex2_half, + vfdsu_ex2_bfloat, + vfdsu_ex2_sqrt, + vfdsu_ex2_srt_skip, + vfpu_yy_xx_dqnan, + vfpu_yy_xx_rm ); -// &Ports; @24 -input [2 :0] dp_xx_ex1_rm; -input ex1_op0_id; -input ex1_op1_id; -input ex1_op1_sel; -input [12:0] ex1_oper_id_expnt_f; -input [51:0] ex1_oper_id_frac_f; -input fdsu_ex1_sel; -input [9 :0] idu_fpu_ex1_func; -input [31:0] idu_fpu_ex1_srcf0; -input [31:0] idu_fpu_ex1_srcf1; -output ex1_div; -output [23:0] ex1_divisor; -output [12:0] ex1_expnt_adder_op0; -output [12:0] ex1_expnt_adder_op1; -output ex1_of_result_lfn; -output ex1_op0_sign; -output ex1_op1_id_vld; -output [12:0] ex1_oper_id_expnt; -output [51:0] ex1_oper_id_frac; -output [31:0] ex1_remainder; -output ex1_result_sign; -output [2 :0] ex1_rm; -output ex1_sqrt; - -// &Regs; @25 -reg [12:0] ex1_expnt_adder_op1; -reg ex1_of_result_lfn; - -// &Wires; @26 -wire div_sign; -wire [2 :0] dp_xx_ex1_rm; -wire ex1_div; +// &Ports; @23 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input ex1_div; +input ex1_double; +input ex1_pipedown; +input ex1_scalar; +input ex1_single; +input ex1_half; +input ex1_bfloat; +input ex1_sqrt; +input [63:0] ex1_src0; +input [63:0] ex1_src1; +input [2 :0] ex1_static_rm; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input vfpu_yy_xx_dqnan; +input [2 :0] vfpu_yy_xx_rm; +output [52:0] ex1_divisor; +output [59:0] ex1_remainder; +output vfdsu_ex2_div; +output vfdsu_ex2_double; +output vfdsu_ex2_dz; +output [12:0] vfdsu_ex2_expnt_add0; +output [12:0] vfdsu_ex2_expnt_add1; +output vfdsu_ex2_nv; +output vfdsu_ex2_of_rm_lfn; +output vfdsu_ex2_op0_norm; +output vfdsu_ex2_op1_norm; +output [51:0] vfdsu_ex2_qnan_f; +output vfdsu_ex2_qnan_sign; +output vfdsu_ex2_result_inf; +output vfdsu_ex2_result_qnan; +output vfdsu_ex2_result_sign; +output vfdsu_ex2_result_zero; +output [2 :0] vfdsu_ex2_rm; +output vfdsu_ex2_single; +output vfdsu_ex2_half; +output vfdsu_ex2_bfloat; +output vfdsu_ex2_sqrt; +output vfdsu_ex2_srt_skip; + +// &Regs; @24 +reg [12:0] ex1_expnt_adder_op1; +reg ex1_of_result_lfn; +reg [51:0] ex1_qnan_f; +reg ex1_qnan_sign; +reg vfdsu_ex2_div; +reg vfdsu_ex2_double; +reg vfdsu_ex2_dz; +reg [12:0] vfdsu_ex2_expnt_add0; +reg [12:0] vfdsu_ex2_expnt_add1; +reg vfdsu_ex2_nv; +reg vfdsu_ex2_of_rm_lfn; +reg vfdsu_ex2_op0_norm; +reg vfdsu_ex2_op1_norm; +reg [51:0] vfdsu_ex2_qnan_f; +reg vfdsu_ex2_qnan_sign; +reg vfdsu_ex2_result_inf; +reg vfdsu_ex2_result_qnan; +reg vfdsu_ex2_result_sign; +reg vfdsu_ex2_result_zero; +reg [2 :0] vfdsu_ex2_rm; +reg vfdsu_ex2_single; +reg vfdsu_ex2_half; +reg vfdsu_ex2_bfloat; +reg vfdsu_ex2_sqrt; +reg vfdsu_ex2_srt_skip; + +// &Wires; @25 +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire div_sign; +wire ex1_div; +wire ex1_div_dz; wire [52:0] ex1_div_noid_nor_srt_op0; wire [52:0] ex1_div_noid_nor_srt_op1; -wire [52:0] ex1_div_nor_srt_op0; -wire [52:0] ex1_div_nor_srt_op1; -wire [12:0] ex1_div_op0_expnt; -wire [12:0] ex1_div_op1_expnt; -wire [52:0] ex1_div_srt_op0; -wire [52:0] ex1_div_srt_op1; -wire [23:0] ex1_divisor; -wire ex1_double; -wire [12:0] ex1_expnt_adder_op0; -wire ex1_op0_id; -wire ex1_op0_id_nor; -wire ex1_op0_sign; -wire ex1_op1_id; -wire ex1_op1_id_nor; -wire ex1_op1_id_vld; -wire ex1_op1_sel; -wire ex1_op1_sign; -wire [63:0] ex1_oper0; -wire [51:0] ex1_oper0_frac; -wire [12:0] ex1_oper0_id_expnt; -wire [51:0] ex1_oper0_id_frac; -wire [63:0] ex1_oper1; -wire [51:0] ex1_oper1_frac; -wire [12:0] ex1_oper1_id_expnt; -wire [51:0] ex1_oper1_id_frac; -wire [51:0] ex1_oper_frac; -wire [12:0] ex1_oper_id_expnt; -wire [12:0] ex1_oper_id_expnt_f; -wire [51:0] ex1_oper_id_frac; -wire [51:0] ex1_oper_id_frac_f; -wire [31:0] ex1_remainder; -wire ex1_result_sign; -wire [2 :0] ex1_rm; -wire ex1_single; -wire ex1_sqrt; -wire ex1_sqrt_expnt_odd; -wire ex1_sqrt_op0_expnt_0; -wire [12:0] ex1_sqrt_op1_expnt; -wire [52:0] ex1_sqrt_srt_op0; -wire fdsu_ex1_sel; -wire [9 :0] idu_fpu_ex1_func; -wire [31:0] idu_fpu_ex1_srcf0; -wire [31:0] idu_fpu_ex1_srcf1; -wire [59:0] sqrt_remainder; -wire sqrt_sign; - - -assign ex1_sqrt = idu_fpu_ex1_func[0]; -assign ex1_div = idu_fpu_ex1_func[1]; -assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[31:0] & {32{fdsu_ex1_sel}}}; -assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[31:0] & {32{fdsu_ex1_sel}}}; -assign ex1_double = 1'b0; -assign ex1_single = 1'b1; -// &Force("bus", "idu_fpu_ex1_func", 9, 0); @43 -assign ex1_op0_id_nor = ex1_op0_id; -assign ex1_op1_id_nor = ex1_op1_id; +wire [52:0] ex1_div_nor_srt_op0; +wire [52:0] ex1_div_nor_srt_op1; +wire ex1_div_nv; +wire [12:0] ex1_div_op0_expnt; +wire [12:0] ex1_div_op1_expnt; +wire ex1_div_rst_inf; +wire ex1_div_rst_qnan; +wire ex1_div_rst_zero; +wire [52:0] ex1_div_srt_op0; +wire [52:0] ex1_div_srt_op1; +wire [52:0] ex1_divisor; +wire ex1_doub_expnt0_max; +wire ex1_doub_expnt0_zero; +wire ex1_doub_expnt1_max; +wire ex1_doub_expnt1_zero; +wire ex1_doub_frac0_all0; +wire ex1_doub_frac1_all0; +wire ex1_double; +wire ex1_dz; +wire ex1_expnt0_max; +wire ex1_expnt0_zero; +wire ex1_expnt1_max; +wire ex1_expnt1_zero; +wire [12:0] ex1_expnt_adder_op0; +wire ex1_frac0_all0; +wire ex1_frac0_msb; +wire ex1_frac1_all0; +wire ex1_frac1_msb; +wire ex1_half_expnt0_max; +wire ex1_half_expnt0_zero; +wire ex1_half_expnt1_max; +wire ex1_half_expnt1_zero; +wire ex1_half_frac0_all0; +wire ex1_half_frac1_all0; +wire ex1_bfloat_expnt0_max; +wire ex1_bfloat_expnt1_max; +wire ex1_bfloat_expnt0_zero; +wire ex1_bfloat_expnt1_zero; +wire ex1_bfloat_frac0_all0; +wire ex1_bfloat_frac1_all0; +wire ex1_nv; +wire ex1_op0_cnan; +wire [51:0] ex1_op0_f; +wire ex1_op0_id; +wire ex1_op0_id_nor; +wire ex1_op0_inf; +wire ex1_op0_is_qnan; +wire ex1_op0_is_snan; +wire ex1_op0_norm; +wire ex1_op0_qnan; +wire ex1_op0_sign; +wire ex1_op0_snan; +wire ex1_op0_tt_zero; +wire ex1_op0_zero; +wire ex1_op1_cnan; +wire [51:0] ex1_op1_f; +wire ex1_op1_id; +wire ex1_op1_id_nor; +wire ex1_op1_inf; +wire ex1_op1_is_qnan; +wire ex1_op1_is_snan; +wire ex1_op1_norm; +wire ex1_op1_qnan; +wire ex1_op1_sign; +wire ex1_op1_snan; +wire ex1_op1_tt_zero; +wire ex1_op1_zero; +wire [63:0] ex1_oper0; +wire [51:0] ex1_oper0_frac; +wire ex1_oper0_high_all1; +wire [12:0] ex1_oper0_id_expnt; +wire [51:0] ex1_oper0_id_frac; +wire [63:0] ex1_oper1; +wire [51:0] ex1_oper1_frac; +wire ex1_oper1_high_all1; +wire [12:0] ex1_oper1_id_expnt; +wire [51:0] ex1_oper1_id_frac; +wire ex1_pipe_clk; +wire ex1_pipe_clk_en; +wire ex1_pipedown; +wire [59:0] ex1_remainder; +wire ex1_result_inf; +wire ex1_result_qnan; +wire ex1_result_sign; +wire ex1_result_zero; +wire [2 :0] ex1_rm; +wire ex1_rst_default_qnan; +wire ex1_scalar; +wire ex1_sing_expnt0_max; +wire ex1_sing_expnt0_zero; +wire ex1_sing_expnt1_max; +wire ex1_sing_expnt1_zero; +wire ex1_sing_frac0_all0; +wire ex1_sing_frac1_all0; +wire ex1_single; +wire ex1_half; +wire ex1_bfloat; +wire ex1_sqrt; +wire ex1_sqrt_expnt_odd; +wire ex1_sqrt_expnt_result_odd; +wire ex1_sqrt_nv; +wire [12:0] ex1_sqrt_op1_expnt; +wire ex1_sqrt_rst_inf; +wire ex1_sqrt_rst_qnan; +wire ex1_sqrt_rst_zero; +wire [52:0] ex1_sqrt_srt_op0; +wire [63:0] ex1_src0; +wire [63:0] ex1_src1; +wire ex1_srt_skip; +wire [2 :0] ex1_static_rm; +wire forever_cpuclk; +wire pad_yy_icg_scan_en; +wire [59:0] sqrt_remainder; +wire sqrt_sign; +wire vfpu_yy_xx_dqnan; +wire [2 :0] vfpu_yy_xx_rm; + + +//======================Operator prepare==================== +//VECTOR_SIMD + +assign ex1_oper0[63:0] = ex1_src0[63:0]; +assign ex1_oper1[63:0] = ex1_src1[63:0]; + //Sign bit prepare -assign ex1_op0_sign = ex1_double && ex1_oper0[63] - || ex1_single && ex1_oper0[31]; -assign ex1_op1_sign = ex1_double && ex1_oper1[63] - || ex1_single && ex1_oper1[31]; +assign ex1_op0_sign = ex1_double ? ex1_oper0[63] : + ex1_single ? ex1_oper0[31] : + ex1_half ? ex1_oper0[15] : ex1_oper0[15]; +assign ex1_op1_sign = ex1_double ? ex1_oper1[63] : + ex1_single ? ex1_oper1[31] : + ex1_half ? ex1_oper1[15] : ex1_oper1[15]; assign div_sign = ex1_op0_sign ^ ex1_op1_sign; assign sqrt_sign = ex1_op0_sign; assign ex1_result_sign = (ex1_div) - ? div_sign + ? div_sign : sqrt_sign; +//exponent max +assign ex1_doub_expnt0_max = &ex1_oper0[62:52]; +assign ex1_sing_expnt0_max = &ex1_oper0[30:23]; +assign ex1_doub_expnt1_max = &ex1_oper1[62:52]; +assign ex1_sing_expnt1_max = &ex1_oper1[30:23]; +assign ex1_half_expnt0_max = &ex1_oper0[14:10]; +assign ex1_half_expnt1_max = &ex1_oper1[14:10]; +assign ex1_bfloat_expnt0_max = &ex1_oper0[14:7]; +assign ex1_bfloat_expnt1_max = &ex1_oper1[14:7]; +assign ex1_expnt0_max = ex1_double ? ex1_doub_expnt0_max : + ex1_single ? ex1_sing_expnt0_max : + ex1_half ? ex1_half_expnt0_max : ex1_bfloat_expnt0_max; +assign ex1_expnt1_max = ex1_double ? ex1_doub_expnt1_max : + ex1_single ? ex1_sing_expnt1_max : + ex1_half ? ex1_half_expnt1_max : ex1_bfloat_expnt1_max; + +//exponent zero +assign ex1_doub_expnt0_zero = ~|ex1_oper0[62:52]; +assign ex1_sing_expnt0_zero = ~|ex1_oper0[30:23]; +assign ex1_doub_expnt1_zero = ~|ex1_oper1[62:52]; +assign ex1_sing_expnt1_zero = ~|ex1_oper1[30:23]; +assign ex1_half_expnt0_zero = ~|ex1_oper0[14:10]; +assign ex1_half_expnt1_zero = ~|ex1_oper1[14:10]; +assign ex1_bfloat_expnt0_zero = ~|ex1_oper0[14:7]; +assign ex1_bfloat_expnt1_zero = ~|ex1_oper1[14:7]; +assign ex1_expnt0_zero = ex1_double ? ex1_doub_expnt0_zero : + ex1_single ? ex1_sing_expnt0_zero : + ex1_half ? ex1_half_expnt0_zero : ex1_bfloat_expnt0_zero; +assign ex1_expnt1_zero = ex1_double ? ex1_doub_expnt1_zero : + ex1_single ? ex1_sing_expnt1_zero : + ex1_half ? ex1_half_expnt1_zero : ex1_bfloat_expnt1_zero; + +//fraction zero +assign ex1_doub_frac0_all0 = ~|ex1_oper0[51:0]; +assign ex1_sing_frac0_all0 = ~|ex1_oper0[22:0]; +assign ex1_doub_frac1_all0 = ~|ex1_oper1[51:0]; +assign ex1_sing_frac1_all0 = ~|ex1_oper1[22:0]; +assign ex1_half_frac0_all0 = ~|ex1_oper0[9:0]; +assign ex1_half_frac1_all0 = ~|ex1_oper1[9:0]; +assign ex1_bfloat_frac0_all0 = ~|ex1_oper0[6:0]; +assign ex1_bfloat_frac1_all0 = ~|ex1_oper1[6:0]; +assign ex1_frac0_all0 = ex1_double ? ex1_doub_frac0_all0 : + ex1_single ? ex1_sing_frac0_all0 : + ex1_half ? ex1_half_frac0_all0 : ex1_bfloat_frac0_all0; +assign ex1_frac1_all0 = ex1_double ? ex1_doub_frac1_all0 : + ex1_single ? ex1_sing_frac1_all0 : + ex1_half ? ex1_half_frac1_all0 : ex1_bfloat_frac1_all0; +assign ex1_frac0_msb = ex1_double ? ex1_oper0[51] : + ex1_single ? ex1_oper0[22] : + ex1_half ? ex1_oper0[9] : ex1_oper0[6]; +assign ex1_frac1_msb = ex1_double ? ex1_oper1[51] : + ex1_single ? ex1_oper1[22] : + ex1_half ? ex1_oper1[9] : ex1_oper1[6]; +assign ex1_oper0_high_all1 = ex1_single ? &ex1_oper0[63:32] : &ex1_oper0[63:16]; +assign ex1_oper1_high_all1 = ex1_single ? &ex1_oper1[63:32] : &ex1_oper1[63:16]; + + +//infinity number +assign ex1_op0_inf = ex1_expnt0_max && + ex1_frac0_all0 && + ~ex1_op0_cnan; +assign ex1_op1_inf = ex1_expnt1_max && + ex1_frac1_all0 && + ~ex1_op1_cnan; +//zero +assign ex1_op0_zero = ex1_expnt0_zero && + ex1_frac0_all0 && + ~ex1_op0_cnan; +assign ex1_op1_zero = ex1_expnt1_zero && + ex1_frac1_all0 && + ~ex1_op1_cnan; +//denormalize number +assign ex1_op0_id = ex1_expnt0_zero && + ~ex1_frac0_all0 && + ~ex1_op0_cnan; +assign ex1_op1_id = ex1_expnt1_zero && + ~ex1_frac1_all0 && + ~ex1_op1_cnan; +//assign ex1_op0_id_fm1 = vfpu_yy_xx_fm[1] && +// vfpu_yy_xx_fm[0] && +// ex1_op0_id; +//assign ex1_op1_id_fm1 = vfpu_yy_xx_fm[1] && +// vfpu_yy_xx_fm[0] && +// ex1_op1_id; +//assign ex1_op0_id_fm0 = vfpu_yy_xx_fm[1] && +// !vfpu_yy_xx_fm[0] && +// ex1_op0_id; +//assign ex1_op1_id_fm0 = vfpu_yy_xx_fm[1] && +// !vfpu_yy_xx_fm[0] && +// ex1_op1_id; +assign ex1_op0_id_nor = ex1_op0_id; +assign ex1_op1_id_nor = ex1_op1_id; + +//cNaN +assign ex1_op0_cnan = ex1_scalar && + !ex1_double && + !ex1_oper0_high_all1; + +assign ex1_op1_cnan = ex1_scalar && + !ex1_double && + !ex1_oper1_high_all1; + +//sNaN +assign ex1_op0_snan = ex1_expnt0_max && + ~ex1_frac0_all0 && + ~ex1_frac0_msb && + ~ex1_op0_cnan; +assign ex1_op1_snan = ex1_expnt1_max && + ~ex1_frac1_all0 && + ~ex1_frac1_msb && + ~ex1_op1_cnan; +//qNaN +assign ex1_op0_qnan = (ex1_expnt0_max && + ex1_frac0_msb) || + ex1_op0_cnan; +assign ex1_op1_qnan = (ex1_expnt1_max && + ex1_frac1_msb) || + ex1_op1_cnan; //=====================find first one======================= // this is for the denormal number -assign ex1_oper_frac[51:0] = ex1_op1_sel ? ex1_oper1_frac[51:0] - : ex1_oper0_frac[51:0]; - -// &Instance("pa_fdsu_ff1", "x_frac_expnt"); @63 -pa_fdsu_ff1 x_frac_expnt ( - .fanc_shift_num (ex1_oper_id_frac[51:0] ), - .frac_bin_val (ex1_oper_id_expnt[12:0]), - .frac_num (ex1_oper_frac[51:0] ) +// &Instance("ct_vfdsu_ff1","x_frac0_expnt"); @150 +ct_vfdsu_ff1 x_frac0_expnt ( + .fanc_shift_num (ex1_oper0_id_frac[51:0] ), + .frac_bin_val (ex1_oper0_id_expnt[12:0]), + .frac_num (ex1_oper0_frac[51:0] ) ); -// &Connect(.frac_num(ex1_oper_frac[51:0])); @64 -// &Connect(.frac_bin_val(ex1_oper_id_expnt[12:0])); @65 -// &Connect(.fanc_shift_num(ex1_oper_id_frac[51:0])); @66 -// &Force("output", "ex1_oper_id_expnt"); &Force("bus", "ex1_oper_id_expnt", 12, 0); @67 -// &Force("output", "ex1_oper_id_frac"); &Force("bus", "ex1_oper_id_frac", 51, 0); @68 +// &Connect(.frac_num(ex1_oper0_frac[51:0])); @151 +// &Connect(.frac_bin_val(ex1_oper0_id_expnt[12:0])); @152 +// &Connect(.fanc_shift_num(ex1_oper0_id_frac[51:0])); @153 -assign ex1_oper0_id_expnt[12:0] = ex1_op1_sel ? ex1_oper_id_expnt_f[12:0] - : ex1_oper_id_expnt[12:0]; -assign ex1_oper0_id_frac[51:0] = ex1_op1_sel ? ex1_oper_id_frac_f[51:0] - : ex1_oper_id_frac[51:0]; -assign ex1_oper1_id_expnt[12:0] = ex1_oper_id_expnt[12:0]; -assign ex1_oper1_id_frac[51:0] = ex1_oper_id_frac[51:0]; - -assign ex1_oper0_frac[51:0] = {52{ex1_double}} & ex1_oper0[51:0] - | {52{ex1_single}} & {ex1_oper0[22:0],29'b0}; -assign ex1_oper1_frac[51:0] = {52{ex1_double}} & ex1_oper1[51:0] - | {52{ex1_single}} & {ex1_oper1[22:0],29'b0}; +// &Instance("ct_vfdsu_ff1","x_frac1_expnt"); @155 +ct_vfdsu_ff1 x_frac1_expnt ( + .fanc_shift_num (ex1_oper1_id_frac[51:0] ), + .frac_bin_val (ex1_oper1_id_expnt[12:0]), + .frac_num (ex1_oper1_frac[51:0] ) +); +// &Connect(.frac_num(ex1_oper1_frac[51:0])); @156 +// &Connect(.frac_bin_val(ex1_oper1_id_expnt[12:0])); @157 +// &Connect(.fanc_shift_num(ex1_oper1_id_frac[51:0])); @158 +assign ex1_oper0_frac[51:0] = ex1_double ? ex1_oper0[51:0] : + ex1_single ? {ex1_oper0[22:0],29'b0} : + ex1_half ? {ex1_oper0[9:0],42'b0} + : {ex1_oper0[6:0],45'b0}; +assign ex1_oper1_frac[51:0] = ex1_double ? ex1_oper1[51:0] : + ex1_single ? {ex1_oper1[22:0],29'b0} : + ex1_half ? {ex1_oper1[9:0],42'b0} + : {ex1_oper1[6:0],45'b0}; //=====================exponent add========================= //exponent number 0 -assign ex1_div_op0_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper0[62:52]} - | {13{ex1_single}} & {5'b0,ex1_oper0[30:23]}; +assign ex1_div_op0_expnt[12:0] = ex1_double ? {2'b0,ex1_oper0[62:52]} : + ex1_single ? {5'b0,ex1_oper0[30:23]} : + ex1_half ? {8'b0,ex1_oper0[14:10]} + : {5'b0,ex1_oper0[14:7]}; assign ex1_expnt_adder_op0[12:0] = ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0] - : ex1_div_op0_expnt[12:0]; + : ex1_div_op0_expnt[12:0]; //exponent number 1 -assign ex1_div_op1_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper1[62:52]} - | {13{ex1_single}} & {5'b0,ex1_oper1[30:23]}; -assign ex1_sqrt_op1_expnt[12:0] = {13{ex1_double}} & {3'b0,{10{1'b1}}} //'d1023 - | {13{ex1_single}} & {6'b0,{7{1'b1}}}; //'d127 -// &CombBeg; @93 +assign ex1_div_op1_expnt[12:0] = ex1_double ? {2'b0,ex1_oper1[62:52]} : + ex1_single ? {5'b0,ex1_oper1[30:23]} : + ex1_half ? {8'b0,ex1_oper1[14:10]} + : {5'b0,ex1_oper1[14:7]}; +assign ex1_sqrt_op1_expnt[12:0] = ex1_double ? {3'b0,{10{1'b1}}} : //'d1023 + ex1_single ? {6'b0,{7{1'b1}}} ://'d127 + ex1_half ? {9'b0,{4{1'b1}}} //'d15 + : {6'b0,{7{1'b1}}}; //'d127 + +// &CombBeg; @180 always @( ex1_oper1_id_expnt[12:0] or ex1_div or ex1_op1_id_nor @@ -23845,27 +28364,129 @@ case({ex1_div,ex1_sqrt}) 2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0]; default: ex1_expnt_adder_op1[12:0] = 13'b0; endcase -// &CombEnd; @100 +// &CombEnd; @187 end +//expnt0 sub expnt1 +assign ex1_sqrt_expnt_result_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0]; + + +//======================EX1 expt detect===================== +//ex1_id_detect +//any opration is zero +// no input denormalize exception anymore +// +//ex1_nv_detect +//div_nv +// 1.any operation is sNaN +// 2.0/0(include DN flush to zero) +// 3.inf/inf +//sqrt_nv +// 1.any operation is sNaN +// 2.operation sign is 1 && operation is not zero/qNaN +assign ex1_nv = ex1_div && ex1_div_nv || + ex1_sqrt && ex1_sqrt_nv; +//ex1_div_nv +assign ex1_div_nv = ex1_op0_snan || + ex1_op1_snan || + (ex1_op0_tt_zero && ex1_op1_tt_zero)|| + (ex1_op0_inf && ex1_op1_inf); +assign ex1_op0_tt_zero = ex1_op0_zero; +assign ex1_op1_tt_zero = ex1_op1_zero; +//ex1_sqrt_nv +assign ex1_sqrt_nv = ex1_op0_snan || + ex1_op0_sign && + (ex1_op0_norm || + ex1_op0_inf ); +assign ex1_op0_norm = !ex1_expnt0_zero && !ex1_expnt0_max && !ex1_op0_cnan || ex1_op0_id_nor ; +assign ex1_op1_norm = !ex1_expnt1_zero && !ex1_expnt1_max && !ex1_op1_cnan || ex1_op1_id_nor; + +//ex1_of_detect +//div_of +// 1.only detect id overflow case +//assign ex1_of = ex1_div && ex1_div_of; +//assign ex1_div_of = ex1_op1_id_fm1 && +// ex1_op0_norm && +// ex1_div_id_of; +// +////ex1_uf_detect +////div_uf +//// 1.only detect id underflow case +//assign ex1_uf = ex1_div && ex1_div_uf; +//assign ex1_div_uf = ex1_op0_id && +// ex1_op1_norm && +// ex1_div_id_uf; +//ex1_dz_detect +//div_dz +// 1.op0 is normal && op1 zero +assign ex1_dz = ex1_div && ex1_div_dz; +assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm; +//===================sqrt exponent prepare================== +//sqrt exponent prepare +//afert E sub, div E by 2 +//assign ex1_sqrt_expnt_result[12:0] = {ex1_expnt_result[12], +// ex1_expnt_result[12:1]}; //ex1_sqrt_expnt_odd //fraction will shift left by 1 -// adder_op0/1 timing is bad. -// assign ex1_sqrt_expnt_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0]; +assign ex1_sqrt_expnt_odd = ex1_sqrt_expnt_result_odd; + +//===================special cal result===================== +//ex1 result is zero +//div_zero +// 1.op0 is zero && op1 is normal +// 2.op0 is zero/normal && op1 is inf +//sqrt_zero +// 1.op0 is zero +assign ex1_result_zero = ex1_div_rst_zero && ex1_div || + ex1_sqrt_rst_zero && ex1_sqrt; +assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) || + (!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf); +assign ex1_sqrt_rst_zero = ex1_op0_tt_zero; + +//ex1 result is qNaN +//ex1_nv +//div_qnan +// 1.op0 is qnan || op1 is qnan +//sqrt_qnan +// 1.op0 is qnan +assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div || + ex1_sqrt_rst_qnan && ex1_sqrt || + ex1_nv; +assign ex1_div_rst_qnan = ex1_op0_qnan || + ex1_op1_qnan; +assign ex1_sqrt_rst_qnan = ex1_op0_qnan; + +//ex1_rst_default_qnan +//0/0, inf/inf, sqrt negative should get default qNaN +assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) || + (ex1_div && ex1_op0_inf && ex1_op1_inf) || + (ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf)); + +//ex1 result is inf +//ex1_dz +// +//div_inf +// 1.op0 is inf && op1 is normal/zero +//sqrt_inf +// 1.op0 is inf +assign ex1_result_inf = ex1_div_rst_inf && ex1_div || + ex1_sqrt_rst_inf && ex1_sqrt || + ex1_dz ; +assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan; +assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign; -// sqrt_odd is only used when is sqrt. -assign ex1_sqrt_op0_expnt_0 = ex1_op0_id_nor ? ex1_oper_id_expnt[0] - : ex1_div_op0_expnt[0]; -// ex1_expnt_adder_op1 is always 1'b1, so adder_op0[0] should be 0. -assign ex1_sqrt_expnt_odd = !ex1_sqrt_op0_expnt_0; +//ex1 result is lfn +//ex1_of && round result toward not inc 1 -assign ex1_rm[2:0] = dp_xx_ex1_rm[2:0]; +assign ex1_rm[2:0] = ((ex1_static_rm[2:0] == 3'b111)|| !ex1_scalar) + ? vfpu_yy_xx_rm[2:0] + : ex1_static_rm[2:0]; //RNE : Always inc 1 because round to nearest of 1.111...11 //RTZ : Always not inc 1 //RUP : Always not inc 1 when posetive //RDN : Always not inc 1 when negative //RMM : Always inc 1 because round to max magnitude -// &CombBeg; @119 +// &CombBeg; @308 always @( ex1_rm[2:0] or ex1_result_sign) begin @@ -23877,32 +28498,36 @@ case(ex1_rm[2:0]) 3'b100 : ex1_of_result_lfn = 1'b0; default: ex1_of_result_lfn = 1'b0; endcase -// &CombEnd; @128 +// &CombEnd; @317 end //EX1 Remainder //div : 1/8 <= x < 1/4 //sqrt : 1/16 <= x < 1/4 -assign ex1_remainder[31:0] = {32{ex1_div }} & {5'b0,ex1_div_srt_op0[52:28],2'b0} | - {32{ex1_sqrt}} & sqrt_remainder[59:28]; +assign ex1_remainder[59:0] = {60{ex1_div }} & {5'b0,ex1_div_srt_op0[52:0],2'b0} | + {60{ex1_sqrt}} & sqrt_remainder[59:0]; //EX1 Divisor //1/2 <= y < 1 -assign ex1_divisor[23:0] = ex1_div_srt_op1[52:29]; +assign ex1_divisor[52:0] = ex1_div_srt_op1[52:0]; //ex1_div_srt_op0 assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0]; //ex1_div_srt_op1 assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0]; //ex1_div_nor_srt_op0 -assign ex1_div_noid_nor_srt_op0[52:0] = {53{ex1_double}} & {1'b1,ex1_oper0[51:0]} - | {53{ex1_single}} & {1'b1,ex1_oper0[22:0],29'b0}; -assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0} +assign ex1_div_noid_nor_srt_op0[52:0] = ex1_double ? {1'b1,ex1_oper0[51:0]} : + ex1_single ? {1'b1,ex1_oper0[22:0],29'b0} : + ex1_half ? {1'b1,ex1_oper0[9:0],42'b0} + : {1'b1,ex1_oper0[6:0],45'b0}; +assign ex1_div_noid_nor_srt_op1[52:0] = ex1_double ? {1'b1,ex1_oper1[51:0]} : + ex1_single ? {1'b1,ex1_oper1[22:0],29'b0} : + ex1_half ? {1'b1,ex1_oper1[9:0],42'b0} + : {1'b1,ex1_oper1[6:0],45'b0}; +assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0} : ex1_div_noid_nor_srt_op0[52:0]; //ex1_div_nor_srt_op1 -assign ex1_div_noid_nor_srt_op1[52:0] = {53{ex1_double}} & {1'b1,ex1_oper1[51:0]} - | {53{ex1_single}} & {1'b1,ex1_oper1[22:0],29'b0}; -assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0} +assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0} : ex1_div_noid_nor_srt_op1[52:0]; //sqrt_remainder assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd) @@ -23911,29 +28536,200 @@ assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd) //ex1_sqrt_srt_op0 assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0]; +//Default_qnan/Standard_qnan Select +assign ex1_op0_is_snan = ex1_op0_snan; +assign ex1_op1_is_snan = ex1_op1_snan && ex1_div; +assign ex1_op0_is_qnan = ex1_op0_qnan; +assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div; +assign ex1_op0_f[51:0] = (ex1_op0_cnan) ? 52'b0: ex1_oper0[51:0]; +assign ex1_op1_f[51:0] = (ex1_op1_cnan) ? 52'b0: ex1_oper1[51:0]; +// &CombBeg; @359 +always @( ex1_op0_is_snan + or ex1_op0_is_qnan + or ex1_op0_f[51:0] + or ex1_rst_default_qnan + or ex1_op1_f[51:0] + or vfpu_yy_xx_dqnan + or ex1_op1_is_snan + or ex1_op1_is_qnan) +begin +if(ex1_rst_default_qnan) + ex1_qnan_f[51:0] = {1'b1, 51'b0}; +else if(ex1_op0_is_snan && vfpu_yy_xx_dqnan) + ex1_qnan_f[51:0] = ex1_op0_f[51:0]; +else if(ex1_op1_is_snan && vfpu_yy_xx_dqnan) + ex1_qnan_f[51:0] = ex1_op1_f[51:0]; +else if(ex1_op0_is_qnan && vfpu_yy_xx_dqnan) + ex1_qnan_f[51:0] = ex1_op0_f[51:0]; +else if(ex1_op1_is_qnan && vfpu_yy_xx_dqnan) + ex1_qnan_f[51:0] = ex1_op1_f[51:0]; +else + ex1_qnan_f[51:0] = {1'b1, 51'b0}; +// &CombEnd; @372 +end + +// &CombBeg; @374 +always @( ex1_op0_is_snan + or ex1_op0_cnan + or ex1_op0_is_qnan + or ex1_op1_sign + or ex1_op0_sign + or ex1_rst_default_qnan + or vfpu_yy_xx_dqnan + or ex1_op1_cnan + or ex1_op1_is_snan + or ex1_op1_is_qnan) +begin +if(ex1_rst_default_qnan) + ex1_qnan_sign = 1'b0; +else if(ex1_op0_is_snan && vfpu_yy_xx_dqnan) + ex1_qnan_sign = ex1_op0_sign; +else if(ex1_op1_is_snan && vfpu_yy_xx_dqnan) + ex1_qnan_sign = ex1_op1_sign; +else if(ex1_op0_is_qnan && vfpu_yy_xx_dqnan) + ex1_qnan_sign = ex1_op0_sign && !ex1_op0_cnan; +else if(ex1_op1_is_qnan && vfpu_yy_xx_dqnan) + ex1_qnan_sign = ex1_op1_sign && !ex1_op1_cnan; +else + ex1_qnan_sign = 1'b0; +// &CombEnd; @387 +end + + //========================Pipe to EX2======================= //exponent register cal result -// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @173 -// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @174 -// &Force("output", "ex1_double"); @175 -// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @177 -// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @178 -// &Force("output", "ex1_result_sign"); @180 -// &Force("output", "ex1_div"); @181 -// &Force("output", "ex1_sqrt"); @182 -// &Force("output", "ex1_rm"); &Force("bus", "ex1_rm", 2, 0); @183 -// &Force("output", "ex1_op0_sign"); @184 - -assign ex1_op1_id_vld = ex1_op1_id_nor && ex1_div; - -// &ModuleEnd; @188 -endmodule +//assign ex1_srt_expnt_rst[12:0] = (ex1_sqrt) +// ? ex1_sqrt_expnt_result[12:0] +// : ex1_expnt_result[12:0]; +//Special result should skip SRT logic +assign ex1_srt_skip = ex1_result_zero || + ex1_result_qnan || + ex1_result_inf; +//gate clk +// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @400 +gated_clk_cell x_ex1_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex1_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex1_pipe_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @401 +// .clk_out (ex1_pipe_clk),//Out Clock @402 +// .external_en (1'b0), @403 +// .global_en (cp0_yy_clk_en), @404 +// .local_en (ex1_pipe_clk_en),//Local Condition @405 +// .module_en (cp0_vfpu_icg_en) @406 +// ); @407 +assign ex1_pipe_clk_en = ex1_pipedown; + +always @(posedge ex1_pipe_clk or negedge cpurst_b) +begin + if(!cpurst_b) + begin + vfdsu_ex2_result_zero <= 1'b0; + vfdsu_ex2_result_qnan <= 1'b0; + vfdsu_ex2_result_inf <= 1'b0; + vfdsu_ex2_result_sign <= 1'b0; + vfdsu_ex2_op0_norm <= 1'b0; + vfdsu_ex2_op1_norm <= 1'b0; + vfdsu_ex2_expnt_add0[12:0] <= 13'b0; + vfdsu_ex2_expnt_add1[12:0] <= 13'b0; + vfdsu_ex2_nv <= 1'b0; + vfdsu_ex2_dz <= 1'b0; + vfdsu_ex2_srt_skip <= 1'b0; + vfdsu_ex2_of_rm_lfn <= 1'b0; + vfdsu_ex2_qnan_sign <= 1'b0; + vfdsu_ex2_qnan_f[51:0] <= 52'b0; + vfdsu_ex2_rm[2:0] <= 3'b0; + vfdsu_ex2_div <= 1'b0; + vfdsu_ex2_sqrt <= 1'b0; + vfdsu_ex2_double <= 1'b0; + vfdsu_ex2_single <= 1'b0; + vfdsu_ex2_half <= 1'b0; + vfdsu_ex2_bfloat <= 1'b0; + end + else if(ex1_pipedown) + begin + vfdsu_ex2_result_zero <= ex1_result_zero; + vfdsu_ex2_result_qnan <= ex1_result_qnan; + vfdsu_ex2_result_inf <= ex1_result_inf; + vfdsu_ex2_result_sign <= ex1_result_sign; + vfdsu_ex2_op0_norm <= ex1_op0_norm; + vfdsu_ex2_op1_norm <= ex1_op1_norm; + vfdsu_ex2_expnt_add0[12:0] <= ex1_expnt_adder_op0[12:0]; + vfdsu_ex2_expnt_add1[12:0] <= ex1_expnt_adder_op1[12:0]; + vfdsu_ex2_nv <= ex1_nv; + vfdsu_ex2_dz <= ex1_dz; + vfdsu_ex2_srt_skip <= ex1_srt_skip; + vfdsu_ex2_of_rm_lfn <= ex1_of_result_lfn; + vfdsu_ex2_qnan_sign <= ex1_qnan_sign; + vfdsu_ex2_qnan_f[51:0] <= ex1_qnan_f[51:0]; + vfdsu_ex2_rm[2:0] <= ex1_rm[2:0]; + vfdsu_ex2_div <= ex1_div; + vfdsu_ex2_sqrt <= ex1_sqrt; + vfdsu_ex2_double <= ex1_double; + vfdsu_ex2_single <= ex1_single; + vfdsu_ex2_half <= ex1_half; + vfdsu_ex2_bfloat <= ex1_bfloat; + end + else + begin + vfdsu_ex2_result_zero <= vfdsu_ex2_result_zero; + vfdsu_ex2_result_qnan <= vfdsu_ex2_result_qnan; + vfdsu_ex2_result_inf <= vfdsu_ex2_result_inf; + vfdsu_ex2_result_sign <= vfdsu_ex2_result_sign; + vfdsu_ex2_op0_norm <= vfdsu_ex2_op0_norm; + vfdsu_ex2_op1_norm <= vfdsu_ex2_op1_norm; + vfdsu_ex2_expnt_add0[12:0] <= vfdsu_ex2_expnt_add0[12:0]; + vfdsu_ex2_expnt_add1[12:0] <= vfdsu_ex2_expnt_add1[12:0]; + vfdsu_ex2_nv <= vfdsu_ex2_nv; + vfdsu_ex2_dz <= vfdsu_ex2_dz; + vfdsu_ex2_srt_skip <= vfdsu_ex2_srt_skip; + vfdsu_ex2_of_rm_lfn <= vfdsu_ex2_of_rm_lfn; + vfdsu_ex2_qnan_sign <= vfdsu_ex2_qnan_sign; + vfdsu_ex2_qnan_f[51:0] <= vfdsu_ex2_qnan_f[51:0]; + vfdsu_ex2_rm[2:0] <= vfdsu_ex2_rm[2:0]; + vfdsu_ex2_div <= vfdsu_ex2_div; + vfdsu_ex2_sqrt <= vfdsu_ex2_sqrt; + vfdsu_ex2_double <= vfdsu_ex2_double; + vfdsu_ex2_single <= vfdsu_ex2_single; + vfdsu_ex2_half <= vfdsu_ex2_half; + vfdsu_ex2_bfloat <= vfdsu_ex2_bfloat; + end +end +// &Force("output","vfdsu_ex2_op0_norm"); @480 +// &Force("output","vfdsu_ex2_op1_norm"); @481 +// &Force("output","vfdsu_ex2_dz"); @482 +// &Force("output","vfdsu_ex2_nv"); @483 +// &Force("output","vfdsu_ex2_srt_skip"); @484 +// &Force("output","vfdsu_ex2_of_rm_lfn"); @485 +// &Force("output","vfdsu_ex2_result_inf"); @486 +// &Force("output","vfdsu_ex2_result_qnan"); @487 +// &Force("output","vfdsu_ex2_result_zero"); @488 +// //&Force("output","vfdsu_ex2_expnt_rst"); @489 +// &Force("output","vfdsu_ex2_result_sign"); @490 +// &Force("output","vfdsu_ex2_qnan_f"); @491 +// &Force("output","vfdsu_ex2_qnan_sign"); @492 +// &Force("output","vfdsu_ex2_rm"); @493 +// &Force("output","vfdsu_ex2_div"); @494 +// &Force("output","vfdsu_ex2_sqrt"); @495 +// &Force("output","vfdsu_ex2_double"); @496 +// &Force("output","vfdsu_ex2_single"); @497 +// &Force("output","vfdsu_ex2_expnt_add0"); @498 +// &Force("output","vfdsu_ex2_expnt_add1"); @499 + +// &ModuleEnd; @501 +endmodule -// ----- 8< ----- FILE "./pa_fdsu_round_single.v" ----- 8< ----- +// ----- 8< ----- FILE "./ct_vfdsu_round.v" ----- 8< ----- -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -23948,534 +28744,1152 @@ See the License for the specific language governing permissions and limitations under the License. */ -// &ModuleBeg; @23 -module pa_fdsu_round_single( - cp0_fpu_icg_en, +// &ModuleBeg; @22 +module ct_vfdsu_round( + cp0_vfpu_icg_en, cp0_yy_clk_en, - ex3_expnt_adjust_result, - ex3_frac_final_rst, + cpurst_b, ex3_pipedown, - ex3_rslt_denorm, - fdsu_ex3_id_srt_skip, - fdsu_ex3_rem_sign, - fdsu_ex3_rem_zero, - fdsu_ex3_result_denorm_round_add_num, - fdsu_ex4_denorm_to_tiny_frac, - fdsu_ex4_nx, - fdsu_ex4_potnt_norm, - fdsu_ex4_result_nor, - fdsu_yy_expnt_rst, - fdsu_yy_result_inf, - fdsu_yy_result_lfn, - fdsu_yy_result_sign, - fdsu_yy_rm, - fdsu_yy_rslt_denorm, forever_cpuclk, pad_yy_icg_scan_en, - total_qt_rt_30 + total_qt_rt_58, + vfdsu_ex2_of_rm_lfn, + vfdsu_ex3_doub_expnt_rst, + vfdsu_ex3_double, + vfdsu_ex3_dz, + vfdsu_ex3_half_expnt_rst, + vfdsu_ex3_bfloat_expnt_rst, + vfdsu_ex3_id_srt_skip, + vfdsu_ex3_nv, + vfdsu_ex3_of, + vfdsu_ex3_potnt_of, + vfdsu_ex3_potnt_uf, + vfdsu_ex3_qnan_f, + vfdsu_ex3_qnan_sign, + vfdsu_ex3_rem_sign, + vfdsu_ex3_rem_zero, + vfdsu_ex3_result_denorm_round_add_num, + vfdsu_ex3_result_inf, + vfdsu_ex3_result_lfn, + vfdsu_ex3_result_qnan, + vfdsu_ex3_result_sign, + vfdsu_ex3_result_zero, + vfdsu_ex3_rm, + vfdsu_ex3_rslt_denorm, + vfdsu_ex3_sing_expnt_rst, + vfdsu_ex3_single, + vfdsu_ex3_half, + vfdsu_ex3_bfloat, + vfdsu_ex3_uf, + vfdsu_ex4_denorm_to_tiny_frac, + vfdsu_ex4_double, + vfdsu_ex4_dz, + vfdsu_ex4_expnt_rst, + vfdsu_ex4_frac, + vfdsu_ex4_nv, + vfdsu_ex4_nx, + vfdsu_ex4_of, + vfdsu_ex4_of_rst_lfn, + vfdsu_ex4_potnt_norm, + vfdsu_ex4_potnt_of, + vfdsu_ex4_potnt_uf, + vfdsu_ex4_qnan_f, + vfdsu_ex4_qnan_sign, + vfdsu_ex4_result_inf, + vfdsu_ex4_result_lfn, + vfdsu_ex4_result_nor, + vfdsu_ex4_result_qnan, + vfdsu_ex4_result_sign, + vfdsu_ex4_result_zero, + vfdsu_ex4_rslt_denorm, + vfdsu_ex4_single, + vfdsu_ex4_half, + vfdsu_ex4_bfloat, + vfdsu_ex4_uf ); -// &Ports; @24 -input cp0_fpu_icg_en; -input cp0_yy_clk_en; -input ex3_pipedown; -input fdsu_ex3_id_srt_skip; -input fdsu_ex3_rem_sign; -input fdsu_ex3_rem_zero; -input [23:0] fdsu_ex3_result_denorm_round_add_num; -input [9 :0] fdsu_yy_expnt_rst; -input fdsu_yy_result_inf; -input fdsu_yy_result_lfn; -input fdsu_yy_result_sign; -input [2 :0] fdsu_yy_rm; -input fdsu_yy_rslt_denorm; -input forever_cpuclk; -input pad_yy_icg_scan_en; -input [29:0] total_qt_rt_30; -output [9 :0] ex3_expnt_adjust_result; -output [25:0] ex3_frac_final_rst; -output ex3_rslt_denorm; -output fdsu_ex4_denorm_to_tiny_frac; -output fdsu_ex4_nx; -output [1 :0] fdsu_ex4_potnt_norm; -output fdsu_ex4_result_nor; +// &Ports; @23 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input ex3_pipedown; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input [57:0] total_qt_rt_58; +input vfdsu_ex2_of_rm_lfn; +input [12:0] vfdsu_ex3_doub_expnt_rst; +input vfdsu_ex3_double; +input vfdsu_ex3_dz; +input [12:0] vfdsu_ex3_half_expnt_rst; +input [12:0] vfdsu_ex3_bfloat_expnt_rst; +input vfdsu_ex3_id_srt_skip; +input vfdsu_ex3_nv; +input vfdsu_ex3_of; +input vfdsu_ex3_potnt_of; +input vfdsu_ex3_potnt_uf; +input [51:0] vfdsu_ex3_qnan_f; +input vfdsu_ex3_qnan_sign; +input vfdsu_ex3_rem_sign; +input vfdsu_ex3_rem_zero; +input [52:0] vfdsu_ex3_result_denorm_round_add_num; +input vfdsu_ex3_result_inf; +input vfdsu_ex3_result_lfn; +input vfdsu_ex3_result_qnan; +input vfdsu_ex3_result_sign; +input vfdsu_ex3_result_zero; +input [2 :0] vfdsu_ex3_rm; +input vfdsu_ex3_rslt_denorm; +input [8 :0] vfdsu_ex3_sing_expnt_rst; +input vfdsu_ex3_single; +input vfdsu_ex3_half; +input vfdsu_ex3_bfloat; +input vfdsu_ex3_uf; +output vfdsu_ex4_denorm_to_tiny_frac; +output vfdsu_ex4_double; +output vfdsu_ex4_dz; +output [12:0] vfdsu_ex4_expnt_rst; +output [54:0] vfdsu_ex4_frac; +output vfdsu_ex4_nv; +output vfdsu_ex4_nx; +output vfdsu_ex4_of; +output vfdsu_ex4_of_rst_lfn; +output [1 :0] vfdsu_ex4_potnt_norm; +output vfdsu_ex4_potnt_of; +output vfdsu_ex4_potnt_uf; +output [51:0] vfdsu_ex4_qnan_f; +output vfdsu_ex4_qnan_sign; +output vfdsu_ex4_result_inf; +output vfdsu_ex4_result_lfn; +output vfdsu_ex4_result_nor; +output vfdsu_ex4_result_qnan; +output vfdsu_ex4_result_sign; +output vfdsu_ex4_result_zero; +output vfdsu_ex4_rslt_denorm; +output vfdsu_ex4_single; +output vfdsu_ex4_half; +output vfdsu_ex4_bfloat; +output vfdsu_ex4_uf; + +// &Regs; @24 +reg denorm_to_tiny_frac; +reg double_denorm_lst_frac; +reg [54:0] frac_add1_op1; +reg frac_add_1; +reg frac_orig; +reg [54:0] frac_sub1_op1; +reg frac_sub_1; +reg half_denorm_lst_frac; +reg bfloat_denorm_lst_frac; +reg [56:0] qt_result_double_denorm_for_round; +reg [13:0] qt_result_half_denorm_for_round; +reg [10:0] qt_result_bfloat_denorm_for_round; +reg [27:0] qt_result_single_denorm_for_round; +reg single_denorm_lst_frac; +reg vfdsu_ex4_denorm_to_tiny_frac; +reg vfdsu_ex4_double; +reg vfdsu_ex4_dz; +reg [12:0] vfdsu_ex4_expnt_rst; +reg [54:0] vfdsu_ex4_frac; +reg vfdsu_ex4_nv; +reg vfdsu_ex4_nx; +reg vfdsu_ex4_of; +reg vfdsu_ex4_of_rst_lfn; +reg [1 :0] vfdsu_ex4_potnt_norm; +reg vfdsu_ex4_potnt_of; +reg vfdsu_ex4_potnt_uf; +reg [51:0] vfdsu_ex4_qnan_f; +reg vfdsu_ex4_qnan_sign; +reg vfdsu_ex4_result_inf; +reg vfdsu_ex4_result_lfn; +reg vfdsu_ex4_result_nor; +reg vfdsu_ex4_result_qnan; +reg vfdsu_ex4_result_sign; +reg vfdsu_ex4_result_zero; +reg vfdsu_ex4_rslt_denorm; +reg vfdsu_ex4_single; +reg vfdsu_ex4_half; +reg vfdsu_ex4_bfloat; +reg vfdsu_ex4_uf; + +// &Wires; @25 +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire ex3_denorm_eq; +wire ex3_denorm_gr; +wire ex3_denorm_lst_frac; +wire ex3_denorm_nx; +wire ex3_denorm_plus; +wire ex3_denorm_potnt_norm; +wire ex3_denorm_zero; +wire ex3_doub_denorm_plus; +wire ex3_doub_denorm_potnt_norm; +wire ex3_doub_eq; +wire ex3_doub_gr; +wire ex3_doub_rst_eq_1; +wire ex3_doub_zero; +wire ex3_double_denorm_eq; +wire ex3_double_denorm_gr; +wire ex3_double_denorm_zero; +wire ex3_double_low_not_zero; +wire [12:0] ex3_expnt_adjst; +wire [12:0] ex3_expnt_adjust_result; +wire ex3_half_denorm_eq; +wire ex3_half_denorm_gr; +wire ex3_half_denorm_plus; +wire ex3_half_denorm_potnt_norm; +wire ex3_half_denorm_zero; +wire ex3_half_eq; +wire ex3_half_gr; +wire ex3_half_low_not_zero; +wire ex3_half_rst_eq_1; +wire ex3_half_zero; +wire ex3_bfloat_denorm_eq; +wire ex3_bfloat_denorm_gr; +wire ex3_bfloat_denorm_plus; +wire ex3_bfloat_denorm_potnt_norm; +wire ex3_bfloat_denorm_zero; +wire ex3_bfloat_eq; +wire ex3_bfloat_gr; +wire ex3_bfloat_low_not_zero; +wire ex3_bfloat_rst_eq_1; +wire ex3_bfloat_zero; +wire ex3_nx; +wire ex3_pipe_clk; +wire ex3_pipe_clk_en; +wire ex3_pipedown; +wire [1 :0] ex3_potnt_norm; +wire ex3_qt_doub_lo2_not0; +wire ex3_qt_doub_lo3_not0; +wire ex3_qt_eq; +wire ex3_qt_gr; +wire ex3_qt_half_lo2_not0; +wire ex3_qt_half_lo3_not0; +wire ex3_qt_bfloat_lo2_not0; +wire ex3_qt_bfloat_lo3_not0; +wire ex3_qt_sing_lo3_not0; +wire ex3_qt_sing_lo4_not0; +wire ex3_qt_zero; +wire ex3_rslt_denorm; +wire ex3_rst_eq_1; +wire ex3_rst_nor; +wire ex3_sing_denorm_plus; +wire ex3_sing_denorm_potnt_norm; +wire ex3_sing_eq; +wire ex3_sing_gr; +wire ex3_sing_rst_eq_1; +wire ex3_sing_zero; +wire ex3_single_denorm_eq; +wire ex3_single_denorm_gr; +wire ex3_single_denorm_zero; +wire ex3_single_low_not_zero; +wire forever_cpuclk; +wire [54:0] frac_add1_op1_with_denorm; +wire [54:0] frac_add1_rst; +wire frac_denorm_rdn_add_1; +wire frac_denorm_rdn_sub_1; +wire frac_denorm_rmm_add_1; +wire frac_denorm_rne_add_1; +wire frac_denorm_rtz_sub_1; +wire frac_denorm_rup_add_1; +wire frac_denorm_rup_sub_1; +wire [54:0] frac_final_rst; +wire frac_rdn_add_1; +wire frac_rdn_sub_1; +wire frac_rmm_add_1; +wire frac_rne_add_1; +wire frac_rtz_sub_1; +wire frac_rup_add_1; +wire frac_rup_sub_1; +wire [54:0] frac_sub1_op1_with_denorm; +wire [54:0] frac_sub1_rst; +wire pad_yy_icg_scan_en; +wire [57:0] total_qt_rt_58; +wire vfdsu_ex2_of_rm_lfn; +wire [12:0] vfdsu_ex3_doub_expnt_rst; +wire vfdsu_ex3_double; +wire vfdsu_ex3_dz; +wire [12:0] vfdsu_ex3_expnt_rst; +wire [12:0] vfdsu_ex3_half_expnt_rst; +wire [12:0] vfdsu_ex3_bfloat_expnt_rst; +wire vfdsu_ex3_id_srt_skip; +wire vfdsu_ex3_nv; +wire vfdsu_ex3_of; +wire vfdsu_ex3_potnt_of; +wire vfdsu_ex3_potnt_uf; +wire [51:0] vfdsu_ex3_qnan_f; +wire vfdsu_ex3_qnan_sign; +wire vfdsu_ex3_rem_sign; +wire vfdsu_ex3_rem_zero; +wire [52:0] vfdsu_ex3_result_denorm_round_add_num; +wire vfdsu_ex3_result_inf; +wire vfdsu_ex3_result_lfn; +wire vfdsu_ex3_result_qnan; +wire vfdsu_ex3_result_sign; +wire vfdsu_ex3_result_zero; +wire [2 :0] vfdsu_ex3_rm; +wire vfdsu_ex3_rslt_denorm; +wire [8 :0] vfdsu_ex3_sing_expnt_rst; +wire vfdsu_ex3_single; +wire vfdsu_ex3_half; +wire vfdsu_ex3_bfloat; +wire vfdsu_ex3_uf; -// &Regs; @25 -reg denorm_to_tiny_frac; -reg fdsu_ex4_denorm_to_tiny_frac; -reg fdsu_ex4_nx; -reg [1 :0] fdsu_ex4_potnt_norm; -reg fdsu_ex4_result_nor; -reg [25:0] frac_add1_op1; -reg frac_add_1; -reg frac_orig; -reg [25:0] frac_sub1_op1; -reg frac_sub_1; -reg [27:0] qt_result_single_denorm_for_round; -reg single_denorm_lst_frac; -// &Wires; @26 -wire cp0_fpu_icg_en; -wire cp0_yy_clk_en; -wire ex3_denorm_eq; -wire ex3_denorm_gr; -wire ex3_denorm_lst_frac; -wire ex3_denorm_nx; -wire ex3_denorm_plus; -wire ex3_denorm_potnt_norm; -wire ex3_denorm_zero; -wire [9 :0] ex3_expnt_adjst; -wire [9 :0] ex3_expnt_adjust_result; -wire [25:0] ex3_frac_final_rst; -wire ex3_nx; -wire ex3_pipe_clk; -wire ex3_pipe_clk_en; -wire ex3_pipedown; -wire [1 :0] ex3_potnt_norm; -wire ex3_qt_eq; -wire ex3_qt_gr; -wire ex3_qt_sing_lo3_not0; -wire ex3_qt_sing_lo4_not0; -wire ex3_qt_zero; -wire ex3_rslt_denorm; -wire ex3_rst_eq_1; -wire ex3_rst_nor; -wire ex3_single_denorm_eq; -wire ex3_single_denorm_gr; -wire ex3_single_denorm_zero; -wire ex3_single_low_not_zero; -wire [9 :0] fdsu_ex3_expnt_rst; -wire fdsu_ex3_id_srt_skip; -wire fdsu_ex3_rem_sign; -wire fdsu_ex3_rem_zero; -wire [23:0] fdsu_ex3_result_denorm_round_add_num; -wire fdsu_ex3_result_inf; -wire fdsu_ex3_result_lfn; -wire fdsu_ex3_result_sign; -wire [2 :0] fdsu_ex3_rm; -wire fdsu_ex3_rslt_denorm; -wire [9 :0] fdsu_yy_expnt_rst; -wire fdsu_yy_result_inf; -wire fdsu_yy_result_lfn; -wire fdsu_yy_result_sign; -wire [2 :0] fdsu_yy_rm; -wire fdsu_yy_rslt_denorm; -wire forever_cpuclk; -wire [25:0] frac_add1_op1_with_denorm; -wire [25:0] frac_add1_rst; -wire frac_denorm_rdn_add_1; -wire frac_denorm_rdn_sub_1; -wire frac_denorm_rmm_add_1; -wire frac_denorm_rne_add_1; -wire frac_denorm_rtz_sub_1; -wire frac_denorm_rup_add_1; -wire frac_denorm_rup_sub_1; -wire [25:0] frac_final_rst; -wire frac_rdn_add_1; -wire frac_rdn_sub_1; -wire frac_rmm_add_1; -wire frac_rne_add_1; -wire frac_rtz_sub_1; -wire frac_rup_add_1; -wire frac_rup_sub_1; -wire [25:0] frac_sub1_op1_with_denorm; -wire [25:0] frac_sub1_rst; -wire pad_yy_icg_scan_en; -wire [29:0] total_qt_rt_30; - - -assign fdsu_ex3_result_sign = fdsu_yy_result_sign; -assign fdsu_ex3_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; -assign fdsu_ex3_result_inf = fdsu_yy_result_inf; -assign fdsu_ex3_result_lfn = fdsu_yy_result_lfn; -assign fdsu_ex3_rm[2:0] = fdsu_yy_rm[2:0]; -assign fdsu_ex3_rslt_denorm = fdsu_yy_rslt_denorm; //=======================Round Rule========================= //1/8 <= x < 1/4, 1/2 <= y < 1, => 1/8 < z < 1/2 -//q[29:0] represent the fraction part result of quotient, q[29] for 1/2 -//Thus the first "1" in 30 bit quotient will be in q[28] or q[27] +//q[57:0] represent the fraction part result of quotient, q[57] for 1/2 +//Thus the first "1" in 58 bit quotient will be in q[56] or q[55] +//For Double Float +//29 round to get 58 bit quotient, 52+1 bit as valid result, other for round +//if q[56] is 1, q[56:4] as 1.xxxx valid result, [3:0] for round +//if q[56] is 0, q[55:3] as 1.xxxx valid result, [2:0] for round //For Single Float //15 round to get 30 bit quotient, 23+1 bit as valid result, other for round -//if q[28] is 1, q[28:5] as 1.xxxx valid result, [4:0] for round -//if q[28] is 0, q[27:4] as 1.xxxx valid result, [3:0] for round -// &Force("bus","total_qt_rt_30",29,0); @42 -assign ex3_qt_sing_lo4_not0 = |total_qt_rt_30[3:0]; -assign ex3_qt_sing_lo3_not0 = |total_qt_rt_30[2:0]; +//if q[56] is 1, q[56:33] as 1.xxxx valid result, [32:28] for round +//if q[56] is 0, q[55:32] as 1.xxxx valid result, [31:28] for round +assign ex3_qt_half_lo3_not0 = |total_qt_rt_58[44:42]; +assign ex3_qt_half_lo2_not0 = |total_qt_rt_58[43:42]; +assign ex3_half_gr = total_qt_rt_58[56] + ? total_qt_rt_58[45] && ex3_qt_half_lo3_not0 + : total_qt_rt_58[44] && ex3_qt_half_lo2_not0; +assign ex3_half_eq = (total_qt_rt_58[56]) + ? total_qt_rt_58[45] && !ex3_qt_sing_lo4_not0 + : total_qt_rt_58[44] && !ex3_qt_sing_lo3_not0; +assign ex3_half_zero = (total_qt_rt_58[56]) + ? ~|total_qt_rt_58[45:42] + : ~|total_qt_rt_58[44:42]; +assign ex3_half_rst_eq_1 = total_qt_rt_58[56] && ~|total_qt_rt_58[55:46]; +assign ex3_half_denorm_plus = !total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1ff2); +assign ex3_half_denorm_potnt_norm = total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1ff1); + +assign ex3_qt_bfloat_lo3_not0 = |total_qt_rt_58[47:45]; +assign ex3_qt_bfloat_lo2_not0 = |total_qt_rt_58[46:45]; +assign ex3_bfloat_gr = total_qt_rt_58[56] + ? total_qt_rt_58[48] && ex3_qt_bfloat_lo3_not0 + : total_qt_rt_58[47] && ex3_qt_bfloat_lo2_not0; +assign ex3_bfloat_eq = (total_qt_rt_58[56]) + ? total_qt_rt_58[48] && !ex3_qt_sing_lo4_not0 + : total_qt_rt_58[47] && !ex3_qt_sing_lo3_not0; +assign ex3_bfloat_zero = (total_qt_rt_58[56]) + ? ~|total_qt_rt_58[48:45] + : ~|total_qt_rt_58[47:45]; +assign ex3_bfloat_rst_eq_1 = total_qt_rt_58[56] && ~|total_qt_rt_58[55:49]; +assign ex3_bfloat_denorm_plus = !total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1f82); +assign ex3_bfloat_denorm_potnt_norm = total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1f81); + +assign vfdsu_ex3_expnt_rst[12:0] = vfdsu_ex3_half_expnt_rst[12:0]; +// &Force("bus","total_qt_rt_58",57,0); @54 +assign ex3_qt_doub_lo3_not0 = |total_qt_rt_58[2:0]; +assign ex3_qt_doub_lo2_not0 = |total_qt_rt_58[1:0]; +assign ex3_qt_sing_lo4_not0 = |total_qt_rt_58[31:28]; +assign ex3_qt_sing_lo3_not0 = |total_qt_rt_58[30:28]; //the quotient round bits great than "10000"(ronnd bits 10..0) -assign ex3_qt_gr = (total_qt_rt_30[28]) - ? total_qt_rt_30[4] && ex3_qt_sing_lo4_not0 - : total_qt_rt_30[3] && ex3_qt_sing_lo3_not0; +assign ex3_doub_gr = (total_qt_rt_58[56]) + ? total_qt_rt_58[3] && ex3_qt_doub_lo3_not0 + : total_qt_rt_58[2] && ex3_qt_doub_lo2_not0; +assign ex3_sing_gr = (total_qt_rt_58[56]) + ? total_qt_rt_58[32] && ex3_qt_sing_lo4_not0 + : total_qt_rt_58[31] && ex3_qt_sing_lo3_not0; //the quotient round bits is equal to "10000"(ronnd bits 10..0) -assign ex3_qt_eq = (total_qt_rt_30[28]) - ? total_qt_rt_30[4] && !ex3_qt_sing_lo4_not0 - : total_qt_rt_30[3] && !ex3_qt_sing_lo3_not0; +assign ex3_doub_eq = (total_qt_rt_58[56]) + ? total_qt_rt_58[3] && !ex3_qt_doub_lo3_not0 + : total_qt_rt_58[2] && !ex3_qt_doub_lo2_not0; +assign ex3_sing_eq = (total_qt_rt_58[56]) + ? total_qt_rt_58[32] && !ex3_qt_sing_lo4_not0 + : total_qt_rt_58[31] && !ex3_qt_sing_lo3_not0; //the quotient round bits is zero -assign ex3_qt_zero = (total_qt_rt_30[28]) - ? ~|total_qt_rt_30[4:0] - : ~|total_qt_rt_30[3:0]; +assign ex3_doub_zero = (total_qt_rt_58[56]) + ? ~|total_qt_rt_58[3:0] + : ~|total_qt_rt_58[2:0]; +assign ex3_sing_zero = (total_qt_rt_58[56]) + ? ~|total_qt_rt_58[32:28] + : ~|total_qt_rt_58[31:28]; //quotient is 1.00000..00 need special dealt with in the following -assign ex3_rst_eq_1 = total_qt_rt_30[28] && ~|total_qt_rt_30[27:5]; +assign ex3_doub_rst_eq_1 = total_qt_rt_58[56] && ~|total_qt_rt_58[55:4]; +assign ex3_sing_rst_eq_1 = total_qt_rt_58[56] && ~|total_qt_rt_58[55:33]; // for denormal result, first select the quotation num for rounding // specially for the result e=-126 and e=-1022,the denorm depends on the // MSB of the quotient -assign ex3_denorm_plus = !total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h382); -assign ex3_denorm_potnt_norm = total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h381); -assign ex3_rslt_denorm = ex3_denorm_plus || fdsu_ex3_rslt_denorm; -// &Force("output", "ex3_rslt_denorm"); @66 +assign ex3_doub_denorm_plus = !total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1c02); +assign ex3_sing_denorm_plus = !total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1f82); + +assign ex3_doub_denorm_potnt_norm = total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1c01); +assign ex3_sing_denorm_potnt_norm = total_qt_rt_58[56] && (vfdsu_ex3_expnt_rst[12:0] == 13'h1f81); +assign ex3_rslt_denorm = ex3_denorm_plus || vfdsu_ex3_rslt_denorm; +assign ex3_denorm_potnt_norm = vfdsu_ex3_double ? ex3_doub_denorm_potnt_norm : + vfdsu_ex3_single ? ex3_sing_denorm_potnt_norm : + vfdsu_ex3_half ? ex3_half_denorm_potnt_norm + : ex3_bfloat_denorm_potnt_norm; +assign ex3_rst_eq_1 = (vfdsu_ex3_double)? ex3_doub_rst_eq_1 : + vfdsu_ex3_single ? ex3_sing_rst_eq_1 : + vfdsu_ex3_half ? ex3_half_rst_eq_1 : ex3_bfloat_rst_eq_1; +assign ex3_qt_eq = (vfdsu_ex3_double)? ex3_doub_eq : + vfdsu_ex3_single ? ex3_sing_eq : + vfdsu_ex3_half ? ex3_half_eq : ex3_bfloat_eq; +assign ex3_qt_gr = (vfdsu_ex3_double)? ex3_doub_gr : + vfdsu_ex3_single ? ex3_sing_gr : + vfdsu_ex3_half ? ex3_half_gr : ex3_bfloat_gr; +assign ex3_qt_zero = (vfdsu_ex3_double)? ex3_doub_zero : + vfdsu_ex3_single ? ex3_sing_zero : + vfdsu_ex3_half ? ex3_half_zero : ex3_bfloat_zero; +assign ex3_denorm_plus = (vfdsu_ex3_double) ? ex3_doub_denorm_plus + : vfdsu_ex3_single ? ex3_sing_denorm_plus + : vfdsu_ex3_half ? ex3_half_denorm_plus : ex3_bfloat_denorm_plus; + +// &CombBeg; @108 +always @( vfdsu_ex3_doub_expnt_rst[12:0] + or total_qt_rt_58[56:0]) +begin +case(vfdsu_ex3_doub_expnt_rst[12:0]) + 13'h1c02:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[3:0], 53'b0}; + double_denorm_lst_frac = total_qt_rt_58[4]; + end//-1022 1 + 13'h1c01:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[4:0], 52'b0}; //-1023 0 + double_denorm_lst_frac = total_qt_rt_58[5]; + end//-1022 1 + 13'h1c00:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[5:0], 51'b0}; //-1024 -1 + double_denorm_lst_frac = total_qt_rt_58[6]; + end//-1022 1 + 13'h1bff:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[6:0], 50'b0}; //-1025 -2 + double_denorm_lst_frac = total_qt_rt_58[7]; + end//-1022 1 + 13'h1bfe:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[7:0], 49'b0}; //-1026 -3 + double_denorm_lst_frac = total_qt_rt_58[8]; + end//-1022 1 + 13'h1bfd:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[8:0], 48'b0}; //-1027 -4 + double_denorm_lst_frac = total_qt_rt_58[9]; + end//-1022 1 + 13'h1bfc:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[9:0], 47'b0}; //-1028 -5 + double_denorm_lst_frac = total_qt_rt_58[10]; + end//-1022 1 + 13'h1bfb:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[10:0],46'b0}; //-1029 -6 + double_denorm_lst_frac = total_qt_rt_58[11]; + end//-1022 1 + 13'h1bfa:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[11:0],45'b0}; //-1030 -7 + double_denorm_lst_frac = total_qt_rt_58[12]; + end//-1022 1 + 13'h1bf9:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[12:0],44'b0}; //-1031 -8 + double_denorm_lst_frac = total_qt_rt_58[13]; + end//-1022 1 + 13'h1bf8:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[13:0],43'b0}; //-1032 -9 + double_denorm_lst_frac = total_qt_rt_58[14]; + end//-1022 1 + 13'h1bf7:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[14:0],42'b0}; //-1033 -10 + double_denorm_lst_frac = total_qt_rt_58[15]; + end//-1022 1 + 13'h1bf6:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[15:0],41'b0}; //-1034 -11 + double_denorm_lst_frac = total_qt_rt_58[16]; + end//-1022 1 + 13'h1bf5:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[16:0],40'b0}; //-1035 -12 + double_denorm_lst_frac = total_qt_rt_58[17]; + end//-1022 1 + 13'h1bf4:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[17:0],39'b0}; //-1036 -13 + double_denorm_lst_frac = total_qt_rt_58[18]; + end//-1022 1 + 13'h1bf3:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[18:0],38'b0}; // -1037 + double_denorm_lst_frac = total_qt_rt_58[19]; + end//-1022 1 + 13'h1bf2:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[19:0],37'b0}; //-1038 + double_denorm_lst_frac = total_qt_rt_58[20]; + end//-1022 1 + 13'h1bf1:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[20:0],36'b0}; //-1039 + double_denorm_lst_frac = total_qt_rt_58[21]; + end//-1022 1 + 13'h1bf0:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[21:0],35'b0}; //-1040 + double_denorm_lst_frac = total_qt_rt_58[22]; + end//-1022 1 + 13'h1bef:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[22:0],34'b0}; //-1041 + double_denorm_lst_frac = total_qt_rt_58[23]; + end//-1022 1 + 13'h1bee:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[23:0],33'b0}; //-1042 + double_denorm_lst_frac = total_qt_rt_58[24]; + end//-1022 1 + 13'h1bed:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[24:0],32'b0}; //-1043 + double_denorm_lst_frac = total_qt_rt_58[25]; + end//-1022 1 + 13'h1bec:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[25:0],31'b0}; //-1044 + double_denorm_lst_frac = total_qt_rt_58[26]; + end//-1022 1 + 13'h1beb:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[26:0],30'b0}; //-1045 + double_denorm_lst_frac = total_qt_rt_58[27]; + end//-1022 1 + 13'h1bea:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[27:0],29'b0}; //-1046 + double_denorm_lst_frac = total_qt_rt_58[28]; + end//-1022 1 + 13'h1be9:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[28:0],28'b0}; //-1047 + double_denorm_lst_frac = total_qt_rt_58[29]; + end//-1022 1 + 13'h1be8:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[29:0],27'b0}; //-1048 + double_denorm_lst_frac = total_qt_rt_58[30]; + end//-1022 1 + 13'h1be7:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[30:0],26'b0}; //-1049 + double_denorm_lst_frac = total_qt_rt_58[31]; + end//-1022 1 + 13'h1be6:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[31:0],25'b0}; //-1050 + double_denorm_lst_frac = total_qt_rt_58[32]; + end//-1022 1 + 13'h1be5:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[32:0],24'b0}; //-1056 + double_denorm_lst_frac = total_qt_rt_58[33]; + end//-1022 1 + 13'h1be4:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[33:0],23'b0}; //-1052 + double_denorm_lst_frac = total_qt_rt_58[34]; + end//-1022 1 + 13'h1be3:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[34:0],22'b0}; //-1053 + double_denorm_lst_frac = total_qt_rt_58[35]; + end//-1022 1 + 13'h1be2:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[35:0],21'b0}; //-1054 + double_denorm_lst_frac = total_qt_rt_58[36]; + end//-1022 1 + 13'h1be1:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[36:0],20'b0}; //-1055 + double_denorm_lst_frac = total_qt_rt_58[37]; + end//-1022 1 + 13'h1be0:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[37:0],19'b0}; //-1056 + double_denorm_lst_frac = total_qt_rt_58[38]; + end//-1022 1 + 13'h1bdf:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[38:0],18'b0}; //-1057 + double_denorm_lst_frac = total_qt_rt_58[39]; + end//-1022 1 + 13'h1bde:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[39:0],17'b0}; //-1058 + double_denorm_lst_frac = total_qt_rt_58[40]; + end//-1022 1 + 13'h1bdd:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[40:0],16'b0}; //-1059 + double_denorm_lst_frac = total_qt_rt_58[41]; + end//-1022 1 + 13'h1bdc:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[41:0],15'b0}; //-1060 + double_denorm_lst_frac = total_qt_rt_58[42]; + end//-1022 1 + 13'h1bdb:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[42:0],14'b0}; //-1061 + double_denorm_lst_frac = total_qt_rt_58[43]; + end//-1022 1 + 13'h1bda:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[43:0],13'b0}; //-1062 + double_denorm_lst_frac = total_qt_rt_58[44]; + end//-1022 1 + 13'h1bd9:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[44:0],12'b0}; //-1063 + double_denorm_lst_frac = total_qt_rt_58[45]; + end//-1022 1 + 13'h1bd8:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[45:0],11'b0}; //-1064 + double_denorm_lst_frac = total_qt_rt_58[46]; + end//-1022 1 + 13'h1bd7:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[46:0],10'b0}; //-1065 + double_denorm_lst_frac = total_qt_rt_58[47]; + end//-1022 1 + 13'h1bd6:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[47:0],9'b0}; //-1066 + double_denorm_lst_frac = total_qt_rt_58[48]; + end//-1022 1 + 13'h1bd5:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[48:0],8'b0}; //-1067 + double_denorm_lst_frac = total_qt_rt_58[49]; + end//-1022 1 + 13'h1bd4:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[49:0],7'b0}; //-1068 + double_denorm_lst_frac = total_qt_rt_58[50]; + end//-1022 1 + 13'h1bd3:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[50:0],6'b0}; //-1069 + double_denorm_lst_frac = total_qt_rt_58[51]; + end//-1022 1 + 13'h1bd2:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[51:0],5'b0}; //-1070 + double_denorm_lst_frac = total_qt_rt_58[52]; + end//-1022 1 + 13'h1bd1:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[52:0],4'b0}; //-1071 + double_denorm_lst_frac = total_qt_rt_58[53]; + end//-1022 1 + 13'h1bd0:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[53:0],3'b0}; //-1072 + double_denorm_lst_frac = total_qt_rt_58[54]; + end//-1022 1 + 13'h1bcf:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[54:0],2'b0}; //-1073 + double_denorm_lst_frac = total_qt_rt_58[55]; + end//-1022 1 + 13'h1bce:begin qt_result_double_denorm_for_round[56:0] = {total_qt_rt_58[55:0],1'b0}; + double_denorm_lst_frac = total_qt_rt_58[56]; + end//-1022 1 + default:begin qt_result_double_denorm_for_round[56:0] = total_qt_rt_58[56:0]; + double_denorm_lst_frac = 1'b0; + end//-1022 1 +endcase +// &CombEnd; @274 +end //denomal result, check for rounding further optimization can be done in //future -// &CombBeg; @70 -always @( total_qt_rt_30[28:0] - or fdsu_ex3_expnt_rst[9:0]) +assign ex3_double_denorm_eq = qt_result_double_denorm_for_round[56] + && !ex3_double_low_not_zero; +assign ex3_double_low_not_zero = |qt_result_double_denorm_for_round[55:0]; +assign ex3_double_denorm_gr = qt_result_double_denorm_for_round[56] + && ex3_double_low_not_zero; +assign ex3_double_denorm_zero = !qt_result_double_denorm_for_round[56] + && !ex3_double_low_not_zero; + +// &CombBeg; @285 +always @( vfdsu_ex3_sing_expnt_rst[8:0] + or total_qt_rt_58[56:28]) begin -case(fdsu_ex3_expnt_rst[9:0]) - 10'h382:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[4:0],23'b0}; //-126 1 - single_denorm_lst_frac = total_qt_rt_30[5]; +case(vfdsu_ex3_sing_expnt_rst[8:0]) + 9'h182:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[32:28],23'b0}; //-126 1 + single_denorm_lst_frac = total_qt_rt_58[33]; end//-1022 1 - 10'h381:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[5:0],22'b0}; //-127 0 - single_denorm_lst_frac = total_qt_rt_30[6]; + 9'h181:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[33:28],22'b0}; //-127 0 + single_denorm_lst_frac = total_qt_rt_58[34]; end//-1022 1 - 10'h380:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[6:0],21'b0}; //-128 -1 - single_denorm_lst_frac = total_qt_rt_30[7]; + 9'h180:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[34:28],21'b0}; //-128 -1 + single_denorm_lst_frac = total_qt_rt_58[35]; end//-1022 1 - 10'h37f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[7:0],20'b0}; //-129 -2 - single_denorm_lst_frac = total_qt_rt_30[8]; + 9'h17f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[35:28],20'b0}; //-129 -2 + single_denorm_lst_frac = total_qt_rt_58[36]; end//-1022 1 - 10'h37e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[8:0],19'b0}; //-130 -3 - single_denorm_lst_frac = total_qt_rt_30[9]; + 9'h17e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[36:28],19'b0}; //-90 -3 + single_denorm_lst_frac = total_qt_rt_58[37]; end//-1022 1 - 10'h37d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[9:0],18'b0}; //-131 -4 - single_denorm_lst_frac = total_qt_rt_30[10]; + 9'h17d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[37:28],18'b0}; //-91 -4 + single_denorm_lst_frac = total_qt_rt_58[38]; end//-1022 1 - 10'h37c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[10:0],17'b0}; //-132 -5 - single_denorm_lst_frac = total_qt_rt_30[11]; + 9'h17c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[38:28],17'b0}; //-92 -5 + single_denorm_lst_frac = total_qt_rt_58[39]; end//-1022 1 - 10'h37b:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[11:0],16'b0}; //-133 -6 - single_denorm_lst_frac = total_qt_rt_30[12]; + 9'h17b:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[39:28],16'b0}; //-93 -6 + single_denorm_lst_frac = total_qt_rt_58[40]; end//-1022 1 - 10'h37a:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[12:0],15'b0}; //-134 -7 - single_denorm_lst_frac = total_qt_rt_30[13]; + 9'h17a:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[40:28],15'b0}; //-94 -7 + single_denorm_lst_frac = total_qt_rt_58[41]; end//-1022 1 - 10'h379:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[13:0],14'b0}; //-135 -8 - single_denorm_lst_frac = total_qt_rt_30[14]; + 9'h179:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[41:28],14'b0}; //-95 -8 + single_denorm_lst_frac = total_qt_rt_58[42]; end//-1022 1 - 10'h378:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[14:0],13'b0}; //-136 -9 - single_denorm_lst_frac = total_qt_rt_30[15]; + 9'h178:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[42:28],13'b0}; //-96 -9 + single_denorm_lst_frac = total_qt_rt_58[43]; end//-1022 1 - 10'h377:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[15:0],12'b0}; //-137 -10 - single_denorm_lst_frac = total_qt_rt_30[16]; + 9'h177:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[43:28],12'b0}; //-97 -10 + single_denorm_lst_frac = total_qt_rt_58[44]; end//-1022 1 - 10'h376:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[16:0],11'b0}; //-138 -11 - single_denorm_lst_frac = total_qt_rt_30[17]; + 9'h176:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[44:28],11'b0}; //-98 -11 + single_denorm_lst_frac = total_qt_rt_58[45]; end//-1022 1 - 10'h375:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[17:0],10'b0}; //-139 -12 - single_denorm_lst_frac = total_qt_rt_30[18]; + 9'h175:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[45:28],10'b0}; //-99 -12 + single_denorm_lst_frac = total_qt_rt_58[46]; end//-1022 1 - 10'h374:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[18:0],9'b0}; //-140 -13 - single_denorm_lst_frac = total_qt_rt_30[19]; + 9'h174:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[46:28],9'b0}; //-140 -9 + single_denorm_lst_frac = total_qt_rt_58[47]; end//-1022 1 - 10'h373:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[19:0],8'b0}; // -141 - single_denorm_lst_frac = total_qt_rt_30[20]; + 9'h173:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[47:28],8'b0}; // -141 + single_denorm_lst_frac = total_qt_rt_58[48]; end//-1022 1 - 10'h372:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[20:0],7'b0};//-142 - single_denorm_lst_frac = total_qt_rt_30[21]; + 9'h172:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[48:28],7'b0};//-142 + single_denorm_lst_frac = total_qt_rt_58[49]; end//-1022 1 - 10'h371:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[21:0],6'b0};//-143 - single_denorm_lst_frac = total_qt_rt_30[22]; + 9'h171:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[49:28],6'b0};//-143 + single_denorm_lst_frac = total_qt_rt_58[50]; end//-1022 1 - 10'h370:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[22:0],5'b0}; //-144 - single_denorm_lst_frac = total_qt_rt_30[23]; + 9'h170:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[50:28],5'b0}; //-144 + single_denorm_lst_frac = total_qt_rt_58[51]; end//-1022 1 - 10'h36f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[23:0],4'b0}; //-145 - single_denorm_lst_frac = total_qt_rt_30[24]; + 9'h16f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[51:28],4'b0}; //-145 + single_denorm_lst_frac = total_qt_rt_58[52]; end//-1022 1 - 10'h36e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[24:0],3'b0}; //-146 - single_denorm_lst_frac = total_qt_rt_30[25]; + 9'h16e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[52:28],3'b0}; //-146 + single_denorm_lst_frac = total_qt_rt_58[53]; end//-1022 1 - 10'h36d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[25:0],2'b0}; //-147 - single_denorm_lst_frac = total_qt_rt_30[26]; + 9'h16d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[53:28],2'b0}; //-147 + single_denorm_lst_frac = total_qt_rt_58[54]; end//-1022 1 - 10'h36c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[26:0],1'b0}; //-148 - single_denorm_lst_frac = total_qt_rt_30[27]; + 9'h16c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[54:28],1'b0}; //-148 + single_denorm_lst_frac = total_qt_rt_58[55]; end//-1022 1 - 10'h36b: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[27:0]}; - single_denorm_lst_frac = total_qt_rt_30[28] ; + 9'h16b: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[55:28]}; + single_denorm_lst_frac = total_qt_rt_58[56] ; end//-1022 1 - default: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[28:1]}; + default: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_58[56:29]}; single_denorm_lst_frac = 1'b0; end//-1022 1 endcase -// &CombEnd; @148 +// &CombEnd; @363 end -//rounding evaluation for single denormalize number -assign ex3_single_denorm_eq = qt_result_single_denorm_for_round[27] +//rounding evaluation for single denormalize number +assign ex3_single_denorm_eq = qt_result_single_denorm_for_round[27] && !ex3_single_low_not_zero; assign ex3_single_low_not_zero = |qt_result_single_denorm_for_round[26:0]; -assign ex3_single_denorm_gr = qt_result_single_denorm_for_round[27] +assign ex3_single_denorm_gr = qt_result_single_denorm_for_round[27] && ex3_single_low_not_zero; -assign ex3_single_denorm_zero = !qt_result_single_denorm_for_round[27] +assign ex3_single_denorm_zero = !qt_result_single_denorm_for_round[27] && !ex3_single_low_not_zero; - -//rounding check fo denormalize result -assign ex3_denorm_eq = ex3_single_denorm_eq; -assign ex3_denorm_gr = ex3_single_denorm_gr; -assign ex3_denorm_zero = ex3_single_denorm_zero; -assign ex3_denorm_lst_frac = single_denorm_lst_frac; +// &CombBeg; @372 +always @( total_qt_rt_58[56:42] + or vfdsu_ex3_half_expnt_rst[12:0]) +begin +case(vfdsu_ex3_half_expnt_rst[12:0]) + 13'h1ff2:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[45:42],10'b0}; //-14 1 + half_denorm_lst_frac = total_qt_rt_58[46]; + end//-1022 1 + 13'h1ff1:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[46:42],9'b0}; //-15 0 + half_denorm_lst_frac = total_qt_rt_58[47]; + end//-1022 1 + 13'h1ff0:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[47:42],8'b0}; //-16 -1 + half_denorm_lst_frac = total_qt_rt_58[48]; + end//-1022 1 + 13'h1fef:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[48:42],7'b0}; //-17 -2 + half_denorm_lst_frac = total_qt_rt_58[49]; + end//-1022 1 + 13'h1fee:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[49:42],6'b0}; //-18 -3 + half_denorm_lst_frac = total_qt_rt_58[50]; + end//-1022 1 + 13'h1fed:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[50:42],5'b0}; //-19 -4 + half_denorm_lst_frac = total_qt_rt_58[51]; + end//-1022 1 + 13'h1fec:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[51:42],4'b0}; //-20 -5 + half_denorm_lst_frac = total_qt_rt_58[52]; + end//-1022 1 + 13'h1feb:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[52:42],3'b0}; //-21 -6 + half_denorm_lst_frac = total_qt_rt_58[53]; + end//-1022 1 + 13'h1fea:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[53:42],2'b0}; //-22 -7 + half_denorm_lst_frac = total_qt_rt_58[54]; + end//-1022 1 + 13'h1fe9:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[54:42],1'b0}; //-23 -8 + half_denorm_lst_frac = total_qt_rt_58[55]; + end//-1022 1 + 13'h1fe8:begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[55:42]}; //-24 -9 + half_denorm_lst_frac = total_qt_rt_58[56]; + end//-1022 1 + default: begin qt_result_half_denorm_for_round[13:0] = {total_qt_rt_58[56:43]}; + half_denorm_lst_frac = 1'b0; + end//-1022 1 +endcase +// &CombEnd; @411 +end +//rounding evaluation for single denormalize number +assign ex3_half_denorm_eq = qt_result_half_denorm_for_round[13] + && !ex3_half_low_not_zero; +assign ex3_half_low_not_zero = |qt_result_half_denorm_for_round[12:0]; +assign ex3_half_denorm_gr = qt_result_half_denorm_for_round[13] + && ex3_half_low_not_zero; +assign ex3_half_denorm_zero = !qt_result_half_denorm_for_round[13] + && !ex3_half_low_not_zero; + +always @( vfdsu_ex3_bfloat_expnt_rst[8:0] + or total_qt_rt_58[56:45]) +begin +case(vfdsu_ex3_bfloat_expnt_rst[8:0]) + 9'h182:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[48:45],7'b0}; //-126 1 + bfloat_denorm_lst_frac = total_qt_rt_58[49]; + end//-1022 1 + 9'h181:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[49:45],6'b0}; //-127 0 + bfloat_denorm_lst_frac = total_qt_rt_58[50]; + end//-1022 1 + 9'h180:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[50:45],5'b0}; //-128 -1 + bfloat_denorm_lst_frac = total_qt_rt_58[51]; + end//-1022 1 + 9'h17f:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[51:45],4'b0}; //-129 -2 + bfloat_denorm_lst_frac = total_qt_rt_58[52]; + end//-1022 1 + 9'h17e:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[52:45],3'b0}; //-90 -3 + bfloat_denorm_lst_frac = total_qt_rt_58[53]; + end//-1022 1 + 9'h17d:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[53:45],2'b0}; //-91 -4 + bfloat_denorm_lst_frac = total_qt_rt_58[54]; + end//-1022 1 + 9'h17c:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[54:45],1'b0}; //-92 -5 + bfloat_denorm_lst_frac = total_qt_rt_58[55]; + end//-1022 1 + 9'h17b:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[55:45]}; //-93 -6 + bfloat_denorm_lst_frac = total_qt_rt_58[56]; + end//-1022 1 + 9'h17a:begin qt_result_bfloat_denorm_for_round[10:0] = {total_qt_rt_58[56:46]}; //-93 -6 + bfloat_denorm_lst_frac = 1'b0; + end//-1022 1 + default: begin qt_result_bfloat_denorm_for_round[10:0] = 11'b0; + bfloat_denorm_lst_frac = 1'b0; + end//-1022 1 +endcase +end +//rounding evaluation for bfloat denormalize number +assign ex3_bfloat_denorm_eq = qt_result_bfloat_denorm_for_round[10] + && !ex3_bfloat_low_not_zero; +assign ex3_bfloat_low_not_zero = |qt_result_bfloat_denorm_for_round[9:0]; +assign ex3_bfloat_denorm_gr = qt_result_bfloat_denorm_for_round[10] + && ex3_bfloat_low_not_zero; +assign ex3_bfloat_denorm_zero = !qt_result_bfloat_denorm_for_round[10] + && !ex3_bfloat_low_not_zero; + +assign ex3_denorm_eq = vfdsu_ex3_double ? ex3_double_denorm_eq : + vfdsu_ex3_single ? ex3_single_denorm_eq : + vfdsu_ex3_half ? ex3_half_denorm_eq : ex3_bfloat_denorm_eq; +assign ex3_denorm_gr = vfdsu_ex3_double ? ex3_double_denorm_gr : + vfdsu_ex3_single ? ex3_single_denorm_gr : + vfdsu_ex3_half ? ex3_half_denorm_gr : ex3_bfloat_denorm_gr; +assign ex3_denorm_zero = vfdsu_ex3_double ? ex3_double_denorm_zero : + vfdsu_ex3_single ? ex3_single_denorm_zero : + vfdsu_ex3_half ? ex3_half_denorm_zero : ex3_bfloat_denorm_zero; +assign ex3_denorm_lst_frac = vfdsu_ex3_double ? double_denorm_lst_frac : + vfdsu_ex3_single ? single_denorm_lst_frac : + vfdsu_ex3_half ? half_denorm_lst_frac : bfloat_denorm_lst_frac; + //Different Round Mode with different rounding rule //Here we call rounding bit as "rb", remainder as "rem" -//RNE : +//RNE : // 1.+1 : rb>10000 || rb==10000 && rem>0 // 2. 0 : Rest Condition // 3.-1 : Never occur -//RTZ : +//RTZ : // 1.+1 : Never occur // 2. 0 : Rest Condition // 3.-1 : rb=10000 && rem<0 -//RDN : +//RDN : // 1.+1 : Q>0 Never occur ; Q<0 Rest condition -// 2. 0 : Q>0 Rest condition; Q<0 Rem<0 && rb=0 +// 2. 0 : Q>0 Rest condition; Q<0 Rem<0 && rb=0 // 3.-1 : Q>0 Rem<0 && rb=0 ; Q<0 Never occur -//RUP : +//RUP : // 1.+1 : Q>0 Rest Condition; Q<0 Never occur // 2. 0 : Q>0 Rem<0 && rb=0 ; Q<0 Rest condition -// 3.-1 : Q>0 Never occur ; Q<0 Rem<0 && rb=0 -//RMM : +// 3.-1 : Q>0 Never occur ; Q<0 Rem<0 && rb=0 +//RMM : // 1.+1 : rb>10000 || rb==10000 && rem>0 // 2. 0 : Rest Condition // 3.-1 : Never occur -assign frac_rne_add_1 = ex3_qt_gr || - (ex3_qt_eq && !fdsu_ex3_rem_sign); -assign frac_rtz_sub_1 = ex3_qt_zero && fdsu_ex3_rem_sign; -assign frac_rup_add_1 = !fdsu_ex3_result_sign && - (!ex3_qt_zero || - (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); -assign frac_rup_sub_1 = fdsu_ex3_result_sign && - (ex3_qt_zero && fdsu_ex3_rem_sign); -assign frac_rdn_add_1 = fdsu_ex3_result_sign && - (!ex3_qt_zero || - (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); -assign frac_rdn_sub_1 = !fdsu_ex3_result_sign && - (ex3_qt_zero && fdsu_ex3_rem_sign); -assign frac_rmm_add_1 = ex3_qt_gr || - (ex3_qt_eq && !fdsu_ex3_rem_sign); -//denormal result -assign frac_denorm_rne_add_1 = ex3_denorm_gr || - (ex3_denorm_eq && - ((fdsu_ex3_rem_zero && +assign frac_rne_add_1 = ex3_qt_gr || + (ex3_qt_eq && !vfdsu_ex3_rem_sign); +assign frac_rtz_sub_1 = ex3_qt_zero && vfdsu_ex3_rem_sign; +assign frac_rup_add_1 = !vfdsu_ex3_result_sign && + (!ex3_qt_zero || + (!vfdsu_ex3_rem_sign && !vfdsu_ex3_rem_zero)); +assign frac_rup_sub_1 = vfdsu_ex3_result_sign && + (ex3_qt_zero && vfdsu_ex3_rem_sign); +assign frac_rdn_add_1 = vfdsu_ex3_result_sign && + (!ex3_qt_zero || + (!vfdsu_ex3_rem_sign && !vfdsu_ex3_rem_zero)); +assign frac_rdn_sub_1 = !vfdsu_ex3_result_sign && + (ex3_qt_zero && vfdsu_ex3_rem_sign); +assign frac_rmm_add_1 = ex3_qt_gr || + (ex3_qt_eq && !vfdsu_ex3_rem_sign); +//denormal result +assign frac_denorm_rne_add_1 = ex3_denorm_gr || + (ex3_denorm_eq && + ((vfdsu_ex3_rem_zero && ex3_denorm_lst_frac) || - (!fdsu_ex3_rem_zero && - !fdsu_ex3_rem_sign))); -assign frac_denorm_rtz_sub_1 = ex3_denorm_zero && fdsu_ex3_rem_sign; -assign frac_denorm_rup_add_1 = !fdsu_ex3_result_sign && - (!ex3_denorm_zero || - (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); -assign frac_denorm_rup_sub_1 = fdsu_ex3_result_sign && - (ex3_denorm_zero && fdsu_ex3_rem_sign); -assign frac_denorm_rdn_add_1 = fdsu_ex3_result_sign && - (!ex3_denorm_zero || - (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); -assign frac_denorm_rdn_sub_1 = !fdsu_ex3_result_sign && - (ex3_denorm_zero && fdsu_ex3_rem_sign); -assign frac_denorm_rmm_add_1 = ex3_denorm_gr || - (ex3_denorm_eq && !fdsu_ex3_rem_sign); + (!vfdsu_ex3_rem_zero && + !vfdsu_ex3_rem_sign))); +assign frac_denorm_rtz_sub_1 = ex3_denorm_zero && vfdsu_ex3_rem_sign; +assign frac_denorm_rup_add_1 = !vfdsu_ex3_result_sign && + (!ex3_denorm_zero || + (!vfdsu_ex3_rem_sign && !vfdsu_ex3_rem_zero)); +assign frac_denorm_rup_sub_1 = vfdsu_ex3_result_sign && + (ex3_denorm_zero && vfdsu_ex3_rem_sign); +assign frac_denorm_rdn_add_1 = vfdsu_ex3_result_sign && + (!ex3_denorm_zero || + (!vfdsu_ex3_rem_sign && !vfdsu_ex3_rem_zero)); +assign frac_denorm_rdn_sub_1 = !vfdsu_ex3_result_sign && + (ex3_denorm_zero && vfdsu_ex3_rem_sign); +assign frac_denorm_rmm_add_1 = ex3_denorm_gr || + (ex3_denorm_eq && !vfdsu_ex3_rem_sign); //RM select -// &CombBeg; @222 -always @( fdsu_ex3_rm[2:0] +// &CombBeg; @489 +always @( vfdsu_ex3_result_sign + or frac_rtz_sub_1 + or frac_rdn_add_1 + or frac_denorm_rtz_sub_1 + or frac_rup_sub_1 + or frac_denorm_rmm_add_1 + or frac_denorm_rne_add_1 + or frac_rmm_add_1 or frac_denorm_rdn_add_1 or frac_rne_add_1 or frac_denorm_rdn_sub_1 - or fdsu_ex3_result_sign or frac_rup_add_1 or frac_denorm_rup_sub_1 or frac_rdn_sub_1 - or frac_rtz_sub_1 - or frac_rdn_add_1 - or fdsu_ex3_id_srt_skip - or frac_denorm_rtz_sub_1 or ex3_rslt_denorm - or frac_rup_sub_1 - or frac_denorm_rmm_add_1 + or vfdsu_ex3_rm[2:0] or frac_denorm_rup_add_1 - or frac_denorm_rne_add_1 - or frac_rmm_add_1) + or vfdsu_ex3_id_srt_skip) begin -case(fdsu_ex3_rm[2:0]) +case(vfdsu_ex3_rm[2:0]) 3'b000://round to nearst,ties to even - begin + begin frac_add_1 = ex3_rslt_denorm ? frac_denorm_rne_add_1 : frac_rne_add_1; frac_sub_1 = 1'b0; frac_orig = ex3_rslt_denorm ? !frac_denorm_rne_add_1 : !frac_rne_add_1; - denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rne_add_1; + denorm_to_tiny_frac = vfdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rne_add_1; end 3'b001:// round to 0 - begin + begin frac_add_1 = 1'b0; frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rtz_sub_1 : frac_rtz_sub_1; frac_orig = ex3_rslt_denorm ? !frac_denorm_rtz_sub_1 : !frac_rtz_sub_1; denorm_to_tiny_frac = 1'b0; end 3'b010://round to -inf - begin + begin frac_add_1 = ex3_rslt_denorm ? frac_denorm_rdn_add_1 : frac_rdn_add_1; frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rdn_sub_1 : frac_rdn_sub_1; - frac_orig = ex3_rslt_denorm ? !frac_denorm_rdn_add_1 && !frac_denorm_rdn_sub_1 + frac_orig = ex3_rslt_denorm ? !frac_denorm_rdn_add_1 && !frac_denorm_rdn_sub_1 : !frac_rdn_add_1 && !frac_rdn_sub_1; - denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? fdsu_ex3_result_sign + denorm_to_tiny_frac = vfdsu_ex3_id_srt_skip ? vfdsu_ex3_result_sign : frac_denorm_rdn_add_1; end 3'b011://round to +inf - begin + begin frac_add_1 = ex3_rslt_denorm ? frac_denorm_rup_add_1 : frac_rup_add_1; - frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rup_sub_1 : frac_rup_sub_1; - frac_orig = ex3_rslt_denorm ? !frac_denorm_rup_add_1 && !frac_denorm_rup_sub_1 - : !frac_rup_add_1 && !frac_rup_sub_1; - denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? !fdsu_ex3_result_sign + frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rup_sub_1 : frac_rup_sub_1; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rup_add_1 && !frac_denorm_rup_sub_1 + : !frac_rup_add_1 && !frac_rup_sub_1; + denorm_to_tiny_frac = vfdsu_ex3_id_srt_skip ? !vfdsu_ex3_result_sign : frac_denorm_rup_add_1; end 3'b100://round to nearest,ties to max magnitude - begin + begin frac_add_1 = ex3_rslt_denorm ? frac_denorm_rmm_add_1 : frac_rmm_add_1; frac_sub_1 = 1'b0; frac_orig = ex3_rslt_denorm ? !frac_denorm_rmm_add_1 : !frac_rmm_add_1; - denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rmm_add_1; + denorm_to_tiny_frac = vfdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rmm_add_1; end - default: - begin + default: + begin frac_add_1 = 1'b0; frac_sub_1 = 1'b0; frac_orig = 1'b0; denorm_to_tiny_frac = 1'b0; end endcase -// &CombEnd; @271 +// &CombEnd; @538 end //Add 1 or Sub 1 constant -// &CombBeg; @273 -always @( total_qt_rt_30[28]) +// &CombBeg; @540 +always @( total_qt_rt_58[56] + or vfdsu_ex3_single + or vfdsu_ex3_double + or vfdsu_ex3_half + or vfdsu_ex3_bfloat) begin -case(total_qt_rt_30[28]) - 1'b0: +case({total_qt_rt_58[56],vfdsu_ex3_double,vfdsu_ex3_single}) + 3'b001: + begin + frac_add1_op1[54:0] = {2'b0,24'b1,29'b0}; + frac_sub1_op1[54:0] = {2'b11,{24{1'b1}},29'b0}; + end + 3'b010: + begin + frac_add1_op1[54:0] = 55'b1; + frac_sub1_op1[54:0] = {55{1'b1}}; + end + 3'b101: + begin + frac_add1_op1[54:0] = {25'b1,30'b0}; + frac_sub1_op1[54:0] = {{25{1'b1}},30'b0}; + end + 3'b110: + begin + frac_add1_op1[54:0] = 55'b10; + frac_sub1_op1[54:0] = {{54{1'b1}},1'b0}; + end + 3'b100: begin - frac_add1_op1[25:0] = {2'b0,24'b1}; - frac_sub1_op1[25:0] = {2'b11,{24{1'b1}}}; + if (vfdsu_ex3_half) begin + frac_add1_op1[54:0] = {12'b1,43'b0}; + frac_sub1_op1[54:0] = {{12{1'b1}},43'b0}; + end else begin + frac_add1_op1[54:0] = {9'b1,46'b0}; + frac_sub1_op1[54:0] = {{9{1'b1}},46'b0}; + end end - 1'b1: + 3'b000: begin - frac_add1_op1[25:0] = {25'b1,1'b0}; - frac_sub1_op1[25:0] = {{25{1'b1}},1'b0}; + if (vfdsu_ex3_half) begin + frac_add1_op1[54:0] = {13'b1,42'b0}; + frac_sub1_op1[54:0] = {{13{1'b1}},42'b0}; + end else begin + frac_add1_op1[54:0] = {10'b1,45'b0}; + frac_sub1_op1[54:0] = {{10{1'b1}},45'b0}; + end end default: begin - frac_add1_op1[25:0] = 26'b0; - frac_sub1_op1[25:0] = 26'b0; + frac_add1_op1[54:0] = 55'b0; + frac_sub1_op1[54:0] = 55'b0; end endcase -// &CombEnd; @291 +// &CombEnd; @578 end - //Add 1 or Sub1 final result //Conner case when quotient is 0.010000...00 and remainder is negative, -//The real quotient is actually 0.00fff..ff, +//The real quotient is actually 0.00fff..ff, //The final result will need to sub 1 when //RN : Never occur //RP : sign of quotient is - //RM : sign of quotient is + -assign frac_add1_rst[25:0] = {1'b0,total_qt_rt_30[28:4]} + - frac_add1_op1_with_denorm[25:0]; -assign frac_add1_op1_with_denorm[25:0] = ex3_rslt_denorm ? - {1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} : - frac_add1_op1[25:0]; -assign frac_sub1_rst[25:0] = (ex3_rst_eq_1) - ? {3'b0,{23{1'b1}}} - : {1'b0,total_qt_rt_30[28:4]} + - frac_sub1_op1_with_denorm[25:0] + {25'b0, ex3_rslt_denorm}; -assign frac_sub1_op1_with_denorm[25:0] = ex3_rslt_denorm ? - ~{1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} : - frac_sub1_op1[25:0]; -assign frac_final_rst[25:0] = (frac_add1_rst[25:0] & {26{frac_add_1}}) | - (frac_sub1_rst[25:0] & {26{frac_sub_1}}) | - ({1'b0,total_qt_rt_30[28:4]} & {26{frac_orig}}); +assign frac_add1_rst[54:0] = {1'b0,total_qt_rt_58[56:3]} + + frac_add1_op1_with_denorm[54:0]; +assign frac_add1_op1_with_denorm[54:0] = ex3_rslt_denorm ? + {1'b0,vfdsu_ex3_result_denorm_round_add_num[52:0],1'b0} : + frac_add1_op1[54:0]; +assign frac_sub1_rst[54:0] = (ex3_rst_eq_1) + ? {2'b0,{53{1'b1}}} + : {1'b0,total_qt_rt_58[56:3]} + + frac_sub1_op1_with_denorm[54:0] + {54'b0,ex3_rslt_denorm}; +assign frac_sub1_op1_with_denorm[54:0] = ex3_rslt_denorm ? + ~{1'b0,vfdsu_ex3_result_denorm_round_add_num[52:0],1'b0} : + frac_sub1_op1[54:0]; +assign frac_final_rst[54:0] = (frac_add1_rst[54:0] & {55{frac_add_1}}) | + (frac_sub1_rst[54:0] & {55{frac_sub_1}}) | + ({1'b0,total_qt_rt_58[56:3]} & {55{frac_orig}}); //===============Pipe down signal prepare=================== -// assign ex3_rst_nor = !fdsu_ex3_result_zero && -// !fdsu_ex3_result_qnan && -// !fdsu_ex3_result_inf && -// !fdsu_ex3_result_lfn; -assign ex3_rst_nor = !fdsu_ex3_result_inf && - !fdsu_ex3_result_lfn; -assign ex3_nx = ex3_rst_nor && - (!ex3_qt_zero || !fdsu_ex3_rem_zero || ex3_denorm_nx); -assign ex3_denorm_nx = ex3_rslt_denorm && (!ex3_denorm_zero || !fdsu_ex3_rem_zero); +assign ex3_rst_nor = !vfdsu_ex3_result_zero && + !vfdsu_ex3_result_qnan && + !vfdsu_ex3_result_inf && + !vfdsu_ex3_result_lfn; +assign ex3_nx = ex3_rst_nor && + (!ex3_qt_zero || !vfdsu_ex3_rem_zero || ex3_denorm_nx); +assign ex3_denorm_nx = ex3_rslt_denorm && (!ex3_denorm_zero || !vfdsu_ex3_rem_zero); //Adjust expnt //Div:Actural expnt should plus 1 when op0 is id, sub 1 when op1 id -assign ex3_expnt_adjst[9:0] = 10'h7f; - -assign ex3_expnt_adjust_result[9:0] = fdsu_ex3_expnt_rst[9:0] + - ex3_expnt_adjst[9:0]; +assign ex3_expnt_adjst[12:0] = vfdsu_ex3_double ? 13'h3ff: vfdsu_ex3_single ? 13'h7f : vfdsu_ex3_half ? 13'hf : 13'h7f; +assign ex3_expnt_adjust_result[12:0] = vfdsu_ex3_expnt_rst[12:0] + + ex3_expnt_adjst[12:0]; //this information is for the packing, which determin the result is normal //numer or not; assign ex3_potnt_norm[1:0] = {ex3_denorm_plus,ex3_denorm_potnt_norm}; //=======================Pipe to EX4======================== //gate clk -// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @337 +// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @620 gated_clk_cell x_ex3_pipe_clk ( .clk_in (forever_cpuclk ), .clk_out (ex3_pipe_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), .local_en (ex3_pipe_clk_en ), - .module_en (cp0_fpu_icg_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect( .clk_in (forever_cpuclk), @338 -// .clk_out (ex3_pipe_clk),//Out Clock @339 -// .external_en (1'b0), @340 -// .global_en (cp0_yy_clk_en), @341 -// .local_en (ex3_pipe_clk_en),//Local Condition @342 -// .module_en (cp0_fpu_icg_en) @343 -// ); @344 +// &Connect( .clk_in (forever_cpuclk), @621 +// .clk_out (ex3_pipe_clk),//Out Clock @622 +// .external_en (1'b0), @623 +// .global_en (cp0_yy_clk_en), @624 +// .local_en (ex3_pipe_clk_en),//Local Condition @625 +// .module_en (cp0_vfpu_icg_en) @626 +// ); @627 assign ex3_pipe_clk_en = ex3_pipedown; -always @(posedge ex3_pipe_clk) +always @(posedge ex3_pipe_clk or negedge cpurst_b) begin - if(ex3_pipedown) + if(!cpurst_b) begin - fdsu_ex4_result_nor <= ex3_rst_nor; - fdsu_ex4_nx <= ex3_nx; - fdsu_ex4_denorm_to_tiny_frac + vfdsu_ex4_result_zero <= 1'b0; + vfdsu_ex4_result_qnan <= 1'b0; + vfdsu_ex4_result_inf <= 1'b0; + vfdsu_ex4_result_lfn <= 1'b0; + vfdsu_ex4_result_sign <= 1'b0; + vfdsu_ex4_potnt_of <= 1'b0; + vfdsu_ex4_potnt_uf <= 1'b0; + vfdsu_ex4_result_nor <= 1'b0; + vfdsu_ex4_expnt_rst[12:0] <= 13'b0; + vfdsu_ex4_nv <= 1'b0; + vfdsu_ex4_nx <= 1'b0; + vfdsu_ex4_uf <= 1'b0; + vfdsu_ex4_of <= 1'b0; + vfdsu_ex4_dz <= 1'b0; + vfdsu_ex4_of_rst_lfn <= 1'b0; + vfdsu_ex4_frac[54:0] <= 55'b0; + vfdsu_ex4_qnan_sign <= 1'b0; + vfdsu_ex4_qnan_f[51:0] <= 52'b0; + vfdsu_ex4_rslt_denorm <= 1'b0; + vfdsu_ex4_denorm_to_tiny_frac + <= 1'b0; + vfdsu_ex4_potnt_norm[1:0] <= 2'b0; + vfdsu_ex4_double <= 1'b0; + vfdsu_ex4_single <= 1'b0; + vfdsu_ex4_half <= 1'b0; + vfdsu_ex4_bfloat <= 1'b0; + + end + else if(ex3_pipedown) + begin + vfdsu_ex4_result_zero <= vfdsu_ex3_result_zero; + vfdsu_ex4_result_qnan <= vfdsu_ex3_result_qnan; + vfdsu_ex4_result_inf <= vfdsu_ex3_result_inf; + vfdsu_ex4_result_lfn <= vfdsu_ex3_result_lfn; + vfdsu_ex4_result_sign <= vfdsu_ex3_result_sign; + vfdsu_ex4_potnt_of <= vfdsu_ex3_potnt_of; + vfdsu_ex4_potnt_uf <= vfdsu_ex3_potnt_uf; + vfdsu_ex4_result_nor <= ex3_rst_nor; + vfdsu_ex4_expnt_rst[12:0] <= ex3_expnt_adjust_result[12:0]; + vfdsu_ex4_nv <= vfdsu_ex3_nv; + vfdsu_ex4_nx <= ex3_nx; + vfdsu_ex4_uf <= vfdsu_ex3_uf; + vfdsu_ex4_of <= vfdsu_ex3_of; + vfdsu_ex4_dz <= vfdsu_ex3_dz; + vfdsu_ex4_of_rst_lfn <= vfdsu_ex2_of_rm_lfn; + vfdsu_ex4_frac[54:0] <= frac_final_rst[54:0]; + vfdsu_ex4_qnan_sign <= vfdsu_ex3_qnan_sign; + vfdsu_ex4_qnan_f[51:0] <= vfdsu_ex3_qnan_f[51:0]; + vfdsu_ex4_rslt_denorm <= ex3_rslt_denorm; + vfdsu_ex4_denorm_to_tiny_frac <= denorm_to_tiny_frac; - fdsu_ex4_potnt_norm[1:0] <= ex3_potnt_norm[1:0]; + vfdsu_ex4_potnt_norm[1:0] <= ex3_potnt_norm[1:0]; + vfdsu_ex4_double <= vfdsu_ex3_double; + vfdsu_ex4_single <= vfdsu_ex3_single; + vfdsu_ex4_half <= vfdsu_ex3_half; + vfdsu_ex4_bfloat <= vfdsu_ex3_bfloat; end else begin - fdsu_ex4_result_nor <= fdsu_ex4_result_nor; - fdsu_ex4_nx <= fdsu_ex4_nx; - fdsu_ex4_denorm_to_tiny_frac - <= fdsu_ex4_denorm_to_tiny_frac; - fdsu_ex4_potnt_norm[1:0] <= fdsu_ex4_potnt_norm[1:0]; - end -end - -// ex3_frac Pipedown to ex4 use srt_divisor. -assign ex3_frac_final_rst[25:0] = frac_final_rst[25:0]; -// &Force("output","fdsu_ex4_result_nor"); @397 -// &Force("output","fdsu_ex4_nx"); @398 -// &Force("output","fdsu_ex4_denorm_to_tiny_frac"); @399 -// &Force("output","fdsu_ex4_potnt_norm"); @400 - - -// &ModuleEnd; @403 + vfdsu_ex4_result_zero <= vfdsu_ex4_result_zero; + vfdsu_ex4_result_qnan <= vfdsu_ex4_result_qnan; + vfdsu_ex4_result_inf <= vfdsu_ex4_result_inf; + vfdsu_ex4_result_lfn <= vfdsu_ex4_result_lfn; + vfdsu_ex4_result_sign <= vfdsu_ex4_result_sign; + vfdsu_ex4_potnt_of <= vfdsu_ex4_potnt_of; + vfdsu_ex4_potnt_uf <= vfdsu_ex4_potnt_uf; + vfdsu_ex4_result_nor <= vfdsu_ex4_result_nor; + vfdsu_ex4_expnt_rst[12:0] <= vfdsu_ex4_expnt_rst[12:0]; + vfdsu_ex4_nv <= vfdsu_ex4_nv; + vfdsu_ex4_nx <= vfdsu_ex4_nx; + vfdsu_ex4_uf <= vfdsu_ex4_uf; + vfdsu_ex4_of <= vfdsu_ex4_of; + vfdsu_ex4_dz <= vfdsu_ex4_dz; + vfdsu_ex4_of_rst_lfn <= vfdsu_ex4_of_rst_lfn; + vfdsu_ex4_frac[54:0] <= vfdsu_ex4_frac[54:0]; + vfdsu_ex4_qnan_sign <= vfdsu_ex4_qnan_sign; + vfdsu_ex4_qnan_f[51:0] <= vfdsu_ex4_qnan_f[51:0]; + vfdsu_ex4_rslt_denorm <= vfdsu_ex4_rslt_denorm; + vfdsu_ex4_denorm_to_tiny_frac + <= vfdsu_ex4_denorm_to_tiny_frac; + vfdsu_ex4_potnt_norm[1:0] <= vfdsu_ex4_potnt_norm[1:0]; + vfdsu_ex4_double <= vfdsu_ex4_double; + vfdsu_ex4_single <= vfdsu_ex4_single; + vfdsu_ex4_half <= vfdsu_ex4_half; + vfdsu_ex4_bfloat <= vfdsu_ex4_bfloat; + end +end + +// &Force("output","vfdsu_ex4_result_nor"); @716 +// &Force("output","vfdsu_ex4_nx"); @717 +// &Force("output","vfdsu_ex4_nv"); @718 +// &Force("output","vfdsu_ex4_uf"); @719 +// &Force("output","vfdsu_ex4_of"); @720 +// &Force("output","vfdsu_ex4_dz"); @721 +// &Force("output","vfdsu_ex4_result_sign"); @722 +// &Force("output","vfdsu_ex4_of_rst_lfn"); @723 +// &Force("output","vfdsu_ex4_potnt_of"); @724 +// &Force("output","vfdsu_ex4_potnt_uf"); @725 +// &Force("output","vfdsu_ex4_result_inf"); @726 +// &Force("output","vfdsu_ex4_result_lfn"); @727 +// &Force("output","vfdsu_ex4_result_qnan"); @728 +// &Force("output","vfdsu_ex4_result_zero"); @729 +// &Force("output","vfdsu_ex4_frac"); @730 +// &Force("output","vfdsu_ex4_expnt_rst"); @731 +// &Force("output","vfdsu_ex4_qnan_sign"); @732 +// &Force("output","vfdsu_ex4_qnan_f"); @733 +// &Force("output","vfdsu_ex4_rslt_denorm"); @734 +// &Force("output","vfdsu_ex4_denorm_to_tiny_frac"); @735 +// &Force("output","vfdsu_ex4_potnt_norm"); @736 +// &Force("output","vfdsu_ex4_double"); @737 +// &Force("output","vfdsu_ex4_single"); @738 +// &ModuleEnd; @739 endmodule +// ----- 8< ----- FILE "./ct_vfdsu_scalar_dp.v" ----- 8< ----- -// ----- 8< ----- FILE "./pa_fdsu_special.v" ----- 8< ----- - -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -24490,339 +29904,339 @@ See the License for the specific language governing permissions and limitations under the License. */ +// &Depend("cpu_cfig.h"); @22 // &ModuleBeg; @23 -module pa_fdsu_special( - cp0_fpu_xx_dqnan, - dp_xx_ex1_cnan, - dp_xx_ex1_id, - dp_xx_ex1_inf, - dp_xx_ex1_qnan, - dp_xx_ex1_snan, - dp_xx_ex1_zero, +module ct_vfdsu_scalar_dp( + cp0_vfpu_icg_en, + cp0_yy_clk_en, + cpurst_b, + dp_vfdsu_ex1_pipex_dst_ereg, + dp_vfdsu_ex1_pipex_dst_vreg, + dp_vfdsu_ex1_pipex_iid, + dp_vfdsu_ex1_pipex_imm0, + dp_vfdsu_ex1_pipex_srcf0, + dp_vfdsu_ex1_pipex_srcf1, + ex1_data_clk, ex1_div, - ex1_op0_id, - ex1_op0_norm, - ex1_op0_sign, - ex1_op1_id, - ex1_op1_norm, - ex1_result_sign, - ex1_sqrt, - ex1_srt_skip, - fdsu_fpu_ex1_fflags, - fdsu_fpu_ex1_special_sel, - fdsu_fpu_ex1_special_sign -); - -// &Ports; @24 -input cp0_fpu_xx_dqnan; -input [2:0] dp_xx_ex1_cnan; -input [2:0] dp_xx_ex1_id; -input [2:0] dp_xx_ex1_inf; -input [2:0] dp_xx_ex1_qnan; -input [2:0] dp_xx_ex1_snan; -input [2:0] dp_xx_ex1_zero; -input ex1_div; -input ex1_op0_sign; -input ex1_result_sign; -input ex1_sqrt; -output ex1_op0_id; -output ex1_op0_norm; -output ex1_op1_id; -output ex1_op1_norm; -output ex1_srt_skip; -output [4:0] fdsu_fpu_ex1_fflags; -output [7:0] fdsu_fpu_ex1_special_sel; -output [3:0] fdsu_fpu_ex1_special_sign; - -// &Regs; @25 -reg ex1_result_cnan; -reg ex1_result_qnan_op0; -reg ex1_result_qnan_op1; - -// &Wires; @26 -wire cp0_fpu_xx_dqnan; -wire [2:0] dp_xx_ex1_cnan; -wire [2:0] dp_xx_ex1_id; -wire [2:0] dp_xx_ex1_inf; -wire [2:0] dp_xx_ex1_qnan; -wire [2:0] dp_xx_ex1_snan; -wire [2:0] dp_xx_ex1_zero; -wire ex1_div; -wire ex1_div_dz; -wire ex1_div_nv; -wire ex1_div_rst_inf; -wire ex1_div_rst_qnan; -wire ex1_div_rst_zero; -wire ex1_dz; -wire [4:0] ex1_fflags; -wire ex1_nv; -wire ex1_op0_cnan; -wire ex1_op0_id; -wire ex1_op0_inf; -wire ex1_op0_is_qnan; -wire ex1_op0_is_snan; -wire ex1_op0_norm; -wire ex1_op0_qnan; -wire ex1_op0_sign; -wire ex1_op0_snan; -wire ex1_op0_tt_zero; -wire ex1_op0_zero; -wire ex1_op1_cnan; -wire ex1_op1_id; -wire ex1_op1_inf; -wire ex1_op1_is_qnan; -wire ex1_op1_is_snan; -wire ex1_op1_norm; -wire ex1_op1_qnan; -wire ex1_op1_snan; -wire ex1_op1_tt_zero; -wire ex1_op1_zero; -wire ex1_result_inf; -wire ex1_result_lfn; -wire ex1_result_qnan; -wire ex1_result_sign; -wire ex1_result_zero; -wire ex1_rst_default_qnan; -wire [7:0] ex1_special_sel; -wire [3:0] ex1_special_sign; -wire ex1_sqrt; -wire ex1_sqrt_nv; -wire ex1_sqrt_rst_inf; -wire ex1_sqrt_rst_qnan; -wire ex1_sqrt_rst_zero; -wire ex1_srt_skip; -wire [4:0] fdsu_fpu_ex1_fflags; -wire [7:0] fdsu_fpu_ex1_special_sel; -wire [3:0] fdsu_fpu_ex1_special_sign; - - -//infinity number -// &Force("bus", "dp_xx_ex1_inf", 2, 0); @29 -assign ex1_op0_inf = dp_xx_ex1_inf[0]; -assign ex1_op1_inf = dp_xx_ex1_inf[1]; - -//zero -// &Force("bus", "dp_xx_ex1_zero", 2, 0); @34 -assign ex1_op0_zero = dp_xx_ex1_zero[0]; -assign ex1_op1_zero = dp_xx_ex1_zero[1]; - -//denormalize number -// &Force("bus", "dp_xx_ex1_id", 2, 0); @39 -assign ex1_op0_id = dp_xx_ex1_id[0]; -assign ex1_op1_id = dp_xx_ex1_id[1]; - -//cNaN -// &Force("bus", "dp_xx_ex1_cnan", 2, 0); @44 -assign ex1_op0_cnan = dp_xx_ex1_cnan[0]; -assign ex1_op1_cnan = dp_xx_ex1_cnan[1]; - -//sNaN -// &Force("bus", "dp_xx_ex1_snan", 2, 0); @49 -assign ex1_op0_snan = dp_xx_ex1_snan[0]; -assign ex1_op1_snan = dp_xx_ex1_snan[1]; - -//qNaN -// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @54 -assign ex1_op0_qnan = dp_xx_ex1_qnan[0]; -assign ex1_op1_qnan = dp_xx_ex1_qnan[1]; - - -//======================EX1 expt detect===================== -//ex1_id_detect -//any opration is zero -// no input denormalize exception anymore -// -//ex1_nv_detect -//div_nv -// 1.any operation is sNaN -// 2.0/0(include DN flush to zero) -// 3.inf/inf -//sqrt_nv -// 1.any operation is sNaN -// 2.operation sign is 1 && operation is not zero/qNaN -assign ex1_nv = ex1_div && ex1_div_nv || - ex1_sqrt && ex1_sqrt_nv; -//ex1_div_nv -assign ex1_div_nv = ex1_op0_snan || - ex1_op1_snan || - (ex1_op0_tt_zero && ex1_op1_tt_zero)|| - (ex1_op0_inf && ex1_op1_inf); -assign ex1_op0_tt_zero = ex1_op0_zero; -assign ex1_op1_tt_zero = ex1_op1_zero; -//ex1_sqrt_nv -assign ex1_sqrt_nv = ex1_op0_snan || - ex1_op0_sign && - (ex1_op0_norm || - ex1_op0_inf ); - -// This 'norm' also include denorm. -assign ex1_op0_norm = !ex1_op0_inf && !ex1_op0_zero && !ex1_op0_snan && !ex1_op0_qnan && !ex1_op0_cnan; -assign ex1_op1_norm = !ex1_op1_inf && !ex1_op1_zero && !ex1_op1_snan && !ex1_op1_qnan && !ex1_op1_cnan; - -//ex1_of_detect -//div_of -// 1.only detect id overflow case -//assign ex1_of = ex1_div && ex1_div_of; -//assign ex1_div_of = ex1_op1_id_fm1 && -// ex1_op0_norm && -// ex1_div_id_of; -// -////ex1_uf_detect -////div_uf -//// 1.only detect id underflow case -//assign ex1_uf = ex1_div && ex1_div_uf; -//assign ex1_div_uf = ex1_op0_id && -// ex1_op1_norm && -// ex1_div_id_uf; -//ex1_dz_detect -//div_dz -// 1.op0 is normal && op1 zero -assign ex1_dz = ex1_div && ex1_div_dz; -assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm; - -//===================special cal result===================== -//ex1 result is zero -//div_zero -// 1.op0 is zero && op1 is normal -// 2.op0 is zero/normal && op1 is inf -//sqrt_zero -// 1.op0 is zero -assign ex1_result_zero = ex1_div_rst_zero && ex1_div || - ex1_sqrt_rst_zero && ex1_sqrt; -assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) || - // (!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf); - (!ex1_op0_inf && !ex1_op0_qnan && !ex1_op0_snan && !ex1_op0_cnan && ex1_op1_inf); -assign ex1_sqrt_rst_zero = ex1_op0_tt_zero; + ex1_double, + ex1_pipedown, + ex1_scalar, + ex1_half, + ex1_bfloat, + ex1_single, + ex1_sqrt, + ex1_src0, + ex1_src1, + ex1_static_rm, + ex2_data_clk, + ex2_pipedown, + ex3_data_clk, + ex3_pipedown, + ex4_out_expt, + ex4_out_result, + forever_cpuclk, + idu_vfpu_rf_pipex_func, + idu_vfpu_rf_pipex_gateclk_sel, + pad_yy_icg_scan_en, + pipex_dp_vfdsu_ereg, + pipex_dp_vfdsu_ereg_data, + pipex_dp_vfdsu_freg_data, + pipex_dp_vfdsu_vreg, + vfdsu_ex2_double, + vfdsu_ex2_single, + vfdsu_ex2_half, + vfdsu_ex2_bfloat +); -//ex1 result is qNaN -//ex1_nv -//div_qnan -// 1.op0 is qnan || op1 is qnan -//sqrt_qnan -// 1.op0 is qnan -assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div || - ex1_sqrt_rst_qnan && ex1_sqrt || - ex1_nv; -assign ex1_div_rst_qnan = ex1_op0_qnan || - ex1_op1_qnan; -assign ex1_sqrt_rst_qnan = ex1_op0_qnan; +// &Ports; @24 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; +input [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; +input [6 :0] dp_vfdsu_ex1_pipex_iid; +input [2 :0] dp_vfdsu_ex1_pipex_imm0; +input [63:0] dp_vfdsu_ex1_pipex_srcf0; +input [63:0] dp_vfdsu_ex1_pipex_srcf1; +input ex1_data_clk; +input ex1_pipedown; +input ex2_data_clk; +input ex2_pipedown; +input ex3_data_clk; +input ex3_pipedown; +input [4 :0] ex4_out_expt; +input [63:0] ex4_out_result; +input forever_cpuclk; +input [19:0] idu_vfpu_rf_pipex_func; +input idu_vfpu_rf_pipex_gateclk_sel; +input pad_yy_icg_scan_en; +output ex1_div; +output ex1_double; +output ex1_scalar; +output ex1_single; +output ex1_half; +output ex1_bfloat; +output ex1_sqrt; +output [63:0] ex1_src0; +output [63:0] ex1_src1; +output [2 :0] ex1_static_rm; +output [4 :0] pipex_dp_vfdsu_ereg; +output [4 :0] pipex_dp_vfdsu_ereg_data; +output [63:0] pipex_dp_vfdsu_freg_data; +output [6 :0] pipex_dp_vfdsu_vreg; +output vfdsu_ex2_double; +output vfdsu_ex2_single; +output vfdsu_ex2_half; +output vfdsu_ex2_bfloat; -//ex1_rst_default_qnan -//0/0, inf/inf, sqrt negative should get default qNaN -assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) || - (ex1_div && ex1_op0_inf && ex1_op1_inf) || - (ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf)); +// &Regs; @25 +reg ex1_div; +reg ex1_double; +reg ex1_single; +reg ex1_half; +reg ex1_bfloat; +reg ex1_sqrt; +reg vfdsu_ex2_div; +reg vfdsu_ex2_double; +reg [4 :0] vfdsu_ex2_dst_ereg; +reg [6 :0] vfdsu_ex2_dst_vreg; +reg [6 :0] vfdsu_ex2_iid; +reg vfdsu_ex2_single; +reg vfdsu_ex2_half; +reg vfdsu_ex2_bfloat; +reg vfdsu_ex2_sqrt; +reg [4 :0] vfdsu_ex3_dst_ereg; +reg [6 :0] vfdsu_ex3_dst_vreg; +reg [6 :0] vfdsu_ex3_iid; +reg [4 :0] vfdsu_ex4_dst_ereg; +reg [6 :0] vfdsu_ex4_dst_vreg; +reg [6 :0] vfdsu_ex4_iid; -//ex1 result is inf -//ex1_dz -// -//div_inf -// 1.op0 is inf && op1 is normal/zero -//sqrt_inf -// 1.op0 is inf -assign ex1_result_inf = ex1_div_rst_inf && ex1_div || - ex1_sqrt_rst_inf && ex1_sqrt || - ex1_dz ; -// assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan; -assign ex1_div_rst_inf = ex1_op0_inf && !ex1_op1_inf && !ex1_op1_qnan && !ex1_op1_snan && !ex1_op1_cnan; -assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign; +// &Wires; @26 +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; +wire [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; +wire [6 :0] dp_vfdsu_ex1_pipex_iid; +wire [2 :0] dp_vfdsu_ex1_pipex_imm0; +wire [63:0] dp_vfdsu_ex1_pipex_srcf0; +wire [63:0] dp_vfdsu_ex1_pipex_srcf1; +wire ex1_data_clk; +wire ex1_pipedown; +wire ex1_scalar; +wire [63:0] ex1_src0; +wire [63:0] ex1_src1; +wire [2 :0] ex1_static_rm; +wire ex2_data_clk; +wire ex2_pipedown; +wire ex3_data_clk; +wire ex3_pipedown; +wire [4 :0] ex4_out_expt; +wire [63:0] ex4_out_result; +wire forever_cpuclk; +wire [19:0] idu_vfpu_rf_pipex_func; +wire idu_vfpu_rf_pipex_gateclk_sel; +wire pad_yy_icg_scan_en; +wire [4 :0] pipex_dp_vfdsu_ereg; +wire [4 :0] pipex_dp_vfdsu_ereg_data; +wire [63:0] pipex_dp_vfdsu_freg_data; +wire [6 :0] pipex_dp_vfdsu_vreg; +wire vfdsu_sew_clk; +wire vfdsu_sew_clk_en; -//ex1 result is lfn -//ex1_of && round result toward not inc 1 -assign ex1_result_lfn = 1'b0; -//Default_qnan/Standard_qnan Select -assign ex1_op0_is_snan = ex1_op0_snan; -assign ex1_op1_is_snan = ex1_op1_snan && ex1_div; -assign ex1_op0_is_qnan = ex1_op0_qnan; -assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div; +//========================================================== +// EX1 Stage Control Signal +//========================================================== +// &Force("bus","idu_vfpu_rf_pipex_func",19,0); @31 +//assign func[19:0] = dp_vfdsu_ex1_pipex_func[19:0]; +// &Instance("gated_clk_cell","x_vfdsu_sew_clk"); @33 +gated_clk_cell x_vfdsu_sew_clk ( + .clk_in (forever_cpuclk ), + .clk_out (vfdsu_sew_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (vfdsu_sew_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); -// &CombBeg; @169 -always @( ex1_op0_is_snan - or ex1_op0_cnan - or ex1_result_qnan - or ex1_op0_is_qnan - or ex1_rst_default_qnan - or cp0_fpu_xx_dqnan - or ex1_op1_cnan - or ex1_op1_is_qnan - or ex1_op1_is_snan) -begin -if(ex1_rst_default_qnan) -begin - ex1_result_qnan_op0 = 1'b0; - ex1_result_qnan_op1 = 1'b0; - ex1_result_cnan = ex1_result_qnan; -end -else if(ex1_op0_is_snan && cp0_fpu_xx_dqnan) -begin - ex1_result_qnan_op0 = ex1_result_qnan; - ex1_result_qnan_op1 = 1'b0; - ex1_result_cnan = 1'b0; -end -else if(ex1_op1_is_snan && cp0_fpu_xx_dqnan) +// &Connect( .clk_in (forever_cpuclk), @34 +// .clk_out (vfdsu_sew_clk),//Out Clock @35 +// .external_en (1'b0), @36 +// .global_en (cp0_yy_clk_en), @37 +// .local_en (vfdsu_sew_clk_en),//Local Condition @38 +// .module_en (cp0_vfpu_icg_en) @39 +// ); @40 +assign vfdsu_sew_clk_en = idu_vfpu_rf_pipex_gateclk_sel; +always @(posedge vfdsu_sew_clk or negedge cpurst_b) begin - ex1_result_qnan_op0 = 1'b0; - ex1_result_qnan_op1 = ex1_result_qnan; - ex1_result_cnan = 1'b0; + if(!cpurst_b) + begin + ex1_div <= 1'b0; + ex1_sqrt <= 1'b0; + ex1_double <= 1'b0; + ex1_single <= 1'b0; + ex1_half <= 1'b0; + ex1_bfloat <= 1'b0; + end + else if(idu_vfpu_rf_pipex_gateclk_sel) + begin + ex1_div <= idu_vfpu_rf_pipex_func[0]; + ex1_sqrt <= idu_vfpu_rf_pipex_func[1]; + ex1_double <= idu_vfpu_rf_pipex_func[16]; + ex1_single <= idu_vfpu_rf_pipex_func[15]; + ex1_half <= idu_vfpu_rf_pipex_func[14]; + ex1_bfloat <= idu_vfpu_rf_pipex_func[13]; + end end -else if(ex1_op0_is_qnan && cp0_fpu_xx_dqnan) +assign ex1_scalar = 1'b1; +assign ex1_static_rm[2:0] = dp_vfdsu_ex1_pipex_imm0[2:0]; +// &Force("output","ex1_div"); @61 +// &Force("output","ex1_sqrt"); @62 +// &Force("output","ex1_double"); @63 +// &Force("output","ex1_single"); @64 + +assign ex1_src0[63:0] = dp_vfdsu_ex1_pipex_srcf0[63:0]; +assign ex1_src1[63:0] = dp_vfdsu_ex1_pipex_srcf1[63:0]; + + +always @(posedge ex1_data_clk or negedge cpurst_b) begin - ex1_result_qnan_op0 = ex1_result_qnan && !ex1_op0_cnan; - ex1_result_qnan_op1 = 1'b0; - ex1_result_cnan = ex1_result_qnan && ex1_op0_cnan; + if(!cpurst_b) + begin + vfdsu_ex2_dst_ereg[4:0] <= 5'b0; + vfdsu_ex2_dst_vreg[6:0] <= 7'b0; + vfdsu_ex2_iid[6:0] <= 7'b0; + vfdsu_ex2_double <= 1'b0; + vfdsu_ex2_single <= 1'b0; + vfdsu_ex2_half <= 1'b0; + vfdsu_ex2_bfloat <= 1'b0; + vfdsu_ex2_div <= 1'b0; + vfdsu_ex2_sqrt <= 1'b0; + end + else if(ex1_pipedown) + begin + vfdsu_ex2_dst_ereg[4:0] <= dp_vfdsu_ex1_pipex_dst_ereg[4:0]; + vfdsu_ex2_dst_vreg[6:0] <= dp_vfdsu_ex1_pipex_dst_vreg[6:0]; + vfdsu_ex2_iid[6:0] <= dp_vfdsu_ex1_pipex_iid[6:0]; + vfdsu_ex2_double <= ex1_double; + vfdsu_ex2_single <= ex1_single; + vfdsu_ex2_half <= ex1_half; + vfdsu_ex2_bfloat <= ex1_bfloat; + vfdsu_ex2_div <= ex1_div; + vfdsu_ex2_sqrt <= ex1_sqrt; + end + else + begin + vfdsu_ex2_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0]; + vfdsu_ex2_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0]; + vfdsu_ex2_iid[6:0] <= vfdsu_ex2_iid[6:0]; + vfdsu_ex2_double <= vfdsu_ex2_double; + vfdsu_ex2_single <= vfdsu_ex2_single; + vfdsu_ex2_half <= ex1_half; + vfdsu_ex2_bfloat <= ex1_bfloat; + vfdsu_ex2_div <= vfdsu_ex2_div; + vfdsu_ex2_sqrt <= vfdsu_ex2_sqrt; + end end -else if(ex1_op1_is_qnan && cp0_fpu_xx_dqnan) +// &Force("output","vfdsu_ex2_double"); @103 +// &Force("output","vfdsu_ex2_single"); @104 +// //&Force("output","vfdsu_ex2_div"); @105 +// //&Force("output","vfdsu_ex2_sqrt"); @106 + + +always @(posedge ex2_data_clk or negedge cpurst_b) begin - ex1_result_qnan_op0 = 1'b0; - ex1_result_qnan_op1 = ex1_result_qnan && !ex1_op1_cnan; - ex1_result_cnan = ex1_result_qnan && ex1_op1_cnan; + if(!cpurst_b) + begin + vfdsu_ex3_dst_ereg[4:0] <= 5'b0; + vfdsu_ex3_dst_vreg[6:0] <= 7'b0; + vfdsu_ex3_iid[6:0] <= 7'b0; +// vfdsu_ex3_double <= 1'b0; +// vfdsu_ex3_single <= 1'b0; +// vfdsu_ex3_div <= 1'b0; +// vfdsu_ex3_sqrt <= 1'b0; + end + else if(ex2_pipedown) + begin + vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex2_dst_ereg[4:0]; + vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex2_dst_vreg[6:0]; + vfdsu_ex3_iid[6:0] <= vfdsu_ex2_iid[6:0]; + // vfdsu_ex3_double <= vfdsu_ex2_double; +// vfdsu_ex3_single <= vfdsu_ex2_single; +// vfdsu_ex3_div <= vfdsu_ex2_div; +// vfdsu_ex3_sqrt <= vfdsu_ex2_sqrt; + end + else + begin + vfdsu_ex3_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0]; + vfdsu_ex3_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0]; + vfdsu_ex3_iid[6:0] <= vfdsu_ex3_iid[6:0]; +// vfdsu_ex3_double <= vfdsu_ex3_double; +// vfdsu_ex3_single <= vfdsu_ex3_single; +// vfdsu_ex3_div <= vfdsu_ex3_div; +// vfdsu_ex3_sqrt <= vfdsu_ex3_sqrt; + end end -else +// //&Force("output","vfdsu_ex3_double"); @142 +// //&Force("output","vfdsu_ex3_single"); @143 + +always @(posedge ex3_data_clk or negedge cpurst_b) begin - ex1_result_qnan_op0 = 1'b0; - ex1_result_qnan_op1 = 1'b0; - ex1_result_cnan = ex1_result_qnan; -end -// &CombEnd; @206 + if(!cpurst_b) + begin + vfdsu_ex4_dst_ereg[4:0] <= 5'b0; + vfdsu_ex4_dst_vreg[6:0] <= 7'b0; + vfdsu_ex4_iid[6:0] <= 7'b0; +// vfdsu_ex4_double <= 1'b0; +// vfdsu_ex4_single <= 1'b0; +// vfdsu_ex4_div <= 1'b0; +// vfdsu_ex4_sqrt <= 1'b0; + end + else if(ex3_pipedown) + begin + vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex3_dst_ereg[4:0]; + vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex3_dst_vreg[6:0]; + vfdsu_ex4_iid[6:0] <= vfdsu_ex3_iid[6:0]; +// vfdsu_ex4_double <= vfdsu_ex3_double; +// vfdsu_ex4_single <= vfdsu_ex3_single; +// vfdsu_ex4_div <= vfdsu_ex3_div; +// vfdsu_ex4_sqrt <= vfdsu_ex3_sqrt; + end + else + begin + vfdsu_ex4_dst_ereg[4:0] <= vfdsu_ex4_dst_ereg[4:0]; + vfdsu_ex4_dst_vreg[6:0] <= vfdsu_ex4_dst_vreg[6:0]; + vfdsu_ex4_iid[6:0] <= vfdsu_ex4_iid[6:0]; +// vfdsu_ex4_double <= vfdsu_ex4_double; +// vfdsu_ex4_single <= vfdsu_ex4_single; +// vfdsu_ex4_div <= vfdsu_ex4_div; +// vfdsu_ex4_sqrt <= vfdsu_ex4_sqrt; + end end +// //&Force("output","vfdsu_ex4_double"); @178 +// //&Force("output","vfdsu_ex4_single"); @179 -//Special result should skip SRT logic -assign ex1_srt_skip = ex1_result_zero || - ex1_result_qnan || - ex1_result_lfn || - ex1_result_inf; -// fflags: -// NV, DZ, OF, UF, NX -assign ex1_fflags[4:0] = {ex1_nv, ex1_dz, 3'b0}; -// Special Sel[7:0]: -// qnan_src2, qnan_src1, qnan_src0, cnan, lfn, inf, zero, src2 -assign ex1_special_sel[7:0] = {1'b0, ex1_result_qnan_op1, ex1_result_qnan_op0, - ex1_result_cnan, ex1_result_lfn, ex1_result_inf, - ex1_result_zero, 1'b0}; -// Special Sign[3:0] -// lfn, inf, zero, src2 -assign ex1_special_sign[3:0] = {ex1_result_sign, ex1_result_sign, ex1_result_sign, 1'b0}; +assign pipex_dp_vfdsu_ereg_data[4:0] = ex4_out_expt[4:0]; +assign pipex_dp_vfdsu_freg_data[63:0] = ex4_out_result[63:0]; +assign pipex_dp_vfdsu_ereg[4:0] = vfdsu_ex4_dst_ereg[4:0]; +assign pipex_dp_vfdsu_vreg[6:0] = vfdsu_ex4_dst_vreg[6:0]; -//========================================================== -// Output Signal -//========================================================== -assign fdsu_fpu_ex1_fflags[4:0] = ex1_fflags[4:0]; -assign fdsu_fpu_ex1_special_sel[7:0] = ex1_special_sel[7:0]; -assign fdsu_fpu_ex1_special_sign[3:0] = ex1_special_sign[3:0]; -// &Force("output", "ex1_op0_norm"); @233 -// &Force("output", "ex1_op1_norm"); @234 -// &ModuleEnd; @236 -endmodule -// ----- 8< ----- FILE "./pa_fdsu_srt_single.v" ----- 8< ----- +// &ModuleEnd; @192 +endmodule -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +// ----- 8< ----- FILE "./ct_vfdsu_srt.v" ----- 8< ----- + +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -24837,233 +30251,270 @@ See the License for the specific language governing permissions and limitations under the License. */ -// &ModuleBeg; @23 -module pa_fdsu_srt_single( - cp0_fpu_icg_en, +// &ModuleBeg; @22 +module ct_vfdsu_srt( + cp0_vfpu_icg_en, cp0_yy_clk_en, + cpurst_b, + ex1_div, ex1_divisor, - ex1_expnt_adder_op1, - ex1_oper_id_frac, - ex1_oper_id_frac_f, ex1_pipedown, - ex1_pipedown_gate, ex1_remainder, - ex1_save_op0, - ex1_save_op0_gate, - ex2_expnt_adder_op0, - ex2_of, - ex2_pipe_clk, + ex1_sqrt, ex2_pipedown, - ex2_potnt_of, - ex2_potnt_uf, - ex2_result_inf, - ex2_result_lfn, - ex2_rslt_denorm, - ex2_srt_expnt_rst, ex2_srt_first_round, - ex2_uf, - ex2_uf_srt_skip, - ex3_frac_final_rst, - ex3_pipedown, - fdsu_ex3_id_srt_skip, - fdsu_ex3_rem_sign, - fdsu_ex3_rem_zero, - fdsu_ex3_result_denorm_round_add_num, - fdsu_ex4_frac, - fdsu_yy_div, - fdsu_yy_of_rm_lfn, - fdsu_yy_op0_norm, - fdsu_yy_op1_norm, - fdsu_yy_sqrt, forever_cpuclk, pad_yy_icg_scan_en, - srt_remainder_zero, + srt_ctrl_rem_zero, + srt_ctrl_skip_srt, + srt_secd_round, srt_sm_on, - total_qt_rt_30 + total_qt_rt_58, + vfdsu_ex2_div, + vfdsu_ex2_double, + vfdsu_ex2_dz, + vfdsu_ex2_expnt_add0, + vfdsu_ex2_expnt_add1, + vfdsu_ex2_nv, + vfdsu_ex2_of_rm_lfn, + vfdsu_ex2_op0_norm, + vfdsu_ex2_op1_norm, + vfdsu_ex2_qnan_f, + vfdsu_ex2_qnan_sign, + vfdsu_ex2_result_inf, + vfdsu_ex2_result_qnan, + vfdsu_ex2_result_sign, + vfdsu_ex2_result_zero, + vfdsu_ex2_rm, + vfdsu_ex2_single, + vfdsu_ex2_half, + vfdsu_ex2_bfloat, + vfdsu_ex2_sqrt, + vfdsu_ex2_srt_skip, + vfdsu_ex3_doub_expnt_rst, + vfdsu_ex3_double, + vfdsu_ex3_dz, + vfdsu_ex3_half_expnt_rst, + vfdsu_ex3_bfloat_expnt_rst, + vfdsu_ex3_id_srt_skip, + vfdsu_ex3_nv, + vfdsu_ex3_of, + vfdsu_ex3_potnt_of, + vfdsu_ex3_potnt_uf, + vfdsu_ex3_qnan_f, + vfdsu_ex3_qnan_sign, + vfdsu_ex3_rem_sign, + vfdsu_ex3_rem_zero, + vfdsu_ex3_result_denorm_round_add_num, + vfdsu_ex3_result_inf, + vfdsu_ex3_result_lfn, + vfdsu_ex3_result_qnan, + vfdsu_ex3_result_sign, + vfdsu_ex3_result_zero, + vfdsu_ex3_rm, + vfdsu_ex3_rslt_denorm, + vfdsu_ex3_sing_expnt_rst, + vfdsu_ex3_single, + vfdsu_ex3_half, + vfdsu_ex3_bfloat, + vfdsu_ex3_uf ); -// &Ports; @24 -input cp0_fpu_icg_en; -input cp0_yy_clk_en; -input [23:0] ex1_divisor; -input [12:0] ex1_expnt_adder_op1; -input [51:0] ex1_oper_id_frac; -input ex1_pipedown; -input ex1_pipedown_gate; -input [31:0] ex1_remainder; -input ex1_save_op0; -input ex1_save_op0_gate; -input [9 :0] ex2_expnt_adder_op0; -input ex2_pipe_clk; -input ex2_pipedown; -input ex2_srt_first_round; -input [25:0] ex3_frac_final_rst; -input ex3_pipedown; -input fdsu_yy_div; -input fdsu_yy_of_rm_lfn; -input fdsu_yy_op0_norm; -input fdsu_yy_op1_norm; -input fdsu_yy_sqrt; -input forever_cpuclk; -input pad_yy_icg_scan_en; -input srt_sm_on; -output [51:0] ex1_oper_id_frac_f; -output ex2_of; -output ex2_potnt_of; -output ex2_potnt_uf; -output ex2_result_inf; -output ex2_result_lfn; -output ex2_rslt_denorm; -output [9 :0] ex2_srt_expnt_rst; -output ex2_uf; -output ex2_uf_srt_skip; -output fdsu_ex3_id_srt_skip; -output fdsu_ex3_rem_sign; -output fdsu_ex3_rem_zero; -output [23:0] fdsu_ex3_result_denorm_round_add_num; -output [25:0] fdsu_ex4_frac; -output srt_remainder_zero; -output [29:0] total_qt_rt_30; - -// &Regs; @25 -reg [31:0] cur_rem; -reg [7 :0] digit_bound_1; -reg [7 :0] digit_bound_2; -reg [23:0] ex2_result_denorm_round_add_num; -reg fdsu_ex3_id_srt_skip; -reg fdsu_ex3_rem_sign; -reg fdsu_ex3_rem_zero; -reg [23:0] fdsu_ex3_result_denorm_round_add_num; -reg [29:0] qt_rt_const_shift_std; -reg [7 :0] qtrt_sel_rem; -reg [31:0] rem_add1_op1; -reg [31:0] rem_add2_op1; -reg [25:0] srt_divisor; -reg [31:0] srt_remainder; -reg [29:0] total_qt_rt_30; -reg [29:0] total_qt_rt_30_next; -reg [29:0] total_qt_rt_minus_30; -reg [29:0] total_qt_rt_minus_30_next; - -// &Wires; @26 -wire [7 :0] bound1_cmp_result; -wire bound1_cmp_sign; -wire [7 :0] bound2_cmp_result; -wire bound2_cmp_sign; -wire [3 :0] bound_sel; -wire cp0_fpu_icg_en; -wire cp0_yy_clk_en; -wire [31:0] cur_doub_rem_1; -wire [31:0] cur_doub_rem_2; -wire [31:0] cur_rem_1; -wire [31:0] cur_rem_2; -wire [31:0] div_qt_1_rem_add_op1; -wire [31:0] div_qt_2_rem_add_op1; -wire [31:0] div_qt_r1_rem_add_op1; -wire [31:0] div_qt_r2_rem_add_op1; -wire [23:0] ex1_divisor; -wire ex1_ex2_pipe_clk; -wire ex1_ex2_pipe_clk_en; -wire [12:0] ex1_expnt_adder_op1; -wire [51:0] ex1_oper_id_frac; -wire [51:0] ex1_oper_id_frac_f; -wire ex1_pipedown; -wire ex1_pipedown_gate; -wire [31:0] ex1_remainder; -wire ex1_save_op0; -wire ex1_save_op0_gate; -wire ex2_div_of; -wire ex2_div_uf; -wire [9 :0] ex2_expnt_adder_op0; -wire [9 :0] ex2_expnt_adder_op1; -wire ex2_expnt_of; -wire [9 :0] ex2_expnt_result; -wire ex2_expnt_uf; -wire ex2_id_nor_srt_skip; -wire ex2_of; -wire ex2_of_plus; -wire ex2_pipe_clk; -wire ex2_pipedown; -wire ex2_potnt_of; -wire ex2_potnt_of_pre; -wire ex2_potnt_uf; -wire ex2_potnt_uf_pre; -wire ex2_result_inf; -wire ex2_result_lfn; -wire ex2_rslt_denorm; -wire [9 :0] ex2_sqrt_expnt_result; -wire [9 :0] ex2_srt_expnt_rst; -wire ex2_srt_first_round; -wire ex2_uf; -wire ex2_uf_plus; -wire ex2_uf_srt_skip; -wire [25:0] ex3_frac_final_rst; -wire ex3_pipedown; -wire fdsu_ex2_div; -wire [9 :0] fdsu_ex2_expnt_rst; -wire fdsu_ex2_of_rm_lfn; -wire fdsu_ex2_op0_norm; -wire fdsu_ex2_op1_norm; -wire fdsu_ex2_result_lfn; -wire fdsu_ex2_sqrt; -wire [25:0] fdsu_ex4_frac; -wire fdsu_yy_div; -wire fdsu_yy_of_rm_lfn; -wire fdsu_yy_op0_norm; -wire fdsu_yy_op1_norm; -wire fdsu_yy_sqrt; -wire forever_cpuclk; -wire pad_yy_icg_scan_en; -wire qt_clk; -wire qt_clk_en; -wire [29:0] qt_rt_const_pre_sel_q1; -wire [29:0] qt_rt_const_pre_sel_q2; -wire [29:0] qt_rt_const_q1; -wire [29:0] qt_rt_const_q2; -wire [29:0] qt_rt_const_q3; -wire [29:0] qt_rt_const_shift_std_next; -wire [29:0] qt_rt_mins_const_pre_sel_q1; -wire [29:0] qt_rt_mins_const_pre_sel_q2; -wire rem_sign; -wire [31:0] sqrt_qt_1_rem_add_op1; -wire [31:0] sqrt_qt_2_rem_add_op1; -wire [31:0] sqrt_qt_r1_rem_add_op1; -wire [31:0] sqrt_qt_r2_rem_add_op1; -wire srt_div_clk; -wire srt_div_clk_en; -wire [31:0] srt_remainder_nxt; -wire [31:0] srt_remainder_shift; -wire srt_remainder_sign; -wire srt_remainder_zero; -wire srt_sm_on; -wire [29:0] total_qt_rt_pre_sel; - - -assign fdsu_ex2_div = fdsu_yy_div; -assign fdsu_ex2_sqrt = fdsu_yy_sqrt; -assign fdsu_ex2_op0_norm = fdsu_yy_op0_norm; -assign fdsu_ex2_op1_norm = fdsu_yy_op1_norm; -assign fdsu_ex2_of_rm_lfn = fdsu_yy_of_rm_lfn; -assign fdsu_ex2_result_lfn = 1'b0; - -//========================================================== -// EX2 Expnt Generate -//========================================================== -//expnt0 sub expnt1 -assign ex2_expnt_result[9:0] = ex2_expnt_adder_op0[9:0] - - ex2_expnt_adder_op1[9:0]; - -//===================sqrt exponent prepare================== -//sqrt exponent prepare -//afert E sub, div E by 2 -assign ex2_sqrt_expnt_result[9:0] = {ex2_expnt_result[9], - ex2_expnt_result[9:1]}; - -assign ex2_srt_expnt_rst[9:0] = (fdsu_ex2_sqrt) - ? ex2_sqrt_expnt_result[9:0] - : ex2_expnt_result[9:0]; -// &Force("output", "ex2_srt_expnt_rst"); &Force("bus", "ex2_srt_expnt_rst", 9, 0); @51 -assign fdsu_ex2_expnt_rst[9:0] = ex2_srt_expnt_rst[9:0]; +// &Ports; @23 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input ex1_div; +input [52:0] ex1_divisor; +input ex1_pipedown; +input [59:0] ex1_remainder; +input ex1_sqrt; +input ex2_pipedown; +input ex2_srt_first_round; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input srt_secd_round; +input srt_sm_on; +input vfdsu_ex2_div; +input vfdsu_ex2_double; +input vfdsu_ex2_dz; +input [12:0] vfdsu_ex2_expnt_add0; +input [12:0] vfdsu_ex2_expnt_add1; +input vfdsu_ex2_nv; +input vfdsu_ex2_of_rm_lfn; +input vfdsu_ex2_op0_norm; +input vfdsu_ex2_op1_norm; +input [51:0] vfdsu_ex2_qnan_f; +input vfdsu_ex2_qnan_sign; +input vfdsu_ex2_result_inf; +input vfdsu_ex2_result_qnan; +input vfdsu_ex2_result_sign; +input vfdsu_ex2_result_zero; +input [2 :0] vfdsu_ex2_rm; +input vfdsu_ex2_single; +input vfdsu_ex2_half; +input vfdsu_ex2_bfloat; +input vfdsu_ex2_sqrt; +input vfdsu_ex2_srt_skip; +output srt_ctrl_rem_zero; +output srt_ctrl_skip_srt; +output [57:0] total_qt_rt_58; +output [12:0] vfdsu_ex3_doub_expnt_rst; +output vfdsu_ex3_double; +output vfdsu_ex3_dz; +output [12:0] vfdsu_ex3_half_expnt_rst; +output [12:0] vfdsu_ex3_bfloat_expnt_rst; +output vfdsu_ex3_id_srt_skip; +output vfdsu_ex3_nv; +output vfdsu_ex3_of; +output vfdsu_ex3_potnt_of; +output vfdsu_ex3_potnt_uf; +output [51:0] vfdsu_ex3_qnan_f; +output vfdsu_ex3_qnan_sign; +output vfdsu_ex3_rem_sign; +output vfdsu_ex3_rem_zero; +output [52:0] vfdsu_ex3_result_denorm_round_add_num; +output vfdsu_ex3_result_inf; +output vfdsu_ex3_result_lfn; +output vfdsu_ex3_result_qnan; +output vfdsu_ex3_result_sign; +output vfdsu_ex3_result_zero; +output [2 :0] vfdsu_ex3_rm; +output vfdsu_ex3_rslt_denorm; +output [8 :0] vfdsu_ex3_sing_expnt_rst; +output vfdsu_ex3_single; +output vfdsu_ex3_half; +output vfdsu_ex3_bfloat; +output vfdsu_ex3_uf; + +// &Regs; @24 +reg [52:0] ex2_result_double_denorm_round_add_num; +reg [52:0] ex2_result_half_denorm_round_add_num; +reg [52:0] ex2_result_single_denorm_round_add_num; +reg [52:0] ex2_result_bfloat_denorm_round_add_num; +reg [12:0] vfdsu_ex3_doub_expnt_rst; +reg vfdsu_ex3_double; +reg vfdsu_ex3_dz; +reg [12:0] vfdsu_ex3_half_expnt_rst; +reg [12:0] vfdsu_ex3_bfloat_expnt_rst; +reg vfdsu_ex3_id_srt_skip; +reg vfdsu_ex3_nv; +reg vfdsu_ex3_of; +reg vfdsu_ex3_potnt_of; +reg vfdsu_ex3_potnt_uf; +reg [51:0] vfdsu_ex3_qnan_f; +reg vfdsu_ex3_qnan_sign; +reg vfdsu_ex3_rem_sign; +reg [52:0] vfdsu_ex3_result_denorm_round_add_num; +reg vfdsu_ex3_result_inf; +reg vfdsu_ex3_result_lfn; +reg vfdsu_ex3_result_qnan; +reg vfdsu_ex3_result_sign; +reg vfdsu_ex3_result_zero; +reg [2 :0] vfdsu_ex3_rm; +reg vfdsu_ex3_rslt_denorm; +reg [8 :0] vfdsu_ex3_sing_expnt_rst; +reg vfdsu_ex3_single; +reg vfdsu_ex3_half; +reg vfdsu_ex3_bfloat; +reg vfdsu_ex3_uf; + +// &Wires; @25 +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire ex1_div; +wire [52:0] ex1_divisor; +wire ex1_pipedown; +wire [59:0] ex1_remainder; +wire ex1_sqrt; +wire ex2_div_of; +wire ex2_div_uf; +wire ex2_doub_expnt_of; +wire ex2_doub_expnt_uf; +wire ex2_doub_potnt_of; +wire ex2_doub_potnt_uf; +wire ex2_double_id_nor_srt_skip; +wire ex2_expnt_of; +wire [12:0] ex2_expnt_result; +wire ex2_expnt_uf; +wire ex2_half_expnt_of; +wire ex2_half_expnt_uf; +wire ex2_half_id_nor_srt_skip; +wire ex2_half_potnt_of; +wire ex2_half_potnt_uf; +wire ex2_bfloat_expnt_of; +wire ex2_bfloat_expnt_uf; +wire ex2_bfloat_id_nor_srt_skip; +wire ex2_bfloat_potnt_of; +wire ex2_bfloat_potnt_uf; +wire ex2_id_nor_srt_skip; +wire ex2_of; +wire ex2_of_plus; +wire ex2_pipe_clk; +wire ex2_pipe_clk_en; +wire ex2_pipedown; +wire ex2_potnt_of; +wire ex2_potnt_of_pre; +wire ex2_potnt_uf; +wire ex2_potnt_uf_pre; +wire [52:0] ex2_result_denorm_round_add_num; +wire ex2_result_inf; +wire ex2_result_lfn; +wire ex2_result_qnan; +wire ex2_result_zero; +wire ex2_rslt_denorm; +wire ex2_sing_expnt_of; +wire ex2_sing_expnt_uf; +wire ex2_sing_potnt_of; +wire ex2_sing_potnt_uf; +wire ex2_single_id_nor_srt_skip; +wire [12:0] ex2_sqrt_expnt_result; +wire ex2_srt_first_round; +wire ex2_uf; +wire ex2_uf_plus; +wire forever_cpuclk; +wire [6 :0] initial_bound_sel_in; +wire [55:0] initial_divisor_in; +wire [60:0] initial_remainder_in; +wire initial_srt_en; +wire initial_srt_sel_div_in; +wire initial_srt_sel_sqrt_in; +wire pad_yy_icg_scan_en; +wire srt_ctrl_rem_zero; +wire srt_ctrl_skip_srt; +wire srt_first_round; +wire [60:0] srt_remainder; +wire [59:0] srt_remainder_out; +wire srt_remainder_sign; +wire srt_secd_round; +wire srt_sm_on; +wire [57:0] total_qt_rt; +wire [57:0] total_qt_rt_58; +wire [57:0] vdiv_qt_rt; +wire vfdsu_ex2_div; +wire vfdsu_ex2_double; +wire vfdsu_ex2_dz; +wire [12:0] vfdsu_ex2_expnt_add0; +wire [12:0] vfdsu_ex2_expnt_add1; +wire [12:0] vfdsu_ex2_expnt_rst; +wire vfdsu_ex2_nv; +wire vfdsu_ex2_of_rm_lfn; +wire vfdsu_ex2_op0_norm; +wire vfdsu_ex2_op1_norm; +wire [51:0] vfdsu_ex2_qnan_f; +wire vfdsu_ex2_qnan_sign; +wire vfdsu_ex2_result_inf; +wire vfdsu_ex2_result_qnan; +wire vfdsu_ex2_result_sign; +wire vfdsu_ex2_result_zero; +wire [2 :0] vfdsu_ex2_rm; +wire vfdsu_ex2_single; +wire vfdsu_ex2_half; +wire vfdsu_ex2_bfloat; +wire vfdsu_ex2_sqrt; +wire vfdsu_ex2_srt_skip; +wire vfdsu_ex3_rem_zero; //====================EX2 Expt info========================= @@ -25071,1047 +30522,1648 @@ assign fdsu_ex2_expnt_rst[9:0] = ex2_srt_expnt_rst[9:0]; //EX2 will deal with other condition //When input is normal, overflow when E1-E2 > 128/1024 -assign ex2_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8] - || (fdsu_ex2_expnt_rst[7] && - |fdsu_ex2_expnt_rst[6:0])); +//here we mov the expnt result calculation into second stage + +assign vfdsu_ex2_expnt_rst[12:0] = (vfdsu_ex2_sqrt) + ? ex2_sqrt_expnt_result[12:0] + : ex2_expnt_result[12:0]; +assign ex2_sqrt_expnt_result[12:0] = {ex2_expnt_result[12], + ex2_expnt_result[12:1]}; +assign ex2_expnt_result[12:0] = vfdsu_ex2_expnt_add0[12:0] - vfdsu_ex2_expnt_add1[12:0]; +assign ex2_doub_expnt_of = ~vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11] + || (vfdsu_ex2_expnt_rst[10] && + |vfdsu_ex2_expnt_rst[9:0])); +assign ex2_sing_expnt_of = ~vfdsu_ex2_expnt_rst[9] && (vfdsu_ex2_expnt_rst[8] + || (vfdsu_ex2_expnt_rst[7] && + |vfdsu_ex2_expnt_rst[6:0])); + +assign ex2_half_expnt_of = ~vfdsu_ex2_expnt_rst[6] && (vfdsu_ex2_expnt_rst[5] + || (vfdsu_ex2_expnt_rst[4] && + |vfdsu_ex2_expnt_rst[3:0])); +assign ex2_bfloat_expnt_of = ~vfdsu_ex2_expnt_rst[9] && (vfdsu_ex2_expnt_rst[8] + || (vfdsu_ex2_expnt_rst[7] && + |vfdsu_ex2_expnt_rst[6:0])); +assign ex2_expnt_of = vfdsu_ex2_double ? ex2_doub_expnt_of : + vfdsu_ex2_single ? ex2_sing_expnt_of : + vfdsu_ex2_half ? ex2_half_expnt_of : ex2_bfloat_expnt_of; +assign ex2_potnt_of_pre = vfdsu_ex2_double ? ex2_doub_potnt_of : + vfdsu_ex2_single ? ex2_sing_potnt_of : + vfdsu_ex2_half ? ex2_half_potnt_of : ex2_bfloat_potnt_of; +assign ex2_potnt_uf_pre = vfdsu_ex2_double ? ex2_doub_potnt_uf : + vfdsu_ex2_single ? ex2_sing_potnt_uf : + vfdsu_ex2_half ? ex2_half_potnt_uf : ex2_bfloat_potnt_uf; +assign ex2_expnt_uf = vfdsu_ex2_double ? ex2_doub_expnt_uf : + vfdsu_ex2_single ? ex2_sing_expnt_uf : + vfdsu_ex2_half ? ex2_half_expnt_uf : ex2_bfloat_expnt_uf; +assign ex2_id_nor_srt_skip = vfdsu_ex2_double ? ex2_double_id_nor_srt_skip : + vfdsu_ex2_single ? ex2_single_id_nor_srt_skip : + vfdsu_ex2_half ? ex2_half_id_nor_srt_skip : ex2_bfloat_id_nor_srt_skip; +assign ex2_result_denorm_round_add_num[52:0] = vfdsu_ex2_double ? + ex2_result_double_denorm_round_add_num[52:0] : + vfdsu_ex2_single ? + ex2_result_single_denorm_round_add_num[52:0] : + vfdsu_ex2_half ? + ex2_result_half_denorm_round_add_num[52:0] : + ex2_result_bfloat_denorm_round_add_num[52:0]; + + //potential overflow when E1-E2 = 128/1024 -assign ex2_potnt_of_pre = ~fdsu_ex2_expnt_rst[9] && - ~fdsu_ex2_expnt_rst[8] && - fdsu_ex2_expnt_rst[7] && - ~|fdsu_ex2_expnt_rst[6:0]; -assign ex2_potnt_of = ex2_potnt_of_pre && - fdsu_ex2_op0_norm && - fdsu_ex2_op1_norm && - fdsu_ex2_div; - -//When input is normal, underflow when E1-E2 <= -127/-1023 -assign ex2_expnt_uf = fdsu_ex2_expnt_rst[9] &&(fdsu_ex2_expnt_rst[8:0] <= 9'h181); +assign ex2_doub_potnt_of = ~vfdsu_ex2_expnt_rst[12] && + ~vfdsu_ex2_expnt_rst[11] && + vfdsu_ex2_expnt_rst[10] && + ~|vfdsu_ex2_expnt_rst[9:0]; +assign ex2_sing_potnt_of = ~vfdsu_ex2_expnt_rst[9] && + ~vfdsu_ex2_expnt_rst[8] && + vfdsu_ex2_expnt_rst[7] && + ~|vfdsu_ex2_expnt_rst[6:0]; +assign ex2_half_potnt_of = ~vfdsu_ex2_expnt_rst[6] && + ~vfdsu_ex2_expnt_rst[5] && + vfdsu_ex2_expnt_rst[4] && + ~|vfdsu_ex2_expnt_rst[3:0]; +assign ex2_bfloat_potnt_of = ~vfdsu_ex2_expnt_rst[9] && + ~vfdsu_ex2_expnt_rst[8] && + vfdsu_ex2_expnt_rst[7] && + ~|vfdsu_ex2_expnt_rst[6:0]; +assign ex2_potnt_of = ex2_potnt_of_pre && + vfdsu_ex2_op0_norm && + vfdsu_ex2_op1_norm && + vfdsu_ex2_div; + +//When input is normal, underflow when E1-E2 <= -127/-1023/-15 +assign ex2_doub_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hc01); +assign ex2_sing_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hf81); +assign ex2_bfloat_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hf81); +assign ex2_half_expnt_uf = vfdsu_ex2_expnt_rst[12] && (vfdsu_ex2_expnt_rst[11:0] <= 12'hff1); +assign ex2_half_potnt_uf = &vfdsu_ex2_expnt_rst[6:4] && + ~|vfdsu_ex2_expnt_rst[3:2] && + vfdsu_ex2_expnt_rst[1] && + !vfdsu_ex2_expnt_rst[0]; + + //potential underflow when E1-E2 = -126/-1022 -assign ex2_potnt_uf_pre = &fdsu_ex2_expnt_rst[9:7] && - ~|fdsu_ex2_expnt_rst[6:2] && - fdsu_ex2_expnt_rst[1] && - !fdsu_ex2_expnt_rst[0]; -assign ex2_potnt_uf = (ex2_potnt_uf_pre && - fdsu_ex2_op0_norm && - fdsu_ex2_op1_norm && - fdsu_ex2_div) || - (ex2_potnt_uf_pre && - fdsu_ex2_op0_norm); +assign ex2_doub_potnt_uf = &vfdsu_ex2_expnt_rst[12:10] && + ~|vfdsu_ex2_expnt_rst[9:2] && + vfdsu_ex2_expnt_rst[1] && + !vfdsu_ex2_expnt_rst[0]; +assign ex2_sing_potnt_uf = &vfdsu_ex2_expnt_rst[9:7] && + ~|vfdsu_ex2_expnt_rst[6:2] && + vfdsu_ex2_expnt_rst[1] && + !vfdsu_ex2_expnt_rst[0]; +assign ex2_bfloat_potnt_uf = &vfdsu_ex2_expnt_rst[9:7] && + ~|vfdsu_ex2_expnt_rst[6:2] && + vfdsu_ex2_expnt_rst[1] && + !vfdsu_ex2_expnt_rst[0]; + +assign ex2_potnt_uf = (ex2_potnt_uf_pre && + vfdsu_ex2_op0_norm && + vfdsu_ex2_op1_norm && + vfdsu_ex2_div) || + (ex2_potnt_uf_pre && + vfdsu_ex2_op0_norm); //========================EX2 Overflow====================== -//ex2 overflow when +//ex2 overflow when // 1.op0 & op1 both norm && expnt overflow // 2.ex1_id_of -// &Force("output","ex2_of"); @91 assign ex2_of = ex2_of_plus; -assign ex2_of_plus = ex2_div_of && fdsu_ex2_div; -assign ex2_div_of = fdsu_ex2_op0_norm && - fdsu_ex2_op1_norm && +assign ex2_of_plus = ex2_div_of && vfdsu_ex2_div; +assign ex2_div_of = vfdsu_ex2_op0_norm && + vfdsu_ex2_op1_norm && ex2_expnt_of; //=======================EX2 Underflow====================== -//ex2 underflow when +//ex2 underflow when // 1.op0 & op1 both norm && expnt underflow // 2.ex1_id_uf // and detect when to skip the srt, here, we have further optmization assign ex2_uf = ex2_uf_plus; -assign ex2_uf_plus = ex2_div_uf && fdsu_ex2_div; -assign ex2_div_uf = fdsu_ex2_op0_norm && - fdsu_ex2_op1_norm && +assign ex2_uf_plus = ex2_div_uf && vfdsu_ex2_div; +assign ex2_div_uf = vfdsu_ex2_op0_norm && + vfdsu_ex2_op1_norm && ex2_expnt_uf; -assign ex2_id_nor_srt_skip = fdsu_ex2_expnt_rst[9] - && (fdsu_ex2_expnt_rst[8:0]<9'h16a); -assign ex2_uf_srt_skip = ex2_id_nor_srt_skip; +assign ex2_double_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12] + && (vfdsu_ex2_expnt_rst[11:0]<12'hbcd); +assign ex2_single_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12] + && (vfdsu_ex2_expnt_rst[11:0]<12'hf6a); +assign ex2_half_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12] + && (vfdsu_ex2_expnt_rst[11:0]<12'hfe7); +assign ex2_bfloat_id_nor_srt_skip = vfdsu_ex2_expnt_rst[12] + && (vfdsu_ex2_expnt_rst[11:0]<12'hf6a); assign ex2_rslt_denorm = ex2_uf; + +//=======================EX2 skip srt iteration====================== +assign srt_ctrl_skip_srt = ex2_of || ex2_id_nor_srt_skip + || vfdsu_ex2_srt_skip; //===============ex2 round prepare for denormal round====== -// &CombBeg; @113 -always @( fdsu_ex2_expnt_rst[9:0]) +// &CombBeg; @146 +always @( vfdsu_ex2_expnt_rst[12:0]) begin -case(fdsu_ex2_expnt_rst[9:0]) - 10'h382:ex2_result_denorm_round_add_num[23:0] = 24'h1; //-126 1 - 10'h381:ex2_result_denorm_round_add_num[23:0] = 24'h2; //-127 0 - 10'h380:ex2_result_denorm_round_add_num[23:0] = 24'h4; //-128 -1 - 10'h37f:ex2_result_denorm_round_add_num[23:0] = 24'h8; //-129 -2 - 10'h37e:ex2_result_denorm_round_add_num[23:0] = 24'h10; //-130 -3 - 10'h37d:ex2_result_denorm_round_add_num[23:0] = 24'h20; //-131 -4 - 10'h37c:ex2_result_denorm_round_add_num[23:0] = 24'h40; //-132 -5 - 10'h37b:ex2_result_denorm_round_add_num[23:0] = 24'h80; //-133 -6 - 10'h37a:ex2_result_denorm_round_add_num[23:0] = 24'h100; //-134 -7 - 10'h379:ex2_result_denorm_round_add_num[23:0] = 24'h200; //-135 -8 - 10'h378:ex2_result_denorm_round_add_num[23:0] = 24'h400; //-136 -9 - 10'h377:ex2_result_denorm_round_add_num[23:0] = 24'h800; //-137 -10 - 10'h376:ex2_result_denorm_round_add_num[23:0] = 24'h1000; //-138 -11 - 10'h375:ex2_result_denorm_round_add_num[23:0] = 24'h2000; //-139 -12 - 10'h374:ex2_result_denorm_round_add_num[23:0] = 24'h4000; //-140 -13 - 10'h373:ex2_result_denorm_round_add_num[23:0] = 24'h8000; // -141 -14 - 10'h372:ex2_result_denorm_round_add_num[23:0] = 24'h10000;//-142 -15 - 10'h371:ex2_result_denorm_round_add_num[23:0] = 24'h20000;//-143 -16 - 10'h370:ex2_result_denorm_round_add_num[23:0] = 24'h40000; //-144 -17 - 10'h36f:ex2_result_denorm_round_add_num[23:0] = 24'h80000; //-145 -18 - 10'h36e:ex2_result_denorm_round_add_num[23:0] = 24'h100000; //-146 -19 - 10'h36d:ex2_result_denorm_round_add_num[23:0] = 24'h200000; //-147 -20 - 10'h36c:ex2_result_denorm_round_add_num[23:0] = 24'h400000; //-148 -21 - 10'h36b:ex2_result_denorm_round_add_num[23:0] = 24'h800000; //-148 -22 - default: ex2_result_denorm_round_add_num[23:0] = 24'h0; // -23 +case(vfdsu_ex2_expnt_rst[12:0]) + 13'h1c02:ex2_result_double_denorm_round_add_num[52:0] = 53'h1; //-1022 1 + 13'h1c01:ex2_result_double_denorm_round_add_num[52:0] = 53'h2; //-1023 0 + 13'h1c00:ex2_result_double_denorm_round_add_num[52:0] = 53'h4; //-1024 -1 + 13'h1bff:ex2_result_double_denorm_round_add_num[52:0] = 53'h8; //-1025 -2 + 13'h1bfe:ex2_result_double_denorm_round_add_num[52:0] = 53'h10; //-1026 -3 + 13'h1bfd:ex2_result_double_denorm_round_add_num[52:0] = 53'h20; //-1027 -4 + 13'h1bfc:ex2_result_double_denorm_round_add_num[52:0] = 53'h40; //-1028 -5 + 13'h1bfb:ex2_result_double_denorm_round_add_num[52:0] = 53'h80; //-1029 -6 + 13'h1bfa:ex2_result_double_denorm_round_add_num[52:0] = 53'h100; //-1030 -7 + 13'h1bf9:ex2_result_double_denorm_round_add_num[52:0] = 53'h200; //-1031 -8 + 13'h1bf8:ex2_result_double_denorm_round_add_num[52:0] = 53'h400; //-1032 -9 + 13'h1bf7:ex2_result_double_denorm_round_add_num[52:0] = 53'h800; //-1033 -10 + 13'h1bf6:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000; //-1034 -11 + 13'h1bf5:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000; //-1035 -12 + 13'h1bf4:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000; //-1036 -13 + 13'h1bf3:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000; // -1037 + 13'h1bf2:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000;//-1038 + 13'h1bf1:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000;//-1039 + 13'h1bf0:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000; //-1040 + 13'h1bef:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000; //-1041 + 13'h1bee:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000; //-1042 + 13'h1bed:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000; //-1043 + 13'h1bec:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000; //-1044 + 13'h1beb:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000; //-1045 + 13'h1bea:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000;//-1046 + 13'h1be9:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000;//-1047 + 13'h1be8:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000; //-1048 + 13'h1be7:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000; //-1049 + 13'h1be6:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000;//-1050 + 13'h1be5:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000; //-1051 + 13'h1be4:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000; //-1052 + 13'h1be3:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000; //-1053 + 13'h1be2:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000; //-1054 + 13'h1be1:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000; //-1055 + 13'h1be0:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000; //-1056 + 13'h1bdf:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000; //-1057 + 13'h1bde:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000; //-1058 + 13'h1bdd:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000; //-1059 + 13'h1bdc:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000; //-1060 + 13'h1bdb:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000; //-1061 + 13'h1bda:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000; //-1062 + 13'h1bd9:ex2_result_double_denorm_round_add_num[52:0] = 53'h20000000000; //-1063 + 13'h1bd8:ex2_result_double_denorm_round_add_num[52:0] = 53'h40000000000; //-1064 + 13'h1bd7:ex2_result_double_denorm_round_add_num[52:0] = 53'h80000000000; //-1065 + 13'h1bd6:ex2_result_double_denorm_round_add_num[52:0] = 53'h100000000000; //-1066 + 13'h1bd5:ex2_result_double_denorm_round_add_num[52:0] = 53'h200000000000; //-1067 + 13'h1bd4:ex2_result_double_denorm_round_add_num[52:0] = 53'h400000000000; //-1068 + 13'h1bd3:ex2_result_double_denorm_round_add_num[52:0] = 53'h800000000000; //-1069 + 13'h1bd2:ex2_result_double_denorm_round_add_num[52:0] = 53'h1000000000000;//-1070 + 13'h1bd1:ex2_result_double_denorm_round_add_num[52:0] = 53'h2000000000000; //-1071 + 13'h1bd0:ex2_result_double_denorm_round_add_num[52:0] = 53'h4000000000000; //-1072 + 13'h1bcf:ex2_result_double_denorm_round_add_num[52:0] = 53'h8000000000000; //-1073 + 13'h1bce:ex2_result_double_denorm_round_add_num[52:0] = 53'h10000000000000; //-1073 + default: ex2_result_double_denorm_round_add_num[52:0] = 53'h0; endcase -// &CombEnd; @141 +// &CombEnd; @203 end - -//===================special result======================== -assign ex2_result_inf = ex2_of_plus && !fdsu_ex2_of_rm_lfn; -assign ex2_result_lfn = fdsu_ex2_result_lfn || - ex2_of_plus && fdsu_ex2_of_rm_lfn; - - - -//====================Pipe to EX3=========================== -always @(posedge ex1_ex2_pipe_clk) +// &CombBeg; @204 +always @( vfdsu_ex2_expnt_rst[12:0]) begin - if(ex1_pipedown) - begin - fdsu_ex3_result_denorm_round_add_num[23:0] - <= {14'b0, ex1_expnt_adder_op1[9:0]}; - end - else if(ex2_pipedown) - begin - fdsu_ex3_result_denorm_round_add_num[23:0] - <= ex2_result_denorm_round_add_num[23:0]; - end - else - begin - fdsu_ex3_result_denorm_round_add_num[23:0] - <= fdsu_ex3_result_denorm_round_add_num[23:0]; - end +case(vfdsu_ex2_expnt_rst[12:0]) + 13'h1f82:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000; //-126 1 + 13'h1f81:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000; //-127 0 + 13'h1f80:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000; //-128 -1 + 13'h1f7f:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000; //-129 -2 + 13'h1f7e:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000; //-130 -3 + 13'h1f7d:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000; //-131 -4 + 13'h1f7c:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000; //-132 -5 + 13'h1f7b:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000; //-133 -6 + 13'h1f7a:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000; //-134 -7 + 13'h1f79:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000; //-135 -8 + 13'h1f78:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000; //-136 -9 + 13'h1f77:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000; //-137 -10 + 13'h1f76:ex2_result_single_denorm_round_add_num[52:0] = 53'h20000000000; //-138 -11 + 13'h1f75:ex2_result_single_denorm_round_add_num[52:0] = 53'h40000000000; //-139 -12 + 13'h1f74:ex2_result_single_denorm_round_add_num[52:0] = 53'h80000000000; //-140 -13 + 13'h1f73:ex2_result_single_denorm_round_add_num[52:0] = 53'h100000000000; // -141 -14 + 13'h1f72:ex2_result_single_denorm_round_add_num[52:0] = 53'h200000000000;//-142 -15 + 13'h1f71:ex2_result_single_denorm_round_add_num[52:0] = 53'h400000000000;//-143 -16 + 13'h1f70:ex2_result_single_denorm_round_add_num[52:0] = 53'h800000000000; //-144 -17 + 13'h1f6f:ex2_result_single_denorm_round_add_num[52:0] = 53'h1000000000000; //-145 -18 + 13'h1f6e:ex2_result_single_denorm_round_add_num[52:0] = 53'h2000000000000; //-146 -19 + 13'h1f6d:ex2_result_single_denorm_round_add_num[52:0] = 53'h4000000000000; //-147 -20 + 13'h1f6c:ex2_result_single_denorm_round_add_num[52:0] = 53'h8000000000000; //-148 -21 + 13'h1f6b:ex2_result_single_denorm_round_add_num[52:0] = 53'h10000000000000; //-148 -22 + default: ex2_result_single_denorm_round_add_num[52:0] = 53'h0; // -23 +endcase +// &CombEnd; @232 end -assign ex2_expnt_adder_op1 = fdsu_ex3_result_denorm_round_add_num[9:0]; -// &Force("bus", "ex1_expnt_adder_op1", 12, 0); @193 - -assign ex1_ex2_pipe_clk_en = ex1_pipedown_gate || ex2_pipedown; -// &Instance("gated_clk_cell", "x_ex1_ex2_pipe_clk"); @196 -gated_clk_cell x_ex1_ex2_pipe_clk ( - .clk_in (forever_cpuclk ), - .clk_out (ex1_ex2_pipe_clk ), - .external_en (1'b0 ), - .global_en (cp0_yy_clk_en ), - .local_en (ex1_ex2_pipe_clk_en), - .module_en (cp0_fpu_icg_en ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en ) -); - -// &Connect(.clk_in (forever_cpuclk), @197 -// .external_en (1'b0), @198 -// .global_en (cp0_yy_clk_en), @199 -// .module_en (cp0_fpu_icg_en), @200 -// .local_en (ex1_ex2_pipe_clk_en), @201 -// .clk_out (ex1_ex2_pipe_clk)); @202 - -always @(posedge ex2_pipe_clk) +// &CombBeg; @233 +always @( vfdsu_ex2_expnt_rst[12:0]) begin - if(ex2_pipedown) - begin - fdsu_ex3_rem_sign <= srt_remainder_sign; - fdsu_ex3_rem_zero <= srt_remainder_zero; - fdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip; - end - else - begin - fdsu_ex3_rem_sign <= fdsu_ex3_rem_sign; - fdsu_ex3_rem_zero <= fdsu_ex3_rem_zero; - fdsu_ex3_id_srt_skip <= fdsu_ex3_id_srt_skip; - end +case(vfdsu_ex2_expnt_rst[12:0]) + 13'h1ff2:ex2_result_half_denorm_round_add_num[52:0] = 53'h40000000000; //-14 1 + 13'h1ff1:ex2_result_half_denorm_round_add_num[52:0] = 53'h80000000000; //-15 0 + 13'h1ff0:ex2_result_half_denorm_round_add_num[52:0] = 53'h100000000000; //-16 -1 + 13'h1fef:ex2_result_half_denorm_round_add_num[52:0] = 53'h200000000000; //-17 -2 + 13'h1fee:ex2_result_half_denorm_round_add_num[52:0] = 53'h400000000000; //-18 -3 + 13'h1fed:ex2_result_half_denorm_round_add_num[52:0] = 53'h800000000000; //-19 -4 + 13'h1fec:ex2_result_half_denorm_round_add_num[52:0] = 53'h1000000000000; //-20 -5 + 13'h1feb:ex2_result_half_denorm_round_add_num[52:0] = 53'h2000000000000; //-21 -6 + 13'h1fea:ex2_result_half_denorm_round_add_num[52:0] = 53'h4000000000000; //-22 -7 + 13'h1fe9:ex2_result_half_denorm_round_add_num[52:0] = 53'h8000000000000; //-23 -8 + 13'h1fe8:ex2_result_half_denorm_round_add_num[52:0] = 53'h10000000000000; //-24 -9 + default: ex2_result_half_denorm_round_add_num[52:0] = 53'h0; // -23 +endcase +// &CombEnd; @248 end -// &Force("output","fdsu_ex3_rem_sign"); @243 -// &Force("output","fdsu_ex3_rem_zero"); @244 -// &Force("output","fdsu_ex3_result_denorm_round_add_num"); @245 -// &Force("output","fdsu_ex3_id_srt_skip"); @246 - -//========================================================== -// SRT Remainder & Divisor for Quotient/Root Generate -//========================================================== - -//===================Remainder Generate===================== -//gate clk -// &Instance("gated_clk_cell","x_srt_rem_clk"); -// // &Connect( .clk_in (forever_cpuclk), @255 -// // .clk_out (srt_rem_clk),//Out Clock @256 -// // .external_en (1'b0), @257 -// // .global_en (cp0_yy_clk_en), @258 -// // .local_en (srt_rem_clk_en),//Local Condition @259 -// // .module_en (cp0_fpu_icg_en) @260 -// // ); @261 -// assign srt_rem_clk_en = ex1_pipedown || -// srt_sm_on; - -always @(posedge qt_clk) +always @( vfdsu_ex2_expnt_rst[12:0]) begin - if (ex1_pipedown) - srt_remainder[31:0] <= ex1_remainder[31:0]; - else if (srt_sm_on) - srt_remainder[31:0] <= srt_remainder_nxt[31:0]; - else - srt_remainder[31:0] <= srt_remainder[31:0]; +case(vfdsu_ex2_expnt_rst[12:0]) + 13'h1f82:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h200000000000; //-126 1 + 13'h1f81:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h400000000000; //-127 0 + 13'h1f80:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h800000000000; //-128 -1 + 13'h1f7f:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h1000000000000; //-129 -2 + 13'h1f7e:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h2000000000000; //-130 -3 + 13'h1f7d:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h4000000000000; //-131 -4 + 13'h1f7c:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h8000000000000; //-132 -5 + 13'h1f7b:ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h10000000000000; //-133 -6 + default: ex2_result_bfloat_denorm_round_add_num[52:0] = 53'h0; // -23 +endcase end -//=====================Divisor Generate===================== -//gate clk -// &Instance("gated_clk_cell","x_srt_div_clk"); @291 -gated_clk_cell x_srt_div_clk ( - .clk_in (forever_cpuclk ), - .clk_out (srt_div_clk ), - .external_en (1'b0 ), - .global_en (cp0_yy_clk_en ), - .local_en (srt_div_clk_en ), - .module_en (cp0_fpu_icg_en ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en) -); +//===================special result======================== +assign ex2_result_zero = vfdsu_ex2_result_zero; +assign ex2_result_qnan = vfdsu_ex2_result_qnan; +assign ex2_result_inf = vfdsu_ex2_result_inf || + ex2_of_plus && !vfdsu_ex2_of_rm_lfn; +assign ex2_result_lfn = + ex2_of_plus && vfdsu_ex2_of_rm_lfn; -// &Connect( .clk_in (forever_cpuclk), @292 -// .clk_out (srt_div_clk),//Out Clock @293 -// .external_en (1'b0), @294 -// .global_en (cp0_yy_clk_en), @295 -// .local_en (srt_div_clk_en),//Local Condition @296 -// .module_en (cp0_fpu_icg_en) @297 -// ); @298 -assign srt_div_clk_en = ex1_pipedown_gate - || ex1_save_op0_gate - || ex3_pipedown; -// final_rst saved in srt_divisor. -// srt_divisor is 26 bits, final_rst is 24 bits. -always @(posedge srt_div_clk) -begin - if (ex1_save_op0) - srt_divisor[25:0] <= {3'b0, {ex1_oper_id_frac[51:29]}}; - else if (ex1_pipedown) - srt_divisor[25:0] <= {2'b0, ex1_divisor[23:0]}; - else if (ex3_pipedown) - srt_divisor[25:0] <= ex3_frac_final_rst[25:0]; - else - srt_divisor[25:0] <= srt_divisor[25:0]; -end -assign ex1_oper_id_frac_f[51:0] = {srt_divisor[22:0], 29'b0}; -// &Force("bus", "ex1_oper_id_frac", 51, 0); @332 -assign fdsu_ex4_frac[25:0] = srt_divisor[25:0]; - -//=======================Bound Select======================= -//---------------------------------------+ -// K | 8 | 9 | 10| 11| 12| 13| 14|15,16| -//---------------------------------------+ -//32S1 | 7 | 7 | 8 | 9 | 9 | 10| 11| 12 | -//---------------------------------------+ -//32S2 | 25| 28| 31| 33| 36| 39| 41| 47 | -//---------------------------------------+ - -//bound_sel[3:0] -//For div, use divisor high four bit as K -//For sqrt, use 2qi high four bit as K next round and -// use 1010 as K first round -assign bound_sel[3:0] = (fdsu_ex2_div) - ? srt_divisor[23:20] - : (ex2_srt_first_round) - ? 4'b1010 - : total_qt_rt_30[28:25]; -//Select bound as look up table -// K = bound_sel[3:0] -//32S1 = digit_bound_1[7:0] -//32s2 = digit_bound_2[7:0] -// &CombBeg; @357 -always @( bound_sel[3:0]) -begin -case(bound_sel[3:0]) -4'b0000: //when first interation get "10", choose k=16 - begin - digit_bound_1[7:0] = 8'b11110100;//-12 - digit_bound_2[7:0] = 8'b11010001;//-47 - end -4'b1000: - begin - digit_bound_1[7:0] = 8'b11111001;//-7 - digit_bound_2[7:0] = 8'b11100111;//-25 - end -4'b1001: - begin - digit_bound_1[7:0] = 8'b11111001;//-7 - digit_bound_2[7:0] = 8'b11100100;//-28 - end -4'b1010: - begin - digit_bound_1[7:0] = 8'b11111000;//-8 - digit_bound_2[7:0] = 8'b11100001;//-31 - end -4'b1011: - begin - digit_bound_1[7:0] = 8'b11110111;//-9 - digit_bound_2[7:0] = 8'b11011111;//-33 - end -4'b1100: - begin - digit_bound_1[7:0] = 8'b11110111;//-9 - digit_bound_2[7:0] = 8'b11011100;//-36 - end -4'b1101: - begin - digit_bound_1[7:0] = 8'b11110110;//-10 - digit_bound_2[7:0] = 8'b11011001;//-39 - end -4'b1110: - begin - digit_bound_1[7:0] = 8'b11110101;//-11 - digit_bound_2[7:0] = 8'b11010111;//-41 - end -4'b1111: - begin - digit_bound_1[7:0] = 8'b11110100;//-12 - digit_bound_2[7:0] = 8'b11010001;//-47 - end -default: - begin - digit_bound_1[7:0] = 8'b11111001;//-7 - digit_bound_2[7:0] = 8'b11100111;//-25 - end -endcase -// &CombEnd; @410 -end -//==============Prepare for quotient generate=============== -assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0]; -assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0]; -assign bound1_cmp_sign = bound1_cmp_result[7]; -assign bound2_cmp_sign = bound2_cmp_result[7]; -assign rem_sign = srt_remainder[29]; - -//qtrt_sel_rem is use to select quotient -//Only when sqrt first round use 8R0 select quotient(special rule) -//4R0 is used to select quotient on other condition -//For negative remaider, we use ~rem not (~rem + 1) -//Because bound1 <= rem < bound2, when positive rem -// -bound2 <= rem < -bound1, when negative rem -//Thus bound1 < -rem <= bound2, when negative rem -//Thus bound1 <= -rem-1 < bound2, when negative rem -//Thus bound1 <= ~rem < bound2, when negative rem -//srt_remainder[29] used as sign bit -// &CombBeg; @429 -always @( ex2_srt_first_round - or fdsu_ex2_sqrt - or srt_remainder[29:21]) -begin -if(ex2_srt_first_round && fdsu_ex2_sqrt) - qtrt_sel_rem[7:0] = {srt_remainder[29], srt_remainder[27:21]}; -else - qtrt_sel_rem[7:0] = srt_remainder[29] ? ~srt_remainder[29:22] - : srt_remainder[29:22]; -// &CombEnd; @435 -end -//========================================================== -// on fly round method to generate total quotient -//========================================================== +//====================Pipe to EX3=========================== //gate clk -// &Instance("gated_clk_cell","x_qt_clk"); @441 -gated_clk_cell x_qt_clk ( +// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @262 +gated_clk_cell x_ex2_pipe_clk ( .clk_in (forever_cpuclk ), - .clk_out (qt_clk ), + .clk_out (ex2_pipe_clk ), .external_en (1'b0 ), .global_en (cp0_yy_clk_en ), - .local_en (qt_clk_en ), - .module_en (cp0_fpu_icg_en ), + .local_en (ex2_pipe_clk_en ), + .module_en (cp0_vfpu_icg_en ), .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -// &Connect( .clk_in (forever_cpuclk), @442 -// .clk_out (qt_clk),//Out Clock @443 -// .external_en (1'b0), @444 -// .global_en (cp0_yy_clk_en), @445 -// .local_en (qt_clk_en),//Local Condition @446 -// .module_en (cp0_fpu_icg_en) @447 -// ); @448 -assign qt_clk_en = srt_sm_on || - ex1_pipedown_gate; - -//qt_rt_const_shift_std[29:0] is const data for on fly round -// which is used to record the times of round -// -//total_qt_rt[29:0] is total quotient -//total_qt_rt_minus[29:0] is total quotient minus -// which is used to generate quotient rapidly -always @(posedge qt_clk) +// &Connect( .clk_in (forever_cpuclk), @263 +// .clk_out (ex2_pipe_clk),//Out Clock @264 +// .external_en (1'b0), @265 +// .global_en (cp0_yy_clk_en), @266 +// .local_en (ex2_pipe_clk_en),//Local Condition @267 +// .module_en (cp0_vfpu_icg_en) @268 +// ); @269 +assign ex2_pipe_clk_en = ex2_pipedown; + +always @(posedge ex2_pipe_clk or negedge cpurst_b) begin - if(ex1_pipedown) + if(!cpurst_b) begin - qt_rt_const_shift_std[29:0] <= {1'b0,1'b1,28'b0}; - total_qt_rt_30[29:0] <= 30'b0; - total_qt_rt_minus_30[29:0] <= 30'b0; + vfdsu_ex3_result_zero <= 1'b0; + vfdsu_ex3_result_qnan <= 1'b0; + vfdsu_ex3_result_inf <= 1'b0; + vfdsu_ex3_result_lfn <= 1'b0; + vfdsu_ex3_of <= 1'b0; + vfdsu_ex3_uf <= 1'b0; + vfdsu_ex3_nv <= 1'b0; + vfdsu_ex3_dz <= 1'b0; + vfdsu_ex3_potnt_of <= 1'b0; + vfdsu_ex3_potnt_uf <= 1'b0; + vfdsu_ex3_rem_sign <= 1'b0; +// vfdsu_ex3_rem_zero <= 1'b0; + vfdsu_ex3_doub_expnt_rst[12:0] <= 13'b0; + vfdsu_ex3_sing_expnt_rst[8:0] <= 9'b0; + vfdsu_ex3_half_expnt_rst[12:0] <= 13'b0; + vfdsu_ex3_bfloat_expnt_rst[12:0] <= 13'b0; + vfdsu_ex3_result_sign <= 1'b0; + vfdsu_ex3_qnan_sign <= 1'b0; + vfdsu_ex3_qnan_f[51:0] <= 52'b0; + vfdsu_ex3_rm[2:0] <= 3'b0; + vfdsu_ex3_result_denorm_round_add_num[52:0] + <= 53'b0; + vfdsu_ex3_rslt_denorm <= 1'b0; + vfdsu_ex3_id_srt_skip <= 1'b0; + vfdsu_ex3_double <= 1'b0; + vfdsu_ex3_single <= 1'b0; + vfdsu_ex3_half <= 1'b0; + vfdsu_ex3_bfloat <= 1'b0; end - else if(srt_sm_on) + else if(ex2_pipedown) begin - qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std_next[29:0]; - total_qt_rt_30[29:0] <= total_qt_rt_30_next[29:0]; - total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30_next[29:0]; + vfdsu_ex3_result_zero <= ex2_result_zero; + vfdsu_ex3_result_qnan <= ex2_result_qnan; + vfdsu_ex3_result_inf <= ex2_result_inf; + vfdsu_ex3_result_lfn <= ex2_result_lfn; + vfdsu_ex3_of <= ex2_of; + vfdsu_ex3_uf <= ex2_uf; + vfdsu_ex3_nv <= vfdsu_ex2_nv; + vfdsu_ex3_dz <= vfdsu_ex2_dz; + vfdsu_ex3_potnt_of <= ex2_potnt_of; + vfdsu_ex3_potnt_uf <= ex2_potnt_uf; + vfdsu_ex3_rem_sign <= srt_remainder_sign; + //vfdsu_ex3_rem_zero <= srt_remainder_zero; + vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0]; + vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex2_expnt_rst[8:0]; + vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0]; + vfdsu_ex3_bfloat_expnt_rst[12:0] <= vfdsu_ex2_expnt_rst[12:0]; + vfdsu_ex3_result_sign <= vfdsu_ex2_result_sign; + vfdsu_ex3_qnan_sign <= vfdsu_ex2_qnan_sign; + vfdsu_ex3_qnan_f[51:0] <= vfdsu_ex2_qnan_f[51:0]; + vfdsu_ex3_rm[2:0] <= vfdsu_ex2_rm[2:0]; + vfdsu_ex3_result_denorm_round_add_num[52:0] + <= ex2_result_denorm_round_add_num[52:0]; + vfdsu_ex3_rslt_denorm <= ex2_rslt_denorm; + vfdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip; + vfdsu_ex3_double <= vfdsu_ex2_double; + vfdsu_ex3_single <= vfdsu_ex2_single; + vfdsu_ex3_half <= vfdsu_ex2_half; + vfdsu_ex3_bfloat <= vfdsu_ex2_bfloat; end else begin - qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std[29:0]; - total_qt_rt_30[29:0] <= total_qt_rt_30[29:0]; - total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30[29:0]; - end -end -// &Force("output","total_qt_rt_30"); @508 - -//qt_rt_const_q1/q2/q3 for shift 1/2/3 in -assign qt_rt_const_q1[29:0] = qt_rt_const_shift_std[29:0]; -assign qt_rt_const_q2[29:0] = {qt_rt_const_shift_std[28:0],1'b0}; -assign qt_rt_const_q3[29:0] = qt_rt_const_q1[29:0] | - qt_rt_const_q2[29:0]; -//qt_rt_const update value -assign qt_rt_const_shift_std_next[29:0] = {2'b0, qt_rt_const_shift_std[29:2]}; - -//========total_qt_rt & total_qt_rt_minus update value====== -//q(i+1) is the total quotient/root after the (i+1) digit -//is calculated -// q(i+1) qm(i+1) -//d(i+1)=-2 qm(i)+2*shift qm(i)+1*shift -//d(i+1)=-1 qm(i)+3*shift qm(i)+2*shift -//d(i+1)=0 q(i) qm(i)+3*shift -//d(i+1)=1 q(i)+1*shift q(i) -//d(i+1)=2 q(i)+2*shift q(i)+1*shift -//Note: -//shift = 4^(-i-1), qm(i+1)=q(i+1)-shift - -//pre select for quotient -assign total_qt_rt_pre_sel[29:0] = (rem_sign) ? - total_qt_rt_minus_30[29:0] : - total_qt_rt_30[29:0]; -//when the quotient is 2 or -2 -assign qt_rt_const_pre_sel_q2[29:0] = qt_rt_const_q2[29:0]; -assign qt_rt_mins_const_pre_sel_q2[29:0] = qt_rt_const_q1[29:0]; -//when the quotient is 1 or -1 -assign qt_rt_const_pre_sel_q1[29:0] = (rem_sign) ? - qt_rt_const_q3[29:0] ://-1 - qt_rt_const_q1[29:0]; //1 -assign qt_rt_mins_const_pre_sel_q1[29:0] = (rem_sign) ? - qt_rt_const_q2[29:0] : //-1 - 30'b0; - -//After bound compare, the final selection -// &CombBeg; @546 -always @( qt_rt_const_q3[29:0] - or qt_rt_mins_const_pre_sel_q1[29:0] - or bound1_cmp_sign - or total_qt_rt_30[29:0] - or qt_rt_mins_const_pre_sel_q2[29:0] - or total_qt_rt_minus_30[29:0] - or bound2_cmp_sign - or qt_rt_const_pre_sel_q2[29:0] - or qt_rt_const_pre_sel_q1[29:0] - or total_qt_rt_pre_sel[29:0]) -begin -casez({bound1_cmp_sign,bound2_cmp_sign}) - 2'b00:// the quotient is -2 or 2 - begin - total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | - qt_rt_const_pre_sel_q2[29:0]; - total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | - qt_rt_mins_const_pre_sel_q2[29:0]; - end - 2'b01:// quotient is -1 or 1 - begin - total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | - qt_rt_const_pre_sel_q1[29:0]; - total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | - qt_rt_mins_const_pre_sel_q1[29:0]; - end - 2'b1?: // quotient is 0 - begin - total_qt_rt_30_next[29:0] = total_qt_rt_30[29:0]; - total_qt_rt_minus_30_next[29:0] = total_qt_rt_minus_30[29:0] | - qt_rt_const_q3[29:0]; - end - default: - begin - total_qt_rt_30_next[29:0] = 30'b0; - total_qt_rt_minus_30_next[29:0] = 30'b0; + vfdsu_ex3_result_zero <= vfdsu_ex3_result_zero; + vfdsu_ex3_result_qnan <= vfdsu_ex3_result_qnan; + vfdsu_ex3_result_inf <= vfdsu_ex3_result_inf; + vfdsu_ex3_result_lfn <= vfdsu_ex3_result_lfn; + vfdsu_ex3_of <= vfdsu_ex3_of; + vfdsu_ex3_uf <= vfdsu_ex3_uf; + vfdsu_ex3_nv <= vfdsu_ex3_nv; + vfdsu_ex3_dz <= vfdsu_ex3_dz; + vfdsu_ex3_potnt_of <= vfdsu_ex3_potnt_of; + vfdsu_ex3_potnt_uf <= vfdsu_ex3_potnt_uf; + vfdsu_ex3_rem_sign <= vfdsu_ex3_rem_sign; + //vfdsu_ex3_rem_zero <= vfdsu_ex3_rem_zero; + vfdsu_ex3_doub_expnt_rst[12:0] <= vfdsu_ex3_doub_expnt_rst[12:0]; + vfdsu_ex3_sing_expnt_rst[8:0] <= vfdsu_ex3_sing_expnt_rst[8:0]; + vfdsu_ex3_half_expnt_rst[12:0] <= vfdsu_ex3_half_expnt_rst[12:0]; + vfdsu_ex3_bfloat_expnt_rst[12:0] <= vfdsu_ex3_bfloat_expnt_rst[12:0]; + vfdsu_ex3_result_sign <= vfdsu_ex3_result_sign; + vfdsu_ex3_qnan_sign <= vfdsu_ex3_qnan_sign; + vfdsu_ex3_qnan_f[51:0] <= vfdsu_ex3_qnan_f[51:0]; + vfdsu_ex3_rm[2:0] <= vfdsu_ex3_rm[2:0]; + vfdsu_ex3_result_denorm_round_add_num[52:0] + <= vfdsu_ex3_result_denorm_round_add_num[52:0]; + vfdsu_ex3_rslt_denorm <= vfdsu_ex3_rslt_denorm; + vfdsu_ex3_id_srt_skip <= vfdsu_ex3_id_srt_skip; + vfdsu_ex3_double <= vfdsu_ex3_double; + vfdsu_ex3_single <= vfdsu_ex3_single; + vfdsu_ex3_half <= vfdsu_ex3_half; + vfdsu_ex3_bfloat <= vfdsu_ex3_bfloat; end -endcase -// &CombEnd; @574 end +assign vfdsu_ex3_rem_zero = ~|srt_remainder[60:0]; +assign srt_ctrl_rem_zero = vfdsu_ex3_rem_zero; +// &Force("output","vfdsu_ex3_potnt_of"); @365 +// &Force("output","vfdsu_ex3_potnt_uf"); @366 +// &Force("output","vfdsu_ex3_rem_sign"); @367 +// &Force("output","vfdsu_ex3_rem_zero"); @368 +// &Force("output","vfdsu_ex3_result_zero"); @369 +// &Force("output","vfdsu_ex3_result_qnan"); @370 +// &Force("output","vfdsu_ex3_result_inf"); @371 +// &Force("output","vfdsu_ex3_result_lfn"); @372 +// &Force("output","vfdsu_ex3_dz"); @373 +// &Force("output","vfdsu_ex3_nv"); @374 +// &Force("output","vfdsu_ex3_of"); @375 +// &Force("output","vfdsu_ex3_uf"); @376 +// &Force("output","vfdsu_ex3_result_sign"); @377 +// &Force("output","vfdsu_ex3_doub_expnt_rst"); @378 +// &Force("output","vfdsu_ex3_sing_expnt_rst"); @379 +// &Force("output","vfdsu_ex3_half_expnt_rst"); @380 +// &Force("output","vfdsu_ex3_qnan_sign"); @381 +// &Force("output","vfdsu_ex3_qnan_f"); @382 +// &Force("output","vfdsu_ex3_rm"); @383 +// &Force("output","vfdsu_ex3_result_denorm_round_add_num"); @384 +// &Force("output","vfdsu_ex3_rslt_denorm"); @385 +// &Force("output","vfdsu_ex3_id_srt_skip"); @386 +// &Force("output","vfdsu_ex3_single"); @387 +// &Force("output","vfdsu_ex3_double"); @388 //========================================================== -// on fly round method to generate cur remainder +// SRT Remainder & Divisor for Quotient/Root Generate //========================================================== -//Division emainder add value -//Quoit 1 -assign div_qt_1_rem_add_op1[31:0] = ~{3'b0,srt_divisor[23:0],5'b0}; -//Quoit 2 -assign div_qt_2_rem_add_op1[31:0] = ~{2'b0,srt_divisor[23:0],6'b0}; -//Quoit -1 -assign div_qt_r1_rem_add_op1[31:0] = {3'b0,srt_divisor[23:0],5'b0}; -//Quoit -2 -assign div_qt_r2_rem_add_op1[31:0] = {2'b0,srt_divisor[23:0],6'b0}; - -//Sqrt remainder add value op1 -//Quoit 1 -assign sqrt_qt_1_rem_add_op1[31:0] = ~({2'b0,total_qt_rt_30[29:0]} | - {3'b0,qt_rt_const_q1[29:1]}); -//Quoit 2 -assign sqrt_qt_2_rem_add_op1[31:0] = ~({1'b0,total_qt_rt_30[29:0],1'b0} | - {1'b0,qt_rt_const_q1[29:0],1'b0}); -//Quoit -1 -assign sqrt_qt_r1_rem_add_op1[31:0] = {2'b0,total_qt_rt_minus_30[29:0]} | - {1'b0,qt_rt_const_q1[29:0],1'b0} | - {2'b0,qt_rt_const_q1[29:0]} | - {3'b0,qt_rt_const_q1[29:1]}; -//Quoit -2 -assign sqrt_qt_r2_rem_add_op1[31:0] = {1'b0, - total_qt_rt_minus_30[29:0],1'b0} | - {qt_rt_const_q1[29:0],2'b0} | - {1'b0,qt_rt_const_q1[29:0],1'b0}; -//Remainder Adder select logic -// &CombBeg; @607 -always @( div_qt_2_rem_add_op1[31:0] - or sqrt_qt_r2_rem_add_op1[31:0] - or sqrt_qt_r1_rem_add_op1[31:0] - or rem_sign - or div_qt_r2_rem_add_op1[31:0] - or div_qt_1_rem_add_op1[31:0] - or sqrt_qt_2_rem_add_op1[31:0] - or fdsu_ex2_sqrt - or div_qt_r1_rem_add_op1[31:0] - or sqrt_qt_1_rem_add_op1[31:0]) -begin -case({rem_sign,fdsu_ex2_sqrt}) - 2'b01: - begin - rem_add1_op1[31:0] = sqrt_qt_1_rem_add_op1[31:0]; - rem_add2_op1[31:0] = sqrt_qt_2_rem_add_op1[31:0]; - end - 2'b00: - begin - rem_add1_op1[31:0] = div_qt_1_rem_add_op1[31:0]; - rem_add2_op1[31:0] = div_qt_2_rem_add_op1[31:0]; - end - 2'b11: - begin - rem_add1_op1[31:0] = sqrt_qt_r1_rem_add_op1[31:0]; - rem_add2_op1[31:0] = sqrt_qt_r2_rem_add_op1[31:0]; - end - 2'b10: - begin - rem_add1_op1[31:0] = div_qt_r1_rem_add_op1[31:0]; - rem_add2_op1[31:0] = div_qt_r2_rem_add_op1[31:0]; - end - default : - begin - rem_add1_op1[31:0] = 32'b0; - rem_add2_op1[31:0] = 32'b0; - end - endcase -// &CombEnd; @635 -end -assign srt_remainder_shift[31:0] = {srt_remainder[31], - srt_remainder[28:0],2'b0}; -//Remainder add -assign cur_doub_rem_1[31:0] = srt_remainder_shift[31:0] + - rem_add1_op1[31:0] + - {31'b0, ~rem_sign}; -assign cur_doub_rem_2[31:0] = srt_remainder_shift[31:0] + - rem_add2_op1[31:0] + - {31'b0, ~rem_sign}; -assign cur_rem_1[31:0] = cur_doub_rem_1[31:0]; -assign cur_rem_2[31:0] = cur_doub_rem_2[31:0]; -//Generate srt remainder update value -// &CombBeg; @648 -always @( cur_rem_2[31:0] - or bound1_cmp_sign - or srt_remainder_shift[31:0] - or bound2_cmp_sign - or cur_rem_1[31:0]) -begin -case({bound1_cmp_sign,bound2_cmp_sign}) - 2'b00: cur_rem[31:0] = cur_rem_2[31:0]; //+-2 - 2'b01: cur_rem[31:0] = cur_rem_1[31:0]; //+-1 - default: cur_rem[31:0] = srt_remainder_shift[31:0]; //0 -endcase -// &CombEnd; @654 -end -assign srt_remainder_nxt[31:0] = cur_rem[31:0]; - -//Remainder is zero signal in EX3 -assign srt_remainder_zero = ~|srt_remainder[31:0]; -// &Force("output","srt_remainder_zero"); @659 -assign srt_remainder_sign = srt_remainder[31]; - -// &Force("output", "ex2_uf"); @662 -// &ModuleEnd; @663 -endmodule +// &Instance("ct_vfdsu_srt_radix16_with_sqrt_for_vdsp"); @411 +// &Connect(.srt_sm_on (srt_sm_on_all)); @412 +// &Force("bus","ex1_remainder",59,0); @414 +// &Force("bus","srt_remainder_out",69,0); @415 +// &Force("nonport","srt_remainder_out"); @422 +// &Force("nonport","vdiv_qt_rt"); @423 +assign initial_divisor_in[55:0] = {ex1_divisor[52:0],3'b000}; +assign initial_remainder_in[60:0] = {2'b00,ex1_remainder[59:1]}; +assign initial_bound_sel_in[6:0] = ex1_div ? initial_divisor_in[55:49]:{7{1'b0}}; -// ----- 8< ----- FILE "./pa_fdsu_top.v" ----- 8< ----- +assign initial_srt_en = ex1_pipedown; +assign initial_srt_sel_div_in = ex1_div; +assign initial_srt_sel_sqrt_in = ex1_sqrt; -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -*/ +assign srt_first_round = ex2_srt_first_round; -// &ModuleBeg; @23 -module pa_fdsu_top( - cp0_fpu_icg_en, - cp0_fpu_xx_dqnan, - cp0_yy_clk_en, - cpurst_b, - ctrl_fdsu_ex1_sel, - ctrl_xx_ex1_cmplt_dp, - ctrl_xx_ex1_inst_vld, - ctrl_xx_ex1_stall, - ctrl_xx_ex1_warm_up, - ctrl_xx_ex2_warm_up, - ctrl_xx_ex3_warm_up, - dp_xx_ex1_cnan, - dp_xx_ex1_id, - dp_xx_ex1_inf, - dp_xx_ex1_qnan, - dp_xx_ex1_rm, - dp_xx_ex1_snan, - dp_xx_ex1_zero, - fdsu_fpu_debug_info, - fdsu_fpu_ex1_cmplt, - fdsu_fpu_ex1_cmplt_dp, - fdsu_fpu_ex1_fflags, - fdsu_fpu_ex1_special_sel, - fdsu_fpu_ex1_special_sign, - fdsu_fpu_ex1_stall, - fdsu_fpu_no_op, - fdsu_frbus_data, - fdsu_frbus_fflags, - fdsu_frbus_freg, - fdsu_frbus_wb_vld, - forever_cpuclk, - frbus_fdsu_wb_grant, - idu_fpu_ex1_dst_freg, - idu_fpu_ex1_eu_sel, - idu_fpu_ex1_func, - idu_fpu_ex1_srcf0, - idu_fpu_ex1_srcf1, - pad_yy_icg_scan_en, - rtu_xx_ex1_cancel, - rtu_xx_ex2_cancel, - rtu_yy_xx_async_flush, - rtu_yy_xx_flush +// &Instance("ct_vfdsu_srt_radix16_with_sqrt"); @436 +ct_vfdsu_srt_radix16_with_sqrt x_ct_vfdsu_srt_radix16_with_sqrt ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .forever_cpuclk (forever_cpuclk ), + .initial_bound_sel_in (initial_bound_sel_in ), + .initial_divisor_in (initial_divisor_in ), + .initial_remainder_in (initial_remainder_in ), + .initial_srt_en (initial_srt_en ), + .initial_srt_sel_div_in (initial_srt_sel_div_in ), + .initial_srt_sel_sqrt_in (initial_srt_sel_sqrt_in), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .srt_first_round (srt_first_round ), + .srt_remainder (srt_remainder ), + .srt_remainder_out (srt_remainder_out ), + .srt_remainder_sign (srt_remainder_sign ), + .srt_secd_round (srt_secd_round ), + .srt_sm_on (srt_sm_on ), + .total_qt_rt (total_qt_rt ), + .vdiv_qt_rt (vdiv_qt_rt ) ); -// &Ports; @24 -input cp0_fpu_icg_en; -input cp0_fpu_xx_dqnan; -input cp0_yy_clk_en; -input cpurst_b; -input ctrl_fdsu_ex1_sel; -input ctrl_xx_ex1_cmplt_dp; -input ctrl_xx_ex1_inst_vld; -input ctrl_xx_ex1_stall; -input ctrl_xx_ex1_warm_up; -input ctrl_xx_ex2_warm_up; -input ctrl_xx_ex3_warm_up; -input [2 :0] dp_xx_ex1_cnan; -input [2 :0] dp_xx_ex1_id; -input [2 :0] dp_xx_ex1_inf; -input [2 :0] dp_xx_ex1_qnan; -input [2 :0] dp_xx_ex1_rm; -input [2 :0] dp_xx_ex1_snan; -input [2 :0] dp_xx_ex1_zero; -input forever_cpuclk; -input frbus_fdsu_wb_grant; -input [4 :0] idu_fpu_ex1_dst_freg; -input [2 :0] idu_fpu_ex1_eu_sel; -input [9 :0] idu_fpu_ex1_func; -input [31:0] idu_fpu_ex1_srcf0; -input [31:0] idu_fpu_ex1_srcf1; -input pad_yy_icg_scan_en; -input rtu_xx_ex1_cancel; -input rtu_xx_ex2_cancel; -input rtu_yy_xx_async_flush; -input rtu_yy_xx_flush; -output [4 :0] fdsu_fpu_debug_info; -output fdsu_fpu_ex1_cmplt; -output fdsu_fpu_ex1_cmplt_dp; -output [4 :0] fdsu_fpu_ex1_fflags; -output [7 :0] fdsu_fpu_ex1_special_sel; -output [3 :0] fdsu_fpu_ex1_special_sign; -output fdsu_fpu_ex1_stall; -output fdsu_fpu_no_op; -output [31:0] fdsu_frbus_data; -output [4 :0] fdsu_frbus_fflags; -output [4 :0] fdsu_frbus_freg; -output fdsu_frbus_wb_vld; -// &Regs; @25 +// &Force("bus","ex1_remainder",59,0); @438 -// &Wires; @26 -wire cp0_fpu_icg_en; -wire cp0_fpu_xx_dqnan; -wire cp0_yy_clk_en; -wire cpurst_b; -wire ctrl_fdsu_ex1_sel; -wire ctrl_xx_ex1_cmplt_dp; -wire ctrl_xx_ex1_inst_vld; -wire ctrl_xx_ex1_stall; -wire ctrl_xx_ex1_warm_up; -wire ctrl_xx_ex2_warm_up; -wire ctrl_xx_ex3_warm_up; -wire [2 :0] dp_xx_ex1_cnan; -wire [2 :0] dp_xx_ex1_id; -wire [2 :0] dp_xx_ex1_inf; -wire [2 :0] dp_xx_ex1_qnan; -wire [2 :0] dp_xx_ex1_rm; -wire [2 :0] dp_xx_ex1_snan; -wire [2 :0] dp_xx_ex1_zero; -wire ex1_div; -wire [23:0] ex1_divisor; -wire [12:0] ex1_expnt_adder_op0; -wire [12:0] ex1_expnt_adder_op1; -wire ex1_of_result_lfn; -wire ex1_op0_id; -wire ex1_op0_norm; -wire ex1_op0_sign; -wire ex1_op1_id; -wire ex1_op1_id_vld; -wire ex1_op1_norm; -wire ex1_op1_sel; -wire [12:0] ex1_oper_id_expnt; -wire [12:0] ex1_oper_id_expnt_f; -wire [51:0] ex1_oper_id_frac; -wire [51:0] ex1_oper_id_frac_f; -wire ex1_pipedown; -wire ex1_pipedown_gate; -wire [31:0] ex1_remainder; -wire ex1_result_sign; -wire [2 :0] ex1_rm; -wire ex1_save_op0; -wire ex1_save_op0_gate; -wire ex1_sqrt; -wire ex1_srt_skip; -wire [9 :0] ex2_expnt_adder_op0; -wire ex2_of; -wire ex2_pipe_clk; -wire ex2_pipedown; -wire ex2_potnt_of; -wire ex2_potnt_uf; -wire ex2_result_inf; -wire ex2_result_lfn; -wire ex2_rslt_denorm; -wire [9 :0] ex2_srt_expnt_rst; -wire ex2_srt_first_round; -wire ex2_uf; -wire ex2_uf_srt_skip; -wire [9 :0] ex3_expnt_adjust_result; -wire [25:0] ex3_frac_final_rst; -wire ex3_pipedown; -wire ex3_rslt_denorm; -wire fdsu_ex1_sel; -wire fdsu_ex3_id_srt_skip; -wire fdsu_ex3_rem_sign; -wire fdsu_ex3_rem_zero; -wire [23:0] fdsu_ex3_result_denorm_round_add_num; -wire fdsu_ex4_denorm_to_tiny_frac; -wire [25:0] fdsu_ex4_frac; -wire fdsu_ex4_nx; -wire [1 :0] fdsu_ex4_potnt_norm; -wire fdsu_ex4_result_nor; -wire [4 :0] fdsu_fpu_debug_info; -wire fdsu_fpu_ex1_cmplt; -wire fdsu_fpu_ex1_cmplt_dp; -wire [4 :0] fdsu_fpu_ex1_fflags; -wire [7 :0] fdsu_fpu_ex1_special_sel; -wire [3 :0] fdsu_fpu_ex1_special_sign; -wire fdsu_fpu_ex1_stall; -wire fdsu_fpu_no_op; -wire [31:0] fdsu_frbus_data; -wire [4 :0] fdsu_frbus_fflags; -wire [4 :0] fdsu_frbus_freg; -wire fdsu_frbus_wb_vld; -wire fdsu_yy_div; -wire [9 :0] fdsu_yy_expnt_rst; -wire fdsu_yy_of; -wire fdsu_yy_of_rm_lfn; -wire fdsu_yy_op0_norm; -wire fdsu_yy_op1_norm; -wire fdsu_yy_potnt_of; -wire fdsu_yy_potnt_uf; -wire fdsu_yy_result_inf; -wire fdsu_yy_result_lfn; -wire fdsu_yy_result_sign; -wire [2 :0] fdsu_yy_rm; -wire fdsu_yy_rslt_denorm; -wire fdsu_yy_sqrt; -wire fdsu_yy_uf; -wire [4 :0] fdsu_yy_wb_freg; -wire forever_cpuclk; -wire frbus_fdsu_wb_grant; -wire [4 :0] idu_fpu_ex1_dst_freg; -wire [2 :0] idu_fpu_ex1_eu_sel; -wire [9 :0] idu_fpu_ex1_func; -wire [31:0] idu_fpu_ex1_srcf0; -wire [31:0] idu_fpu_ex1_srcf1; -wire pad_yy_icg_scan_en; -wire rtu_xx_ex1_cancel; -wire rtu_xx_ex2_cancel; -wire rtu_yy_xx_async_flush; -wire rtu_yy_xx_flush; -wire srt_remainder_zero; -wire srt_sm_on; -wire [29:0] total_qt_rt_30; - - - -// &Instance("pa_fdsu_special"); @29 -pa_fdsu_special x_pa_fdsu_special ( - .cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ), - .dp_xx_ex1_cnan (dp_xx_ex1_cnan ), - .dp_xx_ex1_id (dp_xx_ex1_id ), - .dp_xx_ex1_inf (dp_xx_ex1_inf ), - .dp_xx_ex1_qnan (dp_xx_ex1_qnan ), - .dp_xx_ex1_snan (dp_xx_ex1_snan ), - .dp_xx_ex1_zero (dp_xx_ex1_zero ), - .ex1_div (ex1_div ), - .ex1_op0_id (ex1_op0_id ), - .ex1_op0_norm (ex1_op0_norm ), - .ex1_op0_sign (ex1_op0_sign ), - .ex1_op1_id (ex1_op1_id ), - .ex1_op1_norm (ex1_op1_norm ), - .ex1_result_sign (ex1_result_sign ), - .ex1_sqrt (ex1_sqrt ), - .ex1_srt_skip (ex1_srt_skip ), - .fdsu_fpu_ex1_fflags (fdsu_fpu_ex1_fflags ), - .fdsu_fpu_ex1_special_sel (fdsu_fpu_ex1_special_sel ), - .fdsu_fpu_ex1_special_sign (fdsu_fpu_ex1_special_sign) -); +assign total_qt_rt_58[57:0] = {total_qt_rt[57:2],2'b00}; + +// &ModuleEnd; @443 +endmodule -// &Instance("pa_fdsu_prepare"); @30 -pa_fdsu_prepare x_pa_fdsu_prepare ( - .dp_xx_ex1_rm (dp_xx_ex1_rm ), - .ex1_div (ex1_div ), - .ex1_divisor (ex1_divisor ), - .ex1_expnt_adder_op0 (ex1_expnt_adder_op0), - .ex1_expnt_adder_op1 (ex1_expnt_adder_op1), - .ex1_of_result_lfn (ex1_of_result_lfn ), - .ex1_op0_id (ex1_op0_id ), - .ex1_op0_sign (ex1_op0_sign ), - .ex1_op1_id (ex1_op1_id ), - .ex1_op1_id_vld (ex1_op1_id_vld ), - .ex1_op1_sel (ex1_op1_sel ), - .ex1_oper_id_expnt (ex1_oper_id_expnt ), - .ex1_oper_id_expnt_f (ex1_oper_id_expnt_f), - .ex1_oper_id_frac (ex1_oper_id_frac ), - .ex1_oper_id_frac_f (ex1_oper_id_frac_f ), - .ex1_remainder (ex1_remainder ), - .ex1_result_sign (ex1_result_sign ), - .ex1_rm (ex1_rm ), - .ex1_sqrt (ex1_sqrt ), - .fdsu_ex1_sel (fdsu_ex1_sel ), - .idu_fpu_ex1_func (idu_fpu_ex1_func ), - .idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ), - .idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 ) -); -// &Instance("pa_fdsu_srt"); @32 -// &Instance("pa_fdsu_round"); @33 -// &Instance("pa_fdsu_pack"); @34 -// &Instance("pa_fdsu_srt_single", "x_pa_fdsu_srt"); @36 -pa_fdsu_srt_single x_pa_fdsu_srt ( - .cp0_fpu_icg_en (cp0_fpu_icg_en ), - .cp0_yy_clk_en (cp0_yy_clk_en ), - .ex1_divisor (ex1_divisor ), - .ex1_expnt_adder_op1 (ex1_expnt_adder_op1 ), - .ex1_oper_id_frac (ex1_oper_id_frac ), - .ex1_oper_id_frac_f (ex1_oper_id_frac_f ), - .ex1_pipedown (ex1_pipedown ), - .ex1_pipedown_gate (ex1_pipedown_gate ), - .ex1_remainder (ex1_remainder ), - .ex1_save_op0 (ex1_save_op0 ), - .ex1_save_op0_gate (ex1_save_op0_gate ), - .ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ), - .ex2_of (ex2_of ), - .ex2_pipe_clk (ex2_pipe_clk ), - .ex2_pipedown (ex2_pipedown ), - .ex2_potnt_of (ex2_potnt_of ), - .ex2_potnt_uf (ex2_potnt_uf ), - .ex2_result_inf (ex2_result_inf ), - .ex2_result_lfn (ex2_result_lfn ), - .ex2_rslt_denorm (ex2_rslt_denorm ), - .ex2_srt_expnt_rst (ex2_srt_expnt_rst ), - .ex2_srt_first_round (ex2_srt_first_round ), - .ex2_uf (ex2_uf ), - .ex2_uf_srt_skip (ex2_uf_srt_skip ), - .ex3_frac_final_rst (ex3_frac_final_rst ), - .ex3_pipedown (ex3_pipedown ), - .fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ), - .fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ), - .fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ), - .fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num), - .fdsu_ex4_frac (fdsu_ex4_frac ), - .fdsu_yy_div (fdsu_yy_div ), - .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), - .fdsu_yy_op0_norm (fdsu_yy_op0_norm ), - .fdsu_yy_op1_norm (fdsu_yy_op1_norm ), - .fdsu_yy_sqrt (fdsu_yy_sqrt ), - .forever_cpuclk (forever_cpuclk ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), - .srt_remainder_zero (srt_remainder_zero ), - .srt_sm_on (srt_sm_on ), - .total_qt_rt_30 (total_qt_rt_30 ) -); +// ----- 8< ----- FILE "./ct_vfdsu_srt_radix16_bound_table.v" ----- 8< ----- -// &Instance("pa_fdsu_round_single", "x_pa_fdsu_round"); @37 -pa_fdsu_round_single x_pa_fdsu_round ( - .cp0_fpu_icg_en (cp0_fpu_icg_en ), - .cp0_yy_clk_en (cp0_yy_clk_en ), - .ex3_expnt_adjust_result (ex3_expnt_adjust_result ), - .ex3_frac_final_rst (ex3_frac_final_rst ), - .ex3_pipedown (ex3_pipedown ), - .ex3_rslt_denorm (ex3_rslt_denorm ), - .fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ), - .fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ), - .fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ), - .fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num), - .fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac ), - .fdsu_ex4_nx (fdsu_ex4_nx ), - .fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ), - .fdsu_ex4_result_nor (fdsu_ex4_result_nor ), - .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), - .fdsu_yy_result_inf (fdsu_yy_result_inf ), - .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), - .fdsu_yy_result_sign (fdsu_yy_result_sign ), - .fdsu_yy_rm (fdsu_yy_rm ), - .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), - .forever_cpuclk (forever_cpuclk ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), - .total_qt_rt_30 (total_qt_rt_30 ) -); +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. -// &Instance("pa_fdsu_pack_single", "x_pa_fdsu_pack"); @38 -pa_fdsu_pack_single x_pa_fdsu_pack ( - .fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac), - .fdsu_ex4_frac (fdsu_ex4_frac ), - .fdsu_ex4_nx (fdsu_ex4_nx ), - .fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ), - .fdsu_ex4_result_nor (fdsu_ex4_result_nor ), - .fdsu_frbus_data (fdsu_frbus_data ), - .fdsu_frbus_fflags (fdsu_frbus_fflags ), - .fdsu_frbus_freg (fdsu_frbus_freg ), - .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), - .fdsu_yy_of (fdsu_yy_of ), - .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), - .fdsu_yy_potnt_of (fdsu_yy_potnt_of ), - .fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ), - .fdsu_yy_result_inf (fdsu_yy_result_inf ), - .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), - .fdsu_yy_result_sign (fdsu_yy_result_sign ), - .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), - .fdsu_yy_uf (fdsu_yy_uf ), - .fdsu_yy_wb_freg (fdsu_yy_wb_freg ) -); +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 -// &Instance("pa_fdsu_ctrl"); @41 -pa_fdsu_ctrl x_pa_fdsu_ctrl ( - .cp0_fpu_icg_en (cp0_fpu_icg_en ), - .cp0_yy_clk_en (cp0_yy_clk_en ), - .cpurst_b (cpurst_b ), - .ctrl_fdsu_ex1_sel (ctrl_fdsu_ex1_sel ), - .ctrl_xx_ex1_cmplt_dp (ctrl_xx_ex1_cmplt_dp ), - .ctrl_xx_ex1_inst_vld (ctrl_xx_ex1_inst_vld ), - .ctrl_xx_ex1_stall (ctrl_xx_ex1_stall ), - .ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ), - .ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ), - .ctrl_xx_ex3_warm_up (ctrl_xx_ex3_warm_up ), - .ex1_div (ex1_div ), - .ex1_expnt_adder_op0 (ex1_expnt_adder_op0 ), - .ex1_of_result_lfn (ex1_of_result_lfn ), - .ex1_op0_id (ex1_op0_id ), - .ex1_op0_norm (ex1_op0_norm ), - .ex1_op1_id_vld (ex1_op1_id_vld ), - .ex1_op1_norm (ex1_op1_norm ), - .ex1_op1_sel (ex1_op1_sel ), - .ex1_oper_id_expnt (ex1_oper_id_expnt ), - .ex1_oper_id_expnt_f (ex1_oper_id_expnt_f ), - .ex1_pipedown (ex1_pipedown ), - .ex1_pipedown_gate (ex1_pipedown_gate ), - .ex1_result_sign (ex1_result_sign ), - .ex1_rm (ex1_rm ), - .ex1_save_op0 (ex1_save_op0 ), - .ex1_save_op0_gate (ex1_save_op0_gate ), - .ex1_sqrt (ex1_sqrt ), - .ex1_srt_skip (ex1_srt_skip ), - .ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ), - .ex2_of (ex2_of ), - .ex2_pipe_clk (ex2_pipe_clk ), - .ex2_pipedown (ex2_pipedown ), - .ex2_potnt_of (ex2_potnt_of ), - .ex2_potnt_uf (ex2_potnt_uf ), - .ex2_result_inf (ex2_result_inf ), - .ex2_result_lfn (ex2_result_lfn ), - .ex2_rslt_denorm (ex2_rslt_denorm ), - .ex2_srt_expnt_rst (ex2_srt_expnt_rst ), - .ex2_srt_first_round (ex2_srt_first_round ), - .ex2_uf (ex2_uf ), - .ex2_uf_srt_skip (ex2_uf_srt_skip ), - .ex3_expnt_adjust_result (ex3_expnt_adjust_result), - .ex3_pipedown (ex3_pipedown ), - .ex3_rslt_denorm (ex3_rslt_denorm ), - .fdsu_ex1_sel (fdsu_ex1_sel ), - .fdsu_fpu_debug_info (fdsu_fpu_debug_info ), - .fdsu_fpu_ex1_cmplt (fdsu_fpu_ex1_cmplt ), - .fdsu_fpu_ex1_cmplt_dp (fdsu_fpu_ex1_cmplt_dp ), - .fdsu_fpu_ex1_stall (fdsu_fpu_ex1_stall ), - .fdsu_fpu_no_op (fdsu_fpu_no_op ), - .fdsu_frbus_wb_vld (fdsu_frbus_wb_vld ), - .fdsu_yy_div (fdsu_yy_div ), - .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), - .fdsu_yy_of (fdsu_yy_of ), - .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), - .fdsu_yy_op0_norm (fdsu_yy_op0_norm ), - .fdsu_yy_op1_norm (fdsu_yy_op1_norm ), - .fdsu_yy_potnt_of (fdsu_yy_potnt_of ), - .fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ), - .fdsu_yy_result_inf (fdsu_yy_result_inf ), - .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), - .fdsu_yy_result_sign (fdsu_yy_result_sign ), - .fdsu_yy_rm (fdsu_yy_rm ), - .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), - .fdsu_yy_sqrt (fdsu_yy_sqrt ), - .fdsu_yy_uf (fdsu_yy_uf ), - .fdsu_yy_wb_freg (fdsu_yy_wb_freg ), - .forever_cpuclk (forever_cpuclk ), - .frbus_fdsu_wb_grant (frbus_fdsu_wb_grant ), - .idu_fpu_ex1_dst_freg (idu_fpu_ex1_dst_freg ), - .idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), - .rtu_xx_ex1_cancel (rtu_xx_ex1_cancel ), - .rtu_xx_ex2_cancel (rtu_xx_ex2_cancel ), - .rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ), - .rtu_yy_xx_flush (rtu_yy_xx_flush ), - .srt_remainder_zero (srt_remainder_zero ), - .srt_sm_on (srt_sm_on ) +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @22 +module ct_vfdsu_srt_radix16_bound_table( + bound_sel, + digit_bound_1, + digit_bound_2, + digit_bound_3, + digit_bound_4, + digit_bound_5, + digit_bound_6, + digit_bound_7, + digit_bound_8, + digit_bound_9, + sqrt_first_round, + sqrt_secd_round, + sqrt_secd_round_sign ); +// &Ports; @23 +input [6 :0] bound_sel; +input sqrt_first_round; +input sqrt_secd_round; +input sqrt_secd_round_sign; +output [11:0] digit_bound_1; +output [11:0] digit_bound_2; +output [11:0] digit_bound_3; +output [11:0] digit_bound_4; +output [11:0] digit_bound_5; +output [11:0] digit_bound_6; +output [11:0] digit_bound_7; +output [11:0] digit_bound_8; +output [11:0] digit_bound_9; + +// &Regs; @24 +reg [11:0] ori_digit_bound_1; +reg [11:0] ori_digit_bound_2; +reg [11:0] ori_digit_bound_3; +reg [11:0] ori_digit_bound_4; +reg [11:0] ori_digit_bound_5; +reg [11:0] ori_digit_bound_6; +reg [11:0] ori_digit_bound_7; +reg [11:0] ori_digit_bound_8; +reg [11:0] ori_digit_bound_9; +reg [11:0] sqrt_digit_boundm2_1; +reg [11:0] sqrt_digit_boundm2_2; +reg [11:0] sqrt_digit_boundm2_3; +reg [11:0] sqrt_digit_boundm2_4; +reg [11:0] sqrt_digit_boundm2_5; +reg [11:0] sqrt_digit_boundm2_6; +reg [11:0] sqrt_digit_boundm2_7; +reg [11:0] sqrt_digit_boundm2_8; +reg [11:0] sqrt_digit_boundm2_9; +reg [11:0] sqrt_digit_boundp2_1; +reg [11:0] sqrt_digit_boundp2_2; +reg [11:0] sqrt_digit_boundp2_3; +reg [11:0] sqrt_digit_boundp2_4; +reg [11:0] sqrt_digit_boundp2_5; +reg [11:0] sqrt_digit_boundp2_6; +reg [11:0] sqrt_digit_boundp2_7; +reg [11:0] sqrt_digit_boundp2_8; +reg [11:0] sqrt_digit_boundp2_9; + +// &Wires; @25 +wire [6 :0] bound_sel; +wire [11:0] digit_bound_1; +wire [11:0] digit_bound_2; +wire [11:0] digit_bound_3; +wire [11:0] digit_bound_4; +wire [11:0] digit_bound_5; +wire [11:0] digit_bound_6; +wire [11:0] digit_bound_7; +wire [11:0] digit_bound_8; +wire [11:0] digit_bound_9; +wire [11:0] sqrt_digit_bound2_1; +wire [11:0] sqrt_digit_bound2_2; +wire [11:0] sqrt_digit_bound2_3; +wire [11:0] sqrt_digit_bound2_4; +wire [11:0] sqrt_digit_bound2_5; +wire [11:0] sqrt_digit_bound2_6; +wire [11:0] sqrt_digit_bound2_7; +wire [11:0] sqrt_digit_bound2_8; +wire [11:0] sqrt_digit_bound2_9; +wire sqrt_first_round; +wire sqrt_secd_round; +wire sqrt_secd_round_sign; + + +// &CombBeg; @27 +always @( bound_sel[6:0]) +begin +case(bound_sel[6:0]) + 7'h40: + begin + ori_digit_bound_1[11:0] = 12'h1b;//27 + ori_digit_bound_2[11:0] = 12'h5c;//92 + ori_digit_bound_3[11:0] = 12'h9d;//157 + ori_digit_bound_4[11:0] = 12'hde;//222 + ori_digit_bound_5[11:0] = 12'h120;//288 + ori_digit_bound_6[11:0] = 12'h161;//353 + ori_digit_bound_7[11:0] = 12'h1a2;//418 + ori_digit_bound_8[11:0] = 12'h1e3;//483 + ori_digit_bound_9[11:0] = 12'h225;//549 + + end + 7'h41: + begin + ori_digit_bound_1[11:0] = 12'h1b;//27 + ori_digit_bound_2[11:0] = 12'h5d;//93 + ori_digit_bound_3[11:0] = 12'ha0;//160 + ori_digit_bound_4[11:0] = 12'he2;//226 + ori_digit_bound_5[11:0] = 12'h124;//292 + ori_digit_bound_6[11:0] = 12'h166;//358 + ori_digit_bound_7[11:0] = 12'h1a9;//425 + ori_digit_bound_8[11:0] = 12'h1eb;//491 + ori_digit_bound_9[11:0] = 12'h22d;//557 + + end + 7'h42: + begin + ori_digit_bound_1[11:0] = 12'h1b;//27 + ori_digit_bound_2[11:0] = 12'h5f;//95 + ori_digit_bound_3[11:0] = 12'ha2;//162 + ori_digit_bound_4[11:0] = 12'he5;//229 + ori_digit_bound_5[11:0] = 12'h128;//296 + ori_digit_bound_6[11:0] = 12'h16c;//364 + ori_digit_bound_7[11:0] = 12'h1af;//431 + ori_digit_bound_8[11:0] = 12'h1f2;//498 + ori_digit_bound_9[11:0] = 12'h236;//566 + + end + 7'h43: + begin + ori_digit_bound_1[11:0] = 12'h1c;//28 + ori_digit_bound_2[11:0] = 12'h60;//96 + ori_digit_bound_3[11:0] = 12'ha4;//164 + ori_digit_bound_4[11:0] = 12'he9;//233 + ori_digit_bound_5[11:0] = 12'h12d;//301 + ori_digit_bound_6[11:0] = 12'h171;//369 + ori_digit_bound_7[11:0] = 12'h1b5;//437 + ori_digit_bound_8[11:0] = 12'h1fa;//506 + ori_digit_bound_9[11:0] = 12'h23e;//574 + + end + 7'h44: + begin + ori_digit_bound_1[11:0] = 12'h1c;//28 + ori_digit_bound_2[11:0] = 12'h61;//97 + ori_digit_bound_3[11:0] = 12'ha7;//167 + ori_digit_bound_4[11:0] = 12'hec;//236 + ori_digit_bound_5[11:0] = 12'h131;//305 + ori_digit_bound_6[11:0] = 12'h177;//375 + ori_digit_bound_7[11:0] = 12'h1bc;//444 + ori_digit_bound_8[11:0] = 12'h201;//513 + ori_digit_bound_9[11:0] = 12'h246;//582 + + end + 7'h45: + begin + ori_digit_bound_1[11:0] = 12'h1d;//29 + ori_digit_bound_2[11:0] = 12'h63;//99 + ori_digit_bound_3[11:0] = 12'ha9;//169 + ori_digit_bound_4[11:0] = 12'hef;//239 + ori_digit_bound_5[11:0] = 12'h136;//310 + ori_digit_bound_6[11:0] = 12'h17c;//380 + ori_digit_bound_7[11:0] = 12'h1c2;//450 + ori_digit_bound_8[11:0] = 12'h208;//520 + ori_digit_bound_9[11:0] = 12'h24f;//591 + + end + 7'h46: + begin + ori_digit_bound_1[11:0] = 12'h1d;//29 + ori_digit_bound_2[11:0] = 12'h64;//100 + ori_digit_bound_3[11:0] = 12'hac;//172 + ori_digit_bound_4[11:0] = 12'hf3;//243 + ori_digit_bound_5[11:0] = 12'h13a;//314 + ori_digit_bound_6[11:0] = 12'h181;//385 + ori_digit_bound_7[11:0] = 12'h1c9;//457 + ori_digit_bound_8[11:0] = 12'h210;//528 + ori_digit_bound_9[11:0] = 12'h257;//599 + + end + 7'h47: + begin + ori_digit_bound_1[11:0] = 12'h1d;//29 + ori_digit_bound_2[11:0] = 12'h66;//102 + ori_digit_bound_3[11:0] = 12'hae;//174 + ori_digit_bound_4[11:0] = 12'hf6;//246 + ori_digit_bound_5[11:0] = 12'h13e;//318 + ori_digit_bound_6[11:0] = 12'h187;//391 + ori_digit_bound_7[11:0] = 12'h1cf;//463 + ori_digit_bound_8[11:0] = 12'h217;//535 + ori_digit_bound_9[11:0] = 12'h260;//608 + + end + 7'h48: + begin + ori_digit_bound_1[11:0] = 12'h1e;//30 + ori_digit_bound_2[11:0] = 12'h67;//103 + ori_digit_bound_3[11:0] = 12'hb0;//176 + ori_digit_bound_4[11:0] = 12'hfa;//250 + ori_digit_bound_5[11:0] = 12'h143;//323 + ori_digit_bound_6[11:0] = 12'h18c;//396 + ori_digit_bound_7[11:0] = 12'h1d5;//469 + ori_digit_bound_8[11:0] = 12'h21f;//543 + ori_digit_bound_9[11:0] = 12'h268;//616 + + end + 7'h49: + begin + ori_digit_bound_1[11:0] = 12'h1e;//30 + ori_digit_bound_2[11:0] = 12'h68;//104 + ori_digit_bound_3[11:0] = 12'hb3;//179 + ori_digit_bound_4[11:0] = 12'hfd;//253 + ori_digit_bound_5[11:0] = 12'h147;//327 + ori_digit_bound_6[11:0] = 12'h192;//402 + ori_digit_bound_7[11:0] = 12'h1dc;//476 + ori_digit_bound_8[11:0] = 12'h226;//550 + ori_digit_bound_9[11:0] = 12'h270;//624 + + end + 7'h4a: + begin + ori_digit_bound_1[11:0] = 12'h1f;//31 + ori_digit_bound_2[11:0] = 12'h6a;//106 + ori_digit_bound_3[11:0] = 12'hb5;//181 + ori_digit_bound_4[11:0] = 12'h100;//256 + ori_digit_bound_5[11:0] = 12'h14c;//332 + ori_digit_bound_6[11:0] = 12'h197;//407 + ori_digit_bound_7[11:0] = 12'h1e2;//482 + ori_digit_bound_8[11:0] = 12'h22d;//557 + ori_digit_bound_9[11:0] = 12'h279;//633 + + end + 7'h4b: + begin + ori_digit_bound_1[11:0] = 12'h1f;//31 + ori_digit_bound_2[11:0] = 12'h6b;//107 + ori_digit_bound_3[11:0] = 12'hb8;//184 + ori_digit_bound_4[11:0] = 12'h104;//260 + ori_digit_bound_5[11:0] = 12'h150;//336 + ori_digit_bound_6[11:0] = 12'h19c;//412 + ori_digit_bound_7[11:0] = 12'h1e9;//489 + ori_digit_bound_8[11:0] = 12'h235;//565 + ori_digit_bound_9[11:0] = 12'h281;//641 + + end + 7'h4c: + begin + ori_digit_bound_1[11:0] = 12'h1f;//31 + ori_digit_bound_2[11:0] = 12'h6d;//109 + ori_digit_bound_3[11:0] = 12'hba;//186 + ori_digit_bound_4[11:0] = 12'h107;//263 + ori_digit_bound_5[11:0] = 12'h154;//340 + ori_digit_bound_6[11:0] = 12'h1a2;//418 + ori_digit_bound_7[11:0] = 12'h1ef;//495 + ori_digit_bound_8[11:0] = 12'h23c;//572 + ori_digit_bound_9[11:0] = 12'h28a;//650 + + end + 7'h4d: + begin + ori_digit_bound_1[11:0] = 12'h20;//32 + ori_digit_bound_2[11:0] = 12'h6e;//110 + ori_digit_bound_3[11:0] = 12'hbc;//188 + ori_digit_bound_4[11:0] = 12'h10b;//267 + ori_digit_bound_5[11:0] = 12'h159;//345 + ori_digit_bound_6[11:0] = 12'h1a7;//423 + ori_digit_bound_7[11:0] = 12'h1f5;//501 + ori_digit_bound_8[11:0] = 12'h244;//580 + ori_digit_bound_9[11:0] = 12'h292;//658 + + end + 7'h4e: + begin + ori_digit_bound_1[11:0] = 12'h20;//32 + ori_digit_bound_2[11:0] = 12'h6f;//111 + ori_digit_bound_3[11:0] = 12'hbf;//191 + ori_digit_bound_4[11:0] = 12'h10e;//270 + ori_digit_bound_5[11:0] = 12'h15d;//349 + ori_digit_bound_6[11:0] = 12'h1ad;//429 + ori_digit_bound_7[11:0] = 12'h1fc;//508 + ori_digit_bound_8[11:0] = 12'h24b;//587 + ori_digit_bound_9[11:0] = 12'h29a;//666 + + end + 7'h4f: + begin + ori_digit_bound_1[11:0] = 12'h21;//33 + ori_digit_bound_2[11:0] = 12'h71;//113 + ori_digit_bound_3[11:0] = 12'hc1;//193 + ori_digit_bound_4[11:0] = 12'h111;//273 + ori_digit_bound_5[11:0] = 12'h162;//354 + ori_digit_bound_6[11:0] = 12'h1b2;//434 + ori_digit_bound_7[11:0] = 12'h202;//514 + ori_digit_bound_8[11:0] = 12'h252;//594 + ori_digit_bound_9[11:0] = 12'h2a3;//675 + + end + 7'h50: + begin + ori_digit_bound_1[11:0] = 12'h21;//33 + ori_digit_bound_2[11:0] = 12'h72;//114 + ori_digit_bound_3[11:0] = 12'hc4;//196 + ori_digit_bound_4[11:0] = 12'h115;//277 + ori_digit_bound_5[11:0] = 12'h166;//358 + ori_digit_bound_6[11:0] = 12'h1b7;//439 + ori_digit_bound_7[11:0] = 12'h209;//521 + ori_digit_bound_8[11:0] = 12'h25a;//602 + ori_digit_bound_9[11:0] = 12'h2ab;//683 + + end + 7'h51: + begin + ori_digit_bound_1[11:0] = 12'h21;//33 + ori_digit_bound_2[11:0] = 12'h74;//116 + ori_digit_bound_3[11:0] = 12'hc6;//198 + ori_digit_bound_4[11:0] = 12'h118;//280 + ori_digit_bound_5[11:0] = 12'h16a;//362 + ori_digit_bound_6[11:0] = 12'h1bd;//445 + ori_digit_bound_7[11:0] = 12'h20f;//527 + ori_digit_bound_8[11:0] = 12'h261;//609 + ori_digit_bound_9[11:0] = 12'h2b4;//692 + + end + 7'h52: + begin + ori_digit_bound_1[11:0] = 12'h22;//34 + ori_digit_bound_2[11:0] = 12'h75;//117 + ori_digit_bound_3[11:0] = 12'hc8;//200 + ori_digit_bound_4[11:0] = 12'h11c;//284 + ori_digit_bound_5[11:0] = 12'h16f;//367 + ori_digit_bound_6[11:0] = 12'h1c2;//450 + ori_digit_bound_7[11:0] = 12'h215;//533 + ori_digit_bound_8[11:0] = 12'h269;//617 + ori_digit_bound_9[11:0] = 12'h2bc;//700 + + end + 7'h53: + begin + ori_digit_bound_1[11:0] = 12'h22;//34 + ori_digit_bound_2[11:0] = 12'h76;//118 + ori_digit_bound_3[11:0] = 12'hcb;//203 + ori_digit_bound_4[11:0] = 12'h11f;//287 + ori_digit_bound_5[11:0] = 12'h173;//371 + ori_digit_bound_6[11:0] = 12'h1c8;//456 + ori_digit_bound_7[11:0] = 12'h21c;//540 + ori_digit_bound_8[11:0] = 12'h270;//624 + ori_digit_bound_9[11:0] = 12'h2c4;//708 + + end + 7'h54: + begin + ori_digit_bound_1[11:0] = 12'h23;//35 + ori_digit_bound_2[11:0] = 12'h78;//120 + ori_digit_bound_3[11:0] = 12'hcd;//205 + ori_digit_bound_4[11:0] = 12'h122;//290 + ori_digit_bound_5[11:0] = 12'h178;//376 + ori_digit_bound_6[11:0] = 12'h1cd;//461 + ori_digit_bound_7[11:0] = 12'h222;//546 + ori_digit_bound_8[11:0] = 12'h277;//631 + ori_digit_bound_9[11:0] = 12'h2cd;//717 + + end + 7'h55: + begin + ori_digit_bound_1[11:0] = 12'h23;//35 + ori_digit_bound_2[11:0] = 12'h79;//121 + ori_digit_bound_3[11:0] = 12'hd0;//208 + ori_digit_bound_4[11:0] = 12'h126;//294 + ori_digit_bound_5[11:0] = 12'h17c;//380 + ori_digit_bound_6[11:0] = 12'h1d2;//466 + ori_digit_bound_7[11:0] = 12'h229;//553 + ori_digit_bound_8[11:0] = 12'h27f;//639 + ori_digit_bound_9[11:0] = 12'h2d5;//725 + + end + 7'h56: + begin + ori_digit_bound_1[11:0] = 12'h23;//35 + ori_digit_bound_2[11:0] = 12'h7b;//123 + ori_digit_bound_3[11:0] = 12'hd2;//210 + ori_digit_bound_4[11:0] = 12'h129;//297 + ori_digit_bound_5[11:0] = 12'h180;//384 + ori_digit_bound_6[11:0] = 12'h1d8;//472 + ori_digit_bound_7[11:0] = 12'h22f;//559 + ori_digit_bound_8[11:0] = 12'h286;//646 + ori_digit_bound_9[11:0] = 12'h2de;//734 + + end + 7'h57: + begin + ori_digit_bound_1[11:0] = 12'h24;//36 + ori_digit_bound_2[11:0] = 12'h7c;//124 + ori_digit_bound_3[11:0] = 12'hd4;//212 + ori_digit_bound_4[11:0] = 12'h12d;//301 + ori_digit_bound_5[11:0] = 12'h185;//389 + ori_digit_bound_6[11:0] = 12'h1dd;//477 + ori_digit_bound_7[11:0] = 12'h235;//565 + ori_digit_bound_8[11:0] = 12'h28e;//654 + ori_digit_bound_9[11:0] = 12'h2e6;//742 + + end + 7'h58: + begin + ori_digit_bound_1[11:0] = 12'h24;//36 + ori_digit_bound_2[11:0] = 12'h7d;//125 + ori_digit_bound_3[11:0] = 12'hd7;//215 + ori_digit_bound_4[11:0] = 12'h130;//304 + ori_digit_bound_5[11:0] = 12'h189;//393 + ori_digit_bound_6[11:0] = 12'h1e3;//483 + ori_digit_bound_7[11:0] = 12'h23c;//572 + ori_digit_bound_8[11:0] = 12'h295;//661 + ori_digit_bound_9[11:0] = 12'h2ee;//750 + + end + 7'h59: + begin + ori_digit_bound_1[11:0] = 12'h25;//37 + ori_digit_bound_2[11:0] = 12'h7f;//127 + ori_digit_bound_3[11:0] = 12'hd9;//217 + ori_digit_bound_4[11:0] = 12'h133;//307 + ori_digit_bound_5[11:0] = 12'h18e;//398 + ori_digit_bound_6[11:0] = 12'h1e8;//488 + ori_digit_bound_7[11:0] = 12'h242;//578 + ori_digit_bound_8[11:0] = 12'h29c;//668 + ori_digit_bound_9[11:0] = 12'h2f7;//759 + + end + 7'h5a: + begin + ori_digit_bound_1[11:0] = 12'h25;//37 + ori_digit_bound_2[11:0] = 12'h80;//128 + ori_digit_bound_3[11:0] = 12'hdc;//220 + ori_digit_bound_4[11:0] = 12'h137;//311 + ori_digit_bound_5[11:0] = 12'h192;//402 + ori_digit_bound_6[11:0] = 12'h1ed;//493 + ori_digit_bound_7[11:0] = 12'h249;//585 + ori_digit_bound_8[11:0] = 12'h2a4;//676 + ori_digit_bound_9[11:0] = 12'h2ff;//767 + + end + 7'h5b: + begin + ori_digit_bound_1[11:0] = 12'h25;//37 + ori_digit_bound_2[11:0] = 12'h82;//130 + ori_digit_bound_3[11:0] = 12'hde;//222 + ori_digit_bound_4[11:0] = 12'h13a;//314 + ori_digit_bound_5[11:0] = 12'h196;//406 + ori_digit_bound_6[11:0] = 12'h1f3;//499 + ori_digit_bound_7[11:0] = 12'h24f;//591 + ori_digit_bound_8[11:0] = 12'h2ab;//683 + ori_digit_bound_9[11:0] = 12'h308;//776 + + end + 7'h5c: + begin + ori_digit_bound_1[11:0] = 12'h26;//38 + ori_digit_bound_2[11:0] = 12'h83;//131 + ori_digit_bound_3[11:0] = 12'he0;//224 + ori_digit_bound_4[11:0] = 12'h13e;//318 + ori_digit_bound_5[11:0] = 12'h19b;//411 + ori_digit_bound_6[11:0] = 12'h1f8;//504 + ori_digit_bound_7[11:0] = 12'h255;//597 + ori_digit_bound_8[11:0] = 12'h2b3;//691 + ori_digit_bound_9[11:0] = 12'h310;//784 + + end + 7'h5d: + begin + ori_digit_bound_1[11:0] = 12'h26;//38 + ori_digit_bound_2[11:0] = 12'h84;//132 + ori_digit_bound_3[11:0] = 12'he3;//227 + ori_digit_bound_4[11:0] = 12'h141;//321 + ori_digit_bound_5[11:0] = 12'h19f;//415 + ori_digit_bound_6[11:0] = 12'h1fe;//510 + ori_digit_bound_7[11:0] = 12'h25c;//604 + ori_digit_bound_8[11:0] = 12'h2ba;//698 + ori_digit_bound_9[11:0] = 12'h318;//792 + + end + 7'h5e: + begin + ori_digit_bound_1[11:0] = 12'h27;//39 + ori_digit_bound_2[11:0] = 12'h86;//134 + ori_digit_bound_3[11:0] = 12'he5;//229 + ori_digit_bound_4[11:0] = 12'h144;//324 + ori_digit_bound_5[11:0] = 12'h1a4;//420 + ori_digit_bound_6[11:0] = 12'h203;//515 + ori_digit_bound_7[11:0] = 12'h262;//610 + ori_digit_bound_8[11:0] = 12'h2c1;//705 + ori_digit_bound_9[11:0] = 12'h321;//801 + + end + 7'h5f: + begin + ori_digit_bound_1[11:0] = 12'h27;//39 + ori_digit_bound_2[11:0] = 12'h87;//135 + ori_digit_bound_3[11:0] = 12'he8;//232 + ori_digit_bound_4[11:0] = 12'h148;//328 + ori_digit_bound_5[11:0] = 12'h1a8;//424 + ori_digit_bound_6[11:0] = 12'h208;//520 + ori_digit_bound_7[11:0] = 12'h269;//617 + ori_digit_bound_8[11:0] = 12'h2c9;//713 + ori_digit_bound_9[11:0] = 12'h329;//809 + + end + 7'h60: + begin + ori_digit_bound_1[11:0] = 12'h27;//39 + ori_digit_bound_2[11:0] = 12'h89;//137 + ori_digit_bound_3[11:0] = 12'hea;//234 + ori_digit_bound_4[11:0] = 12'h14b;//331 + ori_digit_bound_5[11:0] = 12'h1ac;//428 + ori_digit_bound_6[11:0] = 12'h20e;//526 + ori_digit_bound_7[11:0] = 12'h26f;//623 + ori_digit_bound_8[11:0] = 12'h2d0;//720 + ori_digit_bound_9[11:0] = 12'h332;//818 + + end + 7'h61: + begin + ori_digit_bound_1[11:0] = 12'h28;//40 + ori_digit_bound_2[11:0] = 12'h8a;//138 + ori_digit_bound_3[11:0] = 12'hec;//236 + ori_digit_bound_4[11:0] = 12'h14f;//335 + ori_digit_bound_5[11:0] = 12'h1b1;//433 + ori_digit_bound_6[11:0] = 12'h213;//531 + ori_digit_bound_7[11:0] = 12'h275;//629 + ori_digit_bound_8[11:0] = 12'h2d8;//728 + ori_digit_bound_9[11:0] = 12'h33a;//826 + + end + 7'h62: + begin + ori_digit_bound_1[11:0] = 12'h28;//40 + ori_digit_bound_2[11:0] = 12'h8b;//139 + ori_digit_bound_3[11:0] = 12'hef;//239 + ori_digit_bound_4[11:0] = 12'h152;//338 + ori_digit_bound_5[11:0] = 12'h1b5;//437 + ori_digit_bound_6[11:0] = 12'h219;//537 + ori_digit_bound_7[11:0] = 12'h27c;//636 + ori_digit_bound_8[11:0] = 12'h2df;//735 + ori_digit_bound_9[11:0] = 12'h342;//834 + + end + 7'h63: + begin + ori_digit_bound_1[11:0] = 12'h29;//41 + ori_digit_bound_2[11:0] = 12'h8d;//141 + ori_digit_bound_3[11:0] = 12'hf1;//241 + ori_digit_bound_4[11:0] = 12'h155;//341 + ori_digit_bound_5[11:0] = 12'h1ba;//442 + ori_digit_bound_6[11:0] = 12'h21e;//542 + ori_digit_bound_7[11:0] = 12'h282;//642 + ori_digit_bound_8[11:0] = 12'h2e6;//742 + ori_digit_bound_9[11:0] = 12'h34b;//843 + + end + 7'h64: + begin + ori_digit_bound_1[11:0] = 12'h29;//41 + ori_digit_bound_2[11:0] = 12'h8e;//142 + ori_digit_bound_3[11:0] = 12'hf4;//244 + ori_digit_bound_4[11:0] = 12'h159;//345 + ori_digit_bound_5[11:0] = 12'h1be;//446 + ori_digit_bound_6[11:0] = 12'h223;//547 + ori_digit_bound_7[11:0] = 12'h289;//649 + ori_digit_bound_8[11:0] = 12'h2ee;//750 + ori_digit_bound_9[11:0] = 12'h353;//851 + + end + 7'h65: + begin + ori_digit_bound_1[11:0] = 12'h29;//41 + ori_digit_bound_2[11:0] = 12'h90;//144 + ori_digit_bound_3[11:0] = 12'hf6;//246 + ori_digit_bound_4[11:0] = 12'h15c;//348 + ori_digit_bound_5[11:0] = 12'h1c2;//450 + ori_digit_bound_6[11:0] = 12'h229;//553 + ori_digit_bound_7[11:0] = 12'h28f;//655 + ori_digit_bound_8[11:0] = 12'h2f5;//757 + ori_digit_bound_9[11:0] = 12'h35c;//860 + + end + 7'h66: + begin + ori_digit_bound_1[11:0] = 12'h2a;//42 + ori_digit_bound_2[11:0] = 12'h91;//145 + ori_digit_bound_3[11:0] = 12'hf8;//248 + ori_digit_bound_4[11:0] = 12'h160;//352 + ori_digit_bound_5[11:0] = 12'h1c7;//455 + ori_digit_bound_6[11:0] = 12'h22e;//558 + ori_digit_bound_7[11:0] = 12'h295;//661 + ori_digit_bound_8[11:0] = 12'h2fd;//765 + ori_digit_bound_9[11:0] = 12'h364;//868 + + end + 7'h67: + begin + ori_digit_bound_1[11:0] = 12'h2a;//42 + ori_digit_bound_2[11:0] = 12'h92;//146 + ori_digit_bound_3[11:0] = 12'hfb;//251 + ori_digit_bound_4[11:0] = 12'h163;//355 + ori_digit_bound_5[11:0] = 12'h1cb;//459 + ori_digit_bound_6[11:0] = 12'h234;//564 + ori_digit_bound_7[11:0] = 12'h29c;//668 + ori_digit_bound_8[11:0] = 12'h304;//772 + ori_digit_bound_9[11:0] = 12'h36c;//876 + + end + 7'h68: + begin + ori_digit_bound_1[11:0] = 12'h2b;//43 + ori_digit_bound_2[11:0] = 12'h94;//148 + ori_digit_bound_3[11:0] = 12'hfd;//253 + ori_digit_bound_4[11:0] = 12'h166;//358 + ori_digit_bound_5[11:0] = 12'h1d0;//464 + ori_digit_bound_6[11:0] = 12'h239;//569 + ori_digit_bound_7[11:0] = 12'h2a2;//674 + ori_digit_bound_8[11:0] = 12'h30b;//779 + ori_digit_bound_9[11:0] = 12'h375;//885 + + end + 7'h69: + begin + ori_digit_bound_1[11:0] = 12'h2b;//43 + ori_digit_bound_2[11:0] = 12'h95;//149 + ori_digit_bound_3[11:0] = 12'h100;//256 + ori_digit_bound_4[11:0] = 12'h16a;//362 + ori_digit_bound_5[11:0] = 12'h1d4;//468 + ori_digit_bound_6[11:0] = 12'h23e;//574 + ori_digit_bound_7[11:0] = 12'h2a9;//681 + ori_digit_bound_8[11:0] = 12'h313;//787 + ori_digit_bound_9[11:0] = 12'h37d;//893 + + end + 7'h6a: + begin + ori_digit_bound_1[11:0] = 12'h2b;//43 + ori_digit_bound_2[11:0] = 12'h97;//151 + ori_digit_bound_3[11:0] = 12'h102;//258 + ori_digit_bound_4[11:0] = 12'h16d;//365 + ori_digit_bound_5[11:0] = 12'h1d8;//472 + ori_digit_bound_6[11:0] = 12'h244;//580 + ori_digit_bound_7[11:0] = 12'h2af;//687 + ori_digit_bound_8[11:0] = 12'h31a;//794 + ori_digit_bound_9[11:0] = 12'h386;//902 + + end + 7'h6b: + begin + ori_digit_bound_1[11:0] = 12'h2c;//44 + ori_digit_bound_2[11:0] = 12'h98;//152 + ori_digit_bound_3[11:0] = 12'h104;//260 + ori_digit_bound_4[11:0] = 12'h171;//369 + ori_digit_bound_5[11:0] = 12'h1dd;//477 + ori_digit_bound_6[11:0] = 12'h249;//585 + ori_digit_bound_7[11:0] = 12'h2b5;//693 + ori_digit_bound_8[11:0] = 12'h322;//802 + ori_digit_bound_9[11:0] = 12'h38e;//910 + + end + 7'h6c: + begin + ori_digit_bound_1[11:0] = 12'h2c;//44 + ori_digit_bound_2[11:0] = 12'h99;//153 + ori_digit_bound_3[11:0] = 12'h107;//263 + ori_digit_bound_4[11:0] = 12'h174;//372 + ori_digit_bound_5[11:0] = 12'h1e1;//481 + ori_digit_bound_6[11:0] = 12'h24f;//591 + ori_digit_bound_7[11:0] = 12'h2bc;//700 + ori_digit_bound_8[11:0] = 12'h329;//809 + ori_digit_bound_9[11:0] = 12'h396;//918 + + end + 7'h6d: + begin + ori_digit_bound_1[11:0] = 12'h2d;//45 + ori_digit_bound_2[11:0] = 12'h9b;//155 + ori_digit_bound_3[11:0] = 12'h109;//265 + ori_digit_bound_4[11:0] = 12'h177;//375 + ori_digit_bound_5[11:0] = 12'h1e6;//486 + ori_digit_bound_6[11:0] = 12'h254;//596 + ori_digit_bound_7[11:0] = 12'h2c2;//706 + ori_digit_bound_8[11:0] = 12'h330;//816 + ori_digit_bound_9[11:0] = 12'h39f;//927 + + end + 7'h6e: + begin + ori_digit_bound_1[11:0] = 12'h2d;//45 + ori_digit_bound_2[11:0] = 12'h9c;//156 + ori_digit_bound_3[11:0] = 12'h10c;//268 + ori_digit_bound_4[11:0] = 12'h17b;//379 + ori_digit_bound_5[11:0] = 12'h1ea;//490 + ori_digit_bound_6[11:0] = 12'h259;//601 + ori_digit_bound_7[11:0] = 12'h2c9;//713 + ori_digit_bound_8[11:0] = 12'h338;//824 + ori_digit_bound_9[11:0] = 12'h3a7;//935 + + end + 7'h6f: + begin + ori_digit_bound_1[11:0] = 12'h2d;//45 + ori_digit_bound_2[11:0] = 12'h9e;//158 + ori_digit_bound_3[11:0] = 12'h10e;//270 + ori_digit_bound_4[11:0] = 12'h17e;//382 + ori_digit_bound_5[11:0] = 12'h1ee;//494 + ori_digit_bound_6[11:0] = 12'h25f;//607 + ori_digit_bound_7[11:0] = 12'h2cf;//719 + ori_digit_bound_8[11:0] = 12'h33f;//831 + ori_digit_bound_9[11:0] = 12'h3b0;//944 + + end + 7'h70: + begin + ori_digit_bound_1[11:0] = 12'h2e;//46 + ori_digit_bound_2[11:0] = 12'h9f;//159 + ori_digit_bound_3[11:0] = 12'h110;//272 + ori_digit_bound_4[11:0] = 12'h182;//386 + ori_digit_bound_5[11:0] = 12'h1f3;//499 + ori_digit_bound_6[11:0] = 12'h264;//612 + ori_digit_bound_7[11:0] = 12'h2d5;//725 + ori_digit_bound_8[11:0] = 12'h347;//839 + ori_digit_bound_9[11:0] = 12'h3b8;//952 + + end + 7'h71: + begin + ori_digit_bound_1[11:0] = 12'h2e;//46 + ori_digit_bound_2[11:0] = 12'ha0;//160 + ori_digit_bound_3[11:0] = 12'h113;//275 + ori_digit_bound_4[11:0] = 12'h185;//389 + ori_digit_bound_5[11:0] = 12'h1f7;//503 + ori_digit_bound_6[11:0] = 12'h26a;//618 + ori_digit_bound_7[11:0] = 12'h2dc;//732 + ori_digit_bound_8[11:0] = 12'h34e;//846 + ori_digit_bound_9[11:0] = 12'h3c0;//960 + + end + 7'h72: + begin + ori_digit_bound_1[11:0] = 12'h2f;//47 + ori_digit_bound_2[11:0] = 12'ha2;//162 + ori_digit_bound_3[11:0] = 12'h115;//277 + ori_digit_bound_4[11:0] = 12'h188;//392 + ori_digit_bound_5[11:0] = 12'h1fc;//508 + ori_digit_bound_6[11:0] = 12'h26f;//623 + ori_digit_bound_7[11:0] = 12'h2e2;//738 + ori_digit_bound_8[11:0] = 12'h355;//853 + ori_digit_bound_9[11:0] = 12'h3c9;//969 + + end + 7'h73: + begin + ori_digit_bound_1[11:0] = 12'h2f;//47 + ori_digit_bound_2[11:0] = 12'ha3;//163 + ori_digit_bound_3[11:0] = 12'h118;//280 + ori_digit_bound_4[11:0] = 12'h18c;//396 + ori_digit_bound_5[11:0] = 12'h200;//512 + ori_digit_bound_6[11:0] = 12'h274;//628 + ori_digit_bound_7[11:0] = 12'h2e9;//745 + ori_digit_bound_8[11:0] = 12'h35d;//861 + ori_digit_bound_9[11:0] = 12'h3d1;//977 + + end + 7'h74: + begin + ori_digit_bound_1[11:0] = 12'h2f;//47 + ori_digit_bound_2[11:0] = 12'ha5;//165 + ori_digit_bound_3[11:0] = 12'h11a;//282 + ori_digit_bound_4[11:0] = 12'h18f;//399 + ori_digit_bound_5[11:0] = 12'h204;//516 + ori_digit_bound_6[11:0] = 12'h27a;//634 + ori_digit_bound_7[11:0] = 12'h2ef;//751 + ori_digit_bound_8[11:0] = 12'h364;//868 + ori_digit_bound_9[11:0] = 12'h3da;//986 + + end + 7'h75: + begin + ori_digit_bound_1[11:0] = 12'h30;//48 + ori_digit_bound_2[11:0] = 12'ha6;//166 + ori_digit_bound_3[11:0] = 12'h11c;//284 + ori_digit_bound_4[11:0] = 12'h193;//403 + ori_digit_bound_5[11:0] = 12'h209;//521 + ori_digit_bound_6[11:0] = 12'h27f;//639 + ori_digit_bound_7[11:0] = 12'h2f5;//757 + ori_digit_bound_8[11:0] = 12'h36c;//876 + ori_digit_bound_9[11:0] = 12'h3e2;//994 + + end + 7'h76: + begin + ori_digit_bound_1[11:0] = 12'h30;//48 + ori_digit_bound_2[11:0] = 12'ha7;//167 + ori_digit_bound_3[11:0] = 12'h11f;//287 + ori_digit_bound_4[11:0] = 12'h196;//406 + ori_digit_bound_5[11:0] = 12'h20d;//525 + ori_digit_bound_6[11:0] = 12'h285;//645 + ori_digit_bound_7[11:0] = 12'h2fc;//764 + ori_digit_bound_8[11:0] = 12'h373;//883 + ori_digit_bound_9[11:0] = 12'h3ea;//1002 + + end + 7'h77: + begin + ori_digit_bound_1[11:0] = 12'h31;//49 + ori_digit_bound_2[11:0] = 12'ha9;//169 + ori_digit_bound_3[11:0] = 12'h121;//289 + ori_digit_bound_4[11:0] = 12'h199;//409 + ori_digit_bound_5[11:0] = 12'h212;//530 + ori_digit_bound_6[11:0] = 12'h28a;//650 + ori_digit_bound_7[11:0] = 12'h302;//770 + ori_digit_bound_8[11:0] = 12'h37a;//890 + ori_digit_bound_9[11:0] = 12'h3f3;//1011 + + end + 7'h78: + begin + ori_digit_bound_1[11:0] = 12'h31;//49 + ori_digit_bound_2[11:0] = 12'haa;//170 + ori_digit_bound_3[11:0] = 12'h124;//292 + ori_digit_bound_4[11:0] = 12'h19d;//413 + ori_digit_bound_5[11:0] = 12'h216;//534 + ori_digit_bound_6[11:0] = 12'h28f;//655 + ori_digit_bound_7[11:0] = 12'h309;//777 + ori_digit_bound_8[11:0] = 12'h382;//898 + ori_digit_bound_9[11:0] = 12'h3fb;//1019 + + end + 7'h79: + begin + ori_digit_bound_1[11:0] = 12'h31;//49 + ori_digit_bound_2[11:0] = 12'hac;//172 + ori_digit_bound_3[11:0] = 12'h126;//294 + ori_digit_bound_4[11:0] = 12'h1a0;//416 + ori_digit_bound_5[11:0] = 12'h21a;//538 + ori_digit_bound_6[11:0] = 12'h295;//661 + ori_digit_bound_7[11:0] = 12'h30f;//783 + ori_digit_bound_8[11:0] = 12'h389;//905 + ori_digit_bound_9[11:0] = 12'h404;//1028 + + end + 7'h7a: + begin + ori_digit_bound_1[11:0] = 12'h32;//50 + ori_digit_bound_2[11:0] = 12'had;//173 + ori_digit_bound_3[11:0] = 12'h128;//296 + ori_digit_bound_4[11:0] = 12'h1a4;//420 + ori_digit_bound_5[11:0] = 12'h21f;//543 + ori_digit_bound_6[11:0] = 12'h29a;//666 + ori_digit_bound_7[11:0] = 12'h315;//789 + ori_digit_bound_8[11:0] = 12'h391;//913 + ori_digit_bound_9[11:0] = 12'h40c;//1036 + + end + 7'h7b: + begin + ori_digit_bound_1[11:0] = 12'h32;//50 + ori_digit_bound_2[11:0] = 12'hae;//174 + ori_digit_bound_3[11:0] = 12'h12b;//299 + ori_digit_bound_4[11:0] = 12'h1a7;//423 + ori_digit_bound_5[11:0] = 12'h223;//547 + ori_digit_bound_6[11:0] = 12'h2a0;//672 + ori_digit_bound_7[11:0] = 12'h31c;//796 + ori_digit_bound_8[11:0] = 12'h398;//920 + ori_digit_bound_9[11:0] = 12'h414;//1044 + + end + 7'h7c: + begin + ori_digit_bound_1[11:0] = 12'h33;//51 + ori_digit_bound_2[11:0] = 12'hb0;//176 + ori_digit_bound_3[11:0] = 12'h12d;//301 + ori_digit_bound_4[11:0] = 12'h1aa;//426 + ori_digit_bound_5[11:0] = 12'h228;//552 + ori_digit_bound_6[11:0] = 12'h2a5;//677 + ori_digit_bound_7[11:0] = 12'h322;//802 + ori_digit_bound_8[11:0] = 12'h39f;//927 + ori_digit_bound_9[11:0] = 12'h41d;//1053 + + end + 7'h7d: + begin + ori_digit_bound_1[11:0] = 12'h33;//51 + ori_digit_bound_2[11:0] = 12'hb1;//177 + ori_digit_bound_3[11:0] = 12'h130;//304 + ori_digit_bound_4[11:0] = 12'h1ae;//430 + ori_digit_bound_5[11:0] = 12'h22c;//556 + ori_digit_bound_6[11:0] = 12'h2aa;//682 + ori_digit_bound_7[11:0] = 12'h329;//809 + ori_digit_bound_8[11:0] = 12'h3a7;//935 + ori_digit_bound_9[11:0] = 12'h425;//1061 + + end + 7'h7e: + begin + ori_digit_bound_1[11:0] = 12'h33;//51 + ori_digit_bound_2[11:0] = 12'hb3;//179 + ori_digit_bound_3[11:0] = 12'h132;//306 + ori_digit_bound_4[11:0] = 12'h1b1;//433 + ori_digit_bound_5[11:0] = 12'h230;//560 + ori_digit_bound_6[11:0] = 12'h2b0;//688 + ori_digit_bound_7[11:0] = 12'h32f;//815 + ori_digit_bound_8[11:0] = 12'h3ae;//942 + ori_digit_bound_9[11:0] = 12'h42e;//1070 + + end + 7'h7f: + begin + ori_digit_bound_1[11:0] = 12'h34;//52 + ori_digit_bound_2[11:0] = 12'hb4;//180 + ori_digit_bound_3[11:0] = 12'h134;//308 + ori_digit_bound_4[11:0] = 12'h1b5;//437 + ori_digit_bound_5[11:0] = 12'h235;//565 + ori_digit_bound_6[11:0] = 12'h2b5;//693 + ori_digit_bound_7[11:0] = 12'h335;//821 + ori_digit_bound_8[11:0] = 12'h3b6;//950 + ori_digit_bound_9[11:0] = 12'h436;//1078 + + end + 7'h00: + begin + ori_digit_bound_1[11:0] = 12'h34;//52 + ori_digit_bound_2[11:0] = 12'hb5;//181 + ori_digit_bound_3[11:0] = 12'h137;//311 + ori_digit_bound_4[11:0] = 12'h1b8;//440 + ori_digit_bound_5[11:0] = 12'h239;//569 + ori_digit_bound_6[11:0] = 12'h2bb;//699 + ori_digit_bound_7[11:0] = 12'h33c;//828 + ori_digit_bound_8[11:0] = 12'h3bd;//957 + ori_digit_bound_9[11:0] = 12'h43e;//1086 + end + default: + begin + ori_digit_bound_1[11:0] = {12{1'bx}}; + ori_digit_bound_2[11:0] = {12{1'bx}}; + ori_digit_bound_3[11:0] = {12{1'bx}}; + ori_digit_bound_4[11:0] = {12{1'bx}}; + ori_digit_bound_5[11:0] = {12{1'bx}}; + ori_digit_bound_6[11:0] = {12{1'bx}}; + ori_digit_bound_7[11:0] = {12{1'bx}}; + ori_digit_bound_8[11:0] = {12{1'bx}}; + ori_digit_bound_9[11:0] = {12{1'bx}}; + end +endcase +// &CombEnd; @886 +end +// &CombBeg; @887 +always @( bound_sel[6:0]) +begin +case(bound_sel[6:0]) + 7'h40: + begin + sqrt_digit_boundp2_1[11:0] = 12'h21;//33 + sqrt_digit_boundp2_2[11:0] = 12'h62;//98 + sqrt_digit_boundp2_3[11:0] = 12'ha4;//164 + sqrt_digit_boundp2_4[11:0] = 12'he7;//231 + sqrt_digit_boundp2_5[11:0] = 12'h12b;//299 + sqrt_digit_boundp2_6[11:0] = 12'h170;//368 + sqrt_digit_boundp2_7[11:0] = 12'h1b6;//438 + sqrt_digit_boundp2_8[11:0] = 12'h1fd;//509 + sqrt_digit_boundp2_9[11:0] = 12'h245;//581 + end + 7'h50: + begin + sqrt_digit_boundp2_1[11:0] = 12'h29;//41 + sqrt_digit_boundp2_2[11:0] = 12'h7a;//122 + sqrt_digit_boundp2_3[11:0] = 12'hcc;//204 + sqrt_digit_boundp2_4[11:0] = 12'h11f;//287 + sqrt_digit_boundp2_5[11:0] = 12'h173;//371 + sqrt_digit_boundp2_6[11:0] = 12'h1c8;//456 + sqrt_digit_boundp2_7[11:0] = 12'h21e;//542 + sqrt_digit_boundp2_8[11:0] = 12'h275;//629 + sqrt_digit_boundp2_9[11:0] = 12'h2cd;//717 + end + 7'h60: + begin + sqrt_digit_boundp2_1[11:0] = 12'h31;//49 + sqrt_digit_boundp2_2[11:0] = 12'h92;//146 + sqrt_digit_boundp2_3[11:0] = 12'hf4;//244 + sqrt_digit_boundp2_4[11:0] = 12'h157;//343 + sqrt_digit_boundp2_5[11:0] = 12'h1bb;//443 + sqrt_digit_boundp2_6[11:0] = 12'h220;//544 + sqrt_digit_boundp2_7[11:0] = 12'h286;//646 + sqrt_digit_boundp2_8[11:0] = 12'h2ed;//749 + sqrt_digit_boundp2_9[11:0] = 12'h355;//853 + end + 7'h70: + begin + sqrt_digit_boundp2_1[11:0] = 12'h39;//57 + sqrt_digit_boundp2_2[11:0] = 12'haa;//170 + sqrt_digit_boundp2_3[11:0] = 12'h11c;//284 + sqrt_digit_boundp2_4[11:0] = 12'h18f;//399 + sqrt_digit_boundp2_5[11:0] = 12'h203;//515 + sqrt_digit_boundp2_6[11:0] = 12'h278;//632 + sqrt_digit_boundp2_7[11:0] = 12'h2ee;//750 + sqrt_digit_boundp2_8[11:0] = 12'h365;//869 + sqrt_digit_boundp2_9[11:0] = 12'h3dd;//989 + end + 7'h00: + begin + sqrt_digit_boundp2_1[11:0] = 12'h41;//65 + sqrt_digit_boundp2_2[11:0] = 12'hc2;//194 + sqrt_digit_boundp2_3[11:0] = 12'h144;//324 + sqrt_digit_boundp2_4[11:0] = 12'h1c7;//455 + sqrt_digit_boundp2_5[11:0] = 12'h24b;//587 + sqrt_digit_boundp2_6[11:0] = 12'h2d0;//720 + sqrt_digit_boundp2_7[11:0] = 12'h356;//854 + sqrt_digit_boundp2_8[11:0] = 12'h3dd;//989 + sqrt_digit_boundp2_9[11:0] = 12'h465;//1125 + end + default: + begin + sqrt_digit_boundp2_1[11:0] = {12{1'bx}};//-66 + sqrt_digit_boundp2_2[11:0] = {12{1'bx}};//-190 + sqrt_digit_boundp2_3[11:0] = {12{1'bx}};//-324 + sqrt_digit_boundp2_4[11:0] = {12{1'bx}};//-450 + sqrt_digit_boundp2_5[11:0] = {12{1'bx}};//-588 + sqrt_digit_boundp2_6[11:0] = {12{1'bx}};//-720 + sqrt_digit_boundp2_7[11:0] = {12{1'bx}};//-852 + sqrt_digit_boundp2_8[11:0] = {12{1'bx}};//-988 + sqrt_digit_boundp2_9[11:0] = {12{1'bx}};//-1120 + end + +endcase +// &CombEnd; @964 +end +// &CombBeg; @965 +always @( bound_sel[6:0]) +begin +case(bound_sel[6:0]) + 7'h40: + begin + sqrt_digit_boundm2_1[11:0] = 12'h20;//32 + sqrt_digit_boundm2_2[11:0] = 12'h5f;//95 + sqrt_digit_boundm2_3[11:0] = 12'h9d;//157 + sqrt_digit_boundm2_4[11:0] = 12'hda;//218 + sqrt_digit_boundm2_5[11:0] = 12'h116;//278 + sqrt_digit_boundm2_6[11:0] = 12'h151;//337 + sqrt_digit_boundm2_7[11:0] = 12'h18b;//395 + sqrt_digit_boundm2_8[11:0] = 12'h1c4;//452 + sqrt_digit_boundm2_9[11:0] = 12'h1fc;//508 + end + 7'h50: + begin + sqrt_digit_boundm2_1[11:0] = 12'h28;//40 + sqrt_digit_boundm2_2[11:0] = 12'h77;//119 + sqrt_digit_boundm2_3[11:0] = 12'hc5;//197 + sqrt_digit_boundm2_4[11:0] = 12'h112;//274 + sqrt_digit_boundm2_5[11:0] = 12'h15e;//350 + sqrt_digit_boundm2_6[11:0] = 12'h1a9;//425 + sqrt_digit_boundm2_7[11:0] = 12'h1f3;//499 + sqrt_digit_boundm2_8[11:0] = 12'h23c;//572 + sqrt_digit_boundm2_9[11:0] = 12'h284;//644 + end + 7'h60: + begin + sqrt_digit_boundm2_1[11:0] = 12'h30;//48 + sqrt_digit_boundm2_2[11:0] = 12'h8f;//143 + sqrt_digit_boundm2_3[11:0] = 12'hed;//237 + sqrt_digit_boundm2_4[11:0] = 12'h14a;//330 + sqrt_digit_boundm2_5[11:0] = 12'h1a6;//422 + sqrt_digit_boundm2_6[11:0] = 12'h201;//513 + sqrt_digit_boundm2_7[11:0] = 12'h25b;//603 + sqrt_digit_boundm2_8[11:0] = 12'h2b4;//692 + sqrt_digit_boundm2_9[11:0] = 12'h30c;//780 + end + 7'h70: + begin + sqrt_digit_boundm2_1[11:0] = 12'h38;//56 + sqrt_digit_boundm2_2[11:0] = 12'ha7;//167 + sqrt_digit_boundm2_3[11:0] = 12'h115;//277 + sqrt_digit_boundm2_4[11:0] = 12'h182;//386 + sqrt_digit_boundm2_5[11:0] = 12'h1ee;//494 + sqrt_digit_boundm2_6[11:0] = 12'h259;//601 + sqrt_digit_boundm2_7[11:0] = 12'h2c3;//707 + sqrt_digit_boundm2_8[11:0] = 12'h32c;//812 + sqrt_digit_boundm2_9[11:0] = 12'h394;//916 + end + 7'h00: + begin + sqrt_digit_boundm2_1[11:0] = 12'h40;//64 + sqrt_digit_boundm2_2[11:0] = 12'hbf;//191 + sqrt_digit_boundm2_3[11:0] = 12'h13d;//317 + sqrt_digit_boundm2_4[11:0] = 12'h1ba;//442 + sqrt_digit_boundm2_5[11:0] = 12'h236;//566 + sqrt_digit_boundm2_6[11:0] = 12'h2b1;//689 + sqrt_digit_boundm2_7[11:0] = 12'h32b;//811 + sqrt_digit_boundm2_8[11:0] = 12'h3a4;//932 + sqrt_digit_boundm2_9[11:0] = 12'h41c;//1052 + end -// &ModuleEnd; @44 + default: + begin + sqrt_digit_boundm2_1[11:0] = {12{1'bx}};//-66 + sqrt_digit_boundm2_2[11:0] = {12{1'bx}};//-190 + sqrt_digit_boundm2_3[11:0] = {12{1'bx}};//-324 + sqrt_digit_boundm2_4[11:0] = {12{1'bx}};//-450 + sqrt_digit_boundm2_5[11:0] = {12{1'bx}};//-588 + sqrt_digit_boundm2_6[11:0] = {12{1'bx}};//-720 + sqrt_digit_boundm2_7[11:0] = {12{1'bx}};//-852 + sqrt_digit_boundm2_8[11:0] = {12{1'bx}};//-988 + sqrt_digit_boundm2_9[11:0] = {12{1'bx}};//-1120 + end +endcase +// &CombEnd; @1041 +end +assign sqrt_digit_bound2_1[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_1[11:0] : sqrt_digit_boundp2_1[11:0]; +assign sqrt_digit_bound2_2[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_2[11:0] : sqrt_digit_boundp2_2[11:0]; +assign sqrt_digit_bound2_3[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_3[11:0] : sqrt_digit_boundp2_3[11:0]; +assign sqrt_digit_bound2_4[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_4[11:0] : sqrt_digit_boundp2_4[11:0]; +assign sqrt_digit_bound2_5[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_5[11:0] : sqrt_digit_boundp2_5[11:0]; +assign sqrt_digit_bound2_6[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_6[11:0] : sqrt_digit_boundp2_6[11:0]; +assign sqrt_digit_bound2_7[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_7[11:0] : sqrt_digit_boundp2_7[11:0]; +assign sqrt_digit_bound2_8[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_8[11:0] : sqrt_digit_boundp2_8[11:0]; +assign sqrt_digit_bound2_9[11:0] = sqrt_secd_round_sign ? sqrt_digit_boundm2_9[11:0] : sqrt_digit_boundp2_9[11:0]; + + +assign digit_bound_1[11:0] = sqrt_first_round ? 12'h2 : + sqrt_secd_round ? sqrt_digit_bound2_1[11:0] + : ori_digit_bound_1[11:0]; //-2 +assign digit_bound_2[11:0] = sqrt_first_round ? 12'h10 : + sqrt_secd_round ? sqrt_digit_bound2_2[11:0] + : ori_digit_bound_2[11:0]; //-16 +assign digit_bound_3[11:0] = sqrt_first_round ? 12'h35 : + sqrt_secd_round ? sqrt_digit_bound2_3[11:0] + : ori_digit_bound_3[11:0]; //-53 +assign digit_bound_4[11:0] = sqrt_first_round ? 12'h5f : + sqrt_secd_round ? sqrt_digit_bound2_4[11:0] + : ori_digit_bound_4[11:0]; //-95 +assign digit_bound_5[11:0] = sqrt_first_round ? 12'ha0 : + sqrt_secd_round ? sqrt_digit_bound2_5[11:0] + : ori_digit_bound_5[11:0]; //-160 +assign digit_bound_6[11:0] = sqrt_first_round ? 12'hf0 : + sqrt_secd_round ? sqrt_digit_bound2_6[11:0] + : ori_digit_bound_6[11:0]; //-240 +assign digit_bound_7[11:0] = sqrt_first_round ? 12'h14f : + sqrt_secd_round ? sqrt_digit_bound2_7[11:0] + : ori_digit_bound_7[11:0]; //-335 +assign digit_bound_8[11:0] = sqrt_first_round ? 12'h1c2 : + sqrt_secd_round ? sqrt_digit_bound2_8[11:0] + : ori_digit_bound_8[11:0]; //-450 +assign digit_bound_9[11:0] = sqrt_first_round ? 12'h23a : + sqrt_secd_round ? sqrt_digit_bound2_9[11:0] + : ori_digit_bound_9[11:0]; //-570 +// &ModuleEnd; @1080 endmodule -// ----- 8< ----- FILE "./pa_fpu_dp.v" ----- 8< ----- -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +// ----- 8< ----- FILE "./ct_vfdsu_srt_radix16_with_sqrt.v" ----- 8< ----- + +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -26126,293 +32178,1146 @@ See the License for the specific language governing permissions and limitations under the License. */ -module pa_fpu_dp( - cp0_fpu_icg_en, - cp0_fpu_xx_rm, +// &ModuleBeg; @22 +module ct_vfdsu_srt_radix16_with_sqrt( + cp0_vfpu_icg_en, cp0_yy_clk_en, - ctrl_xx_ex1_inst_vld, - ctrl_xx_ex1_stall, - ctrl_xx_ex1_warm_up, - dp_frbus_ex2_data, - dp_frbus_ex2_fflags, - dp_xx_ex1_cnan, - dp_xx_ex1_id, - dp_xx_ex1_inf, - dp_xx_ex1_norm, - dp_xx_ex1_qnan, - dp_xx_ex1_snan, - dp_xx_ex1_zero, - ex2_inst_wb, - fdsu_fpu_ex1_fflags, - fdsu_fpu_ex1_special_sel, - fdsu_fpu_ex1_special_sign, + cpurst_b, forever_cpuclk, - idu_fpu_ex1_eu_sel, - idu_fpu_ex1_func, - idu_fpu_ex1_gateclk_vld, - idu_fpu_ex1_rm, - idu_fpu_ex1_srcf0, - idu_fpu_ex1_srcf1, - idu_fpu_ex1_srcf2, - pad_yy_icg_scan_en + initial_bound_sel_in, + initial_divisor_in, + initial_remainder_in, + initial_srt_en, + initial_srt_sel_div_in, + initial_srt_sel_sqrt_in, + pad_yy_icg_scan_en, + srt_first_round, + srt_remainder, + srt_remainder_out, + srt_remainder_sign, + srt_secd_round, + srt_sm_on, + total_qt_rt, + vdiv_qt_rt ); -input cp0_fpu_icg_en; -input [2 :0] cp0_fpu_xx_rm; -input cp0_yy_clk_en; -input ctrl_xx_ex1_inst_vld; -input ctrl_xx_ex1_stall; -input ctrl_xx_ex1_warm_up; -input [4 :0] fdsu_fpu_ex1_fflags; -input [7 :0] fdsu_fpu_ex1_special_sel; -input [3 :0] fdsu_fpu_ex1_special_sign; -input forever_cpuclk; -input [2 :0] idu_fpu_ex1_eu_sel; -input [9 :0] idu_fpu_ex1_func; -input idu_fpu_ex1_gateclk_vld; -input [2 :0] idu_fpu_ex1_rm; -input [31:0] idu_fpu_ex1_srcf0; -input [31:0] idu_fpu_ex1_srcf1; -input [31:0] idu_fpu_ex1_srcf2; -input pad_yy_icg_scan_en; -output [31:0] dp_frbus_ex2_data; -output [4 :0] dp_frbus_ex2_fflags; -output [2 :0] dp_xx_ex1_cnan; -output [2 :0] dp_xx_ex1_id; -output [2 :0] dp_xx_ex1_inf; -output [2 :0] dp_xx_ex1_norm; -output [2 :0] dp_xx_ex1_qnan; -output [2 :0] dp_xx_ex1_snan; -output [2 :0] dp_xx_ex1_zero; -output ex2_inst_wb; - -reg [4 :0] ex1_fflags; -reg [31:0] ex1_special_data; -reg [8 :0] ex1_special_sel; -reg [3 :0] ex1_special_sign; -reg [4 :0] ex2_fflags; -reg [31:0] ex2_result; -reg [31:0] ex2_special_data; -reg [6 :0] ex2_special_sel; -reg [3 :0] ex2_special_sign; - -wire cp0_fpu_icg_en; -wire [2 :0] cp0_fpu_xx_rm; -wire cp0_yy_clk_en; -wire ctrl_xx_ex1_inst_vld; -wire ctrl_xx_ex1_stall; -wire ctrl_xx_ex1_warm_up; -wire [31:0] dp_frbus_ex2_data; -wire [4 :0] dp_frbus_ex2_fflags; -wire [2 :0] dp_xx_ex1_cnan; -wire [2 :0] dp_xx_ex1_id; -wire [2 :0] dp_xx_ex1_inf; -wire [2 :0] dp_xx_ex1_norm; -wire [2 :0] dp_xx_ex1_qnan; -wire [2 :0] dp_xx_ex1_snan; -wire [2 :0] dp_xx_ex1_zero; -wire [2 :0] ex1_decode_rm; -wire ex1_double; -wire [2 :0] ex1_eu_sel; -wire [9 :0] ex1_func; -wire [2 :0] ex1_global_rm; -wire [2 :0] ex1_rm; -wire ex1_single; -wire [31:0] ex1_special_data_final; -wire [63:0] ex1_src0; -wire [63:0] ex1_src1; -wire [63:0] ex1_src2; -wire ex1_src2_vld; -wire [2 :0] ex1_src_cnan; -wire [2 :0] ex1_src_id; -wire [2 :0] ex1_src_inf; -wire [2 :0] ex1_src_norm; -wire [2 :0] ex1_src_qnan; -wire [2 :0] ex1_src_snan; -wire [2 :0] ex1_src_zero; -wire ex2_data_clk; -wire ex2_data_clk_en; -wire ex2_inst_wb; -wire [4 :0] fdsu_fpu_ex1_fflags; -wire [7 :0] fdsu_fpu_ex1_special_sel; -wire [3 :0] fdsu_fpu_ex1_special_sign; -wire forever_cpuclk; -wire [2 :0] idu_fpu_ex1_eu_sel; -wire [9 :0] idu_fpu_ex1_func; -wire idu_fpu_ex1_gateclk_vld; -wire [2 :0] idu_fpu_ex1_rm; -wire [31:0] idu_fpu_ex1_srcf0; -wire [31:0] idu_fpu_ex1_srcf1; -wire [31:0] idu_fpu_ex1_srcf2; -wire pad_yy_icg_scan_en; - - -parameter DOUBLE_WIDTH =64; -parameter SINGLE_WIDTH =32; -parameter FUNC_WIDTH =10; +// &Ports; @23 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input forever_cpuclk; +input [6 :0] initial_bound_sel_in; +input [55:0] initial_divisor_in; +input [60:0] initial_remainder_in; +input initial_srt_en; +input initial_srt_sel_div_in; +input initial_srt_sel_sqrt_in; +input pad_yy_icg_scan_en; +input srt_first_round; +input srt_secd_round; +input srt_sm_on; +output [60:0] srt_remainder; +output [59:0] srt_remainder_out; +output srt_remainder_sign; +output [57:0] total_qt_rt; +output [57:0] vdiv_qt_rt; + +// &Regs; @24 +reg [6 :0] bound_sel; +reg [60:0] cur_rem; +reg [57:0] qt_rt_const_shift_std; +reg [55:0] srt_divisor; +reg [60:0] srt_remainder; +reg [60:0] srt_remainder_minus; +reg [60:0] srt_remainder_minus_nxt; +reg srt_sel_div; +reg srt_sel_sqrt; +reg [57:0] total_qt_rt; +reg [57:0] total_qt_rt_minus; +reg [57:0] total_qt_rt_minus_next; +reg [57:0] total_qt_rt_next; + +// &Wires; @25 +wire bound1_cmp_sign; +wire bound2_cmp_sign; +wire bound3_cmp_sign; +wire bound4_cmp_sign; +wire bound5_cmp_sign; +wire bound6_cmp_sign; +wire bound7_cmp_sign; +wire bound8_cmp_sign; +wire bound9_cmp_sign; +wire [8 :0] bound_cmp_sign; +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire [60:0] cur_rem_1; +wire [60:0] cur_rem_2; +wire [60:0] cur_rem_3; +wire [60:0] cur_rem_4; +wire [60:0] cur_rem_5; +wire [60:0] cur_rem_6; +wire [60:0] cur_rem_7; +wire [60:0] cur_rem_8; +wire [60:0] cur_rem_9; +wire [11:0] digit_bound_1; +wire [11:0] digit_bound_2; +wire [11:0] digit_bound_3; +wire [11:0] digit_bound_4; +wire [11:0] digit_bound_5; +wire [11:0] digit_bound_6; +wire [11:0] digit_bound_7; +wire [11:0] digit_bound_8; +wire [11:0] digit_bound_9; +wire [60:0] div_qt_1_rem_add_op1; +wire [60:0] div_qt_2_rem_add_op1; +wire [60:0] div_qt_3_rem_add_op1_0; +wire [60:0] div_qt_3_rem_add_op1_1; +wire [60:0] div_qt_4_rem_add_op1; +wire [60:0] div_qt_5_rem_add_op1_0; +wire [60:0] div_qt_5_rem_add_op1_1; +wire [60:0] div_qt_6_rem_add_op1_0; +wire [60:0] div_qt_6_rem_add_op1_1; +wire [60:0] div_qt_7_rem_add_op1_0; +wire [60:0] div_qt_7_rem_add_op1_1; +wire [60:0] div_qt_8_rem_add_op1; +wire [60:0] div_qt_9_rem_add_op1_0; +wire [60:0] div_qt_9_rem_add_op1_1; +wire [60:0] div_qt_r1_rem_add_op1; +wire [60:0] div_qt_r2_rem_add_op1; +wire [60:0] div_qt_r3_rem_add_op1_0; +wire [60:0] div_qt_r3_rem_add_op1_1; +wire [60:0] div_qt_r4_rem_add_op1; +wire [60:0] div_qt_r5_rem_add_op1_0; +wire [60:0] div_qt_r5_rem_add_op1_1; +wire [60:0] div_qt_r6_rem_add_op1_0; +wire [60:0] div_qt_r6_rem_add_op1_1; +wire [60:0] div_qt_r7_rem_add_op1_0; +wire [60:0] div_qt_r7_rem_add_op1_1; +wire [60:0] div_qt_r8_rem_add_op1; +wire [60:0] div_qt_r9_rem_add_op1_0; +wire [60:0] div_qt_r9_rem_add_op1_1; +wire [60:0] div_rem_add1_op1; +wire [60:0] div_rem_add2_op1; +wire [60:0] div_rem_add3_op1_0; +wire [60:0] div_rem_add3_op1_1; +wire [60:0] div_rem_add4_op1; +wire [60:0] div_rem_add5_op1_0; +wire [60:0] div_rem_add5_op1_1; +wire [60:0] div_rem_add6_op1_0; +wire [60:0] div_rem_add6_op1_1; +wire [60:0] div_rem_add7_op1_0; +wire [60:0] div_rem_add7_op1_1; +wire [60:0] div_rem_add8_op1; +wire [60:0] div_rem_add9_op1_0; +wire [60:0] div_rem_add9_op1_1; +wire forever_cpuclk; +wire [6 :0] initial_bound_sel_in; +wire [55:0] initial_divisor_in; +wire [60:0] initial_remainder_in; +wire initial_srt_en; +wire initial_srt_sel_div_in; +wire initial_srt_sel_sqrt_in; +wire pad_yy_icg_scan_en; +wire [11:0] part_rem; +wire [62:0] qt_rt_const_q1; +wire [62:0] qt_rt_const_q10; +wire [62:0] qt_rt_const_q11; +wire [62:0] qt_rt_const_q112; +wire [62:0] qt_rt_const_q12; +wire [62:0] qt_rt_const_q128; +wire [62:0] qt_rt_const_q13; +wire [62:0] qt_rt_const_q14; +wire [62:0] qt_rt_const_q15; +wire [62:0] qt_rt_const_q16; +wire [62:0] qt_rt_const_q17; +wire [62:0] qt_rt_const_q192; +wire [62:0] qt_rt_const_q2; +wire [62:0] qt_rt_const_q23; +wire [62:0] qt_rt_const_q24; +wire [62:0] qt_rt_const_q27; +wire [62:0] qt_rt_const_q3; +wire [62:0] qt_rt_const_q31; +wire [62:0] qt_rt_const_q32; +wire [62:0] qt_rt_const_q4; +wire [62:0] qt_rt_const_q44; +wire [62:0] qt_rt_const_q5; +wire [62:0] qt_rt_const_q56; +wire [62:0] qt_rt_const_q6; +wire [62:0] qt_rt_const_q60; +wire [62:0] qt_rt_const_q64; +wire [62:0] qt_rt_const_q7; +wire [62:0] qt_rt_const_q8; +wire [62:0] qt_rt_const_q80; +wire [62:0] qt_rt_const_q9; +wire [57:0] qt_rt_const_shift_std_next; +wire [60:0] rem_add1_op1; +wire [60:0] rem_add2_op1; +wire [60:0] rem_add3_op1_0; +wire [60:0] rem_add3_op1_1; +wire [60:0] rem_add4_op1; +wire [60:0] rem_add5_op1_0; +wire [60:0] rem_add5_op1_1; +wire [60:0] rem_add6_op1_0; +wire [60:0] rem_add6_op1_1; +wire [60:0] rem_add7_op1_0; +wire [60:0] rem_add7_op1_1; +wire [60:0] rem_add8_op1; +wire [60:0] rem_add9_op1_0; +wire [60:0] rem_add9_op1_1; +wire [60:0] rem_minus_minus_6; +wire rem_sign; +wire [60:0] remainder_minus_nor_nxt_0; +wire [60:0] remainder_minus_nor_nxt_1; +wire [60:0] remainder_minus_nor_nxt_2; +wire [60:0] remainder_minus_nor_nxt_3; +wire [60:0] remainder_minus_nor_nxt_4; +wire [60:0] remainder_minus_nor_nxt_5; +wire [60:0] remainder_minus_nor_nxt_6; +wire [60:0] remainder_minus_nor_nxt_7; +wire [60:0] remainder_minus_nor_nxt_8; +wire [60:0] remainder_minus_nor_nxt_9; +wire [60:0] remainder_minus_shift; +wire [60:0] remainder_shift; +wire sqrt_first_round; +wire [60:0] sqrt_qt_1_rem_add_op1; +wire [60:0] sqrt_qt_2_rem_add_op1; +wire [60:0] sqrt_qt_3_rem_add_op1_0; +wire [60:0] sqrt_qt_3_rem_add_op1_1; +wire [60:0] sqrt_qt_4_rem_add_op1; +wire [60:0] sqrt_qt_5_rem_add_op1_0; +wire [60:0] sqrt_qt_5_rem_add_op1_1; +wire [60:0] sqrt_qt_6_rem_add_op1_0; +wire [60:0] sqrt_qt_6_rem_add_op1_1; +wire [60:0] sqrt_qt_7_rem_add_op1_0; +wire [60:0] sqrt_qt_7_rem_add_op1_1; +wire [60:0] sqrt_qt_8_rem_add_op1; +wire [60:0] sqrt_qt_9_rem_add_op1_0; +wire [60:0] sqrt_qt_9_rem_add_op1_1; +wire [60:0] sqrt_qt_r1_rem_add_op1; +wire [60:0] sqrt_qt_r2_rem_add_op1; +wire [60:0] sqrt_qt_r3_rem_add_op1_0; +wire [60:0] sqrt_qt_r3_rem_add_op1_1; +wire [60:0] sqrt_qt_r4_rem_add_op1; +wire [60:0] sqrt_qt_r5_rem_add_op1_0; +wire [60:0] sqrt_qt_r5_rem_add_op1_1; +wire [60:0] sqrt_qt_r6_rem_add_op1_0; +wire [60:0] sqrt_qt_r6_rem_add_op1_1; +wire [60:0] sqrt_qt_r7_rem_add_op1_0; +wire [60:0] sqrt_qt_r7_rem_add_op1_1; +wire [60:0] sqrt_qt_r8_rem_add_op1; +wire [60:0] sqrt_qt_r9_rem_add_op1_0; +wire [60:0] sqrt_qt_r9_rem_add_op1_1; +wire [60:0] sqrt_rem_add1_op1; +wire [60:0] sqrt_rem_add2_op1; +wire [60:0] sqrt_rem_add3_op1_0; +wire [60:0] sqrt_rem_add3_op1_1; +wire [60:0] sqrt_rem_add4_op1; +wire [60:0] sqrt_rem_add5_op1_0; +wire [60:0] sqrt_rem_add5_op1_1; +wire [60:0] sqrt_rem_add6_op1_0; +wire [60:0] sqrt_rem_add6_op1_1; +wire [60:0] sqrt_rem_add7_op1_0; +wire [60:0] sqrt_rem_add7_op1_1; +wire [60:0] sqrt_rem_add8_op1; +wire [60:0] sqrt_rem_add9_op1_0; +wire [60:0] sqrt_rem_add9_op1_1; +wire sqrt_secd_round; +wire sqrt_secd_round_sign; +wire srt_div_clk; +wire srt_div_clk_en; +wire srt_first_round; +wire srt_qt_rem_clk; +wire srt_qt_rem_clk_en; +wire [60:0] srt_remainder_nxt; +wire [59:0] srt_remainder_out; +wire srt_remainder_sign; +wire srt_secd_round; +wire srt_sm_on; +wire [57:0] vdiv_qt_rt; + + +parameter DATA_WIDTH = 56; +parameter REM_WIDTH = 61; +parameter QT_WIDTH = 58; //========================================================== -// EX1 special data path +// SRT Remainder & Divisor for Quotient/Root Generate //========================================================== -assign ex1_eu_sel[2:0] = idu_fpu_ex1_eu_sel[2:0]; //3'h4 -assign ex1_func[FUNC_WIDTH-1:0] = idu_fpu_ex1_func[FUNC_WIDTH-1:0]; -assign ex1_global_rm[2:0] = cp0_fpu_xx_rm[2:0]; -assign ex1_decode_rm[2:0] = idu_fpu_ex1_rm[2:0]; +assign srt_qt_rem_clk_en = initial_srt_en || srt_sm_on; -assign ex1_rm[2:0] = (ex1_decode_rm[2:0]==3'b111) - ? ex1_global_rm[2:0] : ex1_decode_rm[2:0]; - -assign ex1_src2_vld = idu_fpu_ex1_eu_sel[1] && ex1_func[0]; - -assign ex1_src0[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf0[SINGLE_WIDTH-1:0]}; -assign ex1_src1[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf1[SINGLE_WIDTH-1:0]}; -assign ex1_src2[DOUBLE_WIDTH-1:0] = ex1_src2_vld ? { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf2[SINGLE_WIDTH-1:0]} - : { {SINGLE_WIDTH{1'b1}},{SINGLE_WIDTH{1'b0}} }; - -assign ex1_double = 1'b0; -assign ex1_single = 1'b1; - -//========================================================== -// EX1 special src data judge -//========================================================== -pa_fpu_src_type x_pa_fpu_ex1_srcf0_type ( - .inst_double (ex1_double ), - .inst_single (ex1_single ), - .src_cnan (ex1_src_cnan[0]), - .src_id (ex1_src_id[0] ), - .src_in (ex1_src0 ), - .src_inf (ex1_src_inf[0] ), - .src_norm (ex1_src_norm[0]), - .src_qnan (ex1_src_qnan[0]), - .src_snan (ex1_src_snan[0]), - .src_zero (ex1_src_zero[0]) +// &Instance("gated_clk_cell","x_srt_qt_rem_clk"); @35 +gated_clk_cell x_srt_qt_rem_clk ( + .clk_in (forever_cpuclk ), + .clk_out (srt_qt_rem_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (srt_qt_rem_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -pa_fpu_src_type x_pa_fpu_ex1_srcf1_type ( - .inst_double (ex1_double ), - .inst_single (ex1_single ), - .src_cnan (ex1_src_cnan[1]), - .src_id (ex1_src_id[1] ), - .src_in (ex1_src1 ), - .src_inf (ex1_src_inf[1] ), - .src_norm (ex1_src_norm[1]), - .src_qnan (ex1_src_qnan[1]), - .src_snan (ex1_src_snan[1]), - .src_zero (ex1_src_zero[1]) -); +// &Connect( .clk_in (forever_cpuclk), @36 +// .clk_out (srt_qt_rem_clk), @37 +// .external_en (1'b0), @38 +// .global_en (cp0_yy_clk_en), @39 +// .local_en (srt_qt_rem_clk_en), @40 +// .module_en (cp0_vfpu_icg_en) @41 +// ); @42 + +assign srt_div_clk_en = initial_srt_en; -pa_fpu_src_type x_pa_fpu_ex1_srcf2_type ( - .inst_double (ex1_double ), - .inst_single (ex1_single ), - .src_cnan (ex1_src_cnan[2]), - .src_id (ex1_src_id[2] ), - .src_in (ex1_src2 ), - .src_inf (ex1_src_inf[2] ), - .src_norm (ex1_src_norm[2]), - .src_qnan (ex1_src_qnan[2]), - .src_snan (ex1_src_snan[2]), - .src_zero (ex1_src_zero[2]) +// &Instance("gated_clk_cell","x_srt_div_clk"); @46 +gated_clk_cell x_srt_div_clk ( + .clk_in (forever_cpuclk ), + .clk_out (srt_div_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (srt_div_clk_en ), + .module_en (cp0_vfpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) ); -assign dp_xx_ex1_cnan[2:0] = ex1_src_cnan[2:0]; -assign dp_xx_ex1_snan[2:0] = ex1_src_snan[2:0]; -assign dp_xx_ex1_qnan[2:0] = ex1_src_qnan[2:0]; -assign dp_xx_ex1_norm[2:0] = ex1_src_norm[2:0]; -assign dp_xx_ex1_zero[2:0] = ex1_src_zero[2:0]; -assign dp_xx_ex1_inf[2:0] = ex1_src_inf[2:0]; -assign dp_xx_ex1_id[2:0] = ex1_src_id[2:0]; +// &Connect( .clk_in (forever_cpuclk), @47 +// .clk_out (srt_div_clk), @48 +// .external_en (1'b0), @49 +// .global_en (cp0_yy_clk_en), @50 +// .local_en (srt_div_clk_en), @51 +// .module_en (cp0_vfpu_icg_en) @52 +// ); @53 -//========================================================== -// EX1 special result judge -//========================================================== +always @(posedge srt_qt_rem_clk or negedge cpurst_b) +begin + if(!cpurst_b) + srt_remainder[REM_WIDTH-1:0] <= {REM_WIDTH{1'b0}}; + else if(initial_srt_en) + srt_remainder[REM_WIDTH-1:0] <= initial_remainder_in[REM_WIDTH-1:0]; + else if(srt_sm_on) + srt_remainder[REM_WIDTH-1:0] <= srt_remainder_nxt[REM_WIDTH-1:0]; + else + srt_remainder[REM_WIDTH-1:0] <= srt_remainder[REM_WIDTH-1:0]; +end +// &Force("output","srt_remainder"); @66 +always @(posedge srt_div_clk or negedge cpurst_b) +begin + if(!cpurst_b) + srt_divisor[DATA_WIDTH-1:0] <= {DATA_WIDTH{1'b0}}; + else if(initial_srt_en) + srt_divisor[DATA_WIDTH-1:0] <= initial_divisor_in[DATA_WIDTH-1:0]; + else + srt_divisor[DATA_WIDTH-1:0] <= srt_divisor[DATA_WIDTH-1:0]; +end -always @( fdsu_fpu_ex1_special_sign[3:0] - or fdsu_fpu_ex1_fflags[4:0] - or ex1_eu_sel[2:0] - or fdsu_fpu_ex1_special_sel[7:0]) +always @(posedge srt_qt_rem_clk or negedge cpurst_b) begin -case(ex1_eu_sel[2:0]) //3'h4 - 3'b100: begin//FDSU - ex1_fflags[4:0] = fdsu_fpu_ex1_fflags[4:0]; - ex1_special_sel[8:0] ={1'b0,fdsu_fpu_ex1_special_sel[7:0]}; - ex1_special_sign[3:0] = fdsu_fpu_ex1_special_sign[3:0]; - end -default: begin//FDSU - ex1_fflags[4:0] = {5{1'b0}}; - ex1_special_sel[8:0] = {9{1'b0}}; - ex1_special_sign[3:0] = {4{1'b0}}; - end -endcase + if(!cpurst_b) + bound_sel[6:0] <= {7{1'b0}}; + else if(initial_srt_en) + bound_sel[6:0] <= initial_bound_sel_in[6:0]; + else if(srt_sm_on && srt_sel_sqrt) + bound_sel[6:0] <= total_qt_rt_next[QT_WIDTH-2:QT_WIDTH-8]; + else + bound_sel[6:0] <= bound_sel[6:0]; end -always @( ex1_special_sel[8:5] - or ex1_src0[31:0] - or ex1_src1[31:0] - or ex1_src2[31:0]) +always @(posedge srt_div_clk or negedge cpurst_b) begin -case(ex1_special_sel[8:5]) - 4'b0001: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src0[SINGLE_WIDTH-1:0]; - 4'b0010: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src1[SINGLE_WIDTH-1:0]; - 4'b0100: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; -default : ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; -endcase + if(!cpurst_b) + srt_sel_div <= 1'b0; + else if(initial_srt_en) + srt_sel_div <= initial_srt_sel_div_in; + else + srt_sel_div <= srt_sel_div; end -assign ex1_special_data_final[SINGLE_WIDTH-1:0] = ex1_special_data[SINGLE_WIDTH-1:0]; +always @(posedge srt_div_clk or negedge cpurst_b) +begin + if(!cpurst_b) + srt_sel_sqrt <= 1'b0; + else if(initial_srt_en) + srt_sel_sqrt <= initial_srt_sel_sqrt_in; + else + srt_sel_sqrt <= srt_sel_sqrt; +end -//========================================================== -// EX1-EX2 data pipedown -//========================================================== -assign ex2_data_clk_en = idu_fpu_ex1_gateclk_vld || ctrl_xx_ex1_warm_up; +always @(posedge srt_qt_rem_clk or negedge cpurst_b) +begin + if(!cpurst_b) + begin + qt_rt_const_shift_std[QT_WIDTH-1:0] <= {QT_WIDTH{1'b0}}; + total_qt_rt[QT_WIDTH-1:0] <= {QT_WIDTH{1'b0}}; + total_qt_rt_minus[QT_WIDTH-1:0] <= {QT_WIDTH{1'b0}}; + end + else if(initial_srt_en) + begin + qt_rt_const_shift_std[QT_WIDTH-1:0] <= {4'b0001,{(QT_WIDTH-4){1'b0}}}; + total_qt_rt[QT_WIDTH-1:0] <= {QT_WIDTH{1'b0}}; + total_qt_rt_minus[QT_WIDTH-1:0] <= {QT_WIDTH{1'b0}}; + end + else if(srt_sm_on) + begin + qt_rt_const_shift_std[QT_WIDTH-1:0] <= qt_rt_const_shift_std_next[QT_WIDTH-1:0]; + total_qt_rt[QT_WIDTH-1:0] <= total_qt_rt_next[QT_WIDTH-1:0]; + total_qt_rt_minus[QT_WIDTH-1:0] <= total_qt_rt_minus_next[QT_WIDTH-1:0]; + end + else + begin + qt_rt_const_shift_std[QT_WIDTH-1:0] <= qt_rt_const_shift_std[QT_WIDTH-1:0]; + total_qt_rt[QT_WIDTH-1:0] <= total_qt_rt[QT_WIDTH-1:0]; + total_qt_rt_minus[QT_WIDTH-1:0] <= total_qt_rt_minus[QT_WIDTH-1:0]; + end +end -gated_clk_cell x_fpu_data_ex2_gated_clk ( - .clk_in (forever_cpuclk ), - .clk_out (ex2_data_clk ), - .external_en (1'b0 ), - .global_en (cp0_yy_clk_en ), - .local_en (ex2_data_clk_en ), - .module_en (cp0_fpu_icg_en ), - .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +// &Force("output","total_qt_rt"); @137 +// &Force("output","vdiv_qt_rt"); @138 + +assign vdiv_qt_rt[QT_WIDTH-1:0] = srt_remainder[REM_WIDTH-1] + ? total_qt_rt_minus[QT_WIDTH-1:0] + : total_qt_rt[QT_WIDTH-1:0]; + +assign qt_rt_const_shift_std_next[QT_WIDTH-1:0] = {4'b0, qt_rt_const_shift_std[QT_WIDTH-1:4]}; + +//==================================================== +// boundary calculation +//==================================================== +//assign bound_sel[6:0] = srt_sel_div ? srt_divisor[DATA_WIDTH-1:DATA_WIDTH-7] +// : total_qt_rt[QT_WIDTH-2:QT_WIDTH-8]; + +// &Instance("ct_vfdsu_srt_radix16_bound_table"); @152 +ct_vfdsu_srt_radix16_bound_table x_ct_vfdsu_srt_radix16_bound_table ( + .bound_sel (bound_sel ), + .digit_bound_1 (digit_bound_1 ), + .digit_bound_2 (digit_bound_2 ), + .digit_bound_3 (digit_bound_3 ), + .digit_bound_4 (digit_bound_4 ), + .digit_bound_5 (digit_bound_5 ), + .digit_bound_6 (digit_bound_6 ), + .digit_bound_7 (digit_bound_7 ), + .digit_bound_8 (digit_bound_8 ), + .digit_bound_9 (digit_bound_9 ), + .sqrt_first_round (sqrt_first_round ), + .sqrt_secd_round (sqrt_secd_round ), + .sqrt_secd_round_sign (sqrt_secd_round_sign) ); -always @(posedge ex2_data_clk) +assign sqrt_first_round = srt_sel_sqrt && srt_first_round; +assign sqrt_secd_round = srt_sel_sqrt && srt_secd_round; +assign sqrt_secd_round_sign = rem_sign; +assign rem_sign = srt_remainder[REM_WIDTH-1]; +assign part_rem[11:0] = rem_sign + ? ~srt_remainder[REM_WIDTH-5:REM_WIDTH-16] + : srt_remainder[REM_WIDTH-5:REM_WIDTH-16]; +// &Force("nonport","bound1_cmp_result"); @160 +// &Force("nonport","bound2_cmp_result"); @161 +// &Force("nonport","bound3_cmp_result"); @162 +// &Force("nonport","bound4_cmp_result"); @163 +// &Force("nonport","bound5_cmp_result"); @164 +// &Force("nonport","bound6_cmp_result"); @165 +// &Force("nonport","bound7_cmp_result"); @166 +// &Force("nonport","bound8_cmp_result"); @167 +// &Force("nonport","bound9_cmp_result"); @168 +// &Force("bus","bound1_cmp_result",11,0); @169 +// &Force("bus","bound2_cmp_result",11,0); @170 +// &Force("bus","bound3_cmp_result",11,0); @171 +// &Force("bus","bound4_cmp_result",11,0); @172 +// &Force("bus","bound5_cmp_result",11,0); @173 +// &Force("bus","bound6_cmp_result",11,0); @174 +// &Force("bus","bound7_cmp_result",11,0); @175 +// &Force("bus","bound8_cmp_result",11,0); @176 +// &Force("bus","bound9_cmp_result",11,0); @177 +// &Force("nonport","digit_bound_1"); @178 +// &Force("nonport","digit_bound_2"); @179 +// &Force("nonport","digit_bound_3"); @180 +// &Force("nonport","digit_bound_4"); @181 +// &Force("nonport","digit_bound_5"); @182 +// &Force("nonport","digit_bound_6"); @183 +// &Force("nonport","digit_bound_7"); @184 +// &Force("nonport","digit_bound_8"); @185 +// &Force("nonport","digit_bound_9"); @186 +// &Force("nonport","part_rem"); @187 +////csky vperl_off +//assign bound1_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_1[11:0])); +//assign bound2_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_2[11:0])); +//assign bound3_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_3[11:0])); +//assign bound4_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_4[11:0])); +//assign bound5_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_5[11:0])); +//assign bound6_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_6[11:0])); +//assign bound7_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_7[11:0])); +//assign bound8_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_8[11:0])); +//assign bound9_cmp_result[11:0] = $unsigned($signed(part_rem[11:0]) +// + $signed(digit_bound_9[11:0])); +////csky vperl_on +//assign bound1_cmp_sign = bound1_cmp_result[11]; +//assign bound2_cmp_sign = bound2_cmp_result[11]; +//assign bound3_cmp_sign = bound3_cmp_result[11]; +//assign bound4_cmp_sign = bound4_cmp_result[11]; +//assign bound5_cmp_sign = bound5_cmp_result[11]; +//assign bound6_cmp_sign = bound6_cmp_result[11]; +//assign bound7_cmp_sign = bound7_cmp_result[11]; +//assign bound8_cmp_sign = bound8_cmp_result[11]; +//assign bound9_cmp_sign = bound9_cmp_result[11]; +assign bound1_cmp_sign = part_rem[11:0] < digit_bound_1[11:0]; +assign bound2_cmp_sign = part_rem[11:0] < digit_bound_2[11:0]; +assign bound3_cmp_sign = part_rem[11:0] < digit_bound_3[11:0]; +assign bound4_cmp_sign = part_rem[11:0] < digit_bound_4[11:0]; +assign bound5_cmp_sign = part_rem[11:0] < digit_bound_5[11:0]; +assign bound6_cmp_sign = part_rem[11:0] < digit_bound_6[11:0]; +assign bound7_cmp_sign = part_rem[11:0] < digit_bound_7[11:0]; +assign bound8_cmp_sign = part_rem[11:0] < digit_bound_8[11:0]; +assign bound9_cmp_sign = part_rem[11:0] < digit_bound_9[11:0]; +//==================================================== +// remainder calculation +//==================================================== +// the root preparation +assign qt_rt_const_q1[REM_WIDTH+1:0] = {5'b0,qt_rt_const_shift_std[QT_WIDTH-1:0]}; +assign qt_rt_const_q2[REM_WIDTH+1:0] = {4'b0,qt_rt_const_shift_std[QT_WIDTH-1:0],1'b0}; +assign qt_rt_const_q4[REM_WIDTH+1:0] = {3'b0,qt_rt_const_shift_std[QT_WIDTH-1:0],2'b0}; +assign qt_rt_const_q8[REM_WIDTH+1:0] = {2'b0,qt_rt_const_shift_std[QT_WIDTH-1:0],3'b0}; +assign qt_rt_const_q16[REM_WIDTH+1:0] = {1'b0,qt_rt_const_shift_std[QT_WIDTH-1:0],4'b0}; +assign qt_rt_const_q32[REM_WIDTH+1:0] = {qt_rt_const_shift_std[QT_WIDTH-1:0],5'b0}; +assign qt_rt_const_q64[REM_WIDTH+1:0] = {qt_rt_const_shift_std[QT_WIDTH-2:0],6'b0}; +assign qt_rt_const_q128[REM_WIDTH+1:0] = {qt_rt_const_shift_std[QT_WIDTH-3:0],7'b0}; +assign qt_rt_const_q3[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0]; +assign qt_rt_const_q5[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0]; +assign qt_rt_const_q6[REM_WIDTH+1:0] = qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0]; +assign qt_rt_const_q7[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0]; +assign qt_rt_const_q9[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q10[REM_WIDTH+1:0] = qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q11[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q12[REM_WIDTH+1:0] = qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q13[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q14[REM_WIDTH+1:0] = qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q15[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0]; +assign qt_rt_const_q17[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0]; +assign qt_rt_const_q23[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0]; +assign qt_rt_const_q24[REM_WIDTH+1:0] = qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0]; +assign qt_rt_const_q27[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0]; +assign qt_rt_const_q31[REM_WIDTH+1:0] = qt_rt_const_q1[REM_WIDTH+1:0] + |qt_rt_const_q2[REM_WIDTH+1:0] + |qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0]; +assign qt_rt_const_q44[REM_WIDTH+1:0] = qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q32[REM_WIDTH+1:0]; +assign qt_rt_const_q56[REM_WIDTH+1:0] = qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0] + |qt_rt_const_q32[REM_WIDTH+1:0]; +assign qt_rt_const_q60[REM_WIDTH+1:0] = qt_rt_const_q4[REM_WIDTH+1:0] + |qt_rt_const_q8[REM_WIDTH+1:0] + |qt_rt_const_q16[REM_WIDTH+1:0] + |qt_rt_const_q32[REM_WIDTH+1:0]; +assign qt_rt_const_q80[REM_WIDTH+1:0] = qt_rt_const_q16[REM_WIDTH+1:0] + |qt_rt_const_q64[REM_WIDTH+1:0]; +assign qt_rt_const_q112[REM_WIDTH+1:0] = qt_rt_const_q16[REM_WIDTH+1:0] + |qt_rt_const_q32[REM_WIDTH+1:0] + |qt_rt_const_q64[REM_WIDTH+1:0]; +assign qt_rt_const_q192[REM_WIDTH+1:0] = qt_rt_const_q64[REM_WIDTH+1:0] + |qt_rt_const_q128[REM_WIDTH+1:0]; +//===================================== +// the sqrt current remainder oprand b +//===================================== +// the root is negative +// -1 +assign sqrt_qt_r1_rem_add_op1[REM_WIDTH-1:0] = {4'b0,total_qt_rt_minus[QT_WIDTH-1:1]} + |qt_rt_const_q31[REM_WIDTH+1:2]; +//-2 +assign sqrt_qt_r2_rem_add_op1[REM_WIDTH-1:0] = {3'b0,total_qt_rt_minus[QT_WIDTH-1:0]} + |qt_rt_const_q60[REM_WIDTH+1:2]; +//-4 +assign sqrt_qt_r4_rem_add_op1[REM_WIDTH-1:0] = {2'b0,total_qt_rt_minus[QT_WIDTH-1:0],1'b0} + |qt_rt_const_q112[REM_WIDTH+1:2]; +//-8 +assign sqrt_qt_r8_rem_add_op1[REM_WIDTH-1:0] = {1'b0,total_qt_rt_minus[QT_WIDTH-1:0],2'b0} + |qt_rt_const_q192[REM_WIDTH+1:2]; +//-3 +assign sqrt_qt_r3_rem_add_op1_0[REM_WIDTH-1:0] = sqrt_qt_r2_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_qt_r3_rem_add_op1_1[REM_WIDTH-1:0] = {4'b0,total_qt_rt_minus[QT_WIDTH-1:1]} + |qt_rt_const_q27[REM_WIDTH+1:2]; +//-5 112+23q-i-1 +assign sqrt_qt_r5_rem_add_op1_0[REM_WIDTH-1:0] = sqrt_qt_r4_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_qt_r5_rem_add_op1_1[REM_WIDTH-1:0] = {4'b0,total_qt_rt_minus[QT_WIDTH-1:1]} + |qt_rt_const_q23[REM_WIDTH+1:2]; +//-6 +assign sqrt_qt_r6_rem_add_op1_0[REM_WIDTH-1:0] = sqrt_qt_r4_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_qt_r6_rem_add_op1_1[REM_WIDTH-1:0] = {3'b0,total_qt_rt_minus[QT_WIDTH-1:0]} + |qt_rt_const_q44[REM_WIDTH+1:2]; +//-7 +assign sqrt_qt_r7_rem_add_op1_0[REM_WIDTH-1:0] = sqrt_qt_r8_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_qt_r7_rem_add_op1_1[REM_WIDTH-1:0] = ~({4'b0,total_qt_rt_minus[QT_WIDTH-1:1]} + |qt_rt_const_q17[REM_WIDTH+1:2]); +//-9 +assign sqrt_qt_r9_rem_add_op1_0[REM_WIDTH-1:0] = sqrt_qt_r8_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_qt_r9_rem_add_op1_1[REM_WIDTH-1:0] = {4'b0,total_qt_rt_minus[QT_WIDTH-1:1]} + | qt_rt_const_q15[REM_WIDTH+1:2]; +// the root is positive +// 1 +assign sqrt_qt_1_rem_add_op1[REM_WIDTH-1:0] = ~({4'b0,total_qt_rt[QT_WIDTH-1:1]} + | qt_rt_const_q1[REM_WIDTH+1:2]); +// 2 +assign sqrt_qt_2_rem_add_op1[REM_WIDTH-1:0] = ~({3'b0,total_qt_rt[QT_WIDTH-1:0]} + | qt_rt_const_q4[REM_WIDTH+1:2]); +// 4 +assign sqrt_qt_4_rem_add_op1[REM_WIDTH-1:0] = ~({2'b0,total_qt_rt[QT_WIDTH-1:0],1'b0} + | qt_rt_const_q16[REM_WIDTH+1:2]); +// 8 +assign sqrt_qt_8_rem_add_op1[REM_WIDTH-1:0] = ~({1'b0,total_qt_rt[QT_WIDTH-1:0],2'b0} + | qt_rt_const_q64[REM_WIDTH+1:2]); +// 3 +assign sqrt_qt_3_rem_add_op1_0[REM_WIDTH-1:0] = ~({3'b0,total_qt_rt[QT_WIDTH-1:0]} + |qt_rt_const_q8[REM_WIDTH+1:2]); +assign sqrt_qt_3_rem_add_op1_1[REM_WIDTH-1:0] = sqrt_qt_1_rem_add_op1[REM_WIDTH-1:0]; +//5 +assign sqrt_qt_5_rem_add_op1_0[REM_WIDTH-1:0] = ~({2'b0,total_qt_rt[QT_WIDTH-1:0],1'b0} + | qt_rt_const_q24[REM_WIDTH+1:2]); +assign sqrt_qt_5_rem_add_op1_1[REM_WIDTH-1:0] = sqrt_qt_1_rem_add_op1[REM_WIDTH-1:0]; +//6 +assign sqrt_qt_6_rem_add_op1_0[REM_WIDTH-1:0] = ~({2'b0,total_qt_rt[QT_WIDTH-1:0],1'b0} + | qt_rt_const_q32[REM_WIDTH+1:2]); +assign sqrt_qt_6_rem_add_op1_1[REM_WIDTH-1:0] = sqrt_qt_2_rem_add_op1[REM_WIDTH-1:0]; +//7 +assign sqrt_qt_7_rem_add_op1_0[REM_WIDTH-1:0] = ~({1'b0,total_qt_rt[QT_WIDTH-1:0],2'b0} + | qt_rt_const_q56[REM_WIDTH+1:2]); +assign sqrt_qt_7_rem_add_op1_1[REM_WIDTH-1:0] = {4'b0,total_qt_rt[QT_WIDTH-1:1]} + | qt_rt_const_q7[REM_WIDTH+1:2]; +//9 +assign sqrt_qt_9_rem_add_op1_0[REM_WIDTH-1:0] = ~({1'b0,total_qt_rt[QT_WIDTH-1:0],2'b0} + | qt_rt_const_q80[REM_WIDTH+1:2]); +assign sqrt_qt_9_rem_add_op1_1[REM_WIDTH-1:0] = sqrt_qt_1_rem_add_op1[REM_WIDTH-1:0]; + +assign sqrt_rem_add1_op1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r1_rem_add_op1[REM_WIDTH-1:0] + : sqrt_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_rem_add2_op1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r2_rem_add_op1[REM_WIDTH-1:0] + : sqrt_qt_2_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_rem_add4_op1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r4_rem_add_op1[REM_WIDTH-1:0] + : sqrt_qt_4_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_rem_add8_op1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r8_rem_add_op1[REM_WIDTH-1:0] + : sqrt_qt_8_rem_add_op1[REM_WIDTH-1:0]; +assign sqrt_rem_add3_op1_0[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r3_rem_add_op1_0[REM_WIDTH-1:0] + : sqrt_qt_3_rem_add_op1_0[REM_WIDTH-1:0]; +assign sqrt_rem_add3_op1_1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r3_rem_add_op1_1[REM_WIDTH-1:0] + : sqrt_qt_3_rem_add_op1_1[REM_WIDTH-1:0]; +assign sqrt_rem_add5_op1_0[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r5_rem_add_op1_0[REM_WIDTH-1:0] + : sqrt_qt_5_rem_add_op1_0[REM_WIDTH-1:0]; +assign sqrt_rem_add5_op1_1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r5_rem_add_op1_1[REM_WIDTH-1:0] + : sqrt_qt_5_rem_add_op1_1[REM_WIDTH-1:0]; +assign sqrt_rem_add6_op1_0[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r6_rem_add_op1_0[REM_WIDTH-1:0] + : sqrt_qt_6_rem_add_op1_0[REM_WIDTH-1:0]; +assign sqrt_rem_add6_op1_1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r6_rem_add_op1_1[REM_WIDTH-1:0] + : sqrt_qt_6_rem_add_op1_1[REM_WIDTH-1:0]; +assign sqrt_rem_add7_op1_0[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r7_rem_add_op1_0[REM_WIDTH-1:0] + : sqrt_qt_7_rem_add_op1_0[REM_WIDTH-1:0]; +assign sqrt_rem_add7_op1_1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r7_rem_add_op1_1[REM_WIDTH-1:0] + : sqrt_qt_7_rem_add_op1_1[REM_WIDTH-1:0]; +assign sqrt_rem_add9_op1_0[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r9_rem_add_op1_0[REM_WIDTH-1:0] + : sqrt_qt_9_rem_add_op1_0[REM_WIDTH-1:0]; +assign sqrt_rem_add9_op1_1[REM_WIDTH-1:0] = rem_sign + ? sqrt_qt_r9_rem_add_op1_1[REM_WIDTH-1:0] + : sqrt_qt_9_rem_add_op1_1[REM_WIDTH-1:0]; + +//===================================== +// the div current remainder oprand b +//===================================== +//negative +assign div_qt_r1_rem_add_op1[REM_WIDTH-1:0] = {5'b0,srt_divisor[DATA_WIDTH-1:0]}; +assign div_qt_r2_rem_add_op1[REM_WIDTH-1:0] = {4'b0,srt_divisor[DATA_WIDTH-1:0],1'b0}; +assign div_qt_r4_rem_add_op1[REM_WIDTH-1:0] = {3'b0,srt_divisor[DATA_WIDTH-1:0],2'b0}; +assign div_qt_r8_rem_add_op1[REM_WIDTH-1:0] = {2'b0,srt_divisor[DATA_WIDTH-1:0],3'b0}; +assign div_qt_r3_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_r2_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r3_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_r1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r5_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_r4_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r5_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_r1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r6_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_r4_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r6_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_r2_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r7_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_r8_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r7_rem_add_op1_1[REM_WIDTH-1:0] =~div_qt_r1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r9_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_r8_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_r9_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_r1_rem_add_op1[REM_WIDTH-1:0]; +//positive +assign div_qt_1_rem_add_op1[REM_WIDTH-1:0] =~div_qt_r1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_2_rem_add_op1[REM_WIDTH-1:0] =~div_qt_r2_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_4_rem_add_op1[REM_WIDTH-1:0] =~div_qt_r4_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_8_rem_add_op1[REM_WIDTH-1:0] =~div_qt_r8_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_3_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_2_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_3_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_5_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_4_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_5_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_6_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_4_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_6_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_2_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_7_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_8_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_7_rem_add_op1_1[REM_WIDTH-1:0] = ~div_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_9_rem_add_op1_0[REM_WIDTH-1:0] = div_qt_8_rem_add_op1[REM_WIDTH-1:0]; +assign div_qt_9_rem_add_op1_1[REM_WIDTH-1:0] = div_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign div_rem_add1_op1[REM_WIDTH-1:0] = rem_sign ? div_qt_r1_rem_add_op1[REM_WIDTH-1:0] + : div_qt_1_rem_add_op1[REM_WIDTH-1:0]; +assign div_rem_add2_op1[REM_WIDTH-1:0] = rem_sign ? div_qt_r2_rem_add_op1[REM_WIDTH-1:0] + : div_qt_2_rem_add_op1[REM_WIDTH-1:0]; +assign div_rem_add4_op1[REM_WIDTH-1:0] = rem_sign ? div_qt_r4_rem_add_op1[REM_WIDTH-1:0] + : div_qt_4_rem_add_op1[REM_WIDTH-1:0]; +assign div_rem_add8_op1[REM_WIDTH-1:0] = rem_sign ? div_qt_r8_rem_add_op1[REM_WIDTH-1:0] + : div_qt_8_rem_add_op1[REM_WIDTH-1:0]; +assign div_rem_add3_op1_0[REM_WIDTH-1:0] = rem_sign + ? div_qt_r3_rem_add_op1_0[REM_WIDTH-1:0] + : div_qt_3_rem_add_op1_0[REM_WIDTH-1:0]; +assign div_rem_add3_op1_1[REM_WIDTH-1:0] = rem_sign + ? div_qt_r3_rem_add_op1_1[REM_WIDTH-1:0] + : div_qt_3_rem_add_op1_1[REM_WIDTH-1:0]; +assign div_rem_add5_op1_0[REM_WIDTH-1:0] = rem_sign + ? div_qt_r5_rem_add_op1_0[REM_WIDTH-1:0] + : div_qt_5_rem_add_op1_0[REM_WIDTH-1:0]; +assign div_rem_add5_op1_1[REM_WIDTH-1:0] = rem_sign + ? div_qt_r5_rem_add_op1_1[REM_WIDTH-1:0] + : div_qt_5_rem_add_op1_1[REM_WIDTH-1:0]; +assign div_rem_add6_op1_0[REM_WIDTH-1:0] = rem_sign + ? div_qt_r6_rem_add_op1_0[REM_WIDTH-1:0] + : div_qt_6_rem_add_op1_0[REM_WIDTH-1:0]; +assign div_rem_add6_op1_1[REM_WIDTH-1:0] = rem_sign + ? div_qt_r6_rem_add_op1_1[REM_WIDTH-1:0] + : div_qt_6_rem_add_op1_1[REM_WIDTH-1:0]; +assign div_rem_add7_op1_0[REM_WIDTH-1:0] = rem_sign + ? div_qt_r7_rem_add_op1_0[REM_WIDTH-1:0] + : div_qt_7_rem_add_op1_0[REM_WIDTH-1:0]; +assign div_rem_add7_op1_1[REM_WIDTH-1:0] = rem_sign + ? div_qt_r7_rem_add_op1_1[REM_WIDTH-1:0] + : div_qt_7_rem_add_op1_1[REM_WIDTH-1:0]; +assign div_rem_add9_op1_0[REM_WIDTH-1:0] = rem_sign + ? div_qt_r9_rem_add_op1_0[REM_WIDTH-1:0] + : div_qt_9_rem_add_op1_0[REM_WIDTH-1:0]; +assign div_rem_add9_op1_1[REM_WIDTH-1:0] = rem_sign + ? div_qt_r9_rem_add_op1_1[REM_WIDTH-1:0] + : div_qt_9_rem_add_op1_1[REM_WIDTH-1:0]; +//===================================== +// the remainder calculation +//===================================== +assign rem_add1_op1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add1_op1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add1_op1[REM_WIDTH-1:0]); +assign rem_add2_op1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add2_op1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add2_op1[REM_WIDTH-1:0]); +assign rem_add4_op1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add4_op1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add4_op1[REM_WIDTH-1:0]); +assign rem_add8_op1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add8_op1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add8_op1[REM_WIDTH-1:0]); +assign rem_add3_op1_0[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add3_op1_0[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add3_op1_0[REM_WIDTH-1:0]); +assign rem_add3_op1_1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add3_op1_1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add3_op1_1[REM_WIDTH-1:0]); +assign rem_add5_op1_0[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add5_op1_0[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add5_op1_0[REM_WIDTH-1:0]); +assign rem_add5_op1_1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add5_op1_1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add5_op1_1[REM_WIDTH-1:0]); +assign rem_add6_op1_0[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add6_op1_0[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add6_op1_0[REM_WIDTH-1:0]); +assign rem_add6_op1_1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add6_op1_1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add6_op1_1[REM_WIDTH-1:0]); +assign rem_add7_op1_0[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add7_op1_0[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add7_op1_0[REM_WIDTH-1:0]); +assign rem_add7_op1_1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add7_op1_1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add7_op1_1[REM_WIDTH-1:0]); +assign rem_add9_op1_0[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add9_op1_0[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add9_op1_0[REM_WIDTH-1:0]); +assign rem_add9_op1_1[REM_WIDTH-1:0] = ({REM_WIDTH{srt_sel_div}} & div_rem_add9_op1_1[REM_WIDTH-1:0]) + |({REM_WIDTH{srt_sel_sqrt}} & sqrt_rem_add9_op1_1[REM_WIDTH-1:0]); +// remainder calculation for all of the remainders +assign remainder_shift[REM_WIDTH-1:0] = {srt_remainder[REM_WIDTH-5:0],4'b0}; +// &Force("nonport","cur_rem_1"); @518 +// &Force("nonport","cur_rem_2"); @519 +// &Force("nonport","cur_rem_3"); @520 +// &Force("nonport","cur_rem_4"); @521 +// &Force("nonport","cur_rem_5"); @522 +// &Force("nonport","cur_rem_6"); @523 +// &Force("nonport","cur_rem_7"); @524 +// &Force("nonport","cur_rem_8"); @525 +// &Force("nonport","cur_rem_9"); @526 +// &Force("nonport","remainder_shift"); @527 +// &Force("nonport","rem_add1_op1"); @528 +// &Force("nonport","rem_add2_op1"); @529 +// &Force("nonport","rem_add3_op1_0"); @530 +// &Force("nonport","rem_add3_op1_1"); @531 +// &Force("nonport","rem_add4_op1"); @532 +// &Force("nonport","rem_add5_op1_0"); @533 +// &Force("nonport","rem_add5_op1_1"); @534 +// &Force("nonport","rem_add6_op1_0"); @535 +// &Force("nonport","rem_add6_op1_1"); @536 +// &Force("nonport","rem_add7_op1_0"); @537 +// &Force("nonport","rem_add7_op1_1"); @538 +// &Force("nonport","rem_add8_op1"); @539 +// &Force("nonport","rem_add9_op1_0"); @540 +// &Force("nonport","rem_add9_op1_1"); @541 +//csky vperl_off +assign cur_rem_1[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add1_op1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-1{1'b0}},~rem_sign})); +assign cur_rem_2[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add2_op1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-1{1'b0}},~rem_sign})); +assign cur_rem_4[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add4_op1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-1{1'b0}},~rem_sign})); +assign cur_rem_8[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add8_op1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-1{1'b0}},~rem_sign})); +assign cur_rem_3[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add3_op1_0[REM_WIDTH-1:0]) + + $signed(rem_add3_op1_1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-2{1'b0}},~rem_sign,1'b0})); +assign cur_rem_5[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add5_op1_0[REM_WIDTH-1:0]) + + $signed(rem_add5_op1_1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-2{1'b0}},~rem_sign,1'b0})); +assign cur_rem_6[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add6_op1_0[REM_WIDTH-1:0]) + + $signed(rem_add6_op1_1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-2{1'b0}},~rem_sign,1'b0})); +assign cur_rem_7[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add7_op1_0[REM_WIDTH-1:0]) + + $signed(rem_add7_op1_1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-1{1'b0}},1'b1})); +assign cur_rem_9[REM_WIDTH-1:0] = $unsigned($signed(remainder_shift[REM_WIDTH-1:0]) + + $signed(rem_add9_op1_0[REM_WIDTH-1:0]) + + $signed(rem_add9_op1_1[REM_WIDTH-1:0]) + + $signed({{REM_WIDTH-2{1'b0}},~rem_sign,1'b0})); +//csky vperl_on +//==================================================== +// quotient selection +//==================================================== +assign bound_cmp_sign[8:0] = {bound1_cmp_sign,bound2_cmp_sign,bound3_cmp_sign,bound4_cmp_sign, + bound5_cmp_sign,bound6_cmp_sign,bound7_cmp_sign,bound8_cmp_sign,bound9_cmp_sign}; + +// &CombBeg; @582 +always @( rem_sign + or bound_cmp_sign[8:0] + or qt_rt_const_q10[57:0] + or qt_rt_const_q6[57:0] + or qt_rt_const_q12[57:0] + or qt_rt_const_q13[57:0] + or qt_rt_const_q5[57:0] + or qt_rt_const_q9[57:0] + or qt_rt_const_q8[57:0] + or total_qt_rt_minus[57:0] + or qt_rt_const_q4[57:0] + or qt_rt_const_q2[57:0] + or qt_rt_const_q15[57:0] + or qt_rt_const_q1[57:0] + or qt_rt_const_q7[57:0] + or qt_rt_const_q14[57:0] + or qt_rt_const_q3[57:0] + or qt_rt_const_q11[57:0] + or total_qt_rt[57:0]) begin - if(ctrl_xx_ex1_inst_vld && !ctrl_xx_ex1_stall || ctrl_xx_ex1_warm_up) +case({rem_sign,bound_cmp_sign[8:0]}) + 10'b0111111111: //0 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q15[QT_WIDTH-1:0]; + end + 10'b0011111111: //1 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q1[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0]; + end + 10'b0001111111://2 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q2[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q1[QT_WIDTH-1:0]; + end + 10'b0000111111://3 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q3[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q2[QT_WIDTH-1:0]; + end + 10'b0000011111://4 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q4[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q3[QT_WIDTH-1:0]; + end + 10'b0000001111://5 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q5[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q4[QT_WIDTH-1:0]; + end + 10'b0000000111://6 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q6[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q5[QT_WIDTH-1:0]; + end + 10'b0000000011://7 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q7[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q6[QT_WIDTH-1:0]; + end + 10'b0000000001://8 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q8[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q7[QT_WIDTH-1:0]; + end + 10'b0000000000://9 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q9[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0] + |qt_rt_const_q8[QT_WIDTH-1:0]; + end + 10'b1111111111: //0 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q15[QT_WIDTH-1:0]; + end + 10'b1011111111: //-1 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q15[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q14[QT_WIDTH-1:0]; + end + 10'b1001111111://-2 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q14[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q13[QT_WIDTH-1:0]; + end + 10'b1000111111://-3 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q13[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q12[QT_WIDTH-1:0]; + end + 10'b1000011111://-4 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q12[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q11[QT_WIDTH-1:0]; + end + 10'b1000001111://-5 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q11[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q10[QT_WIDTH-1:0]; + end + 10'b1000000111://-6 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q10[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q9[QT_WIDTH-1:0]; + end + 10'b1000000011://-7 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q9[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q8[QT_WIDTH-1:0]; + end + 10'b1000000001://-8 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q8[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q7[QT_WIDTH-1:0]; + end + 10'b1000000000://-9 + begin + total_qt_rt_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q7[QT_WIDTH-1:0]; + total_qt_rt_minus_next[QT_WIDTH-1:0] = total_qt_rt_minus[QT_WIDTH-1:0] + |qt_rt_const_q6[QT_WIDTH-1:0]; + end + default : begin - ex2_fflags[4:0] <= ex1_fflags[4:0]; - ex2_special_sign[3:0] <= ex1_special_sign[3:0]; - ex2_special_sel[6:0] <={ex1_special_sel[8],|ex1_special_sel[7:5],ex1_special_sel[4:0]}; - ex2_special_data[SINGLE_WIDTH-1:0] <= ex1_special_data_final[SINGLE_WIDTH-1:0]; + total_qt_rt_next[QT_WIDTH-1:0] = {QT_WIDTH{1'bx}}; + total_qt_rt_minus_next[QT_WIDTH-1:0] = {QT_WIDTH{1'bx}}; end +endcase +// &CombEnd; @727 end - -assign ex2_inst_wb = (|ex2_special_sel[6:0]); - -always @( ex2_special_sel[6:0] - or ex2_special_data[31:0] - or ex2_special_sign[3:0]) +//==================================================== +// remainder selection +//==================================================== +// &CombBeg; @731 +always @( cur_rem_2[60:0] + or remainder_shift[60:0] + or bound_cmp_sign[8:0] + or cur_rem_6[60:0] + or cur_rem_8[60:0] + or cur_rem_3[60:0] + or cur_rem_7[60:0] + or cur_rem_4[60:0] + or cur_rem_5[60:0] + or cur_rem_9[60:0] + or cur_rem_1[60:0]) begin -case(ex2_special_sel[6:0]) - 7'b0000_001: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[0],ex2_special_data[SINGLE_WIDTH-2:0]};//src2 - 7'b0000_010: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[1], {31{1'b0}} };//zero - 7'b0000_100: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[2], {8{1'b1}},{23{1'b0}} };//inf - 7'b0001_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[3], {7{1'b1}},1'b0,{23{1'b1}} };//lfn - 7'b0010_000: ex2_result[SINGLE_WIDTH-1:0] = { 1'b0, {8{1'b1}},1'b1, {22{1'b0}} };//cnan - 7'b0100_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_data[31],{8{1'b1}}, 1'b1, ex2_special_data[21:0]};//propagate qnan - 7'b1000_000: ex2_result[SINGLE_WIDTH-1:0] = ex2_special_data[SINGLE_WIDTH-1:0]; //ex1 falu special result - default: ex2_result[SINGLE_WIDTH-1:0] = {SINGLE_WIDTH{1'b0}}; +case(bound_cmp_sign[8:0]) + 9'b111111111: cur_rem[REM_WIDTH-1:0] = remainder_shift[REM_WIDTH-1:0]; //0 + 9'b011111111: cur_rem[REM_WIDTH-1:0] = cur_rem_1[REM_WIDTH-1:0]; //+-1 + 9'b001111111: cur_rem[REM_WIDTH-1:0] = cur_rem_2[REM_WIDTH-1:0]; //+-2 + 9'b000111111: cur_rem[REM_WIDTH-1:0] = cur_rem_3[REM_WIDTH-1:0]; //+-3 + 9'b000011111: cur_rem[REM_WIDTH-1:0] = cur_rem_4[REM_WIDTH-1:0]; //+-4 + 9'b000001111: cur_rem[REM_WIDTH-1:0] = cur_rem_5[REM_WIDTH-1:0]; //+-5 + 9'b000000111: cur_rem[REM_WIDTH-1:0] = cur_rem_6[REM_WIDTH-1:0]; //+-6 + 9'b000000011: cur_rem[REM_WIDTH-1:0] = cur_rem_7[REM_WIDTH-1:0]; //+-7 + 9'b000000001: cur_rem[REM_WIDTH-1:0] = cur_rem_8[REM_WIDTH-1:0]; //+-8 + 9'b000000000: cur_rem[REM_WIDTH-1:0] = cur_rem_9[REM_WIDTH-1:0]; //+-9 + default : cur_rem[REM_WIDTH-1:0] = {REM_WIDTH{1'bx}}; endcase +// &CombEnd; @745 +end +assign srt_remainder_nxt[REM_WIDTH-1:0] = cur_rem[REM_WIDTH-1:0]; +//assign srt_remainder_zero = ~|srt_remainder_nxt[REM_WIDTH-1:0]; +assign srt_remainder_sign = srt_remainder_nxt[REM_WIDTH-1]; + +//==================================================== +// remainder logic for integer VREM/VREMU inst +//==================================================== +always @(posedge srt_qt_rem_clk or negedge cpurst_b) +begin + if(!cpurst_b)begin + srt_remainder_minus[REM_WIDTH-1:0] <= {REM_WIDTH{1'b0}}; + end + else if(srt_sm_on)begin + srt_remainder_minus[REM_WIDTH-1:0] <= srt_remainder_minus_nxt[REM_WIDTH-1:0]; + end + else begin + srt_remainder_minus[REM_WIDTH-1:0] <= srt_remainder_minus[REM_WIDTH-1:0]; + end end -assign dp_frbus_ex2_data[SINGLE_WIDTH-1:0] = ex2_result[SINGLE_WIDTH-1:0]; -assign dp_frbus_ex2_fflags[4:0] = ex2_fflags[4:0]; +assign srt_remainder_out[REM_WIDTH-2:0] = srt_remainder[REM_WIDTH-1] ? srt_remainder_minus[REM_WIDTH-2:0] + : srt_remainder[REM_WIDTH-2:0]; + +assign remainder_minus_shift[REM_WIDTH-1:0] = {srt_remainder_minus[REM_WIDTH-5:0],4'b0}; +//csky vperl_off +assign rem_minus_minus_6[REM_WIDTH-1:0] = $unsigned($signed(remainder_minus_shift[REM_WIDTH-1:0]) + - $signed({div_qt_r4_rem_add_op1[REM_WIDTH-1:0]}) + - $signed({div_qt_r2_rem_add_op1[REM_WIDTH-1:0]})); +//assign rem_minus_minus_4[REM_WIDTH-1:0] = $unsigned($signed(remainder_minus_shift[REM_WIDTH-1:0]) +// - $signed({div_qt_r4_rem_add_op1[REM_WIDTH-1:0]})); +//csky vperl_on + +// &Force("nonport","rem_minus_minus_6"); @778 +// //&Force("nonport","rem_minus_minus_4"); @779 + +// here add for positive remainder calculation +assign remainder_minus_nor_nxt_0[REM_WIDTH-1:0] = rem_sign ? cur_rem_1[REM_WIDTH-1:0] + : remainder_minus_shift[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_1[REM_WIDTH-1:0] = rem_sign ? cur_rem_2[REM_WIDTH-1:0] + : remainder_shift[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_2[REM_WIDTH-1:0] = rem_sign ? cur_rem_3[REM_WIDTH-1:0] + : cur_rem_1[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_3[REM_WIDTH-1:0] = rem_sign ? cur_rem_4[REM_WIDTH-1:0] + : cur_rem_2[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_4[REM_WIDTH-1:0] = rem_sign ? cur_rem_5[REM_WIDTH-1:0] + : cur_rem_3[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_5[REM_WIDTH-1:0] = rem_sign ? cur_rem_6[REM_WIDTH-1:0] + : cur_rem_4[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_6[REM_WIDTH-1:0] = rem_sign ? cur_rem_7[REM_WIDTH-1:0] + : cur_rem_5[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_7[REM_WIDTH-1:0] = rem_sign ? cur_rem_8[REM_WIDTH-1:0] + : cur_rem_6[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_8[REM_WIDTH-1:0] = rem_sign ? cur_rem_9[REM_WIDTH-1:0] + : cur_rem_7[REM_WIDTH-1:0]; +assign remainder_minus_nor_nxt_9[REM_WIDTH-1:0] = rem_sign ? rem_minus_minus_6[REM_WIDTH-1:0] + : cur_rem_8[REM_WIDTH-1:0]; +// &CombBeg; @802 +always @( bound_cmp_sign[8:0] + or remainder_minus_nor_nxt_7[60:0] + or remainder_minus_nor_nxt_1[60:0] + or remainder_minus_nor_nxt_4[60:0] + or remainder_minus_nor_nxt_5[60:0] + or remainder_minus_nor_nxt_2[60:0] + or remainder_minus_nor_nxt_9[60:0] + or remainder_minus_nor_nxt_8[60:0] + or remainder_minus_nor_nxt_0[60:0] + or remainder_minus_nor_nxt_3[60:0] + or remainder_minus_nor_nxt_6[60:0]) +begin +case({bound_cmp_sign[8:0]}) + 9'b111111111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_0[REM_WIDTH-1:0];//0 + 9'b011111111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_1[REM_WIDTH-1:0];//+-1 + 9'b001111111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_2[REM_WIDTH-1:0];//+-2 + 9'b000111111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_3[REM_WIDTH-1:0];//+-3 + 9'b000011111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_4[REM_WIDTH-1:0];//+-4 + 9'b000001111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_5[REM_WIDTH-1:0];//+-5 + 9'b000000111: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_6[REM_WIDTH-1:0];//+-6 + 9'b000000011: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_7[REM_WIDTH-1:0];//+-7 + 9'b000000001: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_8[REM_WIDTH-1:0];//+-8 + 9'b000000000: srt_remainder_minus_nxt[REM_WIDTH-1:0] = remainder_minus_nor_nxt_9[REM_WIDTH-1:0];//+-9 + default : srt_remainder_minus_nxt[REM_WIDTH-1:0] = {REM_WIDTH{1'bx}}; +endcase +// &CombEnd; @816 +end +// &ModuleEnd; @818 endmodule +// ----- 8< ----- FILE "./ct_vfdsu_top.v" ----- 8< ----- -// ----- 8< ----- FILE "./pa_fpu_frbus.v" ----- 8< ----- - -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -26427,179 +33332,340 @@ See the License for the specific language governing permissions and limitations under the License. */ -module pa_fpu_frbus( - ctrl_frbus_ex2_wb_req, - dp_frbus_ex2_data, - dp_frbus_ex2_fflags, - fdsu_frbus_data, - fdsu_frbus_fflags, - fdsu_frbus_wb_vld, - fpu_idu_fwd_data, - fpu_idu_fwd_fflags, - fpu_idu_fwd_vld +// &Depend("cpu_cfig.h"); @22 +// &ModuleBeg; @23 +module ct_vfdsu_top( + cp0_vfpu_icg_en, + cp0_yy_clk_en, + cpurst_b, + dp_vfdsu_ex1_pipex_dst_ereg, + dp_vfdsu_ex1_pipex_dst_vreg, + dp_vfdsu_ex1_pipex_iid, + dp_vfdsu_ex1_pipex_imm0, + dp_vfdsu_ex1_pipex_sel, + dp_vfdsu_ex1_pipex_srcf0, + dp_vfdsu_ex1_pipex_srcf1, + dp_vfdsu_fdiv_gateclk_issue, + dp_vfdsu_idu_fdiv_issue, + forever_cpuclk, + idu_vfpu_rf_pipex_func, + idu_vfpu_rf_pipex_gateclk_sel, + pad_yy_icg_scan_en, + pipex_dp_vfdsu_ereg, + pipex_dp_vfdsu_ereg_data, + pipex_dp_vfdsu_freg_data, + pipex_dp_vfdsu_inst_vld, + pipex_dp_vfdsu_vreg, + rtu_yy_xx_flush, + vfdsu_dp_fdiv_busy, + vfdsu_dp_inst_wb_req, + vfdsu_ifu_debug_ex2_wait, + vfdsu_ifu_debug_idle, + vfdsu_ifu_debug_pipe_busy, + vfpu_yy_xx_dqnan, + vfpu_yy_xx_rm ); -input ctrl_frbus_ex2_wb_req; -input [31:0] dp_frbus_ex2_data; -input [4 :0] dp_frbus_ex2_fflags; -input [31:0] fdsu_frbus_data; -input [4 :0] fdsu_frbus_fflags; -input fdsu_frbus_wb_vld; -output [31:0] fpu_idu_fwd_data; -output [4 :0] fpu_idu_fwd_fflags; -output fpu_idu_fwd_vld; - -reg [31:0] frbus_wb_data; -reg [4 :0] frbus_wb_fflags; - -wire ctrl_frbus_ex2_wb_req; -wire [31:0] fdsu_frbus_data; -wire [4 :0] fdsu_frbus_fflags; -wire fdsu_frbus_wb_vld; -wire [31:0] fpu_idu_fwd_data; -wire [4 :0] fpu_idu_fwd_fflags; -wire fpu_idu_fwd_vld; -wire frbus_ex2_wb_vld; -wire frbus_fdsu_wb_vld; -wire frbus_wb_vld; -wire [3 :0] frbus_source_vld; - - -//========================================================== -// Input Signal Rename -//========================================================== -assign frbus_fdsu_wb_vld = fdsu_frbus_wb_vld; -assign frbus_ex2_wb_vld = ctrl_frbus_ex2_wb_req; -assign frbus_source_vld[3:0] = {1'b0, 1'b0, frbus_ex2_wb_vld, frbus_fdsu_wb_vld}; -assign frbus_wb_vld = frbus_ex2_wb_vld | frbus_fdsu_wb_vld; - -always @( frbus_source_vld[3:0] - or fdsu_frbus_data[31:0] - or dp_frbus_ex2_data[31:0] - or fdsu_frbus_fflags[4:0] - or dp_frbus_ex2_fflags[4:0]) -begin - case(frbus_source_vld[3:0]) - 4'b0001: begin // DIV - frbus_wb_data[31:0] = fdsu_frbus_data[31:0]; - frbus_wb_fflags[4:0] = fdsu_frbus_fflags[4:0]; - end - 4'b0010: begin // EX2 - frbus_wb_data[31:0] = dp_frbus_ex2_data[31:0]; - frbus_wb_fflags[4:0] = dp_frbus_ex2_fflags[4:0]; - end - default: begin - frbus_wb_data[31:0] = {31{1'b0}}; - frbus_wb_fflags[4:0] = 5'b0; - end - endcase -end - -assign fpu_idu_fwd_vld = frbus_wb_vld; -assign fpu_idu_fwd_fflags[4:0] = frbus_wb_fflags[4:0]; -assign fpu_idu_fwd_data[31:0] = frbus_wb_data[31:0]; - -endmodule - - -// ----- 8< ----- FILE "./pa_fpu_src_type.v" ----- 8< ----- - -/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. +// &Ports; @24 +input cp0_vfpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; +input [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; +input [6 :0] dp_vfdsu_ex1_pipex_iid; +input [2 :0] dp_vfdsu_ex1_pipex_imm0; +input dp_vfdsu_ex1_pipex_sel; +input [63:0] dp_vfdsu_ex1_pipex_srcf0; +input [63:0] dp_vfdsu_ex1_pipex_srcf1; +input dp_vfdsu_fdiv_gateclk_issue; +input dp_vfdsu_idu_fdiv_issue; +input forever_cpuclk; +input [19:0] idu_vfpu_rf_pipex_func; +input idu_vfpu_rf_pipex_gateclk_sel; +input pad_yy_icg_scan_en; +input rtu_yy_xx_flush; +input vfpu_yy_xx_dqnan; +input [2 :0] vfpu_yy_xx_rm; +output [4 :0] pipex_dp_vfdsu_ereg; +output [4 :0] pipex_dp_vfdsu_ereg_data; +output [63:0] pipex_dp_vfdsu_freg_data; +output pipex_dp_vfdsu_inst_vld; +output [6 :0] pipex_dp_vfdsu_vreg; +output vfdsu_dp_fdiv_busy; +output vfdsu_dp_inst_wb_req; +output vfdsu_ifu_debug_ex2_wait; +output vfdsu_ifu_debug_idle; +output vfdsu_ifu_debug_pipe_busy; -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at +// &Regs; @25 - http://www.apache.org/licenses/LICENSE-2.0 +// &Wires; @26 +wire cp0_vfpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire [4 :0] dp_vfdsu_ex1_pipex_dst_ereg; +wire [6 :0] dp_vfdsu_ex1_pipex_dst_vreg; +wire [6 :0] dp_vfdsu_ex1_pipex_iid; +wire [2 :0] dp_vfdsu_ex1_pipex_imm0; +wire dp_vfdsu_ex1_pipex_sel; +wire [63:0] dp_vfdsu_ex1_pipex_srcf0; +wire [63:0] dp_vfdsu_ex1_pipex_srcf1; +wire dp_vfdsu_fdiv_gateclk_issue; +wire dp_vfdsu_idu_fdiv_issue; +wire ex1_data_clk; +wire ex1_div; +wire ex1_double; +wire ex1_pipedown; +wire ex1_scalar; +wire ex1_single; +wire ex1_half; +wire ex1_bfloat; +wire ex1_sqrt; +wire [63:0] ex1_src0; +wire [63:0] ex1_src1; +wire [2 :0] ex1_static_rm; +wire ex2_data_clk; +wire ex2_pipedown; +wire ex2_srt_first_round; +wire ex3_data_clk; +wire ex3_pipedown; +wire [4 :0] ex4_out_expt; +wire [63:0] ex4_out_result; +wire forever_cpuclk; +wire [19:0] idu_vfpu_rf_pipex_func; +wire idu_vfpu_rf_pipex_gateclk_sel; +wire pad_yy_icg_scan_en; +wire [4 :0] pipex_dp_vfdsu_ereg; +wire [4 :0] pipex_dp_vfdsu_ereg_data; +wire [63:0] pipex_dp_vfdsu_freg_data; +wire pipex_dp_vfdsu_inst_vld; +wire [6 :0] pipex_dp_vfdsu_vreg; +wire rtu_yy_xx_flush; +wire srt_ctrl_rem_zero; +wire srt_ctrl_skip_srt; +wire srt_secd_round; +wire srt_sm_on; +wire vfdsu_dp_fdiv_busy; +wire vfdsu_dp_inst_wb_req; +wire vfdsu_ex2_double; +wire vfdsu_ex2_single; +wire vfdsu_ex2_half; +wire vfdsu_ex2_bfloat; +wire vfdsu_ifu_debug_ex2_wait; +wire vfdsu_ifu_debug_idle; +wire vfdsu_ifu_debug_pipe_busy; +wire vfpu_yy_xx_dqnan; +wire [2 :0] vfpu_yy_xx_rm; + +// &Instance("ct_vfdsu_ctrl"); @28 +// &Instance("ct_vfdsu_dp"); @29 +// &ConnRule(s/ex4_out/set0_doub_ex4/); @30 +// &ConnRule(s/srt_ctrl/set0_doub_srt_ctrl/); @31 +// &ConnRule(s/vfdsu_ex2_/dp_set0_double_ex2_/); @32 +// &ConnRule(s/slice_x/slice_0/); @33 +// &ConnRule(s/vfdsu_ex3_/dp_set0_double_ex3_/); @34 +// &ConnRule(s/vfdsu_ex4_/dp_set0_double_ex4_/); @35 +// &Instance("ct_vfdsu_double","x_ct_vfdsu_double_set0"); @36 +// &Connect(.ex1_src0(ex1_src0[63:0])); @37 +// &Connect(.ex1_src1(ex1_src1[63:0])); @38 +// &Connect(.ex1_double(set0_ex1_double)); @39 +// &Connect(.srt_secd_round(srt_secd_round[0])); @40 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[0])); @41 +// &ConnRule(s/ex4_out/set0_half0_ex4/); @43 +// &ConnRule(s/_pipedown/_half_pipedown/); @44 +// &ConnRule(s/srt_ctrl/set0_half0_srt_ctrl/); @45 +// &ConnRule(s/vfdsu_ex2_/dp_set0_half0_ex2_/); @46 +// &ConnRule(s/vfdsu_ex3_/dp_set0_half0_ex3_/); @47 +// &ConnRule(s/vfdsu_ex4_/dp_set0_half0_ex4_/); @48 +// &Instance("ct_vfdsu_half","x_ct_vfdsu_half0_set0"); @49 +// &Connect(.ex1_src0(ex1_src0[31:16])); @50 +// &Connect(.ex1_src1(ex1_src1[31:16])); @51 +// &Connect(.srt_secd_round(srt_secd_round[1])); @52 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @53 +// &ConnRule(s/ex4_out/set0_sing_ex4/); @56 +// &ConnRule(s/_pipedown/_sing_pipedown/); @57 +// &ConnRule(s/srt_ctrl/set0_sing_srt_ctrl/); @58 +// &ConnRule(s/slice_x/slice_0/); @59 +// &Instance("ct_vfdsu_single","x_ct_vfdsu_single_set0"); @60 +// &Connect(.ex1_src0(ex1_src0[63:32])); @61 +// &Connect(.ex1_src1(ex1_src1[63:32])); @62 +// &Connect(.srt_secd_round(srt_secd_round[1])); @63 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @64 +// &ConnRule(s/ex4_out/set0_half1_ex4/); @68 +// &ConnRule(s/_pipedown/_half_pipedown/); @69 +// &ConnRule(s/srt_ctrl/set0_half1_srt_ctrl/); @70 +// &ConnRule(s/vfdsu_ex2_/dp_set0_half1_ex2_/); @71 +// &ConnRule(s/vfdsu_ex3_/dp_set0_half1_ex3_/); @72 +// &ConnRule(s/vfdsu_ex4_/dp_set0_half1_ex4_/); @73 +// &Instance("ct_vfdsu_half","x_ct_vfdsu_half1_set0"); @74 +// &Connect(.ex1_src0(ex1_src0[63:48])); @75 +// &Connect(.ex1_src1(ex1_src1[63:48])); @76 +// &Connect(.srt_secd_round(srt_secd_round[1])); @77 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[1])); @78 +// &ConnRule(s/ex4_out/set1_doub_ex4/); @81 +// &ConnRule(s/srt_ctrl/set1_doub_srt_ctrl/); @82 +// &ConnRule(s/vfdsu_ex2_/dp_set1_double_ex2_/); @83 +// &ConnRule(s/slice_x/slice_1/); @84 +// &ConnRule(s/vfdsu_ex3_/dp_set1_double_ex3_/); @85 +// &ConnRule(s/vfdsu_ex4_/dp_set1_double_ex4_/); @86 +// &Instance("ct_vfdsu_double","x_ct_vfdsu_double_set1"); @87 +// &Connect(.ex1_src0(ex1_src0[127:64])); @88 +// &Connect(.ex1_src1(ex1_src1[127:64])); @89 +// &Connect(.ex1_double(set1_ex1_double)); @90 +// &Connect(.srt_secd_round(srt_secd_round[2])); @91 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[2])); @92 +// &ConnRule(s/ex4_out/set1_half0_ex4/); @95 +// &ConnRule(s/_pipedown/_half_pipedown/); @96 +// &ConnRule(s/srt_ctrl/set1_half0_srt_ctrl/); @97 +// &ConnRule(s/vfdsu_ex2_/dp_set1_half0_ex2_/); @98 +// &ConnRule(s/vfdsu_ex3_/dp_set1_half0_ex3_/); @99 +// &ConnRule(s/vfdsu_ex4_/dp_set1_half0_ex4_/); @100 +// &Instance("ct_vfdsu_half","x_ct_vfdsu_half0_set1"); @101 +// &Connect(.ex1_src0(ex1_src0[95:80])); @102 +// &Connect(.ex1_src1(ex1_src1[95:80])); @103 +// &Connect(.srt_secd_round(srt_secd_round[3])); @104 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @105 +// &ConnRule(s/ex4_out/set1_sing_ex4/); @108 +// &ConnRule(s/_pipedown/_sing_pipedown/); @109 +// &ConnRule(s/srt_ctrl/set1_sing_srt_ctrl/); @110 +// &ConnRule(s/slice_x/slice_1/); @111 +// &Instance("ct_vfdsu_single","x_ct_vfdsu_single_set1"); @112 +// &Connect(.ex1_src0(ex1_src0[127:96])); @113 +// &Connect(.ex1_src1(ex1_src1[127:96])); @114 +// &Connect(.srt_secd_round(srt_secd_round[3])); @115 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @116 +// &ConnRule(s/ex4_out/set1_half1_ex4/); @119 +// &ConnRule(s/_pipedown/_half_pipedown/); @120 +// &ConnRule(s/srt_ctrl/set1_half1_srt_ctrl/); @121 +// &ConnRule(s/vfdsu_ex2_/dp_set1_half1_ex2_/); @122 +// &ConnRule(s/vfdsu_ex3_/dp_set1_half1_ex3_/); @123 +// &ConnRule(s/vfdsu_ex4_/dp_set1_half1_ex4_/); @124 +// &Instance("ct_vfdsu_half","x_ct_vfdsu_half1_set1"); @125 +// &Connect(.ex1_src0(ex1_src0[127:112])); @126 +// &Connect(.ex1_src1(ex1_src1[127:112])); @127 +// &Connect(.srt_secd_round(srt_secd_round[3])); @128 +// &Connect(.ex2_srt_first_round(ex2_srt_first_round[3])); @129 +// &Instance("ct_vfdsu_ctrl"); @132 +ct_vfdsu_ctrl x_ct_vfdsu_ctrl ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .dp_vfdsu_ex1_pipex_sel (dp_vfdsu_ex1_pipex_sel ), + .dp_vfdsu_fdiv_gateclk_issue (dp_vfdsu_fdiv_gateclk_issue), + .dp_vfdsu_idu_fdiv_issue (dp_vfdsu_idu_fdiv_issue ), + .ex1_data_clk (ex1_data_clk ), + .ex1_double (ex1_double ), + .ex1_pipedown (ex1_pipedown ), + .ex1_single (ex1_single ), + .ex1_half (ex1_half ), + .ex1_bfloat (ex1_bfloat ), + .ex2_data_clk (ex2_data_clk ), + .ex2_pipedown (ex2_pipedown ), + .ex2_srt_first_round (ex2_srt_first_round ), + .ex3_data_clk (ex3_data_clk ), + .ex3_pipedown (ex3_pipedown ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .pipex_dp_vfdsu_inst_vld (pipex_dp_vfdsu_inst_vld ), + .rtu_yy_xx_flush (rtu_yy_xx_flush ), + .srt_ctrl_rem_zero (srt_ctrl_rem_zero ), + .srt_ctrl_skip_srt (srt_ctrl_skip_srt ), + .srt_secd_round (srt_secd_round ), + .srt_sm_on (srt_sm_on ), + .vfdsu_dp_fdiv_busy (vfdsu_dp_fdiv_busy ), + .vfdsu_dp_inst_wb_req (vfdsu_dp_inst_wb_req ), + .vfdsu_ex2_double (vfdsu_ex2_double ), + .vfdsu_ex2_single (vfdsu_ex2_single ), + .vfdsu_ex2_half (vfdsu_ex2_half ), + .vfdsu_ex2_bfloat (vfdsu_ex2_bfloat ), + .vfdsu_ifu_debug_ex2_wait (vfdsu_ifu_debug_ex2_wait ), + .vfdsu_ifu_debug_idle (vfdsu_ifu_debug_idle ), + .vfdsu_ifu_debug_pipe_busy (vfdsu_ifu_debug_pipe_busy ) +); -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -*/ +// &Instance("ct_vfdsu_double"); @133 +ct_vfdsu_double x_ct_vfdsu_double ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .ex1_div (ex1_div ), + .ex1_double (ex1_double ), + .ex1_pipedown (ex1_pipedown ), + .ex1_scalar (ex1_scalar ), + .ex1_single (ex1_single ), + .ex1_half (ex1_half ), + .ex1_bfloat (ex1_bfloat ), + .ex1_sqrt (ex1_sqrt ), + .ex1_src0 (ex1_src0 ), + .ex1_src1 (ex1_src1 ), + .ex1_static_rm (ex1_static_rm ), + .ex2_pipedown (ex2_pipedown ), + .ex2_srt_first_round (ex2_srt_first_round), + .ex3_pipedown (ex3_pipedown ), + .ex4_out_expt (ex4_out_expt ), + .ex4_out_result (ex4_out_result ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .srt_ctrl_rem_zero (srt_ctrl_rem_zero ), + .srt_ctrl_skip_srt (srt_ctrl_skip_srt ), + .srt_secd_round (srt_secd_round ), + .srt_sm_on (srt_sm_on ), + .vfpu_yy_xx_dqnan (vfpu_yy_xx_dqnan ), + .vfpu_yy_xx_rm (vfpu_yy_xx_rm ) +); -// &ModuleBeg; @24 -module pa_fpu_src_type( - inst_double, - inst_single, - src_cnan, - src_id, - src_in, - src_inf, - src_norm, - src_qnan, - src_snan, - src_zero +// &Instance("ct_vfdsu_scalar_dp"); @134 +ct_vfdsu_scalar_dp x_ct_vfdsu_scalar_dp ( + .cp0_vfpu_icg_en (cp0_vfpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .dp_vfdsu_ex1_pipex_dst_ereg (dp_vfdsu_ex1_pipex_dst_ereg ), + .dp_vfdsu_ex1_pipex_dst_vreg (dp_vfdsu_ex1_pipex_dst_vreg ), + .dp_vfdsu_ex1_pipex_iid (dp_vfdsu_ex1_pipex_iid ), + .dp_vfdsu_ex1_pipex_imm0 (dp_vfdsu_ex1_pipex_imm0 ), + .dp_vfdsu_ex1_pipex_srcf0 (dp_vfdsu_ex1_pipex_srcf0 ), + .dp_vfdsu_ex1_pipex_srcf1 (dp_vfdsu_ex1_pipex_srcf1 ), + .ex1_data_clk (ex1_data_clk ), + .ex1_div (ex1_div ), + .ex1_double (ex1_double ), + .ex1_pipedown (ex1_pipedown ), + .ex1_scalar (ex1_scalar ), + .ex1_single (ex1_single ), + .ex1_half (ex1_half ), + .ex1_bfloat (ex1_bfloat ), + .ex1_sqrt (ex1_sqrt ), + .ex1_src0 (ex1_src0 ), + .ex1_src1 (ex1_src1 ), + .ex1_static_rm (ex1_static_rm ), + .ex2_data_clk (ex2_data_clk ), + .ex2_pipedown (ex2_pipedown ), + .ex3_data_clk (ex3_data_clk ), + .ex3_pipedown (ex3_pipedown ), + .ex4_out_expt (ex4_out_expt ), + .ex4_out_result (ex4_out_result ), + .forever_cpuclk (forever_cpuclk ), + .idu_vfpu_rf_pipex_func (idu_vfpu_rf_pipex_func ), + .idu_vfpu_rf_pipex_gateclk_sel (idu_vfpu_rf_pipex_gateclk_sel), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .pipex_dp_vfdsu_ereg (pipex_dp_vfdsu_ereg ), + .pipex_dp_vfdsu_ereg_data (pipex_dp_vfdsu_ereg_data ), + .pipex_dp_vfdsu_freg_data (pipex_dp_vfdsu_freg_data ), + .pipex_dp_vfdsu_vreg (pipex_dp_vfdsu_vreg ), + .vfdsu_ex2_double (vfdsu_ex2_double ), + .vfdsu_ex2_single (vfdsu_ex2_single ), + .vfdsu_ex2_half (vfdsu_ex2_half ), + .vfdsu_ex2_bfloat (vfdsu_ex2_bfloat ) ); -// &Ports; @25 -input inst_double; -input inst_single; -input [63:0] src_in; -output src_cnan; -output src_id; -output src_inf; -output src_norm; -output src_qnan; -output src_snan; -output src_zero; - -// &Regs; @26 - -// &Wires; @27 -wire inst_double; -wire inst_single; -wire [63:0] src; -wire src_cnan; -wire src_expn_max; -wire src_expn_zero; -wire src_frac_msb; -wire src_frac_zero; -wire src_id; -wire [63:0] src_in; -wire src_inf; -wire src_norm; -wire src_qnan; -wire src_snan; -wire src_zero; - - -// &Depend("cpu_cfig.h"); @29 -assign src[63:0] = src_in[63:0]; - -assign src_cnan = !(&src[63:32]) && inst_single; - -assign src_expn_zero = !(|src[62:52]) && inst_double || - !(|src[30:23]) && inst_single; - -assign src_expn_max = (&src[62:52]) && inst_double || - (&src[30:23]) && inst_single; - -assign src_frac_zero = !(|src[51:0]) && inst_double || - !(|src[22:0]) && inst_single; - -assign src_frac_msb = src[51] && inst_double || src[22] && inst_single; - -assign src_snan = src_expn_max && !src_frac_msb && !src_frac_zero && !src_cnan; -assign src_qnan = src_expn_max && src_frac_msb || src_cnan; -assign src_zero = src_expn_zero && src_frac_zero && !src_cnan; -assign src_id = src_expn_zero && !src_frac_zero && !src_cnan; -assign src_inf = src_expn_max && src_frac_zero && !src_cnan; -assign src_norm =!(src_expn_zero && src_frac_zero) && - ! src_expn_max && !src_cnan; - -// &Force("output","src_cnan"); @53 - -// &ModuleEnd; @55 -endmodule +// &ModuleEnd; @137 +endmodule -// ----- 8< ----- FILE "./fpnew_divsqrt_th_32.sv" ----- 8< ----- +// ----- 8< ----- FILE "./fpnew_divsqrt_th_64_multi.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 -// Copyright 2019-2022 ETH Zurich and University of Bologna. +// Generated by CIRCT firtool-1.133.0 +// Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in @@ -26613,23 +33679,22 @@ endmodule // SPDX-License-Identifier: SHL-0.51 // Authors: Stefan Mach -// Luca Bertaccini -// Jiang Lannan -// Kexin Li +// Roman Marquart -module fpnew_divsqrt_th_32 #( - // FP32-only DivSqrt + +module fpnew_divsqrt_th_64_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, // FPU configuration parameter int unsigned NumPipeRegs = 0, - parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::AFTER, parameter type TagType = logic, parameter type AuxType = logic, // Do not change - localparam int unsigned WIDTH = 32, - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -26638,12 +33703,18 @@ module fpnew_divsqrt_th_32 #( input logic [NUM_FORMATS-1:0][1:0] is_boxed_i, // 2 operands input fpnew_pkg::roundmode_e rnd_mode_i, input fpnew_pkg::operation_e op_i, + input fpnew_pkg::fp_format_e dst_fmt_i, input TagType tag_i, input logic mask_i, input AuxType aux_i, + input logic vectorial_op_i, // Input Handshake input logic in_valid_i, output logic in_ready_o, + output logic divsqrt_done_o, + input logic simd_synch_done_i, + output logic divsqrt_ready_o, + input logic simd_synch_rdy_i, input logic flush_i, // Output signals output logic [WIDTH-1:0] result_o, @@ -26658,7 +33729,9 @@ module fpnew_divsqrt_th_32 #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); // ---------- @@ -26683,15 +33756,18 @@ module fpnew_divsqrt_th_32 #( logic [1:0][WIDTH-1:0] operands_q; fpnew_pkg::roundmode_e rnd_mode_q; fpnew_pkg::operation_e op_q; + fpnew_pkg::fp_format_e dst_fmt_q; logic in_valid_q; // Input pipeline signals, index i holds signal after i register stages logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q; - fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q /*verilator split_var */; fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; TagType [0:NUM_INP_REGS] inp_pipe_tag_q; logic [0:NUM_INP_REGS] inp_pipe_mask_q; AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_vec_op_q; logic [0:NUM_INP_REGS] inp_pipe_valid_q; // Ready signal is combinatorial for all stages logic [0:NUM_INP_REGS] inp_pipe_ready; @@ -26700,11 +33776,13 @@ module fpnew_divsqrt_th_32 #( assign inp_pipe_operands_q[0] = operands_i; assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; assign inp_pipe_tag_q[0] = tag_i; assign inp_pipe_mask_q[0] = mask_i; assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_vec_op_q[0] = vectorial_op_i; assign inp_pipe_valid_q[0] = in_valid_i; - // Input stage: Propagate pipeline ready signal to updtream circuitry + // Input stage: Propagate pipeline ready signal to upstream circuitry assign in_ready_o = inp_pipe_ready[0]; // Generate the register stages for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline @@ -26722,85 +33800,148 @@ module fpnew_divsqrt_th_32 #( `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + `FFL(inp_pipe_vec_op_q[i+1], inp_pipe_vec_op_q[i], reg_ena, AuxType'('0)) end // Output stage: assign selected pipe outputs to signals for later use assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS]; assign op_q = inp_pipe_op_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS]; + logic last_inp_reg_ena; + if (NUM_INP_REGS >= 1) begin : gen_last_inp_reg_ena_valid + assign last_inp_reg_ena = reg_ena_i[NUM_INP_REGS-1]; + end else begin : gen_last_inp_reg_ena_zero + assign last_inp_reg_ena = 1'b0; + end + + logic ext_op_start_q; + `FF(ext_op_start_q, last_inp_reg_ena, 1'b0) + + // ----------------- + // Input processing + // ----------------- + logic [3:0] divsqrt_fmt; + + // Translate fpnew formats into divsqrt formats + if(WIDTH == 64) begin : translate_fmt_64_bits + always_comb begin : translate_fmt + unique case (dst_fmt_q) + fpnew_pkg::FP64: divsqrt_fmt = 4'b1000; + fpnew_pkg::FP32: divsqrt_fmt = 4'b0100; + fpnew_pkg::FP16: divsqrt_fmt = 4'b0010; + fpnew_pkg::FP16ALT: divsqrt_fmt = 4'b0001; + default: divsqrt_fmt = 4'b1000; // 64 bit max width + endcase + end + end else if(WIDTH == 32) begin : translate_fmt_32_bits + always_comb begin : translate_fmt + unique case (dst_fmt_q) + fpnew_pkg::FP32: divsqrt_fmt = 4'b0100; + fpnew_pkg::FP16: divsqrt_fmt = 4'b0010; + fpnew_pkg::FP16ALT: divsqrt_fmt = 4'b0001; + default: divsqrt_fmt = 4'b0100; // 32 bit max width + endcase + end + end else if(WIDTH == 16) begin : translate_fmt_16_bits + always_comb begin : translate_fmt + unique case (dst_fmt_q) + fpnew_pkg::FP16: divsqrt_fmt = 4'b0010; + fpnew_pkg::FP16ALT: divsqrt_fmt = 4'b0001; + default: divsqrt_fmt = 4'b0010; // 16 bit max width + endcase + end + end else begin + $fatal(1, "DivSqrt THMULTI: Unsupported WIDTH (the supported width are 64, 32, 16)"); + end + // ------------ // Control FSM // ------------ + logic in_ready; // input handshake with upstream - logic div_op, sqrt_op; // input signalling with unit - logic unit_ready_q, unit_done; // status signals from unit instance + logic div_valid, sqrt_valid; // input signalling with unit + logic unit_ready, unit_done, unit_done_q; // status signals from unit instance logic op_starting; // high in the cycle a new operation starts logic out_valid, out_ready; // output handshake with downstream - logic hold_result; // whether to put result into hold register - logic data_is_held; // data in hold register is valid logic unit_busy; // valid data in flight + logic simd_synch_done; // FSM states typedef enum logic [1:0] {IDLE, BUSY, HOLD, UNREACHABLE} fsm_state_e; fsm_state_e state_q, state_d; - // Operations are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr. - assign div_op = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i; //in_ready delete, valid independent of ready - assign sqrt_op = in_valid_q & (op_q == fpnew_pkg::SQRT) & in_ready & ~flush_i; - assign op_starting = div_op | sqrt_op; //start computing or handshake, modify tb handshake right + // Valids are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr. + assign div_valid = ((in_valid_q & in_ready & ~flush_i) | ext_op_start_q) & (op_q == fpnew_pkg::DIV); + assign sqrt_valid = ((in_valid_q & in_ready & ~flush_i) | ext_op_start_q) & (op_q != fpnew_pkg::DIV); + assign op_starting = div_valid | sqrt_valid; - logic fdsu_fpu_ex1_stall, fdsu_fpu_ex1_stall_q; - logic div_op_d, div_op_q; - logic sqrt_op_d, sqrt_op_q; - - assign div_op_d = (fdsu_fpu_ex1_stall) ? div_op : 1'b0; - assign sqrt_op_d = (fdsu_fpu_ex1_stall) ? sqrt_op : 1'b0; + // Hold additional information while the operation is in progress + + TagType result_tag_q; + logic result_mask_q; + AuxType result_aux_q; + logic result_vec_op_q; - `FFL(fdsu_fpu_ex1_stall_q, fdsu_fpu_ex1_stall, 1'b1, '0) - `FFL(div_op_q, div_op_d, 1'b1, '0) - `FFL(sqrt_op_q, sqrt_op_d, 1'b1, '0) + // Fill the registers everytime a valid operation arrives (load FF, active low asynch rst) + `FFL(result_tag_q, inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0) + `FFL(result_mask_q, inp_pipe_mask_q[NUM_INP_REGS],op_starting, '0) + `FFL(result_aux_q, inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0) + `FFL(result_vec_op_q, inp_pipe_vec_op_q[NUM_INP_REGS], op_starting, '0) + + // Wait for other lanes only if the operation is vectorial + assign simd_synch_done = simd_synch_done_i || ~result_vec_op_q; + + // Valid synch with other lanes + // When one divsqrt unit completes an operation, keep its done high, waiting for the other lanes + // As soon as all the lanes are over, we can clear this FF and start with a new operation + logic unit_done_clear; + `FFLARNC(unit_done_q, unit_done, unit_done, unit_done_clear, 1'b0, clk_i, rst_ni); + assign unit_done_clear = simd_synch_done | last_inp_reg_ena; + // Tell the other units that this unit has finished now or in the past + assign divsqrt_done_o = (unit_done_q | unit_done) & result_vec_op_q; + + // Ready synch with other lanes + // Bring the FSM-generated ready outside the unit, to synchronize it with the other lanes + assign divsqrt_ready_o = in_ready; + // Upstream ready comes from sanitization FSM, and it is synched among all the lanes + assign inp_pipe_ready[NUM_INP_REGS] = result_vec_op_q ? simd_synch_rdy_i : in_ready; // FSM to safely apply and receive data from DIVSQRT unit always_comb begin : flag_fsm // Default assignments in_ready = 1'b0; out_valid = 1'b0; - hold_result = 1'b0; - data_is_held = 1'b0; unit_busy = 1'b0; state_d = state_q; - inp_pipe_ready[NUM_INP_REGS] = unit_ready_q; unique case (state_q) // Waiting for work IDLE: begin - // in_ready = 1'b1; // we're ready - in_ready = unit_ready_q; //*** - if (in_valid_q && unit_ready_q) begin // New work arrives - inp_pipe_ready[NUM_INP_REGS] = unit_ready_q && !fdsu_fpu_ex1_stall; + in_ready = 1'b1; // we're ready + if (in_valid_q && unit_ready) begin // New work arrives state_d = BUSY; // go into processing state end end // Operation in progress BUSY: begin - inp_pipe_ready[NUM_INP_REGS] = fdsu_fpu_ex1_stall_q; unit_busy = 1'b1; // data in flight - // If the unit is done with processing - if (unit_done) begin + // If all the lanes are done with processing + if (simd_synch_done_i || (~result_vec_op_q && unit_done)) begin out_valid = 1'b1; // try to commit result downstream // If downstream accepts our result if (out_ready) begin state_d = IDLE; // we anticipate going back to idling.. - if (in_valid_q && unit_ready_q) begin // ..unless new work comes in - in_ready = 1'b1; // we acknowledge the instruction + in_ready = 1'b1; // we acknowledge the instruction + if (in_valid_q && unit_ready) begin // ..unless new work comes in state_d = BUSY; // and stay busy with it end // Otherwise if downstream is not ready for the result end else begin - hold_result = 1'b1; // activate the hold register state_d = HOLD; // wait for the pipeline to take the data end end @@ -26808,12 +33949,11 @@ module fpnew_divsqrt_th_32 #( // Waiting with valid result for downstream HOLD: begin unit_busy = 1'b1; // data in flight - data_is_held = 1'b1; // data in hold register is valid out_valid = 1'b1; // try to commit result downstream // If the result is accepted by downstream if (out_ready) begin state_d = IDLE; // go back to idle.. - if (in_valid_q && unit_ready_q) begin // ..unless new work comes in + if (in_valid_q && unit_ready) begin // ..unless new work comes in in_ready = 1'b1; // acknowledge the new transaction state_d = BUSY; // will be busy with the next instruction end @@ -26834,187 +33974,80 @@ module fpnew_divsqrt_th_32 #( // FSM status register (asynch active low reset) `FF(state_q, state_d, IDLE) - // Hold additional information while the operation is in progress - TagType result_tag_q; - AuxType result_aux_q; - logic result_mask_q; - - // Fill the registers everytime a valid operation arrives (load FF, active low asynch rst) - `FFL(result_tag_q, inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0) - `FFL(result_mask_q, inp_pipe_mask_q[NUM_INP_REGS], op_starting, '0) - `FFL(result_aux_q, inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0) - // ----------------- // DIVSQRT instance // ----------------- - logic [WIDTH-1:0] unit_result, held_result_q; + logic [63:0] unit_result, held_result_q; fpnew_pkg::status_t unit_status, held_status_q; - - // thead define fdsu module's input and output - logic ctrl_fdsu_ex1_sel; - logic fdsu_fpu_ex1_cmplt; - logic [4:0] fdsu_fpu_ex1_fflags; - logic [7:0] fdsu_fpu_ex1_special_sel; - logic [3:0] fdsu_fpu_ex1_special_sign; - logic fdsu_fpu_no_op; - logic [2:0] idu_fpu_ex1_eu_sel; - logic [31:0] fdsu_frbus_data; - logic [4:0] fdsu_frbus_fflags; - logic fdsu_frbus_wb_vld; - - // dp - logic [31:0] dp_frbus_ex2_data; - logic [4:0] dp_frbus_ex2_fflags; - logic [2:0] dp_xx_ex1_cnan; - logic [2:0] dp_xx_ex1_id; - logic [2:0] dp_xx_ex1_inf; - logic [2:0] dp_xx_ex1_norm; - logic [2:0] dp_xx_ex1_qnan; - logic [2:0] dp_xx_ex1_snan; - logic [2:0] dp_xx_ex1_zero; - logic ex2_inst_wb; - logic ex2_inst_wb_vld_d, ex2_inst_wb_vld_q; - - // frbus - logic [31:0] fpu_idu_fwd_data; - logic [4:0] fpu_idu_fwd_fflags; - logic fpu_idu_fwd_vld; - - logic unit_ready_d; - - // unit_ready_q related to state machine, different under special and normal cases. - always_comb begin - if(op_starting && unit_ready_q) begin - if(ex2_inst_wb && ex2_inst_wb_vld_q) begin - unit_ready_d = 1'b1; - end else begin - unit_ready_d = 1'b0; - end - end else if(fpu_idu_fwd_vld | flush_i) begin - unit_ready_d = 1'b1; - end else begin - unit_ready_d = unit_ready_q; - end - end - - `FFL(unit_ready_q, unit_ready_d, 1'b1, 1'b1) - - // determine input of time to select operands - always_comb begin - ctrl_fdsu_ex1_sel = 1'b0; - idu_fpu_ex1_eu_sel = 3'h0; - if (op_starting) begin // time to start calculation - ctrl_fdsu_ex1_sel = 1'b1; // time to select operands - idu_fpu_ex1_eu_sel = 3'h4; // time to select operands, only idu_fpu_ex1_eu_sel_i[2] works in fdsu module - end else if (fdsu_fpu_ex1_stall_q) begin - ctrl_fdsu_ex1_sel = 1'b1; // time to select operands - idu_fpu_ex1_eu_sel = 3'h4; // time to select operands, only idu_fpu_ex1_eu_sel_i[2] works in fdsu module - end else begin - ctrl_fdsu_ex1_sel = 1'b0; - idu_fpu_ex1_eu_sel = 3'h0; - end - end - - pa_fdsu_top i_divsqrt_thead ( - .cp0_fpu_icg_en ( 1'b0 ), // input clock gate enable in gated_clk_cell, active 0. - .cp0_fpu_xx_dqnan ( 1'b0 ), // When dqnan = 0, QNAN (0x7fc00000). - .cp0_yy_clk_en ( 1'b1 ), // clock enable in gated_clk_cell, active 1. - .cpurst_b ( rst_ni ), // If negedge cpu reset, all state machines reset to IDLE. - .ctrl_fdsu_ex1_sel ( ctrl_fdsu_ex1_sel ), // select operands - .ctrl_xx_ex1_cmplt_dp ( ctrl_fdsu_ex1_sel ), // complete datapath - .ctrl_xx_ex1_inst_vld ( ctrl_fdsu_ex1_sel ), // instance valid - .ctrl_xx_ex1_stall ( fdsu_fpu_ex1_stall ), - .ctrl_xx_ex1_warm_up ( 1'b0 ), - .ctrl_xx_ex2_warm_up ( 1'b0 ), - .ctrl_xx_ex3_warm_up ( 1'b0 ), - .dp_xx_ex1_cnan ( dp_xx_ex1_cnan ), // Special input type determination - .dp_xx_ex1_id ( dp_xx_ex1_id ), - .dp_xx_ex1_inf ( dp_xx_ex1_inf ), - .dp_xx_ex1_qnan ( dp_xx_ex1_qnan ), - .dp_xx_ex1_rm ( rnd_mode_q ), // rounding mode - .dp_xx_ex1_snan ( dp_xx_ex1_snan ), - .dp_xx_ex1_zero ( dp_xx_ex1_zero ), - .fdsu_fpu_debug_info ( ), // output, not used - .fdsu_fpu_ex1_cmplt ( fdsu_fpu_ex1_cmplt ), // output, ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel_i[2] - .fdsu_fpu_ex1_cmplt_dp ( ), // output, not used - .fdsu_fpu_ex1_fflags ( fdsu_fpu_ex1_fflags ), // output, special case fflags - .fdsu_fpu_ex1_special_sel ( fdsu_fpu_ex1_special_sel ), // output, special case type selection - .fdsu_fpu_ex1_special_sign ( fdsu_fpu_ex1_special_sign ), // output, special case sign determination - .fdsu_fpu_ex1_stall ( fdsu_fpu_ex1_stall ), // output, determine whether stall in ex1 - .fdsu_fpu_no_op ( fdsu_fpu_no_op ), // output, if Write Back SM and fdsu SM no operation, fdsu_fpu_no_op = 1; Otherwise if busy, fdsu_fpu_no_op = 0. (not used) - .fdsu_frbus_data ( fdsu_frbus_data ), // output, normal case result - .fdsu_frbus_fflags ( fdsu_frbus_fflags ), // output, normal case fflags - .fdsu_frbus_freg ( ), // output, determined by input idu_fpu_ex1_dst_freg - .fdsu_frbus_wb_vld ( fdsu_frbus_wb_vld ), // output, determine whether write back valid - .forever_cpuclk ( clk_i ), - .frbus_fdsu_wb_grant ( fdsu_frbus_wb_vld ), // input is fdsu_frbus_wb_vld - .idu_fpu_ex1_dst_freg ( 5'h0f ), // register index to write back (not used) - .idu_fpu_ex1_eu_sel ( idu_fpu_ex1_eu_sel ), // time to select operands - .idu_fpu_ex1_func ( {8'b0, div_op | div_op_q, sqrt_op | sqrt_op_q} ), - .idu_fpu_ex1_srcf0 ( operands_q[0][31:0] ), // the first operand - .idu_fpu_ex1_srcf1 ( operands_q[1][31:0] ), // the second operand - .pad_yy_icg_scan_en ( 1'b0 ), // input of core_top, set to 1'b0 from the beginning to end - .rtu_xx_ex1_cancel ( 1'b0 ), - .rtu_xx_ex2_cancel ( 1'b0 ), - .rtu_yy_xx_async_flush ( flush_i ), - .rtu_yy_xx_flush ( 1'b0 ) - ); - - pa_fpu_dp x_pa_fpu_dp ( - .cp0_fpu_icg_en ( 1'b0 ), - .cp0_fpu_xx_rm ( rnd_mode_q ), - .cp0_yy_clk_en ( 1'b1 ), - .ctrl_xx_ex1_inst_vld ( ctrl_fdsu_ex1_sel ), - .ctrl_xx_ex1_stall ( 1'b0 ), - .ctrl_xx_ex1_warm_up ( 1'b0 ), - .dp_frbus_ex2_data ( dp_frbus_ex2_data ), // output - .dp_frbus_ex2_fflags ( dp_frbus_ex2_fflags ), // output - .dp_xx_ex1_cnan ( dp_xx_ex1_cnan ), // output - .dp_xx_ex1_id ( dp_xx_ex1_id ), // output - .dp_xx_ex1_inf ( dp_xx_ex1_inf ), // output - .dp_xx_ex1_norm ( dp_xx_ex1_norm ), // output - .dp_xx_ex1_qnan ( dp_xx_ex1_qnan ), // output - .dp_xx_ex1_snan ( dp_xx_ex1_snan ), // output - .dp_xx_ex1_zero ( dp_xx_ex1_zero ), // output - .ex2_inst_wb ( ex2_inst_wb ), // output - .fdsu_fpu_ex1_fflags ( fdsu_fpu_ex1_fflags ), - .fdsu_fpu_ex1_special_sel ( fdsu_fpu_ex1_special_sel ), - .fdsu_fpu_ex1_special_sign ( fdsu_fpu_ex1_special_sign ), - .forever_cpuclk ( clk_i ), - .idu_fpu_ex1_eu_sel ( idu_fpu_ex1_eu_sel ), - .idu_fpu_ex1_func ( {8'b0, div_op, sqrt_op} ), - .idu_fpu_ex1_gateclk_vld ( fdsu_fpu_ex1_cmplt ), - .idu_fpu_ex1_rm ( rnd_mode_q ), - .idu_fpu_ex1_srcf0 ( operands_q[0][31:0] ), - .idu_fpu_ex1_srcf1 ( operands_q[1][31:0] ), - .idu_fpu_ex1_srcf2 ( '0 ), - .pad_yy_icg_scan_en ( 1'b0 ) - ); - - assign ex2_inst_wb_vld_d = ctrl_fdsu_ex1_sel; - `FF(ex2_inst_wb_vld_q, ex2_inst_wb_vld_d, '0) - - pa_fpu_frbus x_pa_fpu_frbus ( - .ctrl_frbus_ex2_wb_req ( ex2_inst_wb & ex2_inst_wb_vld_q ), - .dp_frbus_ex2_data ( dp_frbus_ex2_data ), - .dp_frbus_ex2_fflags ( dp_frbus_ex2_fflags ), - .fdsu_frbus_data ( fdsu_frbus_data ), - .fdsu_frbus_fflags ( fdsu_frbus_fflags ), - .fdsu_frbus_wb_vld ( fdsu_frbus_wb_vld ), - .fpu_idu_fwd_data ( fpu_idu_fwd_data ), // output - .fpu_idu_fwd_fflags ( fpu_idu_fwd_fflags ), // output - .fpu_idu_fwd_vld ( fpu_idu_fwd_vld ) // output + logic hold_en; + + logic vfdsu_dp_fdiv_busy; + + // Regs to save current instruction + fpnew_pkg::roundmode_e rm_q; + logic[3:0] divsqrt_fmt_q; + fpnew_pkg::operation_e divsqrt_op_q; + logic div_op, sqrt_op; + logic [WIDTH-1:0] srcf0_q, srcf1_q; + + // Save operands in regs, C910 saves all the following information in its regs in the next cycle. + `FFL(rm_q, rnd_mode_q, op_starting, fpnew_pkg::RNE) + `FFL(divsqrt_fmt_q, divsqrt_fmt, op_starting, '0) + `FFL(divsqrt_op_q, op_q, op_starting, fpnew_pkg::DIV) + `FFL(srcf0_q, operands_q[0], op_starting, '0) + `FFL(srcf1_q, operands_q[1], op_starting, '0) + + assign div_op = (divsqrt_op_q == fpnew_pkg::DIV) ? 1'b1 : 1'b0; + assign sqrt_op = (divsqrt_op_q != fpnew_pkg::DIV) ? 1'b1 : 1'b0; + + // Select func 1 cycle after div issue + logic func_sel; + `FFLARNC(func_sel, 1'b1, op_starting, func_sel, 1'b0, clk_i, rst_ni) + + // Select operands 2 cycles after div issue + logic op_sel; + `FFLARNC(op_sel, 1'b1, func_sel, op_sel, 1'b0, clk_i, rst_ni) + + ct_vfdsu_top i_ct_vfdsu_top ( + .cp0_vfpu_icg_en ( 1'b0 ), // Internal clock gating, (module enable) doesn't matter when the clk_gate module is redundant anyway + .cp0_yy_clk_en ( 1'b1 ), // Global clock enable (same as above) + .cpurst_b ( rst_ni ), // Reset + .dp_vfdsu_ex1_pipex_dst_ereg ( '0 ), // Don't care, used in C910 + .dp_vfdsu_ex1_pipex_dst_vreg ( '0 ), // Don't care, used in C910 + .dp_vfdsu_ex1_pipex_iid ( '0 ), // Don't care, used in C910 + .dp_vfdsu_ex1_pipex_imm0 ( 3'b111 ), // Round mode, set to 3'b111 to select vfpu_yy_xx_rm signal + .dp_vfdsu_ex1_pipex_sel ( op_sel ), // 3. Select operands, start operation + .dp_vfdsu_ex1_pipex_srcf0 ( {{(64-WIDTH){1'b1}}, srcf0_q} ), // Input for operand 0 + .dp_vfdsu_ex1_pipex_srcf1 ( {{(64-WIDTH){1'b1}}, srcf1_q} ), // Input for operand 1 + .dp_vfdsu_fdiv_gateclk_issue ( 1'b1 ), // Local clock enable (same as above) + .dp_vfdsu_idu_fdiv_issue ( op_starting ), // 1. Issue fdiv (FSM in ctrl) + .forever_cpuclk ( clk_i ), // Clock input + .idu_vfpu_rf_pipex_func ( {3'b0, divsqrt_fmt_q, 11'b0 ,sqrt_op, div_op} ), // Defines format (bits 16,15) and operation (bits 1,0) + .idu_vfpu_rf_pipex_gateclk_sel ( func_sel ), // 2. Select func + .pad_yy_icg_scan_en ( 1'b0 ), // SE signal for the redundant clock gating module + .rtu_yy_xx_flush ( flush_i | last_inp_reg_ena), // Flush + .vfpu_yy_xx_dqnan ( 1'b0 ), // Disable qNaN, set to 1 if sNaN is used + .vfpu_yy_xx_rm ( rm_q ), // Round mode. redundant if imm0 set to the same + .pipex_dp_vfdsu_ereg ( ), // Don't care, used by C910 + .pipex_dp_vfdsu_ereg_data ( unit_status ), // Output: status flags + .pipex_dp_vfdsu_freg_data ( unit_result ), // Output: result + .pipex_dp_vfdsu_inst_vld ( unit_done ), // The result is valid + .pipex_dp_vfdsu_vreg ( ), // Don't care, used by C910 + .vfdsu_dp_fdiv_busy ( vfdsu_dp_fdiv_busy ), // Unit is busy, data in flight + .vfdsu_dp_inst_wb_req ( ), // Don't care, used by C910 + .vfdsu_ifu_debug_ex2_wait ( ), // Debug output + .vfdsu_ifu_debug_idle ( ), // Debug output + .vfdsu_ifu_debug_pipe_busy ( ) // Debug output ); - always_comb begin - unit_result[31:0] = fpu_idu_fwd_data[31:0]; - unit_status[4:0] = fpu_idu_fwd_fflags[4:0]; - unit_done = fpu_idu_fwd_vld; - end + assign unit_ready = !vfdsu_dp_fdiv_busy; + // Hold the result when one lane has finished execution, except when all the lanes finish together, + // or the operation is not vectorial, and the result can be accepted downstream + assign hold_en = unit_done & (~simd_synch_done_i | ~out_ready) & ~(~result_vec_op_q & out_ready); // The Hold register (load, no reset) - `FFLNR(held_result_q, unit_result, hold_result, clk_i) - `FFLNR(held_status_q, unit_status, hold_result, clk_i) + `FFLNR(held_result_q, unit_result, hold_en, clk_i) + `FFLNR(held_status_q, unit_status, hold_en, clk_i) // -------------- // Output Select @@ -27022,8 +34055,8 @@ module fpnew_divsqrt_th_32 #( logic [WIDTH-1:0] result_d; fpnew_pkg::status_t status_d; // Prioritize hold register data - assign result_d = data_is_held ? held_result_q : unit_result; - assign status_d = data_is_held ? held_status_q : unit_status; + assign result_d[WIDTH-1:0] = unit_done_q ? held_result_q[WIDTH-1:0] : unit_result[WIDTH-1:0]; + assign status_d = unit_done_q ? held_status_q : unit_status; // ---------------- // Output Pipeline @@ -27032,8 +34065,8 @@ module fpnew_divsqrt_th_32 #( logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; TagType [0:NUM_OUT_REGS] out_pipe_tag_q; - AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; logic [0:NUM_OUT_REGS] out_pipe_valid_q; // Ready signal is combinatorial for all stages logic [0:NUM_OUT_REGS] out_pipe_ready; @@ -27077,10 +34110,83 @@ module fpnew_divsqrt_th_32 #( assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q}); + + // Early valid_o signal. This is used for dispatching instructions for dual-issue processor. + if (NUM_OUT_REGS > 0) begin + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], + out_pipe_valid_q[NUM_OUT_REGS-1]}; + end else if (NUM_INP_REGS > 0) begin + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], + inp_pipe_valid_q[NUM_INP_REGS-1]}; + end else begin + assign early_out_valid_o = 1'b0; + end +endmodule + +// ----- 8< ----- FILE "./fmalza.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.133.0 +/////////////////////////////////////////// +// fmalza.sv +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: Leading Zero Anticipator +// +// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14) +// See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module fmalza #(WIDTH, NF) ( + input logic [WIDTH-1:0] A, // addend + input logic [2*NF+1:0] Pm, // product + input logic Cin, // carry in + input logic sub, // subtraction + output logic [WIDTH:0] F // normalization shift leading pattern for the positive result +); + + logic [WIDTH-1:0] B; // zero-extended product with same size as aligned A + logic [WIDTH-1:0] P, G, K; // propagate, generate, kill for each column + logic [WIDTH-1:0] Pp1, Gm1, Km1; // propagate shifted right by 1, generate/kill shifted left 1 + + assign B = {{(NF+2){1'b0}}, Pm, 2'b0}; // Zero extend product + + assign P = A^B; + assign G = A&B; + assign K = ~A&~B; + + assign Pp1 = {sub, P[WIDTH-1:1]}; // shift P right by 1 (for P_i+1) , use subtract flag in most significant bit + assign Gm1 = {G[WIDTH-2:0], Cin}; // shift G left by 1 (for G_i-1) and bring in Cin + assign Km1 = {K[WIDTH-2:0], ~Cin}; // shift K left by 1 (for K_i-1) and bring in Cin + + // Apply function to determine Leading pattern + // - note: Schmookler01 uses the numbering system where 0 is the most significant bit + assign F[WIDTH] = ~sub&P[WIDTH-1]; + assign F[WIDTH-1:0] = (Pp1&(G&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | G&~Gm1)); + endmodule // ----- 8< ----- FILE "./fpnew_fma.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -27105,8 +34211,8 @@ module fpnew_fma #( parameter type TagType = logic, parameter type AuxType = logic, // Do not change - localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -27136,14 +34242,16 @@ module fpnew_fma #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); // ---------- // Constants // ---------- - localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); - localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + parameter int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + parameter int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); localparam int unsigned BIAS = fpnew_pkg::bias(FpFormat); // Precision bits 'p' include the implicit bit localparam int unsigned PRECISION_BITS = MAN_BITS + 1; @@ -27160,13 +34268,15 @@ module fpnew_fma #( localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED - ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + ? ((NumPipeRegs == 4) ? 1 : ((NumPipeRegs + 2) / 3)) // Second to get distributed regs : 0); // no regs here otherwise localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED ? ((NumPipeRegs + 2) / 3) // First to get distributed regs : 0); // no regs here otherwise + localparam NUM_SUM_REGS = (NUM_MID_REGS > 1) ? (NUM_MID_REGS - 1) : NUM_MID_REGS; + localparam NUM_NORM_REGS = (NUM_MID_REGS > 1) ? 1 : 0; localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED @@ -27279,7 +34389,8 @@ module fpnew_fma #( unique case (inp_pipe_op_q[NUM_INP_REGS]) fpnew_pkg::FMADD: ; // do nothing fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product - fpnew_pkg::ADD: begin // Set multiplicand to +1 + fpnew_pkg::ADD, + fpnew_pkg::ADDS: begin // Set multiplicand to +1 operand_a = '{sign: 1'b0, exponent: BIAS, mantissa: '0}; info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. end @@ -27346,7 +34457,7 @@ module fpnew_fma #( // Special cases involving infinity end else if (any_operand_inf) begin result_is_special = 1'b1; // bypass FMA - // Effective addition of opposite infinities (??inf - ??inf) is invalid! + // Effective addition of opposite infinities (±inf - ±inf) is invalid! if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) special_status.NV = 1'b1; // invalid operation // Handle cases where output will be inf because of inf product input @@ -27452,17 +34563,22 @@ module fpnew_fma #( // ------ // Adder // ------ - logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry - logic sum_carry; // observe carry bit from sum for sign fixing - logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic [3*PRECISION_BITS+4:0] sum_pos, sum_neg; // added one bit for the carry + logic sum_carry; // observe carry bit from positive sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow logic final_sign; //Mantissa adder (ab+c). In normal addition, it cannot overflow. - assign sum_raw = product_shifted + addend_shifted + inject_carry_in; - assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + assign sum_pos = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_pos[3*PRECISION_BITS+4]; + + // Parallel adder for negative sum (only used for effective subtractions). + // Note: inject_carry_in is used to complete the negation of the addend in the positive sum but + // for the negative sum the addend is not negated, so no carry needs to be injected. + assign sum_neg = addend_after_shift - product_shifted; // Complement negative sum (can only happen in subtraction -> overflows for positive results) - assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + assign sum = (effective_subtraction && ~sum_carry) ? sum_neg : sum_pos; // In case of a mispredicted subtraction result, do a sign flip assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) @@ -27486,24 +34602,24 @@ module fpnew_fma #( fp_t special_result_q; fpnew_pkg::status_t special_status_q; // Internal pipeline signals, index i holds signal after i register stages - logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + logic [0:NUM_SUM_REGS] mid_pipe_eff_sub_q; logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; - logic [0:NUM_MID_REGS] mid_pipe_sticky_q; + logic [0:NUM_SUM_REGS] mid_pipe_sticky_q; logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; - logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; - fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; - logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; - fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; - fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; - TagType [0:NUM_MID_REGS] mid_pipe_tag_q; - logic [0:NUM_MID_REGS] mid_pipe_mask_q; - AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; - logic [0:NUM_MID_REGS] mid_pipe_valid_q; + logic [0:NUM_SUM_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_SUM_REGS] mid_pipe_rnd_mode_q; + logic [0:NUM_SUM_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_SUM_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_SUM_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_SUM_REGS] mid_pipe_tag_q; + logic [0:NUM_SUM_REGS] mid_pipe_mask_q; + AuxType [0:NUM_SUM_REGS] mid_pipe_aux_q; + logic [0:NUM_SUM_REGS] mid_pipe_valid_q; // Ready signal is combinatorial for all stages - logic [0:NUM_MID_REGS] mid_pipe_ready; + logic [0:NUM_SUM_REGS] mid_pipe_ready; // Input stage: First element of pipeline is taken from upstream logic assign mid_pipe_eff_sub_q[0] = effective_subtraction; @@ -27526,7 +34642,7 @@ module fpnew_fma #( assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; // Generate the register stages - for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + for (genvar i = 0; i < NUM_SUM_REGS; i++) begin : gen_inside_pipeline // Internal register enable for this stage logic reg_ena; // Determine the ready signal of the current stage - advance the pipeline: @@ -27555,18 +34671,18 @@ module fpnew_fma #( `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) end // Output stage: assign selected pipe outputs to signals for later use - assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; - assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; - assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; - assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; - assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; - assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; - assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; - assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; - assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; - assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; - assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; - assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_SUM_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_SUM_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_SUM_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_SUM_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_SUM_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_SUM_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_SUM_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_SUM_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_SUM_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_SUM_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_SUM_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_SUM_REGS]; // -------------- // Normalization @@ -27681,24 +34797,80 @@ module fpnew_fma #( // In case of overflow, the round and sticky bits are set for proper rounding assign round_sticky_bits = (of_before_round) ? 2'b11 : {final_mantissa[0], sticky_after_norm}; + // ---------------------- + // Normalization Pipeline + // ---------------------- + logic [0:NUM_NORM_REGS][EXP_BITS+MAN_BITS-1:0] norm_pipe_abs_q; + logic [0:NUM_NORM_REGS] norm_pipe_sign_q; + logic [0:NUM_NORM_REGS][1:0] norm_pipe_round_sticky_q; + fpnew_pkg::roundmode_e [0:NUM_NORM_REGS] norm_pipe_rnd_mode_q; + logic [0:NUM_NORM_REGS] norm_pipe_eff_sub_q; + logic [0:NUM_NORM_REGS] norm_pipe_of_before_round_q; + logic [0:NUM_NORM_REGS] norm_pipe_sum_sticky_msb_q; + logic [0:NUM_NORM_REGS] norm_pipe_res_is_spec_q; + fp_t [0:NUM_NORM_REGS] norm_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_NORM_REGS] norm_pipe_spec_stat_q; + TagType [0:NUM_NORM_REGS] norm_pipe_tag_q; + logic [0:NUM_NORM_REGS] norm_pipe_mask_q; + AuxType [0:NUM_NORM_REGS] norm_pipe_aux_q; + logic [0:NUM_NORM_REGS] norm_pipe_valid_q; + logic [0:NUM_NORM_REGS] norm_pipe_ready; + + assign norm_pipe_abs_q[0] = pre_round_abs; + assign norm_pipe_sign_q[0] = pre_round_sign; + assign norm_pipe_round_sticky_q[0] = round_sticky_bits; + assign norm_pipe_rnd_mode_q[0] = rnd_mode_q; + assign norm_pipe_eff_sub_q[0] = effective_subtraction_q; + assign norm_pipe_of_before_round_q[0] = of_before_round; + assign norm_pipe_sum_sticky_msb_q[0] = sum_sticky_bits[MAN_BITS*2 + 4]; + assign norm_pipe_res_is_spec_q[0] = result_is_special_q; + assign norm_pipe_spec_res_q[0] = special_result_q; + assign norm_pipe_spec_stat_q[0] = special_status_q; + assign norm_pipe_tag_q[0] = mid_pipe_tag_q[NUM_SUM_REGS]; + assign norm_pipe_mask_q[0] = mid_pipe_mask_q[NUM_SUM_REGS]; + assign norm_pipe_aux_q[0] = mid_pipe_aux_q[NUM_SUM_REGS]; + assign norm_pipe_valid_q[0] = mid_pipe_valid_q[NUM_SUM_REGS]; + + assign mid_pipe_ready[NUM_SUM_REGS] = norm_pipe_ready[0]; + + for (genvar i = 0; i < NUM_NORM_REGS; i++) begin : gen_norm_pipeline + logic reg_ena; + assign norm_pipe_ready[i] = norm_pipe_ready[i+1] | ~norm_pipe_valid_q[i+1]; + `FFLARNC(norm_pipe_valid_q[i+1], norm_pipe_valid_q[i], norm_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + assign reg_ena = (norm_pipe_ready[i] & norm_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + NUM_SUM_REGS + i]; + `FFL(norm_pipe_abs_q[i+1], norm_pipe_abs_q[i], reg_ena, '0) + `FFL(norm_pipe_sign_q[i+1], norm_pipe_sign_q[i], reg_ena, '0) + `FFL(norm_pipe_round_sticky_q[i+1], norm_pipe_round_sticky_q[i], reg_ena, '0) + `FFL(norm_pipe_rnd_mode_q[i+1], norm_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(norm_pipe_eff_sub_q[i+1], norm_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(norm_pipe_of_before_round_q[i+1], norm_pipe_of_before_round_q[i], reg_ena, '0) + `FFL(norm_pipe_sum_sticky_msb_q[i+1], norm_pipe_sum_sticky_msb_q[i], reg_ena, '0) + `FFL(norm_pipe_res_is_spec_q[i+1], norm_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(norm_pipe_spec_res_q[i+1], norm_pipe_spec_res_q[i], reg_ena, '0) + `FFL(norm_pipe_spec_stat_q[i+1], norm_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(norm_pipe_tag_q[i+1], norm_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(norm_pipe_mask_q[i+1], norm_pipe_mask_q[i], reg_ena, '0) + `FFL(norm_pipe_aux_q[i+1], norm_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Perform the rounding fpnew_rounding #( .AbsWidth ( EXP_BITS + MAN_BITS ) ) i_fpnew_rounding ( - .abs_value_i ( pre_round_abs ), - .sign_i ( pre_round_sign ), - .round_sticky_bits_i ( round_sticky_bits ), - .rnd_mode_i ( rnd_mode_q ), - .effective_subtraction_i ( effective_subtraction_q ), - .abs_rounded_o ( rounded_abs ), - .sign_o ( rounded_sign ), - .exact_zero_o ( result_zero ) + .abs_value_i ( norm_pipe_abs_q[NUM_NORM_REGS] ), + .sign_i ( norm_pipe_sign_q[NUM_NORM_REGS] ), + .round_sticky_bits_i ( norm_pipe_round_sticky_q[NUM_NORM_REGS] ), + .rnd_mode_i ( norm_pipe_rnd_mode_q[NUM_NORM_REGS] ), + .effective_subtraction_i ( norm_pipe_eff_sub_q[NUM_NORM_REGS] ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) ); // Classification after rounding assign uf_after_round = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal - || ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && - ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_i == fpnew_pkg::RNE) || (rnd_mode_i == fpnew_pkg::RMM))))); + || ((norm_pipe_abs_q[NUM_NORM_REGS][EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && + ((norm_pipe_round_sticky_q[NUM_NORM_REGS] != 2'b11) || (!norm_pipe_sum_sticky_msb_q[NUM_NORM_REGS] && ((norm_pipe_rnd_mode_q[NUM_NORM_REGS] == fpnew_pkg::RNE) || (norm_pipe_rnd_mode_q[NUM_NORM_REGS] == fpnew_pkg::RMM))))); assign of_after_round = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // exponent all ones // ----------------- @@ -27711,17 +34883,17 @@ module fpnew_fma #( assign regular_result = {rounded_sign, rounded_abs}; assign regular_status.NV = 1'b0; // only valid cases are handled in regular path assign regular_status.DZ = 1'b0; // no divisions - assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.OF = norm_pipe_of_before_round_q[NUM_NORM_REGS] | of_after_round; // rounding can introduce overflow assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF - assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + assign regular_status.NX = (| norm_pipe_round_sticky_q[NUM_NORM_REGS]) | norm_pipe_of_before_round_q[NUM_NORM_REGS] | of_after_round; // Final results for output pipeline fp_t result_d; fpnew_pkg::status_t status_d; // Select output depending on special case detection - assign result_d = result_is_special_q ? special_result_q : regular_result; - assign status_d = result_is_special_q ? special_status_q : regular_status; + assign result_d = norm_pipe_res_is_spec_q[NUM_NORM_REGS] ? norm_pipe_spec_res_q[NUM_NORM_REGS] : regular_result; + assign status_d = norm_pipe_res_is_spec_q[NUM_NORM_REGS] ? norm_pipe_spec_stat_q[NUM_NORM_REGS] : regular_status; // ---------------- // Output Pipeline @@ -27739,12 +34911,12 @@ module fpnew_fma #( // Input stage: First element of pipeline is taken from inputs assign out_pipe_result_q[0] = result_d; assign out_pipe_status_q[0] = status_d; - assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; - assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; - assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; - assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; - // Input stage: Propagate pipeline ready signal to inside pipe - assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + assign out_pipe_tag_q[0] = norm_pipe_tag_q[NUM_NORM_REGS]; + assign out_pipe_mask_q[0] = norm_pipe_mask_q[NUM_NORM_REGS]; + assign out_pipe_aux_q[0] = norm_pipe_aux_q[NUM_NORM_REGS]; + assign out_pipe_valid_q[0] = norm_pipe_valid_q[NUM_NORM_REGS]; + // Input stage: Propagate pipeline ready signal to normalization pipe + assign norm_pipe_ready[NUM_NORM_REGS] = out_pipe_ready[0]; // Generate the register stages for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline // Internal register enable for this stage @@ -27774,11 +34946,28 @@ module fpnew_fma #( assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; - assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, norm_pipe_valid_q, out_pipe_valid_q}); + + // Early valid_o signal. This is used for dispatching instructions for dual-issue processor. + if (NUM_OUT_REGS > 0) begin + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], + out_pipe_valid_q[NUM_OUT_REGS-1]}; + end else if (NUM_NORM_REGS > 0) begin + assign early_out_valid_o = |{norm_pipe_valid_q[NUM_NORM_REGS] & ~norm_pipe_ready[NUM_NORM_REGS], + norm_pipe_valid_q[NUM_NORM_REGS-1]}; + end else if (NUM_SUM_REGS > 0) begin + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_SUM_REGS] & ~mid_pipe_ready[NUM_SUM_REGS], + mid_pipe_valid_q[NUM_SUM_REGS-1]}; + end else if (NUM_INP_REGS > 0) begin + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], + inp_pipe_valid_q[NUM_INP_REGS-1]}; + end else begin + assign early_out_valid_o = 1'b0; + end endmodule // ----- 8< ----- FILE "./fpnew_fma_multi.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -27803,9 +34992,9 @@ module fpnew_fma_multi #( parameter type TagType = logic, parameter type AuxType = logic, // Do not change - localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -27815,8 +35004,9 @@ module fpnew_fma_multi #( input fpnew_pkg::roundmode_e rnd_mode_i, input fpnew_pkg::operation_e op_i, input logic op_mod_i, - input fpnew_pkg::fp_format_e src_fmt_i, // format of the multiplicands - input fpnew_pkg::fp_format_e dst_fmt_i, // format of the addend and result + input fpnew_pkg::fp_format_e src_fmt_i, // format of the multiplicands + input fpnew_pkg::fp_format_e src2_fmt_i, // format of the addend + input fpnew_pkg::fp_format_e dst_fmt_i, // format of the result input TagType tag_i, input logic mask_i, input AuxType aux_i, @@ -27837,7 +35027,9 @@ module fpnew_fma_multi #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); // ---------- @@ -27864,13 +35056,15 @@ module fpnew_fma_multi #( localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED - ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + ? ((NumPipeRegs == 4) ? 1 : ((NumPipeRegs + 2) / 3)) // Second to get distributed regs : 0); // no regs here otherwise localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED ? ((NumPipeRegs + 2) / 3) // First to get distributed regs : 0); // no regs here otherwise + localparam NUM_SUM_REGS = (NUM_MID_REGS > 1) ? (NUM_MID_REGS - 1) : NUM_MID_REGS; + localparam NUM_NORM_REGS = (NUM_MID_REGS > 1) ? 1 : 0; localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER ? NumPipeRegs : (PipeConfig == fpnew_pkg::DISTRIBUTED @@ -27892,6 +35086,7 @@ module fpnew_fma_multi #( // Selected pipeline output signals as non-arrays logic [2:0][WIDTH-1:0] operands_q; fpnew_pkg::fp_format_e src_fmt_q; + fpnew_pkg::fp_format_e src2_fmt_q; fpnew_pkg::fp_format_e dst_fmt_q; // Input pipeline signals, index i holds signal after i register stages @@ -27901,6 +35096,7 @@ module fpnew_fma_multi #( fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src2_fmt_q; fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; TagType [0:NUM_INP_REGS] inp_pipe_tag_q; logic [0:NUM_INP_REGS] inp_pipe_mask_q; @@ -27916,6 +35112,7 @@ module fpnew_fma_multi #( assign inp_pipe_op_q[0] = op_i; assign inp_pipe_op_mod_q[0] = op_mod_i; assign inp_pipe_src_fmt_q[0] = src_fmt_i; + assign inp_pipe_src2_fmt_q[0] = src2_fmt_i; assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; assign inp_pipe_tag_q[0] = tag_i; assign inp_pipe_mask_q[0] = mask_i; @@ -27942,6 +35139,7 @@ module fpnew_fma_multi #( `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) `FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_src2_fmt_q[i+1], inp_pipe_src2_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) @@ -27950,6 +35148,7 @@ module fpnew_fma_multi #( // Output stage: assign selected pipe outputs to signals for later use assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS]; + assign src2_fmt_q = inp_pipe_src2_fmt_q[NUM_INP_REGS]; assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; // ----------------- @@ -27969,12 +35168,13 @@ module fpnew_fma_multi #( localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); if (FpFmtConfig[fmt]) begin : active_format + localparam fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(fmt); logic [2:0][FP_WIDTH-1:0] trimmed_ops; // Classify input fpnew_classifier #( - .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), - .NumOperands ( 3 ) + .FpFormat ( FpFormat ), + .NumOperands ( 3 ) ) i_fpnew_classifier ( .operands_i ( trimmed_ops ), .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS][fmt] ), @@ -28005,20 +35205,20 @@ module fpnew_fma_multi #( // | FMADD | \c 1 | FMSUB: Invert sign of operand C // | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A // | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C - // | ADD | \c 0 | ADD: Set operand A to +1.0 - // | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C + // | ADD/ADDS | \c 0 | ADD: Set operand A to +1.0 + // | ADD/ADDS | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C // | MUL | \c 0 | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode // | *others* | \c - | *invalid* // \note \c op_mod_q always inverts the sign of the addend. always_comb begin : op_select // Default assignments - packing-order-agnostic - operand_a = {fmt_sign[src_fmt_q][0], fmt_exponent[src_fmt_q][0], fmt_mantissa[src_fmt_q][0]}; - operand_b = {fmt_sign[src_fmt_q][1], fmt_exponent[src_fmt_q][1], fmt_mantissa[src_fmt_q][1]}; - operand_c = {fmt_sign[dst_fmt_q][2], fmt_exponent[dst_fmt_q][2], fmt_mantissa[dst_fmt_q][2]}; - info_a = info_q[src_fmt_q][0]; - info_b = info_q[src_fmt_q][1]; - info_c = info_q[dst_fmt_q][2]; + operand_a = {fmt_sign[src_fmt_q ][0], fmt_exponent[src_fmt_q ][0], fmt_mantissa[src_fmt_q ][0]}; + operand_b = {fmt_sign[src_fmt_q ][1], fmt_exponent[src_fmt_q ][1], fmt_mantissa[src_fmt_q ][1]}; + operand_c = {fmt_sign[src2_fmt_q][2], fmt_exponent[src2_fmt_q][2], fmt_mantissa[src2_fmt_q][2]}; + info_a = info_q[src_fmt_q ][0]; + info_b = info_q[src_fmt_q ][1]; + info_c = info_q[src2_fmt_q][2]; // op_mod_q inverts sign of operand C operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS]; @@ -28026,7 +35226,8 @@ module fpnew_fma_multi #( unique case (inp_pipe_op_q[NUM_INP_REGS]) fpnew_pkg::FMADD: ; // do nothing fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product - fpnew_pkg::ADD: begin // Set multiplicand to +1 + fpnew_pkg::ADD, + fpnew_pkg::ADDS: begin // Set multiplicand to +1 operand_a = '{sign: 1'b0, exponent: fpnew_pkg::bias(src_fmt_q), mantissa: '0}; info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. end @@ -28111,7 +35312,7 @@ module fpnew_fma_multi #( // Special cases involving infinity end else if (any_operand_inf) begin fmt_result_is_special[fmt] = 1'b1; // bypass FMA - // Effective addition of opposite infinities (??inf - ??inf) is invalid! + // Effective addition of opposite infinities (±inf - ±inf) is invalid! if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) fmt_special_status[fmt].NV = 1'b1; // invalid operation // Handle cases where output will be inf because of inf product input @@ -28156,7 +35357,10 @@ module fpnew_fma_multi #( // Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx) // with Ex the encoded exponent and nx the implicit bit. Internal exponents are biased to dst fmt. - assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm + assign exponent_addend = info_c.is_zero ? 1 // in case the addend is zero, set minimum exp + : signed'(exponent_c + $signed({1'b0, ~info_c.is_normal}) // 0 as subnorm + - signed'(fpnew_pkg::bias(src2_fmt_q)) + + signed'(fpnew_pkg::bias(dst_fmt_q))); // rebias for dst fmt // Biased product exponent is the sum of encoded exponents minus the bias. assign exponent_product = (info_a.is_zero || info_b.is_zero) // in case the product is zero, set minimum exp. ? 2 - signed'(fpnew_pkg::bias(dst_fmt_q)) @@ -28166,8 +35370,6 @@ module fpnew_fma_multi #( + signed'(fpnew_pkg::bias(dst_fmt_q))); // rebias for dst fmt // Exponent difference is the addend exponent minus the product exponent assign exponent_difference = exponent_addend - exponent_product; - // The tentative exponent will be the larger of the product or addend exponent - assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product; // Shift amount for addend based on exponents (unsigned as only right shifts) logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt; @@ -28184,6 +35386,43 @@ module fpnew_fma_multi #( addend_shamt = 0; end + // LZC for addend normalization + logic [$clog2(SUPER_MAN_BITS)-1:0] addend_lzc_count; + logic [$clog2(SUPER_MAN_BITS) :0] addend_lzc_count_sgn; + logic [SHIFT_AMOUNT_WIDTH -1:0] addend_normalize_shamt; + + // Leading zero counter for addend normalization + lzc #( + .WIDTH ( SUPER_MAN_BITS ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_addend_lzc ( + .in_i ( operand_c.mantissa ), + .cnt_o ( addend_lzc_count ), + .empty_o ( ) + ); + + assign addend_lzc_count_sgn = signed'({1'b0, addend_lzc_count}); + + // Determine addend normalization shift amount (used for sum shifting in addend-ancored case) + always_comb begin + // normal or zero addend + if (info_c.is_normal || info_c.is_zero) begin + addend_normalize_shamt = 0; + // subnormal and will still be subnormal in destination format (no positive rebias added to exponent) + end else if (exponent_addend <= 1) begin + addend_normalize_shamt = 0; + // subnormal and will likely be normal in destination format in addend-anchored case + end else if (addend_lzc_count_sgn + 1 < exponent_addend) begin + addend_normalize_shamt = addend_lzc_count + 1; + // subnormal and will still be subnormal in destination format (insufficient positive rebias added to exponent) + end else begin + addend_normalize_shamt = exponent_addend - 1; + end + end + + // The tentative exponent will be the larger of the product or addend exponent + assign tentative_exponent = (exponent_difference > 0) ? exponent_addend - addend_normalize_shamt : exponent_product; + // ------------------ // Product data path // ------------------ @@ -28233,23 +35472,45 @@ module fpnew_fma_multi #( // ------ // Adder // ------ - logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry - logic sum_carry; // observe carry bit from sum for sign fixing - logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic [3*PRECISION_BITS+4:0] sum_pos, sum_neg; // added one bit for the carry + logic sum_carry; // observe carry bit from positive sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow logic final_sign; //Mantissa adder (ab+c). In normal addition, it cannot overflow. - assign sum_raw = product_shifted + addend_shifted + inject_carry_in; - assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + assign sum_pos = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_pos[3*PRECISION_BITS+4]; + + // Parallel adder for negative sum (only used for effective subtractions). + // Note: inject_carry_in is used to complete the negation of the addend in the positive sum but + // for the negative sum the addend is not negated, so no carry needs to be injected. + assign sum_neg = addend_after_shift - product_shifted; // Complement negative sum (can only happen in subtraction -> overflows for positive results) - assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + assign sum = (effective_subtraction && ~sum_carry) ? sum_neg : sum_pos; // In case of a mispredicted subtraction result, do a sign flip assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) ? 1'b1 : (effective_subtraction ? 1'b0 : tentative_sign); + // ------ + // Leading Zero Anticipator + // ------ + logic [LOWER_SUM_WIDTH:0] lza_pattern; + + fmalza #( + .WIDTH ( LOWER_SUM_WIDTH ), + .NF ( PRECISION_BITS-1 ) + ) i_fmalza ( + .A ( addend_shifted[LOWER_SUM_WIDTH-1:0] ), + .Pm ( product ), + .Cin ( inject_carry_in ), + .sub ( effective_subtraction ), + .F ( lza_pattern ) + ); + + // --------------- // Internal pipeline // --------------- @@ -28261,6 +35522,7 @@ module fpnew_fma_multi #( logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q; logic sticky_before_add_q; logic [3*PRECISION_BITS+3:0] sum_q; + logic [LOWER_SUM_WIDTH:0] lza_pattern_q; logic final_sign_q; fpnew_pkg::fp_format_e dst_fmt_q2; fpnew_pkg::roundmode_e rnd_mode_q; @@ -28268,34 +35530,36 @@ module fpnew_fma_multi #( fp_t special_result_q; fpnew_pkg::status_t special_status_q; // Internal pipeline signals, index i holds signal after i register stages - logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; - logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; - logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; - logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; - logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; - logic [0:NUM_MID_REGS] mid_pipe_sticky_q; - logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; - logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; - fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; - fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q; - logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; - fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; - fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; - TagType [0:NUM_MID_REGS] mid_pipe_tag_q; - logic [0:NUM_MID_REGS] mid_pipe_mask_q; - AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; - logic [0:NUM_MID_REGS] mid_pipe_valid_q; + logic [0:NUM_SUM_REGS] mid_pipe_eff_sub_q; + logic signed [0:NUM_SUM_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; + logic signed [0:NUM_SUM_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; + logic signed [0:NUM_SUM_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; + logic [0:NUM_SUM_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; + logic [0:NUM_SUM_REGS] mid_pipe_sticky_q; + logic [0:NUM_SUM_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; + logic [0:NUM_SUM_REGS][LOWER_SUM_WIDTH:0] mid_pipe_lza_pattern_q; + logic [0:NUM_SUM_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_SUM_REGS] mid_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_SUM_REGS] mid_pipe_dst_fmt_q; + logic [0:NUM_SUM_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_SUM_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_SUM_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_SUM_REGS] mid_pipe_tag_q; + logic [0:NUM_SUM_REGS] mid_pipe_mask_q; + AuxType [0:NUM_SUM_REGS] mid_pipe_aux_q; + logic [0:NUM_SUM_REGS] mid_pipe_valid_q; // Ready signal is combinatorial for all stages - logic [0:NUM_MID_REGS] mid_pipe_ready; + logic [0:NUM_SUM_REGS] mid_pipe_ready; // Input stage: First element of pipeline is taken from upstream logic assign mid_pipe_eff_sub_q[0] = effective_subtraction; assign mid_pipe_exp_prod_q[0] = exponent_product; assign mid_pipe_exp_diff_q[0] = exponent_difference; assign mid_pipe_tent_exp_q[0] = tentative_exponent; - assign mid_pipe_add_shamt_q[0] = addend_shamt; + assign mid_pipe_add_shamt_q[0] = addend_shamt + addend_normalize_shamt; assign mid_pipe_sticky_q[0] = sticky_before_add; assign mid_pipe_sum_q[0] = sum; + assign mid_pipe_lza_pattern_q[0] = lza_pattern; assign mid_pipe_final_sign_q[0] = final_sign; assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; assign mid_pipe_dst_fmt_q[0] = dst_fmt_q; @@ -28310,7 +35574,7 @@ module fpnew_fma_multi #( assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; // Generate the register stages - for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + for (genvar i = 0; i < NUM_SUM_REGS; i++) begin : gen_inside_pipeline // Internal register enable for this stage logic reg_ena; // Determine the ready signal of the current stage - advance the pipeline: @@ -28329,6 +35593,7 @@ module fpnew_fma_multi #( `FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0) `FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0) `FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0) + `FFL(mid_pipe_lza_pattern_q[i+1], mid_pipe_lza_pattern_q[i], reg_ena, '0) `FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0) `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) `FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) @@ -28340,27 +35605,31 @@ module fpnew_fma_multi #( `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) end // Output stage: assign selected pipe outputs to signals for later use - assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; - assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; - assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; - assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; - assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; - assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; - assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; - assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; - assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; - assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS]; - assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; - assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; - assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_SUM_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_SUM_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_SUM_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_SUM_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_SUM_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_SUM_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_SUM_REGS]; + assign lza_pattern_q = mid_pipe_lza_pattern_q[NUM_SUM_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_SUM_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_SUM_REGS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_SUM_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_SUM_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_SUM_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_SUM_REGS]; // -------------- // Normalization // -------------- logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched + logic [LZC_RESULT_WIDTH-1:0] lza_count_q; // the number of leading zeroes from LZA logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count - logic lzc_zeroes; // in case only zeroes found + logic sum_lower_zero; // in case only zeroes found + logic [LOWER_SUM_WIDTH:0] least_leading_0_onehot; // onehot encoded least leading 0 + logic lza_overpredict; // LZA over-predicted actual LZC by 1 logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount logic signed [EXP_WIDTH-1:0] normalized_exponent; @@ -28372,18 +35641,28 @@ module fpnew_fma_multi #( logic signed [EXP_WIDTH-1:0] final_exponent; - assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; - // Leading zero counter for cancellations lzc #( - .WIDTH ( LOWER_SUM_WIDTH ), - .MODE ( 1 ) // MODE = 1 counts leading zeroes + .WIDTH ( LOWER_SUM_WIDTH + 1 ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes ) i_lzc ( - .in_i ( sum_lower ), - .cnt_o ( leading_zero_count ), - .empty_o ( lzc_zeroes ) + .in_i ( lza_pattern_q ), + .cnt_o ( lza_count_q ), + .empty_o ( /*unused*/ ) ); + assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; + + assign sum_lower_zero = sum_lower == '0; + + // A carry might have propagated into the least leading 0 bit (the lowest 0 bits just before the + // first 1 bit) predicted by the LZA. + // Note: This is a mux that only looks at `sum_q[LOWER_SUM_WIDTH:0]`. + assign least_leading_0_onehot = {1'b1, {LOWER_SUM_WIDTH{1'b0}}} >> lza_count_q; + assign lza_overpredict = |(sum_q[LOWER_SUM_WIDTH:0] & least_leading_0_onehot); + + // Get actual LZC by correcting LZA in case of over-prediction + assign leading_zero_count = lza_overpredict ? lza_count_q - 1 : lza_count_q; assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count}); // Normalization shift amount based on exponents and LZC (unsigned as only left shifts) @@ -28391,15 +35670,20 @@ module fpnew_fma_multi #( // Product-anchored case or cancellations require LZC if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin // Normal result (biased exponent > 0 and not a zero) - if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin + if ((exponent_product_q - signed'({1'b0, lza_count_q}) + 1 >= 0) && !sum_lower_zero) begin // Undo initial product shift, remove the counted zeroes - norm_shamt = PRECISION_BITS + 2 + leading_zero_count; - normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift + norm_shamt = PRECISION_BITS + 1 + lza_count_q; + normalized_exponent = exponent_product_q - signed'({1'b0, lza_count_q}) + 2; // account for shift // Subnormal result end else begin // Cap the shift distance to align mantissa with minimum exponent norm_shamt = unsigned'(signed'(PRECISION_BITS + 2 + exponent_product_q)); normalized_exponent = 0; // subnormals encoded as 0 + // Fix exponent in case of a normal number accidentally being classified as subnormal due + // to LZA over-prediction (LZA could be 1 larger than actual LZC) + if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !sum_lower_zero) begin + normalized_exponent = 1; + end end // Addend-anchored case end else begin @@ -28502,18 +35786,77 @@ module fpnew_fma_multi #( // In case of overflow, the round and sticky bits are set for proper rounding assign round_sticky_bits = fmt_round_sticky_bits[dst_fmt_q2]; + // ---------------------- + // Normalization Pipeline + // ---------------------- + logic [0:NUM_NORM_REGS][SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] norm_pipe_abs_q; + logic [0:NUM_NORM_REGS] norm_pipe_sign_q; + logic [0:NUM_NORM_REGS][1:0] norm_pipe_round_sticky_q; + fpnew_pkg::roundmode_e [0:NUM_NORM_REGS] norm_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_NORM_REGS] norm_pipe_dst_fmt_q; + logic [0:NUM_NORM_REGS] norm_pipe_eff_sub_q; + logic [0:NUM_NORM_REGS] norm_pipe_of_before_round_q; + logic [0:NUM_NORM_REGS][2*PRECISION_BITS+2:0] norm_pipe_sum_sticky_q; + logic [0:NUM_NORM_REGS] norm_pipe_res_is_spec_q; + fp_t [0:NUM_NORM_REGS] norm_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_NORM_REGS] norm_pipe_spec_stat_q; + TagType [0:NUM_NORM_REGS] norm_pipe_tag_q; + logic [0:NUM_NORM_REGS] norm_pipe_mask_q; + AuxType [0:NUM_NORM_REGS] norm_pipe_aux_q; + logic [0:NUM_NORM_REGS] norm_pipe_valid_q; + logic [0:NUM_NORM_REGS] norm_pipe_ready; + + assign norm_pipe_abs_q[0] = pre_round_abs; + assign norm_pipe_sign_q[0] = pre_round_sign; + assign norm_pipe_round_sticky_q[0] = round_sticky_bits; + assign norm_pipe_rnd_mode_q[0] = rnd_mode_q; + assign norm_pipe_dst_fmt_q[0] = dst_fmt_q2; + assign norm_pipe_eff_sub_q[0] = effective_subtraction_q; + assign norm_pipe_of_before_round_q[0] = of_before_round; + assign norm_pipe_sum_sticky_q[0] = sum_sticky_bits; + assign norm_pipe_res_is_spec_q[0] = result_is_special_q; + assign norm_pipe_spec_res_q[0] = special_result_q; + assign norm_pipe_spec_stat_q[0] = special_status_q; + assign norm_pipe_tag_q[0] = mid_pipe_tag_q[NUM_SUM_REGS]; + assign norm_pipe_mask_q[0] = mid_pipe_mask_q[NUM_SUM_REGS]; + assign norm_pipe_aux_q[0] = mid_pipe_aux_q[NUM_SUM_REGS]; + assign norm_pipe_valid_q[0] = mid_pipe_valid_q[NUM_SUM_REGS]; + + assign mid_pipe_ready[NUM_SUM_REGS] = norm_pipe_ready[0]; + + for (genvar i = 0; i < NUM_NORM_REGS; i++) begin : gen_norm_pipeline + logic reg_ena; + assign norm_pipe_ready[i] = norm_pipe_ready[i+1] | ~norm_pipe_valid_q[i+1]; + `FFLARNC(norm_pipe_valid_q[i+1], norm_pipe_valid_q[i], norm_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + assign reg_ena = (norm_pipe_ready[i] & norm_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + NUM_SUM_REGS + i]; + `FFL(norm_pipe_abs_q[i+1], norm_pipe_abs_q[i], reg_ena, '0) + `FFL(norm_pipe_sign_q[i+1], norm_pipe_sign_q[i], reg_ena, '0) + `FFL(norm_pipe_round_sticky_q[i+1], norm_pipe_round_sticky_q[i], reg_ena, '0) + `FFL(norm_pipe_rnd_mode_q[i+1], norm_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(norm_pipe_dst_fmt_q[i+1], norm_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(norm_pipe_eff_sub_q[i+1], norm_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(norm_pipe_of_before_round_q[i+1], norm_pipe_of_before_round_q[i], reg_ena, '0) + `FFL(norm_pipe_sum_sticky_q[i+1], norm_pipe_sum_sticky_q[i], reg_ena, '0) + `FFL(norm_pipe_res_is_spec_q[i+1], norm_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(norm_pipe_spec_res_q[i+1], norm_pipe_spec_res_q[i], reg_ena, '0) + `FFL(norm_pipe_spec_stat_q[i+1], norm_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(norm_pipe_tag_q[i+1], norm_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(norm_pipe_mask_q[i+1], norm_pipe_mask_q[i], reg_ena, '0) + `FFL(norm_pipe_aux_q[i+1], norm_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Perform the rounding fpnew_rounding #( .AbsWidth ( SUPER_EXP_BITS + SUPER_MAN_BITS ) ) i_fpnew_rounding ( - .abs_value_i ( pre_round_abs ), - .sign_i ( pre_round_sign ), - .round_sticky_bits_i ( round_sticky_bits ), - .rnd_mode_i ( rnd_mode_q ), - .effective_subtraction_i ( effective_subtraction_q ), - .abs_rounded_o ( rounded_abs ), - .sign_o ( rounded_sign ), - .exact_zero_o ( result_zero ) + .abs_value_i ( norm_pipe_abs_q[NUM_NORM_REGS] ), + .sign_i ( norm_pipe_sign_q[NUM_NORM_REGS] ), + .round_sticky_bits_i ( norm_pipe_round_sticky_q[NUM_NORM_REGS] ), + .rnd_mode_i ( norm_pipe_rnd_mode_q[NUM_NORM_REGS] ), + .effective_subtraction_i ( norm_pipe_eff_sub_q[NUM_NORM_REGS] ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) ); logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result; @@ -28526,10 +35869,10 @@ module fpnew_fma_multi #( if (FpFmtConfig[fmt]) begin : active_format always_comb begin : post_process - // detect of / uf + // detect of / uf fmt_uf_after_round[fmt] = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal - || ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && - ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_i == fpnew_pkg::RNE) || (rnd_mode_i == fpnew_pkg::RMM))))); + || ((norm_pipe_abs_q[NUM_NORM_REGS][EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && + ((norm_pipe_round_sticky_q[NUM_NORM_REGS] != 2'b11) || (!norm_pipe_sum_sticky_q[NUM_NORM_REGS][MAN_BITS*2 + 4] && ((norm_pipe_rnd_mode_q[NUM_NORM_REGS] == fpnew_pkg::RNE) || (norm_pipe_rnd_mode_q[NUM_NORM_REGS] == fpnew_pkg::RMM))))); fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. // Assemble regular result, nan box short ones. @@ -28544,8 +35887,8 @@ module fpnew_fma_multi #( end // Classification after rounding select by destination format - assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; - assign of_after_round = fmt_of_after_round[dst_fmt_q2]; + assign uf_after_round = fmt_uf_after_round[norm_pipe_dst_fmt_q[NUM_NORM_REGS]]; + assign of_after_round = fmt_of_after_round[norm_pipe_dst_fmt_q[NUM_NORM_REGS]]; // ----------------- @@ -28555,20 +35898,20 @@ module fpnew_fma_multi #( fpnew_pkg::status_t regular_status; // Assemble regular result - assign regular_result = fmt_result[dst_fmt_q2]; + assign regular_result = fmt_result[norm_pipe_dst_fmt_q[NUM_NORM_REGS]]; assign regular_status.NV = 1'b0; // only valid cases are handled in regular path assign regular_status.DZ = 1'b0; // no divisions - assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.OF = norm_pipe_of_before_round_q[NUM_NORM_REGS] | of_after_round; // rounding can introduce overflow assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF - assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + assign regular_status.NX = (| norm_pipe_round_sticky_q[NUM_NORM_REGS]) | norm_pipe_of_before_round_q[NUM_NORM_REGS] | of_after_round; // Final results for output pipeline logic [WIDTH-1:0] result_d; fpnew_pkg::status_t status_d; // Select output depending on special case detection - assign result_d = result_is_special_q ? special_result_q : regular_result; - assign status_d = result_is_special_q ? special_status_q : regular_status; + assign result_d = norm_pipe_res_is_spec_q[NUM_NORM_REGS] ? norm_pipe_spec_res_q[NUM_NORM_REGS] : regular_result; + assign status_d = norm_pipe_res_is_spec_q[NUM_NORM_REGS] ? norm_pipe_spec_stat_q[NUM_NORM_REGS] : regular_status; // ---------------- // Output Pipeline @@ -28586,12 +35929,12 @@ module fpnew_fma_multi #( // Input stage: First element of pipeline is taken from inputs assign out_pipe_result_q[0] = result_d; assign out_pipe_status_q[0] = status_d; - assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; - assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; - assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; - assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; - // Input stage: Propagate pipeline ready signal to inside pipe - assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + assign out_pipe_tag_q[0] = norm_pipe_tag_q[NUM_NORM_REGS]; + assign out_pipe_mask_q[0] = norm_pipe_mask_q[NUM_NORM_REGS]; + assign out_pipe_aux_q[0] = norm_pipe_aux_q[NUM_NORM_REGS]; + assign out_pipe_valid_q[0] = norm_pipe_valid_q[NUM_NORM_REGS]; + // Input stage: Propagate pipeline ready signal to normalization pipe + assign norm_pipe_ready[NUM_NORM_REGS] = out_pipe_ready[0]; // Generate the register stages for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline // Internal register enable for this stage @@ -28621,11 +35964,29 @@ module fpnew_fma_multi #( assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; - assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, norm_pipe_valid_q, out_pipe_valid_q}); + + // Early valid_o signal. This is used for dispatching instructions for dual-issue processor. + if (NUM_OUT_REGS > 0) begin + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], + out_pipe_valid_q[NUM_OUT_REGS-1]}; + end else if (NUM_NORM_REGS > 0) begin + assign early_out_valid_o = |{norm_pipe_valid_q[NUM_NORM_REGS] & ~norm_pipe_ready[NUM_NORM_REGS], + norm_pipe_valid_q[NUM_NORM_REGS-1]}; + end else if (NUM_SUM_REGS > 0) begin + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_SUM_REGS] & ~mid_pipe_ready[NUM_SUM_REGS], + mid_pipe_valid_q[NUM_SUM_REGS-1]}; + end else if (NUM_INP_REGS > 0) begin + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], + inp_pipe_valid_q[NUM_INP_REGS-1]}; + end else begin + assign early_out_valid_o = 1'b0; + end + endmodule // ----- 8< ----- FILE "./fpnew_noncomp.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -28650,8 +36011,8 @@ module fpnew_noncomp #( parameter type TagType = logic, parameter type AuxType = logic, // Do not change - localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -28683,14 +36044,16 @@ module fpnew_noncomp #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); // ---------- // Constants // ---------- - localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); - localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + parameter int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + parameter int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); // Pipelines localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE) ? NumPipeRegs @@ -28888,10 +36251,12 @@ module fpnew_noncomp #( cmp_result = '0; // false cmp_status = '0; // no flags - // Signalling NaNs always compare as false and are illegal - if (signalling_nan) cmp_status.NV = 1'b1; // invalid operation + // Signalling NaNs always compare as false (except for "not equal" compares) and are illegal + if (signalling_nan) begin + cmp_status.NV = 1'b1; // invalid operation + cmp_result = inp_pipe_rnd_mode_q[NUM_INP_REGS] == fpnew_pkg::RDN && inp_pipe_op_mod_q[NUM_INP_REGS]; // Otherwise do comparisons - else begin + end else begin unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) fpnew_pkg::RNE: begin // Less than or equal if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid @@ -29043,10 +36408,22 @@ module fpnew_noncomp #( assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; assign busy_o = (| {inp_pipe_valid_q, out_pipe_valid_q}); + + // Early valid_o signal. This is used for dispatching instructions for dual-issue processor. + if (NUM_OUT_REGS > 0) begin + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], + out_pipe_valid_q[NUM_OUT_REGS-1]}; + end else if (NUM_INP_REGS > 0) begin + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], + inp_pipe_valid_q[NUM_INP_REGS-1]}; + end else begin + assign early_out_valid_o = 1'b0; + end + endmodule // ----- 8< ----- FILE "./fpnew_opgroup_block.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -29067,7 +36444,7 @@ module fpnew_opgroup_block #( // FPU configuration parameter int unsigned Width = 32, parameter logic EnableVectors = 1'b1, - parameter logic PulpDivsqrt = 1'b1, + parameter fpnew_pkg::divsqrt_unit_t DivSqrtSel = fpnew_pkg::THMULTI, parameter fpnew_pkg::fmt_logic_t FpFmtMask = '1, parameter fpnew_pkg::ifmt_logic_t IntFmtMask = '1, parameter fpnew_pkg::fmt_unsigned_t FmtPipeRegs = '{default: 0}, @@ -29076,10 +36453,10 @@ module fpnew_opgroup_block #( parameter type TagType = logic, parameter int unsigned TrueSIMDClass = 0, // Do not change - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, - localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), - localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtMask, EnableVectors), - localparam type MaskType = logic [NUM_LANES-1:0] + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + parameter int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + parameter int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtMask, EnableVectors), + parameter type MaskType = logic [NUM_LANES-1:0] ) ( input logic clk_i, input logic rst_ni, @@ -29108,7 +36485,8 @@ module fpnew_opgroup_block #( output logic out_valid_o, input logic out_ready_i, // Indication of valid data in flight - output logic busy_o + output logic busy_o, + output logic early_valid_o ); // ---------------- @@ -29123,6 +36501,7 @@ module fpnew_opgroup_block #( // Handshake signals for the slices logic [NUM_FORMATS-1:0] fmt_in_ready, fmt_out_valid, fmt_out_ready, fmt_busy; + logic [NUM_FORMATS-1:0] early_valid; output_t [NUM_FORMATS-1:0] fmt_outputs; // ----------- @@ -29141,10 +36520,11 @@ module fpnew_opgroup_block #( // Generate slice only if format enabled if (FpFmtMask[fmt] && (FmtUnitTypes[fmt] == fpnew_pkg::PARALLEL)) begin : active_format + localparam fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(fmt); logic in_valid; - assign in_valid = in_valid_i & (dst_fmt_i == fmt); // enable selected format + assign in_valid = in_valid_i & (dst_fmt_i == fpnew_pkg::fp_format_e'(fmt)); // enable selected format // Forward masks related to the right SIMD lane localparam int unsigned INTERNAL_LANES = fpnew_pkg::num_lanes(Width, fpnew_pkg::fp_format_e'(fmt), EnableVectors); @@ -29152,36 +36532,37 @@ module fpnew_opgroup_block #( always_comb for (int b = 0; b < INTERNAL_LANES; b++) mask_slice[b] = simd_mask_i[(NUM_LANES/INTERNAL_LANES)*b]; fpnew_opgroup_fmt_slice #( - .OpGroup ( OpGroup ), - .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), - .Width ( Width ), - .EnableVectors ( EnableVectors ), - .NumPipeRegs ( FmtPipeRegs[fmt] ), - .PipeConfig ( PipeConfig ), - .TagType ( TagType ), - .TrueSIMDClass ( TrueSIMDClass ) + .OpGroup ( OpGroup ), + .FpFormat ( FpFormat ), + .Width ( Width ), + .EnableVectors ( EnableVectors ), + .NumPipeRegs ( FmtPipeRegs[fmt] ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) ) i_fmt_slice ( .clk_i, .rst_ni, - .operands_i ( operands_i ), - .is_boxed_i ( is_boxed_i[fmt] ), + .operands_i ( operands_i ), + .is_boxed_i ( is_boxed_i[fmt] ), .rnd_mode_i, .op_i, .op_mod_i, .vectorial_op_i, .tag_i, - .simd_mask_i ( mask_slice ), - .in_valid_i ( in_valid ), - .in_ready_o ( fmt_in_ready[fmt] ), + .simd_mask_i ( mask_slice ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[fmt] ), .flush_i, - .result_o ( fmt_outputs[fmt].result ), - .status_o ( fmt_outputs[fmt].status ), - .extension_bit_o( fmt_outputs[fmt].ext_bit ), - .tag_o ( fmt_outputs[fmt].tag ), - .out_valid_o ( fmt_out_valid[fmt] ), - .out_ready_i ( fmt_out_ready[fmt] ), - .busy_o ( fmt_busy[fmt] ), - .reg_ena_i ( '0 ) + .result_o ( fmt_outputs[fmt].result ), + .status_o ( fmt_outputs[fmt].status ), + .extension_bit_o ( fmt_outputs[fmt].ext_bit ), + .tag_o ( fmt_outputs[fmt].tag ), + .out_valid_o ( fmt_out_valid[fmt] ), + .out_ready_i ( fmt_out_ready[fmt] ), + .busy_o ( fmt_busy[fmt] ), + .reg_ena_i ( '0 ), + .early_out_valid_o( early_valid[fmt] ) ); // If the format wants to use merged ops, tie off the dangling ones not used here end else if (FpFmtMask[fmt] && ANY_MERGED && !IS_FIRST_MERGED) begin : merged_unused @@ -29197,7 +36578,7 @@ module fpnew_opgroup_block #( assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); - + assign early_valid[fmt] = 1'b0; // Tie off disabled formats end else if (!FpFmtMask[fmt] || (FmtUnitTypes[fmt] == fpnew_pkg::DISABLED)) begin : disable_fmt assign fmt_in_ready[fmt] = 1'b0; // don't accept operations @@ -29208,6 +36589,7 @@ module fpnew_opgroup_block #( assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); + assign early_valid[fmt] = 1'b0; end end @@ -29229,7 +36611,7 @@ module fpnew_opgroup_block #( .FpFmtConfig ( FpFmtMask ), .IntFmtConfig ( IntFmtMask ), .EnableVectors ( EnableVectors ), - .PulpDivsqrt ( PulpDivsqrt ), + .DivSqrtSel ( DivSqrtSel ), .NumPipeRegs ( REG ), .PipeConfig ( PipeConfig ), .TagType ( TagType ) @@ -29246,18 +36628,19 @@ module fpnew_opgroup_block #( .int_fmt_i, .vectorial_op_i, .tag_i, - .simd_mask_i ( simd_mask_i ), - .in_valid_i ( in_valid ), - .in_ready_o ( fmt_in_ready[FMT] ), + .simd_mask_i ( simd_mask_i ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[FMT] ), .flush_i, - .result_o ( fmt_outputs[FMT].result ), - .status_o ( fmt_outputs[FMT].status ), - .extension_bit_o ( fmt_outputs[FMT].ext_bit ), - .tag_o ( fmt_outputs[FMT].tag ), - .out_valid_o ( fmt_out_valid[FMT] ), - .out_ready_i ( fmt_out_ready[FMT] ), - .busy_o ( fmt_busy[FMT] ), - .reg_ena_i ( '0 ) + .result_o ( fmt_outputs[FMT].result ), + .status_o ( fmt_outputs[FMT].status ), + .extension_bit_o ( fmt_outputs[FMT].ext_bit ), + .tag_o ( fmt_outputs[FMT].tag ), + .out_valid_o ( fmt_out_valid[FMT] ), + .out_ready_i ( fmt_out_ready[FMT] ), + .busy_o ( fmt_busy[FMT] ), + .reg_ena_i ( '0 ), + .early_out_valid_o( early_valid[FMT] ) ); end @@ -29292,12 +36675,14 @@ module fpnew_opgroup_block #( assign extension_bit_o = arbiter_output.ext_bit; assign tag_o = arbiter_output.tag; + assign early_valid_o = |early_valid; + assign busy_o = (| fmt_busy); endmodule // ----- 8< ----- FILE "./fpnew_opgroup_fmt_slice.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -29325,10 +36710,10 @@ module fpnew_opgroup_fmt_slice #( parameter type TagType = logic, parameter int unsigned TrueSIMDClass = 0, // Do not change - localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), - localparam int unsigned NUM_LANES = fpnew_pkg::num_lanes(Width, FpFormat, EnableVectors), - localparam type MaskType = logic [NUM_LANES-1:0], - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + parameter int unsigned NUM_LANES = fpnew_pkg::num_lanes(Width, FpFormat, EnableVectors), + parameter type MaskType = logic [NUM_LANES-1:0], + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -29356,7 +36741,9 @@ module fpnew_opgroup_fmt_slice #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(FpFormat); @@ -29375,6 +36762,7 @@ module fpnew_opgroup_fmt_slice #( TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used logic [NUM_LANES-1:0] lane_masks; logic [NUM_LANES-1:0] lane_vectorial, lane_busy, lane_is_class; // dito + logic [NUM_LANES-1:0] lane_early_out_valid; logic result_is_vector, result_is_class; @@ -29418,27 +36806,28 @@ module fpnew_opgroup_fmt_slice #( ) i_fma ( .clk_i, .rst_ni, - .operands_i ( local_operands ), - .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + .operands_i ( local_operands ), + .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), .rnd_mode_i, .op_i, .op_mod_i, .tag_i, - .mask_i ( simd_mask_i[lane] ), - .aux_i ( vectorial_op ), // Remember whether operation was vectorial - .in_valid_i ( in_valid ), - .in_ready_o ( lane_in_ready[lane] ), + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), .flush_i, - .result_o ( op_result ), - .status_o ( op_status ), - .extension_bit_o ( lane_ext_bit[lane] ), - .tag_o ( lane_tags[lane] ), - .mask_o ( lane_masks[lane] ), - .aux_o ( lane_vectorial[lane] ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( lane_busy[lane] ), - .reg_ena_i + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) ); assign lane_is_class[lane] = 1'b0; assign lane_class_mask[lane] = fpnew_pkg::NEGINF; @@ -29489,23 +36878,24 @@ module fpnew_opgroup_fmt_slice #( .op_i, .op_mod_i, .tag_i, - .mask_i ( simd_mask_i[lane] ), - .aux_i ( vectorial_op ), // Remember whether operation was vectorial - .in_valid_i ( in_valid ), - .in_ready_o ( lane_in_ready[lane] ), + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), .flush_i, - .result_o ( op_result ), - .status_o ( op_status ), - .extension_bit_o ( lane_ext_bit[lane] ), - .class_mask_o ( lane_class_mask[lane] ), - .is_class_o ( lane_is_class[lane] ), - .tag_o ( lane_tags[lane] ), - .mask_o ( lane_masks[lane] ), - .aux_o ( lane_vectorial[lane] ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( lane_busy[lane] ), - .reg_ena_i + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .class_mask_o ( lane_class_mask[lane] ), + .is_class_o ( lane_is_class[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o ( lane_early_out_valid[lane] ) ); end // ADD OTHER OPTIONS HERE @@ -29585,6 +36975,7 @@ module fpnew_opgroup_fmt_slice #( assign tag_o = lane_tags[0]; // upper lanes unused assign busy_o = (| lane_busy); assign out_valid_o = lane_out_valid[0]; // upper lanes unused + assign early_out_valid_o = |lane_early_out_valid; // Collapse the lane status @@ -29599,7 +36990,7 @@ module fpnew_opgroup_fmt_slice #( endmodule // ----- 8< ----- FILE "./fpnew_opgroup_multifmt_slice.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -29618,23 +37009,23 @@ endmodule module fpnew_opgroup_multifmt_slice #( - parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV, - parameter int unsigned Width = 64, + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV, + parameter int unsigned Width = 64, // FPU configuration - parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, - parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, - parameter logic EnableVectors = 1'b1, - parameter logic PulpDivsqrt = 1'b1, - parameter int unsigned NumPipeRegs = 0, - parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, - parameter logic ExtRegEna = 1'b0, - parameter type TagType = logic, + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, + parameter logic EnableVectors = 1'b1, + parameter fpnew_pkg::divsqrt_unit_t DivSqrtSel = fpnew_pkg::THMULTI, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter logic ExtRegEna = 1'b0, + parameter type TagType = logic, // Do not change - localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, - localparam int unsigned NUM_SIMD_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors), - localparam type MaskType = logic [NUM_SIMD_LANES-1:0], - localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs + parameter int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + parameter int unsigned NUM_SIMD_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors), + parameter type MaskType = logic [NUM_SIMD_LANES-1:0], + parameter int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs ) ( input logic clk_i, input logic rst_ni, @@ -29665,19 +37056,25 @@ module fpnew_opgroup_multifmt_slice #( // Indication of valid data in flight output logic busy_o, // External register enable override - input logic [ExtRegEnaWidth-1:0] reg_ena_i + input logic [ExtRegEnaWidth-1:0] reg_ena_i, + // Early valid for external structural hazard generation + output logic early_out_valid_o ); - if ((OpGroup == fpnew_pkg::DIVSQRT) && !PulpDivsqrt && - !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:NUM_FORMATS-1] == '0))) begin - $fatal(1, "T-Head-based DivSqrt unit supported only in FP32-only configurations. \ -Set PulpDivsqrt to 1 not to use the PULP DivSqrt unit \ -or set Features.FpFmtMask to support only FP32"); + if ((OpGroup == fpnew_pkg::DIVSQRT)) begin + if ((DivSqrtSel == fpnew_pkg::TH32) && !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:NUM_FORMATS-1] == '0))) begin + $fatal(1, "T-Head-based DivSqrt unit supported only in FP32-only configurations. \ +Set DivSqrtSel = THMULTI or DivSqrtSel = PULP to use a multi-format divider"); + end else if ((DivSqrtSel == fpnew_pkg::THMULTI) && (FpFmtConfig[3] == 1'b1)) begin + $warning("The DivSqrt unit of C910 (instantiated by DivSqrtSel = THMULTI) does not support \ +FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8."); + end end localparam int unsigned MAX_FP_WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig); localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig); - localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, 1'b1); + localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors); + localparam int unsigned NUM_DIVSQRT_LANES = fpnew_pkg::num_divsqrt_lanes(Width, FpFmtConfig, EnableVectors, DivSqrtSel); localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS; // We will send the format information along with the data localparam int unsigned FMT_BITS = @@ -29706,6 +37103,8 @@ or set Features.FpFmtMask to support only FP32"); logic [NUM_LANES-1:0] lane_masks; logic [NUM_LANES-1:0][AUX_BITS-1:0] lane_aux; // only the first one is actually used logic [NUM_LANES-1:0] lane_busy; // dito + logic [NUM_LANES-1:0] lane_early_out_valid; + logic result_is_vector; logic [FMT_BITS-1:0] result_fmt; @@ -29781,7 +37180,7 @@ or set Features.FpFmtMask to support only FP32"); logic [LANE_WIDTH-1:0] local_result; // lane-local results // Generate instances only if needed, lane 0 always generated - if ((lane == 0) || EnableVectors) begin : active_lane + if ((lane == 0) || (EnableVectors & (!(OpGroup == fpnew_pkg::DIVSQRT && (lane >= NUM_DIVSQRT_LANES))))) begin : active_lane logic in_valid, out_valid, out_ready; // lane-local handshake logic [NUM_OPERANDS-1:0][LANE_WIDTH-1:0] local_operands; // lane-local oprands @@ -29794,7 +37193,7 @@ or set Features.FpFmtMask to support only FP32"); always_comb begin : prepare_input for (int unsigned i = 0; i < NUM_OPERANDS; i++) begin if (i == 2) begin - local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(dst_fmt_i); + local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(op_i == fpnew_pkg::ADDS ? src_fmt_i : dst_fmt_i); end else begin local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(src_fmt_i); end @@ -29831,33 +37230,35 @@ or set Features.FpFmtMask to support only FP32"); ) i_fpnew_fma_multi ( .clk_i, .rst_ni, - .operands_i ( local_operands ), + .operands_i ( local_operands ), .is_boxed_i, .rnd_mode_i, .op_i, .op_mod_i, .src_fmt_i, + .src2_fmt_i ( op_i == fpnew_pkg::ADDS ? src_fmt_i : dst_fmt_i ), .dst_fmt_i, .tag_i, - .mask_i ( simd_mask_i[lane] ), - .aux_i ( aux_data ), - .in_valid_i ( in_valid ), - .in_ready_o ( lane_in_ready[lane] ), + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), .flush_i, - .result_o ( op_result ), - .status_o ( op_status ), - .extension_bit_o ( lane_ext_bit[lane] ), - .tag_o ( lane_tags[lane] ), - .mask_o ( lane_masks[lane] ), - .aux_o ( lane_aux[lane] ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( lane_busy[lane] ), - .reg_ena_i + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) ); end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance - if (!PulpDivsqrt && LANE_FORMATS[0] && (LANE_FORMATS[1:fpnew_pkg::NUM_FP_FORMATS-1] == '0)) begin + if (DivSqrtSel == fpnew_pkg::TH32 && LANE_FORMATS[0] && (LANE_FORMATS[1:fpnew_pkg::NUM_FP_FORMATS-1] == '0)) begin : gen_th32_e906_divsqrt // The T-head-based DivSqrt unit is supported only in FP32-only configurations fpnew_divsqrt_th_32 #( .NumPipeRegs ( NumPipeRegs ), @@ -29867,28 +37268,67 @@ or set Features.FpFmtMask to support only FP32"); ) i_fpnew_divsqrt_multi_th ( .clk_i, .rst_ni, - .operands_i ( local_operands[1:0] ), // 2 operands - .is_boxed_i ( is_boxed_2op ), // 2 operands + .operands_i ( local_operands[1:0] ), // 2 operands + .is_boxed_i ( is_boxed_2op ), // 2 operands + .rnd_mode_i, + .op_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) + ); + end else if(DivSqrtSel == fpnew_pkg::THMULTI) begin : gen_thmulti_c910_divsqrt + fpnew_divsqrt_th_64_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_divsqrt_th_64_c910 ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[1:0] ), // 2 operands + .is_boxed_i ( is_boxed_2op ), // 2 operands .rnd_mode_i, .op_i, + .dst_fmt_i, .tag_i, - .mask_i ( simd_mask_i[lane] ), - .aux_i ( aux_data ), - .in_valid_i ( in_valid ), - .in_ready_o ( lane_in_ready[lane] ), + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .vectorial_op_i ( vectorial_op ), // synchronize only vectorial operations + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .divsqrt_done_o ( divsqrt_done[lane] ), + .simd_synch_done_i( simd_synch_done ), + .divsqrt_ready_o ( divsqrt_ready[lane] ), + .simd_synch_rdy_i ( simd_synch_rdy ), .flush_i, - .result_o ( op_result ), - .status_o ( op_status ), - .extension_bit_o ( lane_ext_bit[lane] ), - .tag_o ( lane_tags[lane] ), - .mask_o ( lane_masks[lane] ), - .aux_o ( lane_aux[lane] ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( lane_busy[lane] ), - .reg_ena_i + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) ); - end else begin + end else begin : gen_pulp_divsqrt fpnew_divsqrt_multi #( .FpFmtConfig ( LANE_FORMATS ), .NumPipeRegs ( NumPipeRegs ), @@ -29923,9 +37363,11 @@ or set Features.FpFmtMask to support only FP32"); .out_valid_o ( out_valid ), .out_ready_i ( out_ready ), .busy_o ( lane_busy[lane] ), - .reg_ena_i + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) ); end + end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance end else if (OpGroup == fpnew_pkg::CONV) begin : lane_instance @@ -29948,21 +37390,22 @@ or set Features.FpFmtMask to support only FP32"); .dst_fmt_i, .int_fmt_i, .tag_i, - .mask_i ( simd_mask_i[lane] ), - .aux_i ( aux_data ), - .in_valid_i ( in_valid ), - .in_ready_o ( lane_in_ready[lane] ), + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), .flush_i, - .result_o ( op_result ), - .status_o ( op_status ), - .extension_bit_o ( lane_ext_bit[lane] ), - .tag_o ( lane_tags[lane] ), - .mask_o ( lane_masks[lane] ), - .aux_o ( lane_aux[lane] ), - .out_valid_o ( out_valid ), - .out_ready_i ( out_ready ), - .busy_o ( lane_busy[lane] ), - .reg_ena_i + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i, + .early_out_valid_o( lane_early_out_valid[lane] ) ); end // ADD OTHER OPTIONS HERE @@ -29976,6 +37419,7 @@ or set Features.FpFmtMask to support only FP32"); // Otherwise generate constant sign-extension end else begin : inactive_lane + assign lane_early_out_valid[lane] = 1'b0; // unused lane assign lane_out_valid[lane] = 1'b0; // unused lane assign lane_in_ready[lane] = 1'b0; // unused lane assign lane_aux[lane] = 1'b0; // unused lane @@ -30086,12 +37530,12 @@ or set Features.FpFmtMask to support only FP32"); assign conv_target_q = '0; end - if (PulpDivsqrt) begin + if ((DivSqrtSel != fpnew_pkg::TH32) && !ExtRegEna) begin // Synch lanes if there is more than one - assign simd_synch_rdy = EnableVectors ? &divsqrt_ready : divsqrt_ready[0]; - assign simd_synch_done = EnableVectors ? &divsqrt_done : divsqrt_done[0]; + assign simd_synch_rdy = EnableVectors ? &divsqrt_ready[NUM_DIVSQRT_LANES-1:0] : divsqrt_ready[0]; + assign simd_synch_done = EnableVectors ? &divsqrt_done[NUM_DIVSQRT_LANES-1:0] : divsqrt_done[0]; end else begin - // Unused (alternative divider only supported for scalar FP32 divsqrt) + // Unused (TH32 divider only supported for scalar FP32 divsqrt) assign simd_synch_rdy = '0; assign simd_synch_done = '0; end @@ -30108,6 +37552,7 @@ or set Features.FpFmtMask to support only FP32"); assign extension_bit_o = lane_ext_bit[0]; // don't care about upper ones assign tag_o = lane_tags[0]; // don't care about upper ones assign busy_o = (| lane_busy); + assign early_out_valid_o = |lane_early_out_valid; assign out_valid_o = lane_out_valid[0]; // don't care about upper ones @@ -30124,7 +37569,7 @@ or set Features.FpFmtMask to support only FP32"); endmodule // ----- 8< ----- FILE "./fpnew_rounding.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -30203,7 +37648,7 @@ module fpnew_rounding #( endmodule // ----- 8< ----- FILE "./fpnew_top.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 // Copyright 2019 ETH Zurich and University of Bologna. // // Copyright and related rights are licensed under the Solderpad Hardware @@ -30223,16 +37668,16 @@ module fpnew_top #( // FPU configuration parameter fpnew_pkg::fpu_features_t Features = fpnew_pkg::RV64D_Xsflt, parameter fpnew_pkg::fpu_implementation_t Implementation = fpnew_pkg::DEFAULT_NOREGS, - // PulpDivSqrt = 0 enables T-head-based DivSqrt unit. Supported only for FP32-only instances of Fpnew - parameter logic PulpDivsqrt = 1'b1, + // DivSqrtSel chooses among PULP, TH32, or THMULTI (see documentation and fpnew_pkg.sv for further details) + parameter fpnew_pkg::divsqrt_unit_t DivSqrtSel = fpnew_pkg::THMULTI, parameter type TagType = logic, parameter int unsigned TrueSIMDClass = 0, parameter int unsigned EnableSIMDMask = 0, // Do not change - localparam int unsigned NumLanes = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors), - localparam type MaskType = logic [NumLanes-1:0], - localparam int unsigned WIDTH = Features.Width, - localparam int unsigned NUM_OPERANDS = 3 + parameter int unsigned NumLanes = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors), + parameter type MaskType = logic [NumLanes-1:0], + parameter int unsigned WIDTH = Features.Width, + parameter int unsigned NUM_OPERANDS = 3 ) ( input logic clk_i, input logic rst_ni, @@ -30259,11 +37704,12 @@ module fpnew_top #( output logic out_valid_o, input logic out_ready_i, // Indication of valid data in flight - output logic busy_o + output logic busy_o, + output logic early_valid_o ); localparam int unsigned NUM_OPGROUPS = fpnew_pkg::NUM_OPGROUPS; - localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS; + parameter int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS; // ---------------- // Type Definition @@ -30276,6 +37722,7 @@ module fpnew_top #( // Handshake signals for the blocks logic [NUM_OPGROUPS-1:0] opgrp_in_ready, opgrp_out_valid, opgrp_out_ready, opgrp_ext, opgrp_busy; + logic [NUM_OPGROUPS-1:0] opgrp_early_valid; output_t [NUM_OPGROUPS-1:0] opgrp_outputs; logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed; @@ -30309,6 +37756,13 @@ module fpnew_top #( // ------------------------- for (genvar opgrp = 0; opgrp < int'(NUM_OPGROUPS); opgrp++) begin : gen_operation_groups localparam int unsigned NUM_OPS = fpnew_pkg::num_operands(fpnew_pkg::opgroup_e'(opgrp)); + localparam fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::opgroup_e'(opgrp); + localparam logic EnableVectors = Features.EnableVectors; + localparam fpnew_pkg::fmt_logic_t FpFmtMask = Features.FpFmtMask; + localparam fpnew_pkg::ifmt_logic_t IntFmtMask = Features.IntFmtMask; + localparam fpnew_pkg::fmt_unsigned_t FmtPipeRegs = Implementation.PipeRegs[opgrp]; + localparam fpnew_pkg::fmt_unit_types_t FmtUnitTypes = Implementation.UnitTypes[opgrp]; + localparam fpnew_pkg::pipe_config_t PipeConfig = Implementation.PipeConfig; logic in_valid; logic [NUM_FORMATS-1:0][NUM_OPS-1:0] input_boxed; @@ -30322,17 +37776,17 @@ module fpnew_top #( end fpnew_opgroup_block #( - .OpGroup ( fpnew_pkg::opgroup_e'(opgrp) ), - .Width ( WIDTH ), - .EnableVectors ( Features.EnableVectors ), - .PulpDivsqrt ( PulpDivsqrt ), - .FpFmtMask ( Features.FpFmtMask ), - .IntFmtMask ( Features.IntFmtMask ), - .FmtPipeRegs ( Implementation.PipeRegs[opgrp] ), - .FmtUnitTypes ( Implementation.UnitTypes[opgrp] ), - .PipeConfig ( Implementation.PipeConfig ), - .TagType ( TagType ), - .TrueSIMDClass ( TrueSIMDClass ) + .OpGroup ( OpGroup ), + .Width ( WIDTH ), + .EnableVectors ( EnableVectors ), + .DivSqrtSel ( DivSqrtSel ), + .FpFmtMask ( FpFmtMask ), + .IntFmtMask ( IntFmtMask ), + .FmtPipeRegs ( FmtPipeRegs ), + .FmtUnitTypes ( FmtUnitTypes ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) ) i_opgroup_block ( .clk_i, .rst_ni, @@ -30356,7 +37810,8 @@ module fpnew_top #( .tag_o ( opgrp_outputs[opgrp].tag ), .out_valid_o ( opgrp_out_valid[opgrp] ), .out_ready_i ( opgrp_out_ready[opgrp] ), - .busy_o ( opgrp_busy[opgrp] ) + .busy_o ( opgrp_busy[opgrp] ), + .early_valid_o ( opgrp_early_valid[opgrp] ) ); end @@ -30389,12 +37844,14 @@ module fpnew_top #( assign status_o = arbiter_output.status; assign tag_o = arbiter_output.tag; + assign early_valid_o = |opgrp_early_valid; assign busy_o = (| opgrp_busy); endmodule // ----- 8< ----- FILE "./FloatCoreWrapper.sv" ----- 8< ----- -// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Generated by CIRCT firtool-1.133.0 + module FloatCoreWrapper( input logic clk_i, input logic rst_ni, @@ -30406,19 +37863,43 @@ module FloatCoreWrapper( input logic[4-1:0] op_i, input logic op_mod_i, input logic[2:0] rnd_mode_i, + input logic[2:0] src_fmt_i, + input logic[2:0] dst_fmt_i, + input logic[1:0] int_fmt_i, input logic flush_i, output logic out_valid_o, input logic out_ready_i, output logic[32-1:0] result_o, - output logic[4:0] status_o, - output logic busy_o); + output logic status_o_0, + output logic status_o_1, + output logic status_o_2, + output logic status_o_3, + output logic status_o_4, + output logic busy_o, + output logic early_valid_o +); logic [3-1:0][32-1:0] operands_i; assign operands_i[0] = operands_i_0; assign operands_i[1] = operands_i_1; assign operands_i[2] = operands_i_2; + fpnew_pkg::status_t status_o_pkg; + assign status_o_0 = status_o_pkg[0]; + assign status_o_1 = status_o_pkg[1]; + assign status_o_2 = status_o_pkg[2]; + assign status_o_3 = status_o_pkg[3]; + assign status_o_4 = status_o_pkg[4]; + // 4-stage pipeline breaks the 32-bit mantissa multiply from the LZA/normalization stage. + // 5 stages are supported for ultra-high-frequency (1.0 GHz) timing closure. + // Note for Physical Design: If 3-cycle architectural latency is preferred, synthesis + // register retiming ('set_optimize_registers true') on the 3-stage core is an option. +`ifdef FPU_PIPEREGS + localparam int unsigned FPU_PIPE_REGS = `FPU_PIPEREGS; +`else + localparam int unsigned FPU_PIPE_REGS = 4; +`endif localparam fpnew_pkg::fpu_implementation_t impl = '{ - PipeRegs: '{default: 'd3}, + PipeRegs: '{default: FPU_PIPE_REGS}, UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, // ADDMUL '{default: fpnew_pkg::MERGED}, // DIVSQRT '{default: fpnew_pkg::PARALLEL}, // NONCOMP @@ -30426,9 +37907,15 @@ module FloatCoreWrapper( PipeConfig: fpnew_pkg::DISTRIBUTED }; fpnew_top#( - .Features(fpnew_pkg::RV32F), + .Features(fpnew_pkg::fpu_features_t'{ + Width: 32, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10001, + IntFmtMask: 4'b0010 +}), .Implementation(impl), - .PulpDivsqrt(0) + .DivSqrtSel(fpnew_pkg::THMULTI) ) core( .clk_i(clk_i), .rst_ni(rst_ni), @@ -30436,25 +37923,25 @@ module FloatCoreWrapper( .rnd_mode_i(fpnew_pkg::roundmode_e'(rnd_mode_i)), .op_i(fpnew_pkg::operation_e'(op_i)), .op_mod_i(op_mod_i), - .src_fmt_i(fpnew_pkg::FP32), - .dst_fmt_i(fpnew_pkg::FP32), - .int_fmt_i(fpnew_pkg::INT32), + .src_fmt_i(fpnew_pkg::fp_format_e'(src_fmt_i)), + .dst_fmt_i(fpnew_pkg::fp_format_e'(dst_fmt_i)), + .int_fmt_i(fpnew_pkg::int_format_e'(int_fmt_i)), .vectorial_op_i(1'b0), .tag_i(1'b0), .simd_mask_i(1'b0), .in_valid_i(in_valid_i), .flush_i(flush_i), .out_ready_i(out_ready_i), - .in_ready_o(in_ready_o), .result_o(result_o), - .status_o(status_o), + .status_o(status_o_pkg), .tag_o(), .out_valid_o(out_valid_o), - .busy_o(busy_o) + .busy_o(busy_o), + .early_valid_o(early_valid_o) ); endmodule -// ----- 8< ----- FILE "./Sram_512x128.v" ----- 8< ----- +// ----- 8< ----- FILE "./Sram.v" ----- 8< ----- // Copyright 2024 Google LLC // @@ -30470,159 +37957,338 @@ endmodule // See the License for the specific language governing permissions and // limitations under the License. -module Sram_512x128( - input clock, - input enable, - input write, - input [8:0] addr, - input [127:0] wdata, - input [15:0] wmask, - output [127:0] rdata +module Sram #( + parameter NUM_ENTRIES = 128, + parameter GLOBAL_BASE_ADDR = 0 +) ( + input clock, + input enable, + input write, + input [$clog2(NUM_ENTRIES)-1:0] addr, + input [ 127:0] wdata, + input [ 15:0] wmask, + output [ 127:0] rdata, + output rvalid ); -/////////////////////////// -///// SRAM Selection ////// -/////////////////////////// -`ifdef USE_ASAP7 -/////////////////////////// -//////// ASAP7 SRAM //////// -/////////////////////////// - wire [127:0] nwmask; - genvar i; - generate - for (i = 0; i < 16; i++) begin - assign nwmask[8*i +: 8] = {8{wmask[i]}}; - end - endgenerate - - fakeram_512x128 u_asap7_sram ( - .rd_out(rdata), - .addr_in(addr), - .wd_in(wdata), - .we_in(write), - .ce_in(enable), - .clk(clock) + /////////////////////////// + ///// SRAM Selection ////// + /////////////////////////// + +`ifdef USE_TSMC12FFC + /////////////////////////// + ///// TSMC12FFC SRAM ////// + /////////////////////////// + wire [127:0] nwmask; + genvar i_wmask; + generate + for (i_wmask = 0; i_wmask < 16; i_wmask = i_wmask + 1) begin : gen_wmask + assign nwmask[8*i_wmask+:8] = {8{~wmask[i_wmask]}}; + end + endgenerate + + // Note on RTSEL/WTSEL: Different macro sizes require different timing control settings. + // The simulation models check these pins and may error out if they don't match recommended values. + // For synthesized netlist simulation (GLS), the ifdef's area already evaluated and cannot be changed + // Use +define+TSMC_NO_TESTPINS_DEFAULT_VALUE_CHECK in VCS, to skip checks in simulation + // RTSEL and WTSEL for synthesis may be required for tuning + if (NUM_ENTRIES == 2048) begin + TS1N12FFCLLMBLVTD2048X128M4SWBSHO u_sram ( + .BIST(1'b0), + .SLP(1'b0), + .DSLP(1'b0), + .SD(1'b0), + .CLK(clock), + .CEB(~enable), + .WEB(~write), + .A(addr), + .D(wdata), + .BWEB(nwmask), + .CEBM(1'b0), + .WEBM(1'b0), + .AM(11'b0), + .DM(128'b0), + .BWEBM({128{1'b1}}), + .Q(rdata), + .PUDELAY(), +`ifndef SIMULATION + .RTSEL(2'b0), + .WTSEL(2'b0) +`else + .RTSEL(2'b1), + .WTSEL(2'b1) +`endif ); + end else if (NUM_ENTRIES == 512) begin + TS1N12FFCLLSBLVTD512X128M4SWBSHO u_sram ( + .BIST(1'b0), + .SLP(1'b0), + .DSLP(1'b0), + .SD(1'b0), + .CLK(clock), + .CEB(~enable), + .WEB(~write), + .A(addr), + .D(wdata), + .BWEB(nwmask), + .CEBM(1'b0), + .WEBM(1'b0), + .AM(9'b0), + .DM(128'b0), + .BWEBM({128{1'b1}}), + .Q(rdata), + .PUDELAY(), +`ifndef SIMULATION + .RTSEL(2'b0), + .WTSEL(2'b0) `else -/////////////////////////// -////// Generic SRAM /////// -/////////////////////////// - reg [127:0] mem [0:511]; - reg [8:0] raddr; - - assign rdata = mem[raddr]; - -`ifndef SYNTHESIS - task randomMemoryAll; - for (int i = 0; i < 128; i++) begin - for (int j = 0; j < 512; j++) begin - mem[i][j] = $random; + .RTSEL(2'b1), + .WTSEL(2'b0) +`endif + ); + end else begin + initial begin + $error("Unsupported SRAM size for TSMC12FFC: %d", NUM_ENTRIES); end end - endtask - initial begin - randomMemoryAll; + reg rvalid_reg; + always @(posedge clock) rvalid_reg <= enable; + assign rvalid = rvalid_reg; + +`elsif USE_GF12LPP + /////////////////////////// + //////// GF12LPP SRAM //////// + /////////////////////////// + // MEM_TCM2048 and MEM_TCM512 macros must be defined at compile/synthesis time + wire [127:0] nwmask; + genvar i_wmask; + generate + for (i_wmask = 0; i_wmask < 16; i_wmask = i_wmask + 1) begin : gen_wmask + assign nwmask[8*i_wmask+:8] = {8{~wmask[i_wmask]}}; + end + endgenerate + + if (NUM_ENTRIES == 2048) begin + `MEM_TCM2048 u_sram_lower ( + .Q(rdata[63:0]), + .A(addr), + .D(wdata[63:0]), + .WEN(nwmask[63:0]), + .GWEN(~write), + .CEN(~enable), + .CLK(clock), + .STOV(1'b0), + .EMA(3'b0), + .EMAW(2'b0), + .EMAS(1'b0), + .RET1N(1'b1), + .WABL(1'b0), + .WABLM(2'b0) + ); + `MEM_TCM2048 u_sram_upper ( + .Q(rdata[127:64]), + .A(addr), + .D(wdata[127:64]), + .WEN(nwmask[127:64]), + .GWEN(~write), + .CEN(~enable), + .CLK(clock), + .STOV(1'b0), + .EMA(3'b0), + .EMAW(2'b0), + .EMAS(1'b0), + .RET1N(1'b1), + .WABL(1'b0), + .WABLM(2'b0) + ); + end else if (NUM_ENTRIES == 512) begin + `MEM_TCM512 u_sram ( + .Q(rdata), + .A(addr), + .D(wdata), + .WEN(nwmask), + .GWEN(~write), + .CEN(~enable), + .CLK(clock), + .STOV(1'b0), + .EMA(3'b0), + .EMAW(2'b0), + .EMAS(1'b0), + .RET1N(1'b1), + .WABL(1'b0), + .WABLM(2'b0) + ); + end else begin + initial begin + $error("Unsupported SRAM size for GF12LPP: %d", NUM_ENTRIES); + end end -`endif - always @(posedge clock) begin - for (int i = 0; i < 16; i++) begin - if (enable & write & wmask[i]) begin - mem[addr][i*8 +: 8] <= wdata[8*i +: 8]; - end + reg rvalid_reg; + always @(posedge clock) rvalid_reg <= enable; + assign rvalid = rvalid_reg; + +`elsif USE_GF22 + /////////////////////////// + //////// GF22 SRAM //////// + /////////////////////////// + wire [127:0] nwmask; + genvar i_wmask; + generate + for (i_wmask = 0; i_wmask < 16; i_wmask = i_wmask + 1) begin : gen_wmask + assign nwmask[8*i_wmask+:8] = {8{wmask[i_wmask]}}; end - - if (enable & ~write) begin - raddr <= addr; + endgenerate + + if (NUM_ENTRIES == 2048) begin + sasdulssd8LOW1p2048x128m4b2w0c0p0d0l0rm3sdrw01 u_sram ( + .Q(rdata), + .ADR(addr), + .D(wdata), + .WEM(nwmask), + .WE(write), + .ME(enable), + .CLK(clock), + .TEST1(1'b0), + .TEST_RNM(1'b0), + .RME(1'b0), + .RM(4'b0), + .WA(2'b0), + .WPULSE(3'b0), + .LS(1'b0), + .BC0(1'b0), + .BC1(1'b0), + .BC2(1'b0) + ); + end else if (NUM_ENTRIES == 512) begin + sasdulssd8LOW1p512x128m4b1w0c0p0d0l0rm3sdrw01 u_sram ( + .Q(rdata), + .ADR(addr), + .D(wdata), + .WEM(nwmask), + .WE(write), + .ME(enable), + .CLK(clock), + .TEST1(1'b0), + .TEST_RNM(1'b0), + .RME(1'b0), + .RM(4'b0), + .WA(2'b0), + .WPULSE(3'b0), + .LS(1'b0), + .BC0(1'b0), + .BC1(1'b0), + .BC2(1'b0) + ); + end else begin + initial begin + $error("Unsupported SRAM size for GF22: %d", NUM_ENTRIES); end end -`endif -endmodule -// ----- 8< ----- FILE "./Sram_2048x128.v" ----- 8< ----- - -// Copyright 2024 Google LLC -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. + reg rvalid_reg; + always @(posedge clock) rvalid_reg <= enable; + assign rvalid = rvalid_reg; -module Sram_2048x128( - input clock, - input enable, - input write, - input [10:0] addr, - input [127:0] wdata, - input [15:0] wmask, - output [127:0] rdata -); -/////////////////////////// -///// SRAM Selection ////// -/////////////////////////// -`ifdef USE_ASAP7 -/////////////////////////// -//////// ASAP7 SRAM //////// -/////////////////////////// - wire [127:0] nwmask; - genvar i; - generate - for (i = 0; i < 16; i++) begin - assign nwmask[8*i +: 8] = {8{wmask[i]}}; - end - endgenerate - - fakeram_2048x128 u_asap7_sram ( - .rd_out(rdata), - .addr_in(addr), - .wd_in(wdata), - .we_in(write), - .ce_in(enable), - .clk(clock) - ); `else -/////////////////////////// -////// Generic SRAM /////// -/////////////////////////// - reg [127:0] mem [0:2047]; - reg [10:0] raddr; + /////////////////////////// + ////// Generic SRAM /////// + /////////////////////////// + localparam SRAM_WIDTH_BYTES = 16; + localparam ADDR_WIDTH = $clog2(NUM_ENTRIES); + + reg rvalid_reg; + always @(posedge clock) rvalid_reg <= enable; + assign rvalid = rvalid_reg; + +`ifdef SYNTHESIS + (* ram_style = "ultra" *) + bit [127:0] mem[0:NUM_ENTRIES-1]; + reg [ADDR_WIDTH-1:0] raddr; assign rdata = mem[raddr]; -`ifndef SYNTHESIS - task randomMemoryAll; - for (int i = 0; i < 128; i++) begin - for (int j = 0; j < 2048; j++) begin - mem[i][j] = $random; + always @(posedge clock) begin + begin : mem_write + integer i; + for (i = 0; i < 16; i = i + 1) begin + if (enable & write & wmask[i]) begin + mem[addr][i*8+:8] <= wdata[8*i+:8]; + end + end + end + + if (enable & ~write) begin + raddr <= addr; end end - endtask +`else + // Simulation Path: DPI-based storage +`ifdef VERILATOR + `define DPI_MEMORY +`elsif VCS + `define DPI_MEMORY +`endif +`ifdef DPI_MEMORY + import "DPI-C" function chandle sram_init( + input longint global_addr, + input longint size_bytes, + input int width_bytes + ); + import "DPI-C" function void sram_read( + input chandle handle, + input int addr, + output bit [127:0] data + ); + import "DPI-C" function void sram_write( + input chandle handle, + input int addr, + input bit [127:0] data, + input int wmask + ); + import "DPI-C" function void sram_cleanup(input chandle handle); + + chandle backdoor_handle; + reg [127:0] rdata_reg; + assign rdata = rdata_reg; initial begin - randomMemoryAll; + backdoor_handle = sram_init(GLOBAL_BASE_ADDR, NUM_ENTRIES * SRAM_WIDTH_BYTES, SRAM_WIDTH_BYTES); end -`endif - always @(posedge clock) begin - for (int i = 0; i < 16; i++) begin - if (enable & write & wmask[i]) begin - mem[addr][i*8 +: 8] <= wdata[8*i +: 8]; - end + final begin + if (backdoor_handle != null) begin + sram_cleanup(backdoor_handle); end + end + always @(posedge clock) begin + if (enable & write) begin + sram_write(backdoor_handle, 32'(addr), wdata, {16'b0, wmask}); + end if (enable & ~write) begin - raddr <= addr; + sram_read(backdoor_handle, 32'(addr), rdata_reg); + end + end +`else + // Fallback for non-Verilator simulators + bit [127:0] mem[0:NUM_ENTRIES-1]; + reg [ADDR_WIDTH-1:0] raddr; + assign rdata = mem[raddr]; + always @(posedge clock) begin + if (enable & write) begin + integer i; + for (i = 0; i < 16; i = i + 1) begin + if (wmask[i]) mem[addr][i*8+:8] <= wdata[8*i+:8]; + end end + if (enable & ~write) raddr <= addr; end -`endif // FFCP12_SRAM +`endif +`endif -endmodule +`endif // SRAM selection + +endmodule \ No newline at end of file