diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index de94d69ffb1..a012ea8a09c 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -496,6 +496,7 @@ "xuantie/xiaohui/c906", "xuantie/xiaohui/c907", "xuantie/xiaohui/c908", + "xuantie/xiaohui/c908x", "xuantie/xiaohui/c910", "xuantie/xiaohui/r908", "xuantie/xiaohui/r910", diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/SConscript b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/SConscript new file mode 100644 index 00000000000..7c13ee46652 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/SConscript @@ -0,0 +1,13 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['startup.S'] +src += ['system.c'] +src += ['trap_c.c'] +src += ['vectors.S'] + +group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S new file mode 100644 index 00000000000..c5786df51d1 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/startup.S @@ -0,0 +1,200 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 1 +#endif + +.globl Reset_Handler +.global __rt_rvstack +.equ Mcoret_Handler, SW_handler +.equ Mirq_Handler, SW_handler +.section .vectors + .align 6 + .globl __Vectors + .type __Vectors, @object +__Vectors: + j Default_Handler /* 0 */ + j Stspend_Handler /* 1 */ + j Default_Handler /* 2 */ + j Mtspend_Handler /* 3 */ + j Default_Handler /* 4 */ + j Scoret_Handler /* 5 */ + j Default_Handler /* 6 */ + j Mcoret_Handler /* 7 */ + j Default_Handler /* 8 */ + j Sirq_Handler /* 9 */ + j Default_Handler /* 10 */ + j Mirq_Handler /* 11 */ + j Default_Handler /* 12 */ + j Default_Handler /* 13 */ + j Default_Handler /* 14 */ + j Default_Handler /* 15 */ +#if CONFIG_ECC_L1_ENABLE + j ECC_L1_Handler /* 16 */ +#else + j Default_Handler /* 16 */ +#endif + + .text + .align 2 + j Reset_Handler + .align 2 + .long 0x594B5343 /* CSKY ASCII */ + .long 0x594B5343 /* CSKY ASCII */ + .align 2 + .rept 9 + .long 0 + .endr + .long Reset_Handler +_start: + .type Reset_Handler, %function +Reset_Handler: +.option push +.option norelax + /* disable ie and clear all interrupts */ + csrw mie, zero + csrw mip, zero + + /* Disable MIE to avoid triggering interrupts before the first task starts. */ + /* This bit is set when a task recovers context. */ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + csrc mstatus, (1 << 1) +#else + csrc mstatus, (1 << 3) +#endif + + la gp, __global_pointer$ +.option pop + la a0, __Vectors + li a1, 0x1 + or a0, a0,a1 + csrw mtvec, a0 + +#if CONFIG_USE_FASTMEM + li a0, CONFIG_FASTMEM_ADDR + srli a0, a0, 12 + slli a0, a0, 1 + li a1, 0x80000000000001FF + or a0, a0, a1 + csrw 0x7EB, a0 # mtnfastmba +#endif + + /* get cpu id */ + csrr a0, mhartid + +#if defined(CONFIG_SMP) && CONFIG_SMP + /* check if hart is within range */ + /* tp: hart id */ + li t0, CONFIG_NR_CPUS + bge a0, t0, hart_out_of_bounds_loop +#endif + +#ifdef CONFIG_KERNEL_NONE + la sp, g_base_mainstack + addi t1, a0, 1 + li t2, CONFIG_ARCH_MAINSTACK + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_MAINSTACK + g_base_mainstack */ +#else + la sp, g_base_irqstack + addi t1, a0, 1 + li t2, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t2 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ +#endif + + /* other cpu core, jump to cpu entry directly */ + bnez a0, secondary_cpu_entry + +#ifndef __NO_SYSTEM_INIT + la a0, SystemInit + jalr a0 +#endif + +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + la a0, smode_init + jalr a0 +#endif + +#ifdef CONFIG_KERNEL_NONE + /* Enable interrupt */ +#if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE + csrs sstatus, (1 << 1) +#else + csrs mstatus, (1 << 3) +#endif +#endif + + la a0, rtthread_startup + jalr a0 + +.size Reset_Handler, . - Reset_Handler + +__exit: + j __exit + + .type secondary_cpu_entry, %function +secondary_cpu_entry: +#if defined(CONFIG_SMP) && CONFIG_SMP + la a0, secondary_boot_flag + ld a0, 0(a0) + li a1, 0xa55a + beq a0, a1, 1f +#endif + j secondary_cpu_entry + +#if defined(CONFIG_SMP) && CONFIG_SMP +1: + jal secondary_cpu_c_start + +.size secondary_cpu_entry, . - secondary_cpu_entry + +hart_out_of_bounds_loop: + /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ + wfi + j hart_out_of_bounds_loop +#endif + +.section .stack + .align 4 + .global g_base_irqstack + .global g_top_irqstack +g_base_irqstack: + .space CONFIG_ARCH_INTERRUPTSTACK * CONFIG_NR_CPUS +g_top_irqstack: +__rt_rvstack: + +#ifdef CONFIG_KERNEL_NONE + .align 4 + .global g_base_mainstack + .global g_top_mainstack +g_base_mainstack: + .space CONFIG_ARCH_MAINSTACK * CONFIG_NR_CPUS +g_top_mainstack: +#endif + +#if defined(CONFIG_SMP) && CONFIG_SMP +.data +.global secondary_boot_flag +.align 3 +secondary_boot_flag: + .dword 0 +#endif diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/system.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/system.c new file mode 100644 index 00000000000..7eb3535b2a1 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/system.c @@ -0,0 +1,325 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include "riscv_csr.h" + +#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE) +#error "Please check the current system is baremetal or not!!!" +#endif + +#if !defined(CONFIG_SMP) || (defined(CONFIG_SMP) && !CONFIG_SMP) +#if CONFIG_NR_CPUS > 1 +#error "Please define CONFIG_NR_CPUS as 1 or do not need define." +#endif +#endif + +#if CONFIG_ECC_L2_ENABLE +static csi_dev_t ecc_l2_dev; +#endif + +extern void section_data_copy(void); +extern void section_ram_code_copy(void); +extern void section_bss_clear(void); + +#ifdef CONFIG_RISCV_SMODE +extern unsigned long __Vectors; +unsigned long page_table_l2[512] __attribute__ ((aligned(4096))); +unsigned long page_table_l1[512] __attribute__ ((aligned(4096))); +unsigned long page_table_l0[512] __attribute__ ((aligned(4096))); + +void _mmu_init(void) __attribute__((noinline)); +void _mmu_init(void) +{ +#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \ + || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \ + || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 + unsigned long status = __get_MXSTATUS(); + /* open MAEE for thead-mmu extension */ + status |= (1 << 21); + __set_MXSTATUS(status); + + page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; + page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; + /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ + for (unsigned long i = 0; i < 256; i++) { + page_table_l0[i] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | i << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ + for (unsigned long i = 1; i < 512; i++) { + page_table_l1[i] = (UPPER_ATTRS(ATTR_SO | ATTR_SH) | i << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ + page_table_l2[1] = (UPPER_ATTRS(ATTR_CA | ATTR_SH) | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; +#elif CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 + unsigned long envcfgh = __get_MENVCFGH(); + /* enable svpbmt */ + envcfgh |= (1 << 30); + __set_MENVCFGH(envcfgh); + + page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; + /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ + for (unsigned long i = 0; i < 256; i++) { + page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(4M ~ 1G-1) <==> PA(4M ~ 1G-1) */ + for (unsigned long i = 1; i < 256; i++) { + page_table_l1[i] = (SVPBMT_IO | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ + for (unsigned long i = 256; i < 512; i++) { + page_table_l1[i] = (SVPBMT_PMA | (i) << 20 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } +#else + unsigned long envcfg = __get_MENVCFG(); + /* enable svpbmt */ + envcfg |= (1ull << 62); + __set_MENVCFG(envcfg); + + page_table_l2[0] = 0x1 | ((unsigned long)page_table_l1 >> 12) << 10; + page_table_l1[0] = 0x1 | ((unsigned long)page_table_l0 >> 12) << 10; + /* setup mmu VA(0M ~ 1M-1) <==> PA(0M ~ 1M-1) */ + for (unsigned long i = 0; i < 256; i++) { + page_table_l0[i] = (SVPBMT_PMA | (i) << 10 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(2M ~ 1G-1) <==> PA(2M ~ 1G-1) */ + for (unsigned long i = 1; i < 512; i++) { + page_table_l1[i] = (SVPBMT_IO | (i) << 19 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; + } + + /* setup mmu VA(1G ~ 2G-1) <==> PA(1G ~ 2G-1) */ + page_table_l2[1] = (SVPBMT_PMA | (1) << 28 | LOWER_ATTRS(DIRTY_FLAG | ACCESS_FLAG | AP_X | AP_W | AP_R | GLOBAL_FLAG)) | 0x1; +#endif + +#if __riscv_xlen == 64 + csi_dcache_clean_range((unsigned long *)&page_table_l2, sizeof(page_table_l2)); +#endif + csi_dcache_clean_range((unsigned long *)&page_table_l1, sizeof(page_table_l1)); + csi_dcache_clean_range((unsigned long *)&page_table_l0, sizeof(page_table_l0)); + csi_mmu_invalid_tlb_all(); +#if __riscv_xlen == 64 + __set_SATP(((unsigned long)&page_table_l2 >> 12)); + csi_mmu_set_mode(MMU_MODE_39); + csi_mmu_enable(); +#else + __set_SATP(((unsigned long)&page_table_l1 >> 12)); + csi_mmu_set_mode(MMU_MODE_32); + csi_mmu_enable(); +#endif +} + +void _system_switchto_smode(void) +{ + unsigned long m_status = __get_MSTATUS(); + m_status &= ~MSTATUS_TVM_MASK; + m_status &= ~MSTATUS_MPP_MASK; + m_status |= MSTATUS_MPP_S; + __set_MSTATUS(m_status); + + /* setup S-Mode csr regs */ + __set_STVEC((unsigned long)(&__Vectors) | 0x1); + //FIXME: + __ASM("auipc a0, 0"); + __ASM("addi a0, a0, 14"); + __ASM("csrw mepc, a0"); + __ASM("mret"); +} + +void _system_init_for_smode(void) +{ + _system_switchto_smode(); +} + +void smode_init(void) +{ + /* may be not clear after reset on FPGA */ + csi_mmu_disable(); + _mmu_init(); + _system_init_for_smode(); +} +#endif + +/** + * @brief initialize pmp + * @param None + * @return None + */ +static void pmp_init(void) +{ + long addr; + + addr = 0x90000000UL >> 2; + __set_PMPADDR0(addr); + __set_PMPxCFG(0, 0x8f); +} + +static void interrupt_init(void) +{ + int i; + + for (i = 0; i < CONFIG_IRQ_NUM; i++) { + PLIC->PLIC_PRIO[i] = 31; + } + + for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { + PLIC->PLIC_IP[i] = 0; + } + + for (i = 0; i < (CONFIG_IRQ_NUM + 32) / 32; i++) { + PLIC->PLIC_H0_MIE[i] = 0; + PLIC->PLIC_H0_SIE[i] = 0; + } + + /* set hart threshold 0, enable all interrupt */ + PLIC->PLIC_H0_MTH = 0; + PLIC->PLIC_H0_STH = 0; + + for (i = 0; i < CONFIG_IRQ_NUM; i++) { + PLIC->PLIC_H0_MCLAIM = i; + PLIC->PLIC_H0_SCLAIM = i; + } + + /* set PLIC_PER */ + PLIC->PLIC_PER = 0x1; + + /* enable MEIE & MTIE & MSIE */ + uint32_t mie = __get_MIE(); + mie |= (1 << 11 | 1 << 7 | 1 << 3); +#if CONFIG_ECC_L1_ENABLE + mie |= (1 << 16); +#endif + __set_MIE(mie); +} + +static void section_init(void) +{ +#if CONFIG_XIP + section_data_copy(); + section_ram_code_copy(); + csi_dcache_clean(); + csi_icache_invalid(); +#endif + + section_bss_clear(); +} + +static void cache_init(void) +{ + /* enable cache */ + csi_dcache_enable(); + csi_icache_enable(); +} + +/** + * @brief initialize the system + * Initialize the psr and vbr. + * @param None + * @return None + */ +void SystemInit(void) +{ + unsigned long status = __get_MXSTATUS(); +#if CONFIG_CPU_XUANTIE_C908X + /* enable XUANTIEISAEE & MM */ + status |= (1 << 22 | 1 << 15); +#elif CONFIG_CPU_XUANTIE_C908X_CP + /* disable XUANTIEISAEE, enable MM & COPINSTEE */ + status |= (1 << 15 | 1 << 24); + status &= ~(1 << 22); +#elif CONFIG_CPU_XUANTIE_C908X_CP_XT + /* enable XUANTIEISAEE & MM & COPINSTEE */ + status |= (1 << 22 | 1 << 15 | 1 << 24); +#endif + __set_MXSTATUS(status); + +#if __riscv_flen == 64 + /* enable float ISA */ + status = __get_MSTATUS(); + status |= (1 << MSTATUS_FS_SHIFT); + __set_MSTATUS(status); +#endif +#ifdef __riscv_vector + /* enable vector ISA */ + status = __get_MSTATUS(); + status |= (1 << MSTATUS_VS_SHIFT); + __set_MSTATUS(status); +#endif + +#if CONFIG_ECC_L1_ENABLE + /* enable L1 cache ecc */ + uint64_t mhint = __get_MHINT(); + mhint |= (0x1 << 19); + __set_MHINT(mhint); +#endif + +#if CONFIG_ECC_L2_ENABLE + /* enable L2 cache ecc */ + uint64_t mccr2 = __get_MCCR2(); + mccr2 |= (0x1 << 1); + __set_MCCR2(mccr2); +#endif + +#ifdef CONFIG_RISCV_SMODE + /* enable ecall delegate */ + unsigned long medeleg = __get_MEDELEG(); + medeleg |= (1 << 9); + __set_MEDELEG(medeleg); + + /* enable interrupt delegate */ + unsigned long mideleg = __get_MIDELEG(); + mideleg |= 0x222; + __set_MIDELEG(mideleg); +#endif + +#ifdef CONFIG_RISCV_SMODE + /* enable mcounteren for s-mode */ + __set_MCOUNTEREN(0xffffffff); + +#if CBO_INSN_SUPPORT + unsigned long envcfg = __get_MENVCFG(); + /* enable CBIE & CBCFE & CBZE on lower priviledge */ + envcfg |= (3 << 4 | 1 << 6 | 1 << 7); + __set_MENVCFG(envcfg); +#endif +#endif + + cache_init(); + section_init(); + pmp_init(); + + interrupt_init(); + soc_set_sys_freq(20000000); + csi_tick_init(); + +#if CONFIG_ECC_L2_ENABLE + extern void ecc_l2_irqhandler(void *arg); + /* l2 cache ecc interrupt register */ + ecc_l2_dev.irq_num = L2_CACHE_ECC_IRQn; + csi_irq_attach(ecc_l2_dev.irq_num, ecc_l2_irqhandler, &ecc_l2_dev); + csi_irq_enable(ecc_l2_dev.irq_num); +#endif +} diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/trap_c.c b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/trap_c.c new file mode 100644 index 00000000000..f36e86b2595 --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/trap_c.c @@ -0,0 +1,64 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0) +#include +#else +#define printk printf +#endif + +void (*trap_c_callback)(void); + +void trap_c(uintptr_t *regs) +{ + int i; + unsigned long vec = 0; + + vec = __get_MCAUSE(); + + printk("CPU Exception(mcause);: NO.0x%lx", vec); + printk("\n"); + + for (i = 0; i < 31; i++) { + printk("x%d: %p\t", i + 1, (void *)regs[i]); + + if ((i % 4) == 3) { + printk("\n"); + } + } + + printk("\n"); + printk("mepc : %p\n", (void *)regs[31]); + printk("mstatus: %p\n", (void *)regs[32]); + + if (trap_c_callback) { + trap_c_callback(); + } + + while (1); +} + +__attribute__((weak)) void exceptionHandler(void *context) +{ + trap_c((uintptr_t *)context); +} + diff --git a/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/vectors.S b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/vectors.S new file mode 100644 index 00000000000..317c7d4e93d --- /dev/null +++ b/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c908x/vectors.S @@ -0,0 +1,527 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "riscv_asm_macro.h" + +.section .stack + .align 4 + .global g_trapstackbase + .global g_top_trapstack +g_trapstackbase: + .space CONFIG_ARCH_INTERRUPTSTACK +g_top_trapstack: + +.text +.global _interrupt_return_address + + .align 3 + .weak Scoret_Handler + .type Scoret_Handler, %function +Scoret_Handler: + csrw sscratch, sp + la sp, g_top_irqstack + + addi sp, sp, -(76+76) + sd t0, (4+4)(sp) + sd t1, (8+8)(sp) + sd t2, (12+12)(sp) + + csrr t0, sepc + sd t0, (68+68)(sp) + csrr t0, sstatus + sd t0, (72+72)(sp) + + sd ra, (0 +0 )(sp) + sd a0, (16+16)(sp) + sd a1, (20+20)(sp) + sd a2, (24+24)(sp) + sd a3, (28+28)(sp) + sd a4, (32+32)(sp) + sd a5, (36+36)(sp) + sd a6, (40+40)(sp) + sd a7, (44+44)(sp) + sd t3, (48+48)(sp) + sd t4, (52+52)(sp) + sd t5, (56+56)(sp) + sd t6, (60+60)(sp) + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + csrr t3, sstatus +#endif + SAVE_FLOAT_REGISTERS + SAVE_VECTOR_REGISTERS + + la t2, CORET_IRQHandler + jalr t2 + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + RESTORE_SSTATUS +#endif + RESTORE_VECTOR_REGISTERS + RESTORE_FLOAT_REGISTERS + +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) + ld t0, (72+72)(sp) + csrw sstatus, t0 +#endif + ld t0, (68+68)(sp) + csrw sepc, t0 + + ld ra, (0 +0 )(sp) + ld t0, (4 +4 )(sp) + ld t1, (8 +8 )(sp) + ld t2, (12+12)(sp) + ld a0, (16+16)(sp) + ld a1, (20+20)(sp) + ld a2, (24+24)(sp) + ld a3, (28+28)(sp) + ld a4, (32+32)(sp) + ld a5, (36+36)(sp) + ld a6, (40+40)(sp) + ld a7, (44+44)(sp) + ld t3, (48+48)(sp) + ld t4, (52+52)(sp) + ld t5, (56+56)(sp) + ld t6, (60+60)(sp) + + addi sp, sp, (76+76) + csrr sp, sscratch + sret + + + .align 3 + .weak Mcoret_Handler + .type Mcoret_Handler, %function +Mcoret_Handler: + addi sp, sp, -16 + sd t0, (0)(sp) + sd t1, (8)(sp) + csrw mscratch, sp + + csrr t0, mhartid + la sp, g_base_irqstack + addi t1, t0, 1 + li t0, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t0 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ + + addi sp, sp, -(76+76) + sd t0, (4+4)(sp) + sd t1, (8+8)(sp) + sd t2, (12+12)(sp) + + csrr t0, mepc + sd t0, (68+68)(sp) + csrr t0, mstatus + sd t0, (72+72)(sp) + + sd ra, (0 +0 )(sp) + sd a0, (16+16)(sp) + sd a1, (20+20)(sp) + sd a2, (24+24)(sp) + sd a3, (28+28)(sp) + sd a4, (32+32)(sp) + sd a5, (36+36)(sp) + sd a6, (40+40)(sp) + sd a7, (44+44)(sp) + sd t3, (48+48)(sp) + sd t4, (52+52)(sp) + sd t5, (56+56)(sp) + sd t6, (60+60)(sp) + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + csrr t3, mstatus +#endif + SAVE_FLOAT_REGISTERS + SAVE_VECTOR_REGISTERS + + la t2, CORET_IRQHandler + jalr t2 + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + RESTORE_MSTATUS +#endif + RESTORE_VECTOR_REGISTERS + RESTORE_FLOAT_REGISTERS + +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) + ld t0, (72+72)(sp) + csrw mstatus, t0 +#endif + ld t0, (68+68)(sp) + csrw mepc, t0 + + ld ra, (0 +0 )(sp) + ld t0, (4 +4 )(sp) + ld t1, (8 +8 )(sp) + ld t2, (12+12)(sp) + ld a0, (16+16)(sp) + ld a1, (20+20)(sp) + ld a2, (24+24)(sp) + ld a3, (28+28)(sp) + ld a4, (32+32)(sp) + ld a5, (36+36)(sp) + ld a6, (40+40)(sp) + ld a7, (44+44)(sp) + ld t3, (48+48)(sp) + ld t4, (52+52)(sp) + ld t5, (56+56)(sp) + ld t6, (60+60)(sp) + + addi sp, sp, (76+76) + csrr sp, mscratch + + ld t0, (0)(sp) + ld t1, (8)(sp) + addi sp, sp, 16 + mret + +#if CONFIG_ECC_L1_ENABLE + .align 3 + .weak ECC_L1_Handler + .type ECC_L1_Handler, %function +ECC_L1_Handler: + addi sp, sp, -16 + sd t0, (0)(sp) + sd t1, (8)(sp) + csrw mscratch, sp + + csrr t0, mhartid + la sp, g_base_irqstack + addi t1, t0, 1 + li t0, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t0 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ + + addi sp, sp, -(76+76) + sd t0, (4+4)(sp) + sd t1, (8+8)(sp) + sd t2, (12+12)(sp) + + csrr t0, mepc + sd t0, (68+68)(sp) + csrr t0, mstatus + sd t0, (72+72)(sp) + + sd ra, (0 +0 )(sp) + sd a0, (16+16)(sp) + sd a1, (20+20)(sp) + sd a2, (24+24)(sp) + sd a3, (28+28)(sp) + sd a4, (32+32)(sp) + sd a5, (36+36)(sp) + sd a6, (40+40)(sp) + sd a7, (44+44)(sp) + sd t3, (48+48)(sp) + sd t4, (52+52)(sp) + sd t5, (56+56)(sp) + sd t6, (60+60)(sp) + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + csrr t3, mstatus +#endif + SAVE_FLOAT_REGISTERS + SAVE_VECTOR_REGISTERS + + la t2, ECC_L1_IRQHandler + jalr t2 +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + RESTORE_MSTATUS +#endif + + RESTORE_VECTOR_REGISTERS + RESTORE_FLOAT_REGISTERS + +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) + ld t0, (72+72)(sp) + csrw mstatus, t0 +#endif + ld t0, (68+68)(sp) + csrw mepc, t0 + + ld ra, (0 +0 )(sp) + ld t0, (4 +4 )(sp) + ld t1, (8 +8 )(sp) + ld t2, (12+12)(sp) + ld a0, (16+16)(sp) + ld a1, (20+20)(sp) + ld a2, (24+24)(sp) + ld a3, (28+28)(sp) + ld a4, (32+32)(sp) + ld a5, (36+36)(sp) + ld a6, (40+40)(sp) + ld a7, (44+44)(sp) + ld t3, (48+48)(sp) + ld t4, (52+52)(sp) + ld t5, (56+56)(sp) + ld t6, (60+60)(sp) + + addi sp, sp, (76+76) + csrr sp, mscratch + + ld t0, (0)(sp) + ld t1, (8)(sp) + addi sp, sp, 16 + mret +#endif + + .align 3 + .weak Sirq_Handler + .type Sirq_Handler, %function +Sirq_Handler: + csrw sscratch, sp + la sp, g_top_irqstack + addi sp, sp, -(76+76) + sd t0, (4+4)(sp) + sd t1, (8+8)(sp) + sd t2, (12+12)(sp) + + csrr t0, sepc + sd t0, (68+68)(sp) + csrr t0, sstatus + sd t0, (72+72)(sp) + + sd ra, (0 +0 )(sp) + sd a0, (16+16)(sp) + sd a1, (20+20)(sp) + sd a2, (24+24)(sp) + sd a3, (28+28)(sp) + sd a4, (32+32)(sp) + sd a5, (36+36)(sp) + sd a6, (40+40)(sp) + sd a7, (44+44)(sp) + sd t3, (48+48)(sp) + sd t4, (52+52)(sp) + sd t5, (56+56)(sp) + sd t6, (60+60)(sp) + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + csrr t3, sstatus +#endif + SAVE_FLOAT_REGISTERS + SAVE_VECTOR_REGISTERS + + la t2, do_irq + jalr t2 + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + RESTORE_SSTATUS +#endif + RESTORE_VECTOR_REGISTERS + RESTORE_FLOAT_REGISTERS + +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) + ld t0, (72+72)(sp) + csrw sstatus, t0 +#endif + ld t0, (68+68)(sp) + csrw sepc, t0 + + ld ra, (0 +0 )(sp) + ld t0, (4 +4 )(sp) + ld t1, (8 +8 )(sp) + ld t2, (12+12)(sp) + ld a0, (16+16)(sp) + ld a1, (20+20)(sp) + ld a2, (24+24)(sp) + ld a3, (28+28)(sp) + ld a4, (32+32)(sp) + ld a5, (36+36)(sp) + ld a6, (40+40)(sp) + ld a7, (44+44)(sp) + ld t3, (48+48)(sp) + ld t4, (52+52)(sp) + ld t5, (56+56)(sp) + ld t6, (60+60)(sp) + + addi sp, sp, (76+76) + csrr sp, sscratch + sret + + + .align 3 + .weak Mirq_Handler + .type Mirq_Handler, %function +Mirq_Handler: + addi sp, sp, -16 + sd t0, (0)(sp) + sd t1, (8)(sp) +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, -8 + sd s0, (sp) +#endif + csrw mscratch, sp + + csrr t0, mhartid + la sp, g_base_irqstack + addi t1, t0, 1 + li t0, CONFIG_ARCH_INTERRUPTSTACK + mul t1, t1, t0 + add sp, sp, t1 /* sp = (cpuid + 1) * CONFIG_ARCH_INTERRUPTSTACK + g_base_irqstack */ + + addi sp, sp, -(76+76) + sd t0, (4+4)(sp) + sd t1, (8+8)(sp) + sd t2, (12+12)(sp) + + csrr t0, mepc + sd t0, (68+68)(sp) + csrr t0, mstatus + sd t0, (72+72)(sp) + + sd ra, (0 +0 )(sp) + sd a0, (16+16)(sp) + sd a1, (20+20)(sp) + sd a2, (24+24)(sp) + sd a3, (28+28)(sp) + sd a4, (32+32)(sp) + sd a5, (36+36)(sp) + sd a6, (40+40)(sp) + sd a7, (44+44)(sp) + sd t3, (48+48)(sp) + sd t4, (52+52)(sp) + sd t5, (56+56)(sp) + sd t6, (60+60)(sp) + +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + csrr t3, mstatus +#endif + SAVE_FLOAT_REGISTERS + SAVE_VECTOR_REGISTERS + + la t2, do_irq + jalr t2 +_interrupt_return_address: +#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY + RESTORE_MSTATUS +#endif + RESTORE_VECTOR_REGISTERS + RESTORE_FLOAT_REGISTERS + +#if (!CONFIG_CHECK_FPU_DIRTY) && (!CONFIG_CHECK_VECTOR_DIRTY) + ld t0, (72+72)(sp) + csrw mstatus, t0 +#endif + ld t0, (68+68)(sp) + csrw mepc, t0 + + ld ra, (0 +0 )(sp) + ld t0, (4 +4 )(sp) + ld t1, (8 +8 )(sp) + ld t2, (12+12)(sp) + ld a0, (16+16)(sp) + ld a1, (20+20)(sp) + ld a2, (24+24)(sp) + ld a3, (28+28)(sp) + ld a4, (32+32)(sp) + ld a5, (36+36)(sp) + ld a6, (40+40)(sp) + ld a7, (44+44)(sp) + ld t3, (48+48)(sp) + ld t4, (52+52)(sp) + ld t5, (56+56)(sp) + ld t6, (60+60)(sp) + + addi sp, sp, (76+76) + csrr sp, mscratch + +#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP + addi sp, sp, 8 +#endif + ld t0, (0)(sp) + ld t1, (8)(sp) + addi sp, sp, 16 + mret + + +/****************************************************************************** + * Functions: + * void trap(void); + * default exception handler + ******************************************************************************/ + .align 3 + .global trap + .type trap, %function +trap: + csrw mscratch, sp + la sp, g_top_trapstack + addi sp, sp, -(140+140) + sd x1, ( 0 + 0 )(sp) + sd x3, ( 8 + 8 )(sp) + sd x4, ( 12+ 12)(sp) + sd x5, ( 16+ 16)(sp) + sd x6, ( 20+ 20)(sp) + sd x7, ( 24+ 24)(sp) + sd x8, ( 28+ 28)(sp) + sd x9, ( 32+ 32)(sp) + sd x10,( 36+ 36)(sp) + sd x11,( 40+ 40)(sp) + sd x12,( 44+ 44)(sp) + sd x13,( 48+ 48)(sp) + sd x14,( 52+ 52)(sp) + sd x15,( 56+ 56)(sp) + sd x16,( 60+ 60)(sp) + sd x17,( 64+ 64)(sp) + sd x18,( 68+ 68)(sp) + sd x19,( 72+ 72)(sp) + sd x20,( 76+ 76)(sp) + sd x21,( 80+ 80)(sp) + sd x22,( 84+ 84)(sp) + sd x23,( 88+ 88)(sp) + sd x24,( 92+ 92)(sp) + sd x25,( 96+ 96)(sp) + sd x26,(100+100)(sp) + sd x27,(104+104)(sp) + sd x28,(108+108)(sp) + sd x29,(112+112)(sp) + sd x30,(116+116)(sp) + sd x31,(120+120)(sp) + csrr a0, mepc + sd a0, (124+124)(sp) + csrr a0, mstatus + sd a0, (128+128)(sp) + csrr a0, mcause + sd a0, (132+132)(sp) + csrr a0, mtval + sd a0, (136+136)(sp) + csrr a0, mscratch + sd a0, ( 4 + 4 )(sp) + + mv a0, sp + la a1, exceptionHandler + jalr a1 + + .align 3 + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + j trap + + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler Stspend_Handler + def_irq_handler Mtspend_Handler + def_irq_handler CORET_IRQHandler diff --git a/bsp/xuantie/xiaohui/c908x/.config b/bsp/xuantie/xiaohui/c908x/.config new file mode 100644 index 00000000000..2076041d909 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/.config @@ -0,0 +1,1381 @@ +CONFIG_XUANTIAN_XIAOHUI_C908X=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +# CONFIG_RT_USING_MEMPOOL is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +CONFIG_RT_USING_STDC_ATOMIC=y +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_CPU_64BIT=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_NEW_CTX_SWITCH=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=8192 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_XUANTIE=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_ENABLE_FPU is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/xuantie/xiaohui/c908x/.cproject b/bsp/xuantie/xiaohui/c908x/.cproject new file mode 100644 index 00000000000..0d8fe45d516 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/.cproject @@ -0,0 +1,912 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/xuantie/xiaohui/c908x/.project b/bsp/xuantie/xiaohui/c908x/.project new file mode 100644 index 00000000000..c7455faa7a8 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/.project @@ -0,0 +1,27 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + diff --git a/bsp/xuantie/xiaohui/c908x/.settings/org.eclipse.core.runtime.prefs b/bsp/xuantie/xiaohui/c908x/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000000..9f1acfcfba2 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/xuantie/xiaohui/c908x/.settings/projcfg.ini b/bsp/xuantie/xiaohui/c908x/.settings/projcfg.ini new file mode 100644 index 00000000000..6b7c2895f99 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +# Mon Sep 22 18:49:19 2025 +cfg_version=v3.0 + +board_name= +bsp_version= +bsp_path= +chip_name= +project_base_rtt_bsp=true +is_use_scons_build=true +hardware_adapter= +selected_rtt_version=latest +board_base_nano_proj=false +is_base_example_project=false +example_name= +project_type=rt-thread +os_branch=master +os_version=latest +project_name=project +output_project_path=E:\rt-thread\bsp\xuantie\xiaohui\c908x \ No newline at end of file diff --git a/bsp/xuantie/xiaohui/c908x/Kconfig b/bsp/xuantie/xiaohui/c908x/Kconfig new file mode 100644 index 00000000000..848d634e42d --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/Kconfig @@ -0,0 +1,18 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../../ + +PKGS_DIR := packages + + config XUANTIAN_XIAOHUI_C908X + bool + select ARCH_RISCV64 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$(RTT_DIR)/Kconfig" +source "$PKGS_DIR/Kconfig" +source "$BSP_DIR/board/Kconfig" diff --git a/bsp/xuantie/xiaohui/c908x/README.md b/bsp/xuantie/xiaohui/c908x/README.md new file mode 100644 index 00000000000..7b7fd4b5603 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/README.md @@ -0,0 +1,145 @@ +# XuanTie - C908X Series + +## 一 简介 + +### 1. 内核 + +C908X 是基于RISC-V 指令架构的64 位高性能多核心处理器，主要面向市场日益增强的图像、视觉处理 +领域，例如智慧视觉、车载视觉、行车记录仪、智能交互等。其他应用领域还包括扫地机器人、无人机、自 +动化驾驶、增强现实、医疗图像、机器人工业视觉、移动互联网等产品。 +C908X 采用同构多核架构，支持多cluster，每个cluster 支持1~4 个核心。每个C908X 核心采用自主设计 +的微体系结构，并重点针对性能进行优化，采用按序双发射、多模式分支预测和多通道数据预取等高性能 +技术。此外，C908X 核心支持实时检测并关断内部空闲功能模块，降低处理器动态功耗。 + +### 2.特点 +#### 2.1. C908X 处理器体系结构的主要特点 +• 同构多核架构，支持多cluster，每个cluster 支持1~4 个C908X 核心； + +• 支持1 个AXI4.0 Master 接口，128/256 比特的总线宽度； + +• 支持1 个可配置的AXI4.0 低延时外设Master 接口（Low Latency Port, LLP），128 比特的总线宽度； + +• 支持1 个可配的AXI4.0 设备一致性接口(Device Coherence Port, DCP)，128 比特的总线宽度； + +• 一级指令/数据缓存分别支持16KB/32KB/64KB，缓存行SIZE 为64B；可配置ECC/奇偶校验机制； + +• 二级高缓128KB/256KB/512KB/1MB/1.5MB/2MB/3MB/4MB，缓存行SIZE 为64B；可配置ECC 校验机制； + +• 一级缓存支持MESI 一致性协议，二级缓存支持MOESI 一致性协议； + +• 支持私有中断控制器CLINT 和公有中断控制器PLIC；支持多cluster 中断分发； + +• 支持RISC-V 性能计数器和计时器； + +• 支持Sv39 和Sv48 内存管理，支持SVNAPOT 和SVPBMT 标准扩展； + +• 支持8/16/32/64 表项PMP，支持ePMP； + +• 支持XuanTie TEE 扩展； + +• 支持各个核心独立下电以及cluster 下电； + +• 支持RISC-V 调试框架和RISC-V Trace，支持多核多cluster 调试； + +#### 2.2. C908X 核心的主要特点 +• RISC-V 64GCB[V] 指令架构； + +• User Mode 支持RV64 指令集； + +• 支持小端模式； + +• 9 级流水架构； + +• 按序双发射，按序取指、发射、执行和退休； + +• 两级TLB 内存管理单元，实现虚实地址转换与内存管理； + +• 指令高缓和数据高缓大小可配置，支持16KB/32KB/64KB，缓存行为64B； + +• 指令高缓可配置奇偶校验，数据高缓可配置ECC 或奇偶校验； + +• 指令预取功能，硬件自动检测并动态启动； + +• 指令高缓路预测的低功耗访问技术； + +• 支持2KB/4KB/8KB 的多算法分支预测器； + +• 支持256 表项的分支目标缓存器（BTB）； + +• 支持8 层的硬件返回地址堆栈； + +• 支持256 表项的间接跳转分支预测器； + +• 支持循环终止预测； + +• 支持指令融合技术； + +• 双发射按序执行Load、Store 指令； + +• 读、写内存分别支持8 路、12 路并发的总线访问； + +• 支持写合并； + +• 支持8 通道数据预取，支持固定stride 和规律性不定stride 数据预取； + +#### 2.3. 矢量计算单元的主要特点 +• 遵循RISC-V V 矢量扩展； + +• 在4 核、2GHz 最大配置下，算力可达2048 Gops (@int8)/ 1024 GFlops (@FP16)； + +• 矢量执行单元支持FP16/BFP16/FP32 浮点和INT8/INT16/INT32/INT64 整型的矢量运算； + +• 支持512/1024/4096 可配置的矢量寄存器位宽VLEN； + +• 支持512/1024/4096 位矢量数据存储访问位宽； + +• 支持segment load、store 指令； + +• 性能优化的非对齐内存访问； + +### 3.BSP支持情况 + +- 当前BSP支持下述内核： + + ```asciiarmor + c908x c908x-cp c908x-cp-xt + ``` + +- 当前BSP默认设置的内核是c908x，该架构支持[F] [D] [V]扩展，可以通过menuconfig工具使能[F]扩展或者[F] [D] [V] 扩展。 + +- 当使用其他内核架构时需要修改，rtconfig.py文件中的`MCPU`字段。 + +### 4.运行QEMU + +- BSP根目录下存在`qemu.bat`脚本，生成可执行文件后可点击该脚本直接启动QEMU. + +## 二 工具 + +- 编译器： https://www.xrvm.cn/community/download?id=4433353576298909696 +- 模拟器： https://www.xrvm.cn/community/download?id=4397435198627713024 + +注：若上述链接中的编译器与模拟器不能使用，可以使用下述CDK中的编译器与模拟器 + +- SDK：https://www.xrvm.cn/community/download?id=4397799570420076544 + +## 三 调试方法 + +**下述调试方法以E906举例，本BSP操作方式一致**，搭建完成RT-Thread开发环境，在BSP根目录使用env工具在当前目录打开env。 + +![](figures/1.env.png) + +使用前执行一次**menuconfig**命令，更新rtconfig.h配置，然后在当前目录执行**scons -j12**命令编译生成可可执行文件。 + +env + +生成可执行文件，可以直接在命令行启动qemu或者配置vscode脚本借助vscode强大的插件进行图形化调试，qemu的相关命令可以查看玄铁qemu的[用户手册](https://www.xrvm.cn/community/download?id=4397435198627713024)，下述是启动qemu的命令，在powershell或命令行可直接执行下述命令，注意qemu需要导出至环境变量或者使用绝对路径。 + +```shell +qemu-system-riscv64 -machine xiaohui -nographic -kernel rtthread.elf -cpu c908x-cp-xt +``` + +下述是使用vscode调试的展示。 + +env + +一起为RISC-V加油！ \ No newline at end of file diff --git a/bsp/xuantie/xiaohui/c908x/SConscript b/bsp/xuantie/xiaohui/c908x/SConscript new file mode 100644 index 00000000000..27c6c5f6358 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/SConscript @@ -0,0 +1,19 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for item in list: + path = os.path.join(cwd, item) + if item == 'libraries' or not os.path.isdir(path): + continue + + sconscript_path = os.path.join(path, 'SConscript') + if os.path.isfile(sconscript_path): + objs.extend(SConscript(os.path.join(item, 'SConscript'))) + +Return('objs') diff --git a/bsp/xuantie/xiaohui/c908x/SConstruct b/bsp/xuantie/xiaohui/c908x/SConstruct new file mode 100644 index 00000000000..a8f7c02d7fe --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/SConstruct @@ -0,0 +1,54 @@ +import os +import sys +import rtconfig +from SCons.Script import * + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] + +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = os.path.normpath(os.path.join(SDK_ROOT, '..', 'libraries')) +else: + libraries_path_prefix = os.path.normpath(os.path.join(os.path.dirname(SDK_ROOT), '..', 'libraries')) + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +bsp_vdir = 'build' +library_vdir = 'build/libraries' + +# common include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript'), variant_dir=library_vdir, duplicate=0)) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/xuantie/xiaohui/c908x/applications/SConscript b/bsp/xuantie/xiaohui/c908x/applications/SConscript new file mode 100644 index 00000000000..f129b326245 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/applications/SConscript @@ -0,0 +1,10 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = ['main.c'] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/xuantie/xiaohui/c908x/applications/main.c b/bsp/xuantie/xiaohui/c908x/applications/main.c new file mode 100644 index 00000000000..b18d7a7f542 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/applications/main.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-21 Wangshun first version + */ + + #include + #include + #include "pre_main.h" + + int main(void) + { + rt_kprintf("Hello RT-Thread!\r\n"); + return 0; + } + diff --git a/bsp/xuantie/xiaohui/c908x/board/Kconfig b/bsp/xuantie/xiaohui/c908x/board/Kconfig new file mode 100644 index 00000000000..1e26dffa324 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/board/Kconfig @@ -0,0 +1,42 @@ +menu "Hardware Drivers Config" + +config SOC_XUANTIE + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + +menu "On-chip Peripheral Drivers" + + menuconfig BSP_USING_UART + bool "Enable UART" + select RT_USING_SERIAL + default n + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + default n + endif + + menuconfig ENABLE_FPU + bool "Enable FPU" + select ARCH_RISCV_FPU + default n + + if ENABLE_FPU + choice + prompt "FPU Configuration" + default ARCH_RISCV_FPU_S + + config ARCH_RISCV_FPU_S + bool "Enable [F] Extension" + + config ARCH_RISCV_FPU_D + bool "Enable [F][D] Extension" + endchoice + endif +endmenu + +endmenu diff --git a/bsp/xuantie/xiaohui/c908x/board/SConscript b/bsp/xuantie/xiaohui/c908x/board/SConscript new file mode 100644 index 00000000000..f8b81f92d5c --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/board/SConscript @@ -0,0 +1,39 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = ['board.c'] + +path = [cwd] + +CPPDEFINES = [ + 'CONFIG_KERNEL_RTTHREAD=1', + '__RT_KERNEL_SOURCE__=1', + 'CONFIG_CSI_V2=1', + 'CONFIG_CSI="csi2"', + 'CONFIG_SUPPORT_TSPEND=0', + 'CONFIG_SUPPORT_IRQ_NESTED=0', + 'CONFIG_XIP=1', + 'CONFIG_ARCH_MAINSTACK=8192', + 'CONFIG_ARCH_INTERRUPTSTACK=8192', + 'CONFIG_BOARD_XIAOHUI_EVB=1', + 'CLI_CONFIG_STACK_SIZE=8192', + 'CONFIG_PLIC_BASE=134217728', + 'CONFIG_VIC_TSPDR=201326592', + 'CONFIG_CLIC_BASE=201392128', + 'CONFIG_FPP_ENABLE=0', + 'CONFIG_INTC_CLIC_PLIC=1', + 'CONFIG_INIT_TASK_STACK_SIZE=8192', + 'CONFIG_APP_TASK_STACK_SIZE=8192', + 'CONFIG_SYSTICK_HZ=100', + 'CONFIG_DEBUG=1', + 'CONFIG_CPU_XUANTIE_C908X=1' +] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/xuantie/xiaohui/c908x/board/board.c b/bsp/xuantie/xiaohui/c908x/board/board.c new file mode 100644 index 00000000000..48204fda4bb --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/board/board.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-04-23 Wangshun first version + */ + +#include +#include +#include +#include + +extern unsigned long __heap_start; +extern unsigned long __heap_end; + +/** + * This function will initialize your board. + */ +void rt_hw_board_init() +{ + rt_hw_interrupt_init(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)&__heap_start, (void *)&__heap_end); +#endif + +#ifdef BSP_USING_UART + rt_hw_usart_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} diff --git a/bsp/xuantie/xiaohui/c908x/board/board.h b/bsp/xuantie/xiaohui/c908x/board/board.h new file mode 100644 index 00000000000..9f95ecd3e58 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/board/board.h @@ -0,0 +1,442 @@ + /* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + This is an example board.h for Board Component, New Board should follow the macro defines. +*/ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// Common Board Features Define + +/* + The Common BOARD_XXX Macro Defines Boards supported features which may reference by Solutions. + Common board macro include: + . BOARD_NAME + · UART + · GPIO + · PWM + · ADC + · BUTTON + · LED + · WIFI + · BT + · AUDIO + BOARD_XXX Macro described below should be defined if the board support. +*/ + +/****************************************************************************/ + +/* + This riscv dummy board include: + · UART x1 + · GPIO x2 + · PWM x2 + · ADC x1 + · BUTTON x2 + · LED x2 + · WIFI x0 + · BT x0 + · AUDIO x1 +*/ + +#ifndef CONFIG_BOARD_UART +#define CONFIG_BOARD_UART 1 +#endif + +#ifndef CONFIG_BOARD_GPIO +#define CONFIG_BOARD_GPIO 0 +#endif + +#ifndef CONFIG_BOARD_PWM +#define CONFIG_BOARD_PWM 0 +#endif + +#ifndef CONFIG_BOARD_ADC +#define CONFIG_BOARD_ADC 0 +#endif + +#ifndef CONFIG_BOARD_BUTTON +#define CONFIG_BOARD_BUTTON 0 +#endif + +#ifndef CONFIG_BOARD_LED +#define CONFIG_BOARD_LED 0 +#endif + +#ifndef CONFIG_BOARD_WIFI +#define CONFIG_BOARD_WIFI 0 +#endif + +#ifndef CONFIG_BOARD_BT +#define CONFIG_BOARD_BT 0 +#endif + +#ifndef CONFIG_BOARD_AUDIO +#define CONFIG_BOARD_AUDIO 0 +#endif + +#define BOARD_NAME "RISCV_DUMMY" + +/* the board pins, can be used as uart, gpio, pwd... */ +#define BOARD_PIN0 (0) +#define BOARD_PIN1 (1) +#define BOARD_PIN2 (2) +#define BOARD_PIN3 (3) +#define BOARD_PIN4 (4) +#define BOARD_PIN5 (5) +#define BOARD_PIN6 (6) +#define BOARD_PIN7 (7) +#define BOARD_PIN8 (8) +#define BOARD_PIN9 (9) +#define BOARD_PIN10 (10) +#define BOARD_PIN11 (11) +#define BOARD_PIN12 (12) +//... + +#if defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART +// UART + +/* + The total supported uart numbers on this board, 0 means No uart support. + the BOARD_UART_XXX, x in range of (0, BOARD_UART_NUM - 1) +*/ +#ifndef BOARD_UART_NUM +#define BOARD_UART_NUM (1) +#endif + +#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 +/* the board uart0 tx pin */ +#define BOARD_UART0_TX_PIN (BOARD_PIN0) +/* the borad uart0 rx pin */ +#define BOARD_UART0_RX_PIN (BOARD_PIN1) +/* The real UART port reference to board logic port 0 */ +#define BOARD_UART0_IDX (0) +/* The default baudrate for uart0 */ +#define BOARD_UART0_BAUD (115200) + +//#define BOARD_UART1_IDX (1) +//#define BOARD_UART1_BAUD (115200) +// ... +#endif // defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 + +#endif // defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART + +#if defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO +// GPIO +/* + The total supported GPIO Pin numbers on this board, 0 meas No uart support. + the BOARD_GPIO_PIN, x in rang of (0, BOARD_GPIO_PIN_NUM - 1) +*/ +#ifndef BOARD_GPIO_PIN_NUM +#define BOARD_GPIO_PIN_NUM (2) +#endif + +#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +/* The real gpio reference to board logic gpio pin */ +#define BOARD_GPIO_PIN0 (BOARD_PIN2) +#define BOARD_GPIO_PIN1 (BOARD_PIN3) +//#define BOARD_GPIO_PIN2 (x) +//#define BOARD_GPIO_PIN3 (x) +#endif // defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 +#endif // defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO + +#if defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM +// PWM +/* the board supported pwm channels */ +#ifndef BOARD_PWM_NUM +#define BOARD_PWM_NUM (2) +#endif + +#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +/* the board pwm pin */ +#define BOARD_PWM0_PIN (BOARD_PIN4) +/* The real pwm channel reference to board logic pwm channel */ +#define BOARD_PWM0_CH (0) + +#define BOARD_PWM1_PIN (BOARD_PIN5) +#define BOARD_PWM1_CH (1) +#endif // defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 +#endif // defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM + +#if defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 +// ADC +/* the board supported adc channels */ +#ifndef BOARD_ADC_NUM +#define BOARD_ADC_NUM (1) +#endif + +#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +/* the board adc pin */ +#define BOARD_ADC0_PIN (BOARD_PIN6) +/* The real adc channel reference to board logic adc channel */ +#define BOARD_ADC0_CH (0) +#endif // defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 +#endif // defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 + +#if defined(CONFIG_BOARD_BUTTON) && CONFIG_BOARD_BUTTON > 0 +// BUTTON +#ifndef BOARD_BUTTON_NUM +/* + the board supported buttons, include gpio button and adc button, + BOARD_BUTTON_NUM = BOARD_BUTTON_GPIO_NUM + BOARD_BUTTON_ADC_NUM. + +*/ +#define BOARD_BUTTON_NUM (4) +#endif + +#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#define BOARD_BUTTON0_PIN (BOARD_PIN7) +#define BOARD_BUTTON1_PIN (BOARD_PIN8) +#define BOARD_BUTTON2_PIN (BOARD_PIN9) +#define BOARD_BUTTON3_PIN (BOARD_PIN10) + +// GPIO BUTTON +/* the board supported GPIO Buttons */ +#ifndef BOARD_BUTTON_GPIO_NUM +#define BOARD_BUTTON_GPIO_NUM (2) +#endif + +#if defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 +/* the board logic button id, in range of (0, BOARD_BUTTON_GPIO_NUM - 1) */ +#define BOARD_BUTTON0 (0) +/* for gpio button, define the pin numner. if the gpio pin used as gpio button, it shoudn't reference as BOARD_GPIO_PINx + */ +#define BOARD_BUTTON0_GPIO_PIN (BOARD_BUTTON0_PIN) + +#define BOARD_BUTTON1 (1) +#define BOARD_BUTTON1_GPIO_PIN (BOARD_BUTTON1_PIN) +#endif // defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 + +// ADC BUTTON +/* the board supported adc Buttons */ +#ifndef BOARD_BUTTON_ADC_NUM +#define BOARD_BUTTON_ADC_NUM (2) +#endif + +#if defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 +/* the board logic adc button id, in range of (BOARD_BUTTON_GPIO_NUM, BOARD_BUTTON_NUM - 1), if not suuport GPIO Button, + * BOARD_BUTTON_GPIO_NUM should be 0 */ +#define BOARD_BUTTON2 (BOARD_BUTTON_GPIO_NUM + 0) +#define BOARD_BUTTON2_ADC_PIN (BOARD_BUTTON2_PIN) +/* the adc channel used for button2, if the adc channel used as adc button, it shoudn't reference as BOARD_ADCx_CH*/ +#define BOARD_BUTTON2_ADC_CH (1) +/* the adc device name */ +#define BOARD_BUTTON2_ADC_NAME "adc1" +/* adc voltage reference */ +#define BOARD_BUTTON2_ADC_REF (100) +/* adc voltage range */ +#define BOARD_BUTTON2_ADC_RANG (500) + +#define BOARD_BUTTON3 (BOARD_BUTTON_GPIO_NUM + 1) +#define BOARD_BUTTON3_ADC_PIN (BOARD_BUTTON3_PIN) +#define BOARD_BUTTON3_ADC_CH (1) +#define BOARD_BUTTON3_ADC_NAME "adc1" +#define BOARD_BUTTON3_ADC_REF (600) +#define BOARD_BUTTON3_ADC_RANG (500) + +//#define BOARD_ADC_BUTTON2 (2) +//#define BOARD_ADC_BUTTON2_CH (1) +//#define BOARD_ADC_BUTTON2_NAME "adc1" +//#define BOARD_ADC_BUTTON2_REF xxx +//#define BOARD_ADC_BUTTON2_RANG xxx +#endif // defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#endif // defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 + +#if defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 +// LED +/* the board supported leds */ +#ifndef BOARD_LED_NUM +#define BOARD_LED_NUM (2) +#endif + +#define BOARD_LED0_PIN BOARD_PIN11 +#define BOARD_LED1_PIN BOARD_PIN12 + +// PWM LED +/* the board supported pwm leds */ +#ifndef BOARD_LED_PWM_NUM +#define BOARD_LED_PWM_NUM (1) +#endif + +#if defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 +#define BOARD_LED0_PWM_PIN (BOARD_LED0_PIN) +/* the pwm channel used for led0, if the pwm channel used as led0, it shoudn't reference as BOARD_PWMx_CH */ +#define BOARD_LED0_PWM_CH (0) +#endif // defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 + +// GPIO LED +#ifndef BOARD_LED_GPIO_NUM +#define BOARD_LED_GPIO_NUM (1) +#endif + +#if defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +/* the gpio pin used for led0, if the gpio pin used as led, it shoudn't reference as BOARD_GPIO_PINx */ +#define BOARD_LED1_GPIO_PIN (BOARD_LED1_PIN) +#endif // defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 +#endif // defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 + +#if defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 +// BT +/* the board support bluetooth */ +#ifndef BOARD_BT_SUPPORT +#define BOARD_BT_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 + +#if defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 +// WIFI +/* the board support wifi */ +#ifndef BOARD_WIFI_SUPPORT +#define BOARD_WIFI_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 + +#if defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 +// Audio +/* the board support audio */ +#ifndef BOARD_AUDIO_SUPPORT +#define BOARD_AUDIO_SUPPORT 1 +#endif +#endif // defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 + +/****************************************************************************/ +// Common solutions defines + +// Console config, Almost all solutions and demos use these. +#ifndef CONSOLE_UART_IDX +#define CONSOLE_UART_IDX (BOARD_UART0_IDX) +#endif + +#ifndef CONFIG_CLI_USART_BAUD +#define CONFIG_CLI_USART_BAUD (BOARD_UART0_BAUD) +#endif + +#ifndef CONFIG_CONSOLE_UART_BUFSIZE +#define CONFIG_CONSOLE_UART_BUFSIZE (128) +#endif + +/****************************************************************************/ +// Commom test demos defines + +// i2c +#define EXAMPLE_IIC_IDX 0 // 1 +#define EXAMPLE_PIN_IIC_SDA 0 // PC1 +#define EXAMPLE_PIN_IIC_SCL 0 // PC0 +#define EXAMPLE_PIN_IIC_SDA_FUNC 0 // PC1_I2C1_SDA +#define EXAMPLE_PIN_IIC_SCL_FUNC 0 // PC0_I2C1_SCL + +// adc +#define EXAMPLE_ADC_CH0 0 // PA8 +#define EXAMPLE_ADC_CH0_FUNC 0 // PA8_ADC_A0 +#define EXAMPLE_ADC_CH12 0 // PA26 +#define EXAMPLE_ADC_CH12_FUNC 0 // PA26_ADC_A12 + +/****************************************************************************/ +// Vendor board defines + +/* other board specific defines */ +//#define CUSTOM_BOARD_xxx + +/****************************************************************************/ +/** + * @brief init the board for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_init(void); + +/** + * @brief init the board gpio pin for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_gpio_pin_init(void); + +/** + * @brief init the board uart for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_uart_init(void); + +/** + * @brief init the board pwm for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_pwm_init(void); + +/** + * @brief init the board adc for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_adc_init(void); + +/** + * @brief init the board button for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_button_init(void); + +/** + * @brief init the board led for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_led_init(void); + +/** + * @brief init the board wifi for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_wifi_init(void); + +/** + * @brief init the board bt for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_bt_init(void); + +/** + * @brief init the board audio for default: pin mux, etc. + * re-implement if need. + * @return + */ +void board_audio_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/xuantie/xiaohui/c908x/figures/1.env.png b/bsp/xuantie/xiaohui/c908x/figures/1.env.png new file mode 100644 index 00000000000..64f009ee845 Binary files /dev/null and b/bsp/xuantie/xiaohui/c908x/figures/1.env.png differ diff --git a/bsp/xuantie/xiaohui/c908x/figures/2.scons.png b/bsp/xuantie/xiaohui/c908x/figures/2.scons.png new file mode 100644 index 00000000000..1889fed5554 Binary files /dev/null and b/bsp/xuantie/xiaohui/c908x/figures/2.scons.png differ diff --git a/bsp/xuantie/xiaohui/c908x/figures/3.vscode.png b/bsp/xuantie/xiaohui/c908x/figures/3.vscode.png new file mode 100644 index 00000000000..21c9b1be890 Binary files /dev/null and b/bsp/xuantie/xiaohui/c908x/figures/3.vscode.png differ diff --git a/bsp/xuantie/xiaohui/c908x/objdump.bat b/bsp/xuantie/xiaohui/c908x/objdump.bat new file mode 100644 index 00000000000..75f8c9102fd --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/objdump.bat @@ -0,0 +1,8 @@ +@echo off +set OBJDUMP=D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\RISC-V\XTGccElfNewlib\V3.0.1\R\bin\riscv64-unknown-elf-objdump +set TARGET=E:\rt-thread\bsp\xuantie\xiaohui\c908x\rtthread.elf +set OUTPUT=rtthread.asm + +%OBJDUMP% -d %TARGET% > %OUTPUT% +echo Disassembly generated to %OUTPUT% +pause \ No newline at end of file diff --git a/bsp/xuantie/xiaohui/c908x/qemu.bat b/bsp/xuantie/xiaohui/c908x/qemu.bat new file mode 100644 index 00000000000..4376554efb4 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/qemu.bat @@ -0,0 +1,91 @@ +@echo off +cls + +echo /* +echo * Copyright (c) 2006 - 2025, RT-Thread Development Team +echo * +echo * SPDX-License-Identifier: Apache-2.0 +echo * +echo * Change Logs: +echo * Date Author Notes +echo * 2025/04/29 Wangshun first version +echo * 2025/05/14 Optimized Improved robustness and error handling +echo */ +echo. + +setlocal enabledelayedexpansion + +set "CONFIG_FILE=qemu_config.txt" +set "CPU_CONFIG_FILE=cpu_config.txt" +set "DEFAULT_QEMU_DIR=E:\XuanTieCore\6.QEMU" +set "ELF_PATH=%CD%\rtthread.elf" + +:: Load QEMU directory from config file or set default +if exist "!CONFIG_FILE!" ( + set /p QEMU_DIR=<"!CONFIG_FILE!" + if not defined QEMU_DIR set "QEMU_DIR=!DEFAULT_QEMU_DIR!" +) else ( + set "QEMU_DIR=!DEFAULT_QEMU_DIR!" +) + +:: Load CPU parameter from config file or set default +if exist "!CPU_CONFIG_FILE!" ( + set /p CPU_PARAM=<"!CPU_CONFIG_FILE!" + if not defined CPU_PARAM set "CPU_PARAM=c908x" +) else ( + set "CPU_PARAM=c908x" +) + +:: Prompt for new QEMU directory +set /p "USER_INPUT=Enter new QEMU directory (Enter for default: !QEMU_DIR!): " +if defined USER_INPUT ( + set "USER_INPUT=!USER_INPUT: =!" + if not "!USER_INPUT!"=="" ( + set "QEMU_DIR=!USER_INPUT!" + echo !QEMU_DIR!>"!CONFIG_FILE!" + ) +) + +:: Validate QEMU path +set "QEMU_PATH=!QEMU_DIR!\qemu-system-riscv64.exe" +if not exist "!QEMU_PATH!" ( + echo Error: QEMU executable not found at "!QEMU_PATH!". + echo Please verify the QEMU directory and try again. + pause + exit /b 1 +) + +:: Prompt for new CPU parameter +echo Current CPU parameter: !CPU_PARAM! +set /p "CPU_INPUT=Enter new -cpu parameter (Enter for default): " +if defined CPU_INPUT ( + set "CPU_INPUT=!CPU_INPUT: =!" + if not "!CPU_INPUT!"=="" ( + set "CPU_PARAM=!CPU_INPUT!" + echo !CPU_PARAM!>"!CPU_CONFIG_FILE!" + ) +) + +:: Validate ELF file +if not exist "!ELF_PATH!" ( + echo Error: rtthread.elf not found at "!ELF_PATH!". + pause + exit /b 1 +) + +:: Display QEMU version +echo. +"!QEMU_PATH!" --version + +:: Run QEMU +echo. +"!QEMU_PATH!" -machine xiaohui -kernel "!ELF_PATH!" -nographic -cpu !CPU_PARAM! +if !ERRORLEVEL! neq 0 ( + echo Error: QEMU failed to run. Check configuration or paths. + pause + exit /b !ERRORLEVEL! +) + +echo QEMU terminated. +pause +endlocal diff --git a/bsp/xuantie/xiaohui/c908x/rtconfig.h b/bsp/xuantie/xiaohui/c908x/rtconfig.h new file mode 100644 index 00000000000..c7ed0ed47ce --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/rtconfig.h @@ -0,0 +1,403 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define XUANTIAN_XIAOHUI_C908X + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_USING_STDC_ATOMIC +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_CPU_64BIT +#define ARCH_RISCV +#define ARCH_RISCV64 +#define ARCH_USING_NEW_CTX_SWITCH + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 8192 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_XUANTIE + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/xuantie/xiaohui/c908x/rtconfig.py b/bsp/xuantie/xiaohui/c908x/rtconfig.py new file mode 100644 index 00000000000..5a6acc1358e --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/rtconfig.py @@ -0,0 +1,99 @@ +import os +ARCH = 'risc-v' +CPU = 'c908x' +# toolchains options +CROSS_TOOL = 'gcc' + +#------- toolchains path ------------------------------------------------------- +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\RISC-V\XTGccElfNewlib\V3.0.1\R\bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +CORE = 'risc-v' +MAP_FILE = 'rtthread.map' +LINK_FILE = '../../libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld' +if os.path.exists('./libraries'): + LINK_FILE = './libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld' +TARGET_NAME = 'rtthread.bin' + +#------- GCC settings ---------------------------------------------------------- +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'riscv64-unknown-elf-' + CC = PREFIX + 'gcc' + CXX= PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + MCPU = ' -mcpu=c908x ' # Modify here based on CPU architecture. + MCPU_DEFINE = ' -DCONFIG_CPU_XUANTIE_C908X=1 ' # Modify here based on CPU architecture. + DEVICE = MCPU + MCPU_DEFINE + ' -Wno-main -mcmodel=medany -MP -MMD ' + + GLOBAL_DEFINES = ( + ' -DCONFIG_KERNEL_RTTHREAD=1 ' + ' -D__RT_KERNEL_SOURCE__=1 ' + ' -DCONFIG_CSI_V2=1 ' + ' -DCONFIG_CSI="csi2" ' + ' -DCONFIG_SUPPORT_TSPEND=0 ' + ' -DCONFIG_SUPPORT_IRQ_NESTED=0 ' + ' -DCONFIG_XIP=1 ' + ' -DCONFIG_ARCH_MAINSTACK=8192 ' + ' -DCONFIG_ARCH_INTERRUPTSTACK=8192 ' + ' -DCONFIG_BOARD_XIAOHUI_EVB=1 ' + ' -DCLI_CONFIG_STACK_SIZE=8192 ' + ' -DCONFIG_PLIC_BASE=134217728 ' + ' -DCONFIG_VIC_TSPDR=201326592 ' + ' -DCONFIG_CLIC_BASE=201392128 ' + ' -DCONFIG_FPP_ENABLE=0 ' + ' -DCONFIG_INTC_CLIC_PLIC=1 ' + ' -DCONFIG_INIT_TASK_STACK_SIZE=8192 ' + ' -DCONFIG_APP_TASK_STACK_SIZE=8192 ' + ' -DCONFIG_SYSTICK_HZ=100 ' + ' -DCONFIG_DEBUG=1 ' + ) + + CFLAGS = DEVICE + ' -c -Wno-unused-function -g -Wpointer-arith -Wno-undef -Wall -ffunction-sections -fdata-sections -fno-inline-functions \ + -fno-builtin -fno-strict-aliasing -Wno-int-to-pointer-cast -Wno-pointer-to-int-cast' + GLOBAL_DEFINES + + AFLAGS = DEVICE + ' -D"Default_IRQHandler=SW_handler" ' + GLOBAL_DEFINES + + LFLAGS = DEVICE + ' -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -nostartfiles -Wl,--gc-sections ' + LFLAGS += ' -T ' + LINK_FILE + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -g3' + AFLAGS += ' -g3' + else: + CFLAGS += ' -O2 -g2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' + POST_ACTION += SIZE + ' $TARGET\n' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '../tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/xuantie/xiaohui/c908x/rtconfig_preinc.h b/bsp/xuantie/xiaohui/c908x/rtconfig_preinc.h new file mode 100644 index 00000000000..f94e39943ef --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/rtconfig_preinc.h @@ -0,0 +1,36 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define CLI_CONFIG_STACK_SIZE 8192 +#define CONFIG_APP_TASK_STACK_SIZE 8192 +#define CONFIG_ARCH_INTERRUPTSTACK 8192 +#define CONFIG_ARCH_MAINSTACK 8192 +#define CONFIG_BOARD_XIAOHUI_EVB 1 +#define CONFIG_CLIC_BASE 201392128 +#define CONFIG_CPU_XUANTIE_C908X 1 +#define CONFIG_CSI "csi2" +#define CONFIG_CSI_V2 1 +#define CONFIG_DEBUG 1 +#define CONFIG_FPP_ENABLE 0 +#define CONFIG_INIT_TASK_STACK_SIZE 8192 +#define CONFIG_INTC_CLIC_PLIC 1 +#define CONFIG_KERNEL_RTTHREAD 1 +#define CONFIG_PLIC_BASE 134217728 +#define CONFIG_SUPPORT_IRQ_NESTED 0 +#define CONFIG_SUPPORT_TSPEND 0 +#define CONFIG_SYSTICK_HZ 100 +#define CONFIG_VIC_TSPDR 201326592 +#define CONFIG_XIP 1 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define _POSIX_C_SOURCE 1 +#define __RTTHREAD__ +#define __RT_KERNEL_SOURCE__ 1 +#define _REENT_SMALL + +#endif /*RTCONFIG_PREINC_H__*/ + diff --git a/bsp/xuantie/xiaohui/c908x/template.cdkproj b/bsp/xuantie/xiaohui/c908x/template.cdkproj new file mode 100644 index 00000000000..27f8a4488cb --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/template.cdkproj @@ -0,0 +1,250 @@ + + + + + + new_psf_project_SmartL_E906FD-R2S2(V1.7.9) + + + + XTGccElfNewlib + latest + + + + + ;;; + ;;MHZ + + + + + + + + + + + + + no + + + + + no + + + + + no + + + + + no + + + + + no + + + + + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + no + + + yes + + + c908x + yes + little + no + no + no + + + no + + + $(ProjectName) + Executable + no + no + no + yes + no + no + + + + no + + no + + + no + + no + + + no + + no + + + + + + + Optimize size (-Os) + Maximum (-g3) + $(ProjectPath);$(ProjectPath)/../../../../../csi_core/include;$(ProjectPath)/../../../../../csi_driver/include;$(ProjectPath)/../../../../../libs/include;$(ProjectPath)/../../../../../csi_driver/smartl_rv32/include;$(ProjectPath)/../../../../../csi_kernel/include;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/include/;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/include;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/portable/GCC/riscv;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/portable/GCC/riscv/chip_specific_extensions/thead_rv32;$(ProjectPath)/../../../../../board/smartl_e906_evb/include;$(ProjectPath)/../../../../../projects/tests/dtest/include;$(ProjectPath)/../../../../../projects/tests/kernel/include;;;;;;;$(ProjectPath)/../../../../../projects/tests/kernel/freertos/configs + -ffunction-sections -fdata-sections + no + no + no + no + no + no + yes + no + yes + no + no + + + + + + -D"Default_IRQHandler=SW_handler" + gdwarf2 + + + yes + yes + $(ProjectPath)/../../libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_xiaohui.ld + m + + -Wl,-zmax-page-size=1024 + no + + no + none + no + no + + + yes + SIM + yes + main + $(ProjectPath)/utilities/gdb.init + + + yes + Hard Reset + 0 + no + + no + + + + localhost + 1025 + 0 + 12000 + 10 + 100 + 50 + yes + no + no + no + Normal + soft + 0 + None + no + yes + + Local + + no + 1000 + no + 1026 + latest + no + + + soccfg/riscv64/xiaohui_c908x_cfg.xml + + yes + no + no + latest + + + + yes + no + 4444 + no + 6666 + + 5000 + localhost + 3333 + openocd-sifive + latest + + + + + + Erase Sectors + + yes + no + no + Soft Reset + + no + 0 + no + + + + + + diff --git a/bsp/xuantie/xiaohui/c908x/template.cdkws b/bsp/xuantie/xiaohui/c908x/template.cdkws new file mode 100644 index 00000000000..a1c3cd0a730 --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/template.cdkws @@ -0,0 +1,11 @@ + + + $(CDKWS)\__workspace_pack__ + + + + + + + + diff --git a/bsp/xuantie/xiaohui/c908x/utilities/gdb.init b/bsp/xuantie/xiaohui/c908x/utilities/gdb.init new file mode 100644 index 00000000000..7792c77445e --- /dev/null +++ b/bsp/xuantie/xiaohui/c908x/utilities/gdb.init @@ -0,0 +1,6 @@ +set *(int *)0x0=0x6f +si +reset +set *(int *)0x40011008=0x0 +set *(int *)0x4001101c=0x0 +