From d59fd6c131fb27f57496f2f439f1b82f8a686820 Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Fri, 11 Sep 2026 17:37:39 -0700 Subject: [PATCH 01/11] fix: correct veer fpga target clock to match VCK190 hardware (20 MHz) --- target/veer/config.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/veer/config.rs b/target/veer/config.rs index 3a2ab0d8a..b002c8a80 100644 --- a/target/veer/config.rs +++ b/target/veer/config.rs @@ -27,8 +27,11 @@ pub struct KernelConfig; impl KernelConfigInterface for KernelConfig { #[cfg(feature = "silicon")] const SYSTEM_CLOCK_HZ: u64 = 100_000_000; + // Matches TIMER_FREQUENCY_HZ in + // third_party/caliptra/caliptra-mcu-sw/platforms/fpga/runtime/src/main.rs, + // the confirmed clock rate for this core on the VCK190 build. #[cfg(feature = "fpga")] - const SYSTEM_CLOCK_HZ: u64 = 10_000_000; //FIXME + const SYSTEM_CLOCK_HZ: u64 = 20_000_000; #[cfg(feature = "emulator")] const SYSTEM_CLOCK_HZ: u64 = 1_000_000; } From 40227ed193a54957c440c8d26df00c5ed0bdf53c Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Fri, 11 Sep 2026 17:37:41 -0700 Subject: [PATCH 02/11] feat: add fpga console backend using the wrapper debug FIFO --- target/veer/console.rs | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/veer/console.rs b/target/veer/console.rs index 135ecdd9d..a3c508bb4 100644 --- a/target/veer/console.rs +++ b/target/veer/console.rs @@ -5,9 +5,21 @@ use kernel::sync::spinlock::SpinLock; use pw_status::Result; +/// FPGA wrapper debug FIFO push register (`dbg_fifo_push`), absolute address +/// `0xA401_1014`. Writing a byte with bit 8 set pushes it into the FIFO the +/// ARM PS host drains for console output. Matches +/// `caliptra-mcu-sw/platforms/fpga/rom/src/io.rs::FPGA_UART_OUTPUT`, which +/// uses the identical mechanism on the same board. +#[cfg(feature = "fpga")] +const FPGA_DBG_FIFO_PUSH: *mut u32 = core::ptr::without_provenance_mut(0xA401_1014); + +#[cfg(feature = "fpga")] +const FPGA_CHAR_VALID: u32 = 0x100; + struct Uart; impl Uart { + #[cfg(not(feature = "fpga"))] fn write_all(&mut self, buf: &[u8]) -> Result<()> { let tx = core::ptr::with_exposed_provenance_mut::(0x1000_1041); for &byte in buf.iter() { @@ -17,6 +29,16 @@ impl Uart { } Ok(()) } + + #[cfg(feature = "fpga")] + fn write_all(&mut self, buf: &[u8]) -> Result<()> { + for &byte in buf.iter() { + unsafe { + FPGA_DBG_FIFO_PUSH.write_volatile(byte as u32 | FPGA_CHAR_VALID); + } + } + Ok(()) + } } static UART: SpinLock = SpinLock::new(Uart); From 2cce5790e8d60edf8400e45a974c4636fde00c62 Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Fri, 11 Sep 2026 17:37:43 -0700 Subject: [PATCH 03/11] feat: add fpga exit/pass-fail signaling via the wrapper debug FIFO --- target/veer/entry.rs | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/veer/entry.rs b/target/veer/entry.rs index 82bd00f42..cc93fe4c9 100644 --- a/target/veer/entry.rs +++ b/target/veer/entry.rs @@ -25,7 +25,7 @@ fn main() -> ! { } pub fn exit(code: u32) -> ! { - #[cfg(not(feature = "emulator"))] + #[cfg(not(any(feature = "emulator", feature = "fpga")))] let _ = code; #[cfg(feature = "emulator")] @@ -34,6 +34,17 @@ pub fn exit(code: u32) -> ! { let exitcode = core::ptr::with_exposed_provenance_mut::(0x1000_2000); exitcode.write_volatile(code); } + + #[cfg(feature = "fpga")] + unsafe { + // SAFETY: dbg_fifo_push (0xA401_1014) is the FPGA wrapper's + // debug/exit register; writing 0xff/0x01 (valid bit 0x100 set) + // signals pass/fail to the host, matching + // caliptra-mcu-sw/platforms/fpga/rom/src/io.rs::exit_fpga. + let dbg_fifo_push = core::ptr::without_provenance_mut::(0xA401_1014); + let byte: u32 = if code == 0 { 0xff } else { 0x01 }; + dbg_fifo_push.write_volatile(byte | 0x100); + } loop {} } From c90dd482e462ed2fc28ee2fba37bd7db353ac6e0 Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Fri, 11 Sep 2026 17:47:17 -0700 Subject: [PATCH 04/11] config: add k_veer bazel config for veer platform setup --- .bazelrc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.bazelrc b/.bazelrc index 98938f8a2..ca052460b 100644 --- a/.bazelrc +++ b/.bazelrc @@ -104,6 +104,11 @@ test:stress_k_ast1060_evb --run_under="//target/ast10x0/harness:test_runner \ --timeout 0 " test:stress_k_ast1060_evb --test_env=AST1060_EVB_PI_HOST +# ── VeeR RISC-V kernel target ── +# Platform setup for building //target/veer/* artifacts. +common:k_veer --platforms=//target/veer:veer +build:k_veer --build_tag_filters=-do_not_build,-kernel_doc_test + # Site-local overrides. Kept last so developer machine-specific settings (e.g. a # local QEMU source override via --override_repository) take precedence. This # file is not checked in; see third_party/qemu/setup.md. From 35ed2832f63fa9cbc0774c30070cb0272e94888a Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 12:26:38 -0700 Subject: [PATCH 05/11] refactor: extract pass/fail scanning in caliptra_runner.py and add a unit test Add scan_output_for_result(lines) to caliptra_runner.py: a standalone function that scans detokenized output lines for a PASS/FAIL sentinel, with no dependency on the emulator subprocess. This is what Task 5's fpga interface will reuse, and it's what makes this file unit-testable in a sandbox with no board/emulator binary available. Add caliptra_runner_test.py covering the no-sentinel, PASS, FAIL, and first-sentinel-wins cases, and wire it into BUILD.bazel as a py_test. --- target/veer/tooling/BUILD.bazel | 9 +++++++- target/veer/tooling/caliptra_runner.py | 15 +++++++++++++ target/veer/tooling/caliptra_runner_test.py | 25 +++++++++++++++++++++ 3 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 target/veer/tooling/caliptra_runner_test.py diff --git a/target/veer/tooling/BUILD.bazel b/target/veer/tooling/BUILD.bazel index 29b66e4b8..79b5f6f45 100644 --- a/target/veer/tooling/BUILD.bazel +++ b/target/veer/tooling/BUILD.bazel @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 load("@pigweed//pw_build:pw_py_importable_runfile.bzl", "pw_py_importable_runfile") -load("@rules_python//python:defs.bzl", "py_binary") +load("@rules_python//python:defs.bzl", "py_binary", "py_test") load(":caliptra_runner.bzl", "mcu_rom_wrapper") mcu_rom_wrapper( @@ -65,3 +65,10 @@ py_binary( "@rules_python//python/runfiles", ], ) + +py_test( + name = "caliptra_runner_test", + srcs = ["caliptra_runner_test.py"], + imports = ["."], + deps = [":caliptra_runner"], +) diff --git a/target/veer/tooling/caliptra_runner.py b/target/veer/tooling/caliptra_runner.py index ff16f3e12..7832aeefb 100755 --- a/target/veer/tooling/caliptra_runner.py +++ b/target/veer/tooling/caliptra_runner.py @@ -17,6 +17,21 @@ _LOG = logging.getLogger(__name__) _LOG.setLevel(logging.INFO) + +def scan_output_for_result(lines): + """Scan detokenized output lines for a PASS/FAIL sentinel. + + Returns 0 on a line containing "PASS", 1 on a line containing "FAIL", + or None if no sentinel has appeared yet. + """ + for line in lines: + if "PASS" in line: + return 0 + if "FAIL" in line: + return 1 + return None + + try: import caliptra.emulator_cptra_rom # type: ignore diff --git a/target/veer/tooling/caliptra_runner_test.py b/target/veer/tooling/caliptra_runner_test.py new file mode 100644 index 000000000..212e05765 --- /dev/null +++ b/target/veer/tooling/caliptra_runner_test.py @@ -0,0 +1,25 @@ +# Licensed under the Apache-2.0 license +# SPDX-License-Identifier: Apache-2.0 +import unittest + +from caliptra_runner import scan_output_for_result + + +class ScanOutputForResultTest(unittest.TestCase): + def test_no_sentinel_yet(self): + self.assertIsNone(scan_output_for_result(["booting...", "init i3c"])) + + def test_pass_sentinel(self): + self.assertEqual(0, scan_output_for_result(["running tests", "PASS"])) + + def test_fail_sentinel(self): + self.assertEqual(1, scan_output_for_result(["running tests", "FAIL: 1"])) + + def test_first_sentinel_wins(self): + self.assertEqual( + 0, scan_output_for_result(["PASS", "unrelated trailing noise"]) + ) + + +if __name__ == "__main__": + unittest.main() From bc649df4a44e734eff10f78c96483c5da537cd1b Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 12:49:55 -0700 Subject: [PATCH 06/11] feat: implement the fpga interface in caliptra_runner.py Adds an `elif interface == "fpga":` branch alongside the existing "emulator" branch in load_and_run(). It reads the VCK190_FPGA_HOST env var (FPGA_HOST constant), fails loudly with a non-zero exit if unset, scps the image to the board, invokes launch_openocd.sh over ssh, detokenizes the captured output with the existing pw_tokenizer Detokenizer mechanism, and calls scan_output_for_result() (from Task 4) to decide pass/fail. --- target/veer/tooling/caliptra_runner.py | 43 ++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/target/veer/tooling/caliptra_runner.py b/target/veer/tooling/caliptra_runner.py index 7832aeefb..4b4c53b28 100755 --- a/target/veer/tooling/caliptra_runner.py +++ b/target/veer/tooling/caliptra_runner.py @@ -4,6 +4,7 @@ import argparse import logging +import os import subprocess import sys import tempfile @@ -17,6 +18,10 @@ _LOG = logging.getLogger(__name__) _LOG.setLevel(logging.INFO) +# Environment variable naming the SSH host (user@host or host alias) for the +# VCK190 FPGA board used by the "fpga" interface. +FPGA_HOST = "VCK190_FPGA_HOST" + def scan_output_for_result(lines): """Scan detokenized output lines for a PASS/FAIL sentinel. @@ -131,6 +136,7 @@ def load_and_run( interface: str, manifest: str, vendor_pk_hash: str, + elf: Path | None = None, ) -> list[str]: """Prepare arguments to load an image into a board and spawn a console.""" if interface == "emulator": @@ -166,6 +172,42 @@ def load_and_run( if vendor_pk_hash and str(vendor_pk_hash) != "None": cmd.append(f"--vendor-pk-hash={vendor_pk_hash}") return cmd + elif interface == "fpga": + host = os.environ.get(FPGA_HOST) + if not host: + _LOG.fatal( + "%s is not set; cannot reach the VCK190 board", FPGA_HOST + ) + sys.exit(1) + + remote_bin = f"/tmp/{Path(image).name}" + subprocess.run(["scp", str(image), f"{host}:{remote_bin}"], check=True) + + # Loads the image into the MCU ROM backdoor SRAM, deasserts + # cptra_ss_rst_b, and streams the debug FIFO back over stdout. + # See hw/fpga/README.md's "JTAG debug" section and + # hw/fpga/kernel-modules/mcu_rom_backdoor.c for the mechanism. + cmd = [ + "ssh", + host, + "sudo", + "caliptra-mcu-sw/hw/fpga/launch_openocd.sh", + "load-and-run", + remote_bin, + ] + _LOG.info("Invoking fpga runner: %s", cmd) + proc = subprocess.run(cmd, capture_output=True, text=True, check=False) + + # Reuse the same Detokenizer mechanism the emulator's tokenized + # console path uses (see _detokenizer() above), rather than + # introducing a second detokenization code path. + detokenizer = detokenize.Detokenizer(elf) + text = detokenizer.detokenize_text(proc.stdout) + result = scan_output_for_result(text.splitlines()) + if result is None: + _LOG.fatal("Device produced no PASS/FAIL sentinel") + sys.exit(1) + sys.exit(result) else: raise Exception("unknown mechanism", mechanism) @@ -215,6 +257,7 @@ def _main(args) -> int: args.interface, args.manifest, args.vendor_pk_hash, + elf=args.elf, ) # TODO(cfrantz): add support for the tokenized console. return_code = simple_console(cmd) From 03ec7297d1af23930c40345a1745f0393ecfd1f2 Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 13:03:50 -0700 Subject: [PATCH 07/11] fix: handle scp failures and surface ssh stderr in fpga runner branch Wraps the scp subprocess.run(check=True) call in a try/except so a failed copy (bad host, network down, wrong path) logs a clean _LOG.fatal diagnostic and exits 1 instead of propagating a raw CalledProcessError traceback. Also logs the ssh/launch_openocd.sh subprocess's captured stderr (previously discarded), including it in the "no PASS/FAIL sentinel" fatal message so a real remote failure (auth, missing script, wrong path) is diagnosable from the output instead of being silently swallowed behind a generic error. --- target/veer/tooling/caliptra_runner.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target/veer/tooling/caliptra_runner.py b/target/veer/tooling/caliptra_runner.py index 4b4c53b28..ffeb1c349 100755 --- a/target/veer/tooling/caliptra_runner.py +++ b/target/veer/tooling/caliptra_runner.py @@ -181,7 +181,13 @@ def load_and_run( sys.exit(1) remote_bin = f"/tmp/{Path(image).name}" - subprocess.run(["scp", str(image), f"{host}:{remote_bin}"], check=True) + try: + subprocess.run( + ["scp", str(image), f"{host}:{remote_bin}"], check=True + ) + except subprocess.CalledProcessError as e: + _LOG.fatal("Failed to copy %s to %s: %s", image, host, e) + sys.exit(1) # Loads the image into the MCU ROM backdoor SRAM, deasserts # cptra_ss_rst_b, and streams the debug FIFO back over stdout. @@ -197,6 +203,8 @@ def load_and_run( ] _LOG.info("Invoking fpga runner: %s", cmd) proc = subprocess.run(cmd, capture_output=True, text=True, check=False) + if proc.stderr: + _LOG.info("fpga runner stderr: %s", proc.stderr) # Reuse the same Detokenizer mechanism the emulator's tokenized # console path uses (see _detokenizer() above), rather than @@ -205,7 +213,10 @@ def load_and_run( text = detokenizer.detokenize_text(proc.stdout) result = scan_output_for_result(text.splitlines()) if result is None: - _LOG.fatal("Device produced no PASS/FAIL sentinel") + _LOG.fatal( + "Device produced no PASS/FAIL sentinel; fpga runner stderr: %s", + proc.stderr, + ) sys.exit(1) sys.exit(result) else: From aec1949366c7671dc266861732b5f799f794a42c Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 13:17:06 -0700 Subject: [PATCH 08/11] build: add a manual fpga_test target for the veer unittest runner --- target/veer/unittest_runner/BUILD.bazel | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/veer/unittest_runner/BUILD.bazel b/target/veer/unittest_runner/BUILD.bazel index ada0f88f9..c0e6c2224 100644 --- a/target/veer/unittest_runner/BUILD.bazel +++ b/target/veer/unittest_runner/BUILD.bazel @@ -33,6 +33,17 @@ caliptra_test( target = ":unittest_runner", ) +caliptra_test( + name = "fpga_test", + interface = "fpga", + tags = [ + "fpga", + "manual", + "requires-fpga", + ], + target = ":unittest_runner", +) + filegroup( name = "system_config", srcs = ["system.json5"], From 84b8888d96a2e7f3b17e50520bde2330ebe6629d Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 13:39:45 -0700 Subject: [PATCH 09/11] fix: address whole-branch review findings for veer fpga target - target/veer/BUILD.bazel: add the crate_features select to the console rust_library that entry/config already had, so #[cfg(feature = "fpga")] in console.rs actually compiles in when building for the fpga target_type. Previously the fpga console backend (writing to the FPGA wrapper's debug FIFO) was dead code and fpga images silently kept using the emulator-only UART address. - target/veer/tooling/caliptra_runner.py: in the fpga branch of load_and_run, drop the Detokenizer/detokenize_text call (this target's log backend is log_backend_basic, a plain-text logger, so detokenization was a no-op that only added a hard, unmet ELF-file runfiles dependency causing a FileNotFoundError at runtime) and scan proc.stdout directly instead. Also: print the captured device output so operators get diagnostics on both PASS and FAIL, add a timeout to the remote subprocess.run call with a TimeoutExpired handler (the VeeR core spins forever after signaling its exit sentinel, so an unreachable/stuck board no longer hangs indefinitely), and check proc.returncode so an outright ssh/remote failure is logged distinctly from "board ran but printed nothing". - .bazelrc: forward VCK190_FPGA_HOST into the k_veer test sandbox (Bazel scrubs the test environment by default), matching the existing k_ast1060_evb pattern. --- .bazelrc | 2 ++ target/veer/BUILD.bazel | 6 ++++ target/veer/tooling/caliptra_runner.py | 46 ++++++++++++++++++++++---- 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/.bazelrc b/.bazelrc index ca052460b..88f76ba47 100644 --- a/.bazelrc +++ b/.bazelrc @@ -108,6 +108,8 @@ test:stress_k_ast1060_evb --test_env=AST1060_EVB_PI_HOST # Platform setup for building //target/veer/* artifacts. common:k_veer --platforms=//target/veer:veer build:k_veer --build_tag_filters=-do_not_build,-kernel_doc_test +# Usage: VCK190_FPGA_HOST= bazel test --config=k_veer //target/veer/unittest_runner:fpga_test +test:k_veer --test_env=VCK190_FPGA_HOST # Site-local overrides. Kept last so developer machine-specific settings (e.g. a # local QEMU source override via --override_repository) take precedence. This diff --git a/target/veer/BUILD.bazel b/target/veer/BUILD.bazel index 7a5e8f80a..d453b2c03 100644 --- a/target/veer/BUILD.bazel +++ b/target/veer/BUILD.bazel @@ -105,6 +105,12 @@ rust_binary( rust_library( name = "console", srcs = ["console.rs"], + crate_features = select({ + ":emulator": ["emulator"], + ":fpga": ["fpga"], + ":silicon": ["silicon"], + "//conditions:default": [], + }), crate_name = "console_backend", edition = "2024", target_compatible_with = TARGET_COMPATIBLE_WITH, diff --git a/target/veer/tooling/caliptra_runner.py b/target/veer/tooling/caliptra_runner.py index ffeb1c349..e932578f8 100755 --- a/target/veer/tooling/caliptra_runner.py +++ b/target/veer/tooling/caliptra_runner.py @@ -22,6 +22,12 @@ # VCK190 FPGA board used by the "fpga" interface. FPGA_HOST = "VCK190_FPGA_HOST" +# Timeout (seconds) for the remote fpga run. The VeeR core's exit() +# implementation writes the PASS/FAIL sentinel and then spins forever (there's +# no way for it to fully halt itself back to the host), so this bounds how +# long we wait on a stuck or unreachable board rather than hanging forever. +_FPGA_RUN_TIMEOUT_SECONDS = 300 + def scan_output_for_result(lines): """Scan detokenized output lines for a PASS/FAIL sentinel. @@ -202,16 +208,42 @@ def load_and_run( remote_bin, ] _LOG.info("Invoking fpga runner: %s", cmd) - proc = subprocess.run(cmd, capture_output=True, text=True, check=False) + try: + proc = subprocess.run( + cmd, + capture_output=True, + text=True, + check=False, + timeout=_FPGA_RUN_TIMEOUT_SECONDS, + ) + except subprocess.TimeoutExpired as e: + _LOG.fatal( + "fpga runner timed out after %s seconds; stdout so far: %s; " + "stderr so far: %s", + _FPGA_RUN_TIMEOUT_SECONDS, + e.stdout, + e.stderr, + ) + sys.exit(1) + if proc.stderr: _LOG.info("fpga runner stderr: %s", proc.stderr) - # Reuse the same Detokenizer mechanism the emulator's tokenized - # console path uses (see _detokenizer() above), rather than - # introducing a second detokenization code path. - detokenizer = detokenize.Detokenizer(elf) - text = detokenizer.detokenize_text(proc.stdout) - result = scan_output_for_result(text.splitlines()) + if proc.returncode != 0: + _LOG.fatal( + "ssh/remote command failed with exit code %d: %s", + proc.returncode, + proc.stderr, + ) + sys.exit(1) + + # This target's kernel config pins its log backend to + # log_backend_basic (a plain-text logger; see target/veer/BUILD.bazel's + # platform rule), so the board's console output is never tokenized and + # there is nothing to detokenize here, unlike the emulator's tokenized + # console path (see _detokenizer() above). + print(proc.stdout) + result = scan_output_for_result(proc.stdout.splitlines()) if result is None: _LOG.fatal( "Device produced no PASS/FAIL sentinel; fpga runner stderr: %s", From bbc3911952eaa1f6ebe7d39629661dd69213151d Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 14:31:51 -0700 Subject: [PATCH 10/11] ci: build the veer fpga target image on every CI run Adds a build-only (no lab hardware needed) CI job that builds //target/veer/unittest_runner:fpga_test under target_type=fpga, so a regression like the console rust_library silently losing its fpga cfg feature (caught by the final review of the fpga-target plan) gets flagged automatically instead of only being visible under bazel aquery. Actually running the test still requires a VCK190 board and is left manual/opt-in. --- workflows.json | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/workflows.json b/workflows.json index be73c1917..08c439f85 100644 --- a/workflows.json +++ b/workflows.json @@ -117,6 +117,26 @@ "//target/veer/..." ] }, + { + "name": "caliptra_fpga_build", + "build_config": { + "name": "caliptra_fpga_build_config", + "description": "Build (do not run) the Caliptra MCU fpga target image. Catches fpga cfg/build-wiring regressions without requiring lab hardware; actually running it needs a VCK190 board (see //target/veer/unittest_runner:fpga_test, tagged manual).", + "build_type": "bazel", + "args": [ + "--keep_going", + "--config=k_veer", + "--//target/veer:target_type=fpga" + ], + "driver_options": { + "@type": "pw.build.proto.BazelDriverOptions", + "no_test": true + } + }, + "targets": [ + "//target/veer/unittest_runner:fpga_test" + ] + }, { "name": "earlgrey_qemu_tests", "build_config": { @@ -204,7 +224,8 @@ "ci_tests", "ast10x0_qemu_tests", "earlgrey_qemu_tests", - "caliptra_emulator_tests" + "caliptra_emulator_tests", + "caliptra_fpga_build" ] }, { From b8167796f9e38c8520bfdd242aa2e99ee3b521a8 Mon Sep 17 00:00:00 2001 From: Anthony Rocha Date: Mon, 14 Sep 2026 15:08:41 -0700 Subject: [PATCH 11/11] fix: apply pw format to caliptra_runner.py CI's presubmit format check flagged two lines in the fpga branch that didn't match the repo's formatting style. --- target/veer/tooling/caliptra_runner.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/veer/tooling/caliptra_runner.py b/target/veer/tooling/caliptra_runner.py index e932578f8..6bddf1cdc 100755 --- a/target/veer/tooling/caliptra_runner.py +++ b/target/veer/tooling/caliptra_runner.py @@ -181,16 +181,12 @@ def load_and_run( elif interface == "fpga": host = os.environ.get(FPGA_HOST) if not host: - _LOG.fatal( - "%s is not set; cannot reach the VCK190 board", FPGA_HOST - ) + _LOG.fatal("%s is not set; cannot reach the VCK190 board", FPGA_HOST) sys.exit(1) remote_bin = f"/tmp/{Path(image).name}" try: - subprocess.run( - ["scp", str(image), f"{host}:{remote_bin}"], check=True - ) + subprocess.run(["scp", str(image), f"{host}:{remote_bin}"], check=True) except subprocess.CalledProcessError as e: _LOG.fatal("Failed to copy %s to %s: %s", image, host, e) sys.exit(1)